From 5aa9baad7a0cb6a50222b465d72f46ec278d3284 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu@sifive.com>
Date: Thu, 19 Oct 2023 12:18:07 -0700
Subject: [PATCH] [RISCV] Apply `IsSignExtendingOpW = 1` on `fcvtmod.w.d`

Such that RISCVOptWInstrs can eliminate the redundant sign extend.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  1 +
 llvm/test/CodeGen/RISCV/opt-w-instrs.mir   | 30 ++++++++++++++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/opt-w-instrs.mir

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 5d6e8821b85931..6f88ff7f7ac19a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -112,6 +112,7 @@ def FROUND_D : FPUnaryOp_r_frm<0b0100001, 0b00100, FPR64, FPR64, "fround.d">,
 def FROUNDNX_D : FPUnaryOp_r_frm<0b0100001, 0b00101, FPR64, FPR64, "froundnx.d">,
                  Sched<[WriteFRoundF64, ReadFRoundF64]>;
 
+let IsSignExtendingOpW = 1 in
 def FCVTMOD_W_D
     : FPUnaryOp_r_rtz<0b1100001, 0b01000, GPR, FPR64, "fcvtmod.w.d">,
       Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
new file mode 100644
index 00000000000000..0ecf8fd6bef33a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s --check-prefix=CHECK-ZFA
+
+---
+name:            fcvtmod_w_d
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; CHECK-ZFA-LABEL: name: fcvtmod_w_d
+    ; CHECK-ZFA: liveins: $x10, $x11
+    ; CHECK-ZFA-NEXT: {{  $}}
+    ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10
+    ; CHECK-ZFA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK-ZFA-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1
+    ; CHECK-ZFA-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[FCVTMOD_W_D]]
+    ; CHECK-ZFA-NEXT: $x10 = COPY [[ADD]]
+    ; CHECK-ZFA-NEXT: $x11 = COPY [[FCVTMOD_W_D]]
+    ; CHECK-ZFA-NEXT: PseudoRET
+    %0:fpr64 = COPY $x10
+    %1:gpr = COPY $x11
+
+    %2:gpr = nofpexcept FCVTMOD_W_D %0, 1
+    %3:gpr = ADD %1, %2
+    %4:gpr = ADDIW %2, 0
+    $x10 = COPY %3
+    $x11 = COPY %4
+    PseudoRET
+...