Undriven signal in ibex_register_file_fpga.sv

[shareefj]

Observed Behavior

On the following line, oh_raddr_a_err is undriven if RdataMuxCheck is zero.

https://github.com/lowRISC/ibex/blob/master/rtl/ibex_register_file_fpga.sv#L54

This was seen in Verilator linting when trying to integrate Ibex into my design. I've searched the VLT files for any relevant waivers but can't see any relating to this level of hierarchy.

ERROR: %Warning-UNDRIVEN: src/lowrisc_export_ibex_top_0/rtl/ibex_register_file_fpga.sv:54:9: Signal is not driven: 'oh_raddr_a_err'
                                                                                    : ... note: In instance 'ibex_wb.u_top..gen_regfile_fpga.register_file_i'
   54 |   logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err;
      |         ^~~~~~~~~~~~~~
                   ... For warning description see https://verilator.org/warn/UNDRIVEN?v=5.024
                   ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message.
%Warning-UNDRIVEN: src/lowrisc_export_ibex_top_0/rtl/ibex_register_file_fpga.sv:54:25: Signal is not driven: 'oh_raddr_b_err'
                                                                                     : ... note: In instance 'ibex_wb.u_top..gen_regfile_fpga.register_file_i'
   54 |   logic oh_raddr_a_err, oh_raddr_b_err, oh_we_err;
      |                         ^~~~~~~~~~~~~~
%Error: Exiting due to 2 warning(s)
make: *** [Makefile:23: lint-only] Error 1

ERROR: Failed to build nq:ip:ibex_wb:0 : '['make', 'lint-only']' exited with an error: 2

Expected Behavior

Tis lint clean please.

Steps to reproduce the issue

I'm trying to export the Ibex RTL source code to get around the fact that you are using a custom version of Fusesoc. I'm instantiating Ibex with the following parameters:

  ibex_top #(
      .RV32M  (ibex_pkg::RV32MSlow),
      .RV32B  (ibex_pkg::RV32BNone),
      .RegFile(ibex_pkg::RegFileFPGA)
  ) u_top (
<snip>

and then running a Verilator lint using the standard Fusesoc/Edalize flow.

My Environment

EDA tool and version:
Verilator 5.024 2024-04-05 rev v5.024

Operating system:
Rocky 9.4

Version of the Ibex source code:
8f4c75c

[rswarbrick]

I think this should probably be sorted by #2241 (which I just opened). Would you mind taking a look and checking it is?