[fpga] Hyperdebug integration on FPGA targets

[moidx]

This issue is to track the tasks required to enable Hyperdebug integrations on FPGA targets. Currently, host I/O connectivity is routed to the onboard SM3x in the CW310 board. We need an alternate FPGA pinout configuration to start Hyperdebug enablement.

Ideally the alternate pin configuration will be available in the repository, and Bazel/Fusesoc should be able to select between the available pinout configurations.

[msfschaffner]

@a-will is there anything else that needs to be done for this?
CC @toshaq

[a-will]

This isn't actually part of the M2 milestone, is it?

But in any case, we have a bitstream with the alternate pin configuration, but validation on it is still in an early phase.

In addition (or possibly as a separate issue), the bitstream cache and bazel rules need some updates to make the cw310 hyperdebug variant available for use within our build system, and we'll want to add to the docs explaining how to use. The latter would also mean explaining what hyperdebug is, where to get the firmware, how to connect it, and updating opentitantool to make it all work.

[msfschaffner]

Thanks for summarizing this @a-will!

It looks like the P1 aspects of this issue have been addressed (create an alternate pin configuration), hence I think we can relax this to P2 and assign it to M3 for now (please re-categorize if you think this is incorrect).

[a-will]

Things have changed quite a bit since this issue was first created. Some open items:

• Should the breakout board be integrated into the hyperdebug FPGA build? The hyperdebug firmware currently lacks the ability to emulate SPI device and I2C target roles, but the breakout board is not currently available to the wider project.
  • I2C is connected now. The SPI role can still be handled by spi_host0, which is connected to the flash on the CW310 board.
• Should the hyperdebug FPGA build direct the JTAG pins to the JTAG header instead? The hyperdebug firmware currently lacks the ability to perform JTAG operations. The firmware now supports JTAG.
• Should we execute the planned transition to have the hyperdebug variant be the primary FPGA bitstream for functional test?

[msfschaffner]

Assigning this to SV 2 for now - @moidx @timothytrippel @a-will please adjust as needed.