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export as hierarchy (verilog modules) #70
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Right now I see the fact that I can manipulate signals without regard to module boundaries as a major feature of Migen (and I believe it's used in ARTIQ quite a bit, too). Do you suggest blanket prohibiting this, or just when exporting? In any case, splitting the Migen language into two like that seems troublesome... |
No. This shouldn't touch existing code style or features at all. It's just an trade-off that one has to accept and deal with when exporting hierarchy. This will only give you the tools to do so. |
@jordens Are you actively working on this at the moment or is this something you would just like to see in the future? |
I would like to see it and don't have substantial progress. |
I think this can/should be done without requiring the user to specify a list of Just automatically infer them from how the module is used. |
Triage: fixed in nMigen. |
I'd like to be able to translate the migen Module hierarchy into the exported HDL hierarchy at least to some extent.
Implementation idea:
Module
would receive a list ofios
Module
by anInstance
.build()
would export specialized modules.The text was updated successfully, but these errors were encountered: