isrperf.txt

   ISR performance, interrupt latency 
     DUE (84Mhz), maple(72Mhz), teensy3(96MHz)   UNO(16MHz)  mbed LPC1768(96MHz)
	 ZERO (48MHz), pyboard(168MHz), mbed MK64F(120MHz)

Measure ticks for back-to-back calls to systick, ticks for fast pin set,
ticks for digitalWrite.  Measure time to get into and out of ISR from
standard (std) attachInterrupt() to modified kernel ISR (opt)
     DUE sketch  isrperf.ino
     DUE pin set g_APinDescription[13].pPort->PIO_SODR = g_APinDescription[13].ulPin;
	      bit band *(int *) 0x43c2066c =1;
     maple pin set    GPIOA_BASE->BSRR = 1<<5;
		  bit band  *(int *)0x42210194 = 1;
     teensy3 pin set  GPIOC_PSOR = 1<<5;
		  bit band  *(int *)0x43fe1094 = 1;
     LPC pin set   LPC_GPIO1->FIOSET = 1<<18;
	 MK64F pin set GPIOC_PSOR = 1<<5;
	 ZERO pin set REG_PORT_OUTSET0 = PORT_PA17;
	 pyboard firmware pin set GPIOA->BSRRL = GPIO_PIN_13;
	 CC3200 pin set HWREG(GPIOA1_BASE +( 1<<5)) = 1<<3;
	 WICED STM32F205 pin set GPIOA_BASE->BSRRL = 1 << 15;

  (units are cycles from ARM CPU systick counter or UNO timer2)
                      DUE  maple  teensy3  3.1 3.6  4     UNO teensy++2 LPC  MK64F ZERO pyboard CC3200 WICED pico  F767ZI
tickres                 3      3       1     1   1   1    2      2       1     1    8      9      1      1      2      3
set pin                 6      6      12     6  13   3    4      4      10     8    4      7      5      8      1      3
digitalWrite          184     44      64    53  51  67   63      4      19    71   71            33     36      1      8
in to fcn              15     11      19    13  18   1    2      1       1     1   12     21     10     13             2
out of fcn             17     23      20    12   8   5    6      6       4     4   15     12      8     10             3

in to ISR  (std)      355    104     107    88  75  82    57    63     244   272  221     45    172    107     366   225
out of ISR  (std)     128    121     126    87  36  82    50    54      63   670  177     98     35     87     307    37

in to ISR  (opt)       53     45      64    46  55        18    17      46    55          34     31                   69
out of ISR  (opt)      28     58      30    25  30        29    30      19    29          27     49                   24


------------------------------
Arduino UNO interrupt overhead, see
  http://billgrundmann.wordpress.com/2009/03/02/the-overhead-of-arduino-interrupts/

Teensy ++2 digitalWrite is inline if constant
  You may see jitter in your timings from timer or USB interrupts.

Teensy 3* Cortex M4, ISR entry latency 12 cycles, exit latency 10 cycles,
assuming lazy stacking for float, otherwise add 17 cycles.  Tail chaining
helps for back-to-back interrupts. Measured 5 million interrupts/second
on T3.2@120 mhz, 24 cycles.
---------------------------
UNO/AVR timer0 and millis overhead

  Using timer1 as a cycle counter, we measure the duration of
   result = millis()
 at 21 cycles (IDE 1.0.5).  In a loop measuring min and max time for millis()
 we can observe the additional cycles consumed by a timer0 interrupt 
 (every 64*256 cycles).  For the UNO, about 98 cycles every 1024us @16MHz.
 The teensy 2 library is a little faster, millis() is inline so 11 cycles.
 timer0 ISR 104 cycles.

---------------------
 pyboard times are for C in firmware
   ISR callback to python (pass) adds 1024 cycles to ISR
   to set a pin in python pin.value(1) takes 1229 cycles   7.3us