quickfixup

--- arch/arm/mach-s5pv210/cpu-freq.c	2011-02-21 14:43:27.253333375 -0600
+++ ../../JPX/Kernel/arch/arm/mach-s5pv210/cpu-freq.c	2011-02-15 04:20:55.893333340 -0600
@@ -524,12 +524,27 @@ static int s5pc110_target(struct cpufreq
 				DBG("MDSvalue = %08x\n", ret);
 				ret = (ret & ~(0x3)) | 0x3;
 				__raw_writel(ret, S5P_ARM_MCS);
+			}
+		} else if (S5PC11X_FREQ_TAB  == 1) { // for 1.2Ghz table
+			if ((prevIndex < 4) && (index >= 4)) {
+				ret = __raw_readl(S5P_ARM_MCS);
+				ret = (ret & ~(0x3)) | 0x3;
+				__raw_writel(ret, S5P_ARM_MCS);
+			}		
 		} else {
 			DBG("\n\nERROR\n\n INVALID DVFS TABLE !!\n");
 			return ret;
 		}
 
+/* TODO */
+#if 0
+		if (S5PC11X_FREQ_TAB) {	
+			if (index <= 2)
+				dvs_set_for_1dot2Ghz(1);
+			else if (index >= 3)
 				dvs_set_for_1dot2Ghz(0);
+		}
+#endif
 
 #ifdef USE_DVS
 #ifdef GPIO_BASED_DVS
@@ -562,10 +577,17 @@ static int s5pc110_target(struct cpufreq
 
 		// ARM MCS value set
 		if (S5PC11X_FREQ_TAB  == 0) { // for 1G table
 				ret = __raw_readl(S5P_ARM_MCS);
 				DBG("MDSvalue = %08x\n", ret);				
 				ret = (ret & ~(0x3)) | 0x1;
 				__raw_writel(ret, S5P_ARM_MCS);
+			}
+		} else if (S5PC11X_FREQ_TAB  == 1) { // for 1.2G table
+			if ((prevIndex >= 4) && (index < 4)) {
+				ret = __raw_readl(S5P_ARM_MCS);
+				ret = (ret & ~(0x3)) | 0x1;
+				__raw_writel(ret, S5P_ARM_MCS);
+			}		
 		} else {
 			DBG("\n\nERROR\n\n INVALID DVFS TABLE !!\n");
 			return ret;
@@ -686,24 +708,35 @@ static int __init s5pc110_cpu_init(struc
 	policy->cur = policy->min = policy->max = s5pc110_getspeed(0);
 	//spin_lock_irqsave(&g_cpufreq_lock, irqflags);
 
+#if USE_1DOT2GHZ
+		S5PC11X_FREQ_TAB = 1;
+		S5PC11X_MAXFREQLEVEL = 5;
+		MAXFREQ_LEVEL_SUPPORTED = 6;
+		g_dvfs_high_lock_limit = 5;
+#else
 		S5PC11X_FREQ_TAB = 0;
 		S5PC11X_MAXFREQLEVEL = 4;
 		MAXFREQ_LEVEL_SUPPORTED = 5;
 		g_dvfs_high_lock_limit = 4;
+#endif
 	
 	printk("S5PC11X_FREQ_TAB=%d , S5PC11X_MAXFREQLEVEL=%d\n",S5PC11X_FREQ_TAB,S5PC11X_MAXFREQLEVEL);
 
 	s5pc11x_cpufreq_level = S5PC11X_MAXFREQLEVEL;
       //spin_unlock_irqrestore(&g_cpufreq_lock, irqflags);
 
+	if (S5PC11X_FREQ_TAB) {	
 		prevIndex = 2;// we are currently at 800MHZ level
+	} else {
+		prevIndex = 1;// we are currently at 800MHZ level
+	}
 
 #ifdef CONFIG_CPU_FREQ_LOG
 	//schedule_delayed_work(&dvfs_info_print_work, 60 * HZ);
 #endif
 	cpufreq_frequency_table_get_attr(s5pc110_freq_table[S5PC11X_FREQ_TAB], policy->cpu);
 
-	policy->cpuinfo.transition_latency = 40000; //40000;	//1us
+	policy->cpuinfo.transition_latency = 80000; //40000;	//1us
 
 #ifdef CONFIG_HAS_WAKELOCK
 //	register_early_suspend(&s5pc11x_freq_suspend);