PSL assertions dumping in waves

[Blebowski]

It would be handy to see PSL assertion state in waves, it improves debugability of PSL assertions.

I would dump each PSL assertion as one record of:

1. PSL assertion state
   • Inactive - When no state of assertion FSM is active
   • Running - When a PSL assertion has an FSM state active that is not the accept state.
   • Covered - For cover assertions when they reach the final state.
   • Failed - For assert assertions in the cycle they fail (when they print the report).
2. Count of "started" times. Incremented when a non-initial state is activated.
3. Count of "failed" times for assert assertions
4. Count of "covered" times for cover assertions.

[Blebowski]

A simplified version would be without counters containing only the assertion state.
Some of this data would be needed though in the VHDL2019 Assert API.

The state could be displayed "as-if" a string with "red" background in the "failed"
state, "green" in the covered state and some other less distinctive colors for other
states. I dont know if this is feasible just via FST, I dont think so...