diff --git a/NetworkModule/Gpio.c b/NetworkModule/Gpio.c
index c39ec3d..056a2b5 100644
--- a/NetworkModule/Gpio.c
+++ b/NetworkModule/Gpio.c
@@ -30,6 +30,7 @@
 #include "gpio.h"
 #include "main.h"
 #include "uipopt.h"
+#include "build_options.h"
 
 extern uint8_t stored_magic4;		// MSB Magic Number stored in EEPROM
 extern uint8_t stored_magic3;		// 
@@ -52,6 +53,10 @@ extern uint8_t stored_pin_control[16];  // Per pin control settings stored in
 volatile struct io_registers io_reg[ NUM_PORTS ]	@0x5000;	// make room for PA .. PG starting at 0x5000
 
 // Define the pair PORT:BIT for each of the 16 I/Os
+#if IO_PIN_ORDER == 1
+// HW-584
+// 5V 16 15 14 13 12 11 10 09 G
+// 5V 08 07 06 05 04 03 02 01 G
 const struct io_mapping io_map[16] = {
 	{ PA, 0x08 },    // PA bit3, IO1
 	{ PA, 0x20 },    // PA bit5, IO2
@@ -70,6 +75,65 @@ const struct io_mapping io_map[16] = {
 	{ PG, 0x01 },    // PG bit0, IO15
 	{ PC, 0x40 }     // PC bit6, IO16
 };
+#endif IO_PIN_ORDER == 1
+
+#if IO_PIN_ORDER == 2
+// HW-584
+// 5V 16 15 14 13 12 11 10 09 G
+// 5V 08 07 06 05 04 03 02 01 G
+//
+// relay:
+// 5V 02 04 06 08 10 12 14 16 G
+// 5V 01 03 05 07 09 11 13 15 G
+//
+const struct io_mapping io_map[16] = {
+	{ PC, 0x80 },    // PC bit7, IO01
+	{ PC, 0x40 },    // PC bit6, IO02
+	{ PG, 0x02 },    // PG bit1, IO03
+	{ PG, 0x01 },    // PG bit0, IO04
+	{ PE, 0x01 },    // PE bit0, IO05
+	{ PE, 0x08 },    // PE bit3, IO06
+	{ PD, 0x04 },    // PD bit2, IO07
+	{ PD, 0x01 },    // PD bit0, IO08
+	{ PD, 0x10 },    // PD bit4, IO09
+	{ PD, 0x08 },    // PD bit3, IO10
+	{ PD, 0x40 },    // PD bit6, IO11
+	{ PD, 0x20 },    // PD bit5, IO12
+	{ PA, 0x20 },    // PA bit5, IO13
+	{ PD, 0x80 },    // PD bit7, IO14
+	{ PA, 0x08 },    // PA bit3, IO15
+	{ PA, 0x10 }     // PA bit4, IO16
+};
+#endif IO_PIN_ORDER == 2
+
+#if IO_PIN_ORDER == 3
+// HW-584
+// 5V 16 15 14 13 12 11 10 09 G
+// 5V 08 07 06 05 04 03 02 01 G
+//
+// relay:
+// 5V 08 07 06 05 04 03 02 01 G
+// -- -- -- -- -- -- -- -- -- -
+//
+const struct io_mapping io_map[16] = {
+	{ PA, 0x10 },    // PA bit4, IO01
+	{ PD, 0x80 },    // PD bit7, IO02
+	{ PD, 0x20 },    // PD bit5, IO03
+	{ PD, 0x08 },    // PD bit3, IO04
+	{ PD, 0x01 },    // PD bit0, IO05
+	{ PE, 0x08 },    // PE bit3, IO06
+	{ PG, 0x01 },    // PG bit0, IO07
+	{ PC, 0x40 },    // PC bit6, IO08
+	{ PA, 0x08 },    // PA bit3, IO09
+	{ PA, 0x20 },    // PA bit5, IO10
+	{ PD, 0x40 },    // PD bit6, IO11
+	{ PD, 0x10 },    // PD bit4, IO12
+	{ PD, 0x04 },    // PD bit2, IO13
+	{ PE, 0x01 },    // PE bit0, IO14
+	{ PG, 0x02 },    // PG bit1, IO15
+	{ PC, 0x80 }     // PC bit7, IO16
+};
+#endif IO_PIN_ORDER == 3
 
 
 void gpio_init(void)
diff --git a/NetworkModule/Main.c b/NetworkModule/Main.c
index 5e17c31..78735b8 100644
--- a/NetworkModule/Main.c
+++ b/NetworkModule/Main.c
@@ -29,6 +29,7 @@
 
 #include <stdlib.h>
 
+#include "build_options.h"
 #include "main.h"
 #include "Enc28j60.h"
 #include "Spi.h"
@@ -4084,7 +4085,7 @@ void check_runtime_changes(void)
     // received.
 
     // Check all pin_control bytes for changes.
-    // ON/OFF state: If an Output pin�s ON/OFF state changes the EEPROM is
+    // ON/OFF state: If an Output pin’s ON/OFF state changes the EEPROM is
     //   updated only if Retain is set, but a restart must not occur.
     //   IMPORTANT: This routine must only change Output pin ON/OFF states.
     //   The read_input_pins() function is the only place where Input pin
diff --git a/NetworkModule/build_options.h b/NetworkModule/build_options.h
new file mode 100644
index 0000000..2e3a1e7
--- /dev/null
+++ b/NetworkModule/build_options.h
@@ -0,0 +1,48 @@
+/*
+ * Build options for Network module firmware
+ *
+ * Author: P-O Yliniemi
+ * Email: peo@yliniemi.se
+ *
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __BUILD_OPTIONS_H__
+#define __BUILD_OPTIONS_H__
+
+// IO pin order, used in gpio.c to set up the io_mapping structure
+//
+// HW-584 silkscreen pin order
+//
+// 5V 16 15 14 13 12 11 10 09 G
+// 5V 08 07 06 05 04 03 02 01 G
+// #define IO_PIN_ORDER	1
+
+//
+// Typical 16 channel board pin order
+//
+// 5V 02 04 06 08 10 12 14 16 G
+// 5V 01 03 05 07 09 11 13 15 G
+//
+#define IO_PIN_ORDER	2
+
+//
+// Pin order for 8 channel relay board when using inner row for relays
+// (use the default pin order if using the outer row)
+// 
+// 5V 08 07 06 05 04 03 02 01 G
+// -- -- -- -- -- -- -- -- -- -
+//
+// #define IO_PIN_ORDER	3
+
+#endif
\ No newline at end of file