Error while add Traffic generator beside CPU core

[amir-khademhosseini]

I am studying bus contention and have added a traffic generator alongside an ARM core in gem5. When I run the configuration with the gem5 built in 'hello' binary, the simulation runs without errors. However, when I replace the 'hello' binary with my own binary, the simulation encounters the following error:

(The binary runs correctly on its own when no traffic generator is present.)

Can any one help me with this error?

gem5 version 24.1.0.0
gem5 compiled Dec 24 2024 12:58:48
gem5 started Dec 27 2024 16:46:44
gem5 executing on arch-pc, pid 263674
command line: build/ARM/gem5.opt prj/gen/core-tr3.py

Global frequency set at 1000000000000 ticks per second
src/base/statistics.hh:279: warn: One of the stats is a legacy stat. Legacy stat is a stat that does not belong to any statistics::Group. Legacy stat is deprecated.
system.remote_gdb: Listening for connections on port 7000
Beginning simulation!
src/sim/simulate.cc:199: info: Entering event queue @ 0.  Starting simulation...
src/sim/syscall_emul.cc:86: warn: ignoring syscall set_robust_list(...)
src/sim/syscall_emul.cc:97: warn: ignoring syscall rseq(...)
      (further warnings will be suppressed)
src/sim/mem_state.cc:448: info: Increasing stack size by one page.
src/sim/syscall_emul.hh:1117: warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
      Returning '/home/amir/repos/gem5n/gem5/prj/src/memR64-s'
src/arch/arm/insts/pseudo.cc:174: warn: 	instruction 'bti' unimplemented
src/arch/arm/faults.cc:783: panic: Attempted to execute unknown instruction (inst 0x09090909)
Memory Usage: 8563208 KBytes
Program aborted at tick 954364000
--- BEGIN LIBC BACKTRACE ---
build/ARM/gem5.opt(_ZN4gem515print_backtraceEv+0x27) [0x556e734b7907]
build/ARM/gem5.opt(_ZN4gem512abortHandlerEi+0x48) [0x556e734dde78]
/usr/lib/libc.so.6(+0x3d1d0) [0x740378c4c1d0]
/usr/lib/libc.so.6(+0x963f4) [0x740378ca53f4]
/usr/lib/libc.so.6(gsignal+0x20) [0x740378c4c120]
/usr/lib/libc.so.6(abort+0xdf) [0x740378c334c3]
build/ARM/gem5.opt(+0x11796ff) [0x556e712126ff]
build/ARM/gem5.opt(_ZN4gem56ArmISA20UndefinedInstruction6invokeEPNS_13ThreadContextERKNS_14RefCountingPtrINS_10StaticInstEEE+0x11d) [0x556e720c167d]
build/ARM/gem5.opt(_ZN4gem513BaseSimpleCPU9advancePCERKSt10shared_ptrINS_9FaultBaseEE+0xae) [0x556e72074d2e]
build/ARM/gem5.opt(_ZN4gem515TimingSimpleCPU11advanceInstERKSt10shared_ptrINS_9FaultBaseEE+0x84) [0x556e7206cb84]
build/ARM/gem5.opt(_ZN4gem515TimingSimpleCPU14completeIfetchEPNS_6PacketE+0x268) [0x556e7206c218]
build/ARM/gem5.opt(_ZN4gem510EventQueue10serviceOneEv+0x145) [0x556e734cdb05]
build/ARM/gem5.opt(_ZN4gem59doSimLoopEPNS_10EventQueueE+0x68) [0x556e734fac18]
build/ARM/gem5.opt(_ZN4gem58simulateEm+0x27b) [0x556e734fb38b]
build/ARM/gem5.opt(+0x36928ec) [0x556e7372b8ec]
build/ARM/gem5.opt(+0x11693b5) [0x556e712023b5]
/usr/lib/libpython3.13.so.1.0(+0x19499c) [0x74037a79499c]
/usr/lib/libpython3.13.so.1.0(+0x24db36) [0x74037a84db36]
/usr/lib/libpython3.13.so.1.0(_PyEval_EvalFrameDefault+0x6064) [0x74037a7771b4]
/usr/lib/libpython3.13.so.1.0(PyEval_EvalCode+0xb5) [0x74037a840ce5]
/usr/lib/libpython3.13.so.1.0(+0x25a444) [0x74037a85a444]
/usr/lib/libpython3.13.so.1.0(+0x18c55d) [0x74037a78c55d]
/usr/lib/libpython3.13.so.1.0(PyObject_Vectorcall+0x5d) [0x74037a760a1d]
/usr/lib/libpython3.13.so.1.0(_PyEval_EvalFrameDefault+0x4a9b) [0x74037a775beb]
build/ARM/gem5.opt(+0x3446bcc) [0x556e734dfbcc]
build/ARM/gem5.opt(main+0x222) [0x556e711ec1a2]
/usr/lib/libc.so.6(+0x25e08) [0x740378c34e08]
/usr/lib/libc.so.6(__libc_start_main+0x8c) [0x740378c34ecc]
build/ARM/gem5.opt(_start+0x25) [0x556e711f2075]
--- END LIBC BACKTRACE ---
For more info on how to address this issue, please visit https://www.gem5.org/documentation/general_docs/common-errors/

Aborted (core dumped)

[powerjg]

I think your binary is not compatible with the configuration of your Arm ISA. The other problem could be that the traffic generator is overwriting the instructions that the CPU is fetching. See this error line:

src/arch/arm/faults.cc:783: panic: Attempted to execute unknown instruction (inst 0x09090909)

[amir-khademhosseini]

Thanks for your response! I think I’ve identified the issue. Initially, I assumed the traffic generator only mimicked read and write commands without actually modifying the memory, but I was mistaken—it does perform actual writes to RAM. This led to unintended modifications of program data and instructions.

To work around this, I doubled the RAM size, loaded my program into one half, and configured the traffic generator to read and write exclusively on the other half. This setup has resolved the interference, but I’ve encountered a new challenge.

My focus is on studying DRAM controller algorithms and bus contention effects in real-time systems, so interactions with the DRAM row buffer (e.g., accessing open rows) are crucial. Do you have any suggestions for:

Configuring the traffic generator to specifically target open rows?
Modifying or using a traffic generator that performs reads and writes without committing the write phase?
I’d greatly appreciate your insights!

[powerjg]

Configuring the traffic generator to specifically target open rows?

This doesn't seem feasible. Even if you could get that information to the traffic gen object, by the time the request made it to the memory (and through the read queue) it's unlikely that the row would still be open.

Modifying or using a traffic generator that performs reads and writes without committing the write phase?

This is feasible, but it's not an option that's available out of the box. You could probably modify the access function on the AbstractMemory object to ignore writes from a certain RequestorId, but it's going to be brittle and hacky.