O3CPU pipeline efficiency issue when executing ARM SME extension (Streaming SVE mode)

[4lex49]

Hi! I am using Gem5 to test the execution efficiency of some matrix operation instructions on O3CPU in ARM SME Extension(Streaming SVE mode). I found that when the CPU executes a set of consecutive fmopa instructions, the instruction commit interval is as long as 7-8 cycles.
According to the trace file, the second and third fmopa instructions stayed at the Rn level for a long time, but in fact there is only WAW hazard. Is this expected?
SME assembly instructions are as follows:

fmopa #0, p1, p0, z0, z5
fmopa #0, p1, p0, z1, z6
fmopa #0, p1, p0, z2, z7

The following is the trace:

[hanm2019]

Hi, @giactra , sorry to bother you, but I’m stuck on something and was hoping you might be able to help! I’d really appreciate any advice, even just a quick pointer in the right direction! Thanks so much in advance!

[giactra]

Hi, there is a known issue in the gem5 SME implementation:

If you check the RELEASE-NOTES: https://github.com/gem5/gem5/blob/stable/RELEASE-NOTES.md

Architectural support for Armv9 Scalable Matrix extension (FEAT_SME). The implementation employs a simple renaming scheme for the Za array register in the O3 CPU, so that writes to difference tiles in the register are considered a dependency and are therefore serialized.

In other words our SME implementation is mainly architectural and does not reflect the microarchitecture of a real SME implementation.

It would be nice if we could implement renaming properly for ZA