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v_ext_macros.h
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// See LICENSE for license details.
#ifndef _RISCV_V_EXT_MACROS_H
#define _RISCV_V_EXT_MACROS_H
#include "vector_unit.h"
//
// vector: masking skip helper
//
#define VI_MASK_VARS \
const int midx = i / 64; \
const int mpos = i % 64;
#define VI_LOOP_ELEMENT_SKIP(BODY) \
VI_MASK_VARS \
if (insn.v_vm() == 0) { \
BODY; \
bool skip = ((P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1) == 0; \
if (skip) { \
continue; \
} \
}
#define VI_ELEMENT_SKIP \
if (i >= vl) { \
continue; \
} else if (i < P.VU.vstart->read()) { \
continue; \
} else { \
VI_LOOP_ELEMENT_SKIP(); \
}
//
// vector: operation and register acccess check helper
//
static inline bool is_overlapped(const int astart, int asize,
const int bstart, int bsize)
{
asize = asize == 0 ? 1 : asize;
bsize = bsize == 0 ? 1 : bsize;
const int aend = astart + asize;
const int bend = bstart + bsize;
return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize;
}
static inline bool is_overlapped_widen(const int astart, int asize,
const int bstart, int bsize)
{
asize = asize == 0 ? 1 : asize;
bsize = bsize == 0 ? 1 : bsize;
const int aend = astart + asize;
const int bend = bstart + bsize;
if (astart < bstart &&
is_overlapped(astart, asize, bstart, bsize) &&
!is_overlapped(astart, asize, bstart + bsize, bsize)) {
return false;
} else {
return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize;
}
}
#define VI_NARROW_CHECK_COMMON \
require_vector(true); \
require(P.VU.vflmul <= 4); \
require(P.VU.vsew * 2 <= P.VU.ELEN); \
require_align(insn.rs2(), P.VU.vflmul * 2); \
require_align(insn.rd(), P.VU.vflmul); \
require_vm; \
#define VI_WIDE_CHECK_COMMON \
require_vector(true); \
require(P.VU.vflmul <= 4); \
require(P.VU.vsew * 2 <= P.VU.ELEN); \
require_align(insn.rd(), P.VU.vflmul * 2); \
require_vm; \
#define VI_CHECK_ST_INDEX(elt_width) \
require_vector(false); \
require(elt_width <= P.VU.ELEN); \
float vemul = ((float)elt_width / P.VU.vsew * P.VU.vflmul); \
require(vemul >= 0.125 && vemul <= 8); \
reg_t UNUSED emul = vemul < 1 ? 1 : vemul; \
reg_t flmul = P.VU.vflmul < 1 ? 1 : P.VU.vflmul; \
require_align(insn.rd(), P.VU.vflmul); \
require_align(insn.rs2(), vemul); \
require((nf * flmul) <= (NVPR / 4) && \
(insn.rd() + nf * flmul) <= NVPR); \
#define VI_CHECK_LD_INDEX(elt_width) \
VI_CHECK_ST_INDEX(elt_width); \
for (reg_t idx = 0; idx < nf; ++idx) { \
reg_t flmul = P.VU.vflmul < 1 ? 1 : P.VU.vflmul; \
reg_t seg_vd = insn.rd() + flmul * idx; \
if (elt_width > P.VU.vsew) { \
if (seg_vd != insn.rs2()) \
require_noover(seg_vd, P.VU.vflmul, insn.rs2(), vemul); \
} else if (elt_width < P.VU.vsew) { \
if (vemul < 1) { \
require_noover(seg_vd, P.VU.vflmul, insn.rs2(), vemul); \
} else { \
require_noover_widen(seg_vd, P.VU.vflmul, insn.rs2(), vemul); \
} \
} \
if (nf >= 2) { \
require_noover(seg_vd, P.VU.vflmul, insn.rs2(), vemul); \
} \
} \
require_vm; \
#define VI_CHECK_MSS(is_vs1) \
if (insn.rd() != insn.rs2()) \
require_noover(insn.rd(), 1, insn.rs2(), P.VU.vflmul); \
require_align(insn.rs2(), P.VU.vflmul); \
if (is_vs1) { \
if (insn.rd() != insn.rs1()) \
require_noover(insn.rd(), 1, insn.rs1(), P.VU.vflmul); \
require_align(insn.rs1(), P.VU.vflmul); \
} \
#define VI_CHECK_SSS(is_vs1) \
require_vm; \
if (P.VU.vflmul > 1) { \
require_align(insn.rd(), P.VU.vflmul); \
require_align(insn.rs2(), P.VU.vflmul); \
if (is_vs1) { \
require_align(insn.rs1(), P.VU.vflmul); \
} \
}
#define VI_CHECK_STORE(elt_width, is_mask_ldst) \
require_vector(false); \
reg_t veew = is_mask_ldst ? 1 : sizeof(elt_width##_t) * 8; \
float vemul = is_mask_ldst ? 1 : ((float)veew / P.VU.vsew * P.VU.vflmul); \
reg_t emul = vemul < 1 ? 1 : vemul; \
require(vemul >= 0.125 && vemul <= 8); \
require_align(insn.rd(), vemul); \
require((nf * emul) <= (NVPR / 4) && \
(insn.rd() + nf * emul) <= NVPR); \
require(veew <= P.VU.ELEN); \
#define VI_CHECK_LOAD(elt_width, is_mask_ldst) \
VI_CHECK_STORE(elt_width, is_mask_ldst); \
require_vm; \
#define VI_CHECK_DSS(is_vs1) \
VI_WIDE_CHECK_COMMON; \
require_align(insn.rs2(), P.VU.vflmul); \
if (P.VU.vflmul < 1) { \
require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs2(), P.VU.vflmul); \
} else { \
require_noover_widen(insn.rd(), P.VU.vflmul * 2, insn.rs2(), P.VU.vflmul); \
} \
if (is_vs1) { \
require_align(insn.rs1(), P.VU.vflmul); \
if (P.VU.vflmul < 1) { \
require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \
} else { \
require_noover_widen(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \
} \
}
#define VI_CHECK_DDS(is_rs) \
VI_WIDE_CHECK_COMMON; \
require_align(insn.rs2(), P.VU.vflmul * 2); \
if (is_rs) { \
require_align(insn.rs1(), P.VU.vflmul); \
if (P.VU.vflmul < 1) { \
require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \
} else { \
require_noover_widen(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \
} \
}
#define VI_CHECK_SDS(is_vs1) \
VI_NARROW_CHECK_COMMON; \
if (insn.rd() != insn.rs2()) \
require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vflmul * 2); \
if (is_vs1) \
require_align(insn.rs1(), P.VU.vflmul); \
#define VI_CHECK_REDUCTION(is_wide) \
require_vector(true); \
if (is_wide) { \
require(P.VU.vsew * 2 <= P.VU.ELEN); \
} \
require_align(insn.rs2(), P.VU.vflmul); \
require(P.VU.vstart->read() == 0); \
#define VI_CHECK_SLIDE(is_over) \
require_align(insn.rs2(), P.VU.vflmul); \
require_align(insn.rd(), P.VU.vflmul); \
require_vm; \
if (is_over) \
require(insn.rd() != insn.rs2()); \
//
// vector: loop header and end helper
//
#define VI_GENERAL_LOOP_BASE \
require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \
require_vector(true); \
reg_t vl = P.VU.vl->read(); \
reg_t UNUSED sew = P.VU.vsew; \
reg_t rd_num = insn.rd(); \
reg_t UNUSED rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) {
#define VI_LOOP_BASE \
VI_GENERAL_LOOP_BASE \
VI_LOOP_ELEMENT_SKIP();
#define VI_LOOP_END_BASE \
}
#define VI_LOOP_END \
VI_LOOP_END_BASE \
P.VU.vstart->write(0);
#define VI_LOOP_REDUCTION_END(x) \
} \
if (vl > 0) { \
vd_0_des = vd_0_res; \
} \
P.VU.vstart->write(0);
#define VI_LOOP_CARRY_BASE \
VI_GENERAL_LOOP_BASE \
VI_MASK_VARS \
auto v0 = P.VU.elt<uint64_t>(0, midx); \
const uint64_t mmask = UINT64_C(1) << mpos; \
const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); \
uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0; \
uint128_t res = 0; \
auto &vd = P.VU.elt<uint64_t>(rd_num, midx, true);
#define VI_LOOP_CARRY_END \
vd = (vd & ~mmask) | (((res) << mpos) & mmask); \
} \
P.VU.vstart->write(0);
#define VI_LOOP_WITH_CARRY_BASE \
VI_GENERAL_LOOP_BASE \
VI_MASK_VARS \
auto &v0 = P.VU.elt<uint64_t>(0, midx); \
const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); \
uint64_t carry = (v0 >> mpos) & 0x1;
#define VI_LOOP_CMP_BASE \
require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \
require_vector(true); \
reg_t vl = P.VU.vl->read(); \
reg_t sew = P.VU.vsew; \
reg_t UNUSED rd_num = insn.rd(); \
reg_t UNUSED rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
VI_LOOP_ELEMENT_SKIP(); \
uint64_t mmask = UINT64_C(1) << mpos; \
uint64_t &vdi = P.VU.elt<uint64_t>(insn.rd(), midx, true); \
uint64_t res = 0;
#define VI_LOOP_CMP_END \
vdi = (vdi & ~mmask) | (((res) << mpos) & mmask); \
} \
P.VU.vstart->write(0);
#define VI_LOOP_MASK(op) \
require(P.VU.vsew <= e64); \
require_vector(true); \
reg_t vl = P.VU.vl->read(); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
int midx = i / 64; \
int mpos = i % 64; \
uint64_t mmask = UINT64_C(1) << mpos; \
uint64_t vs2 = P.VU.elt<uint64_t>(insn.rs2(), midx); \
uint64_t vs1 = P.VU.elt<uint64_t>(insn.rs1(), midx); \
uint64_t &res = P.VU.elt<uint64_t>(insn.rd(), midx, true); \
res = (res & ~mmask) | ((op) & (1ULL << mpos)); \
} \
P.VU.vstart->write(0);
#define VI_LOOP_NSHIFT_BASE \
VI_GENERAL_LOOP_BASE; \
VI_LOOP_ELEMENT_SKIP({ \
require(!(insn.rd() == 0 && P.VU.vflmul > 1)); \
});
#define INT_ROUNDING(result, xrm, gb) \
do { \
const uint64_t lsb = 1UL << (gb); \
const uint64_t lsb_half = lsb >> 1; \
switch (xrm) { \
case VRM::RNU: \
result += lsb_half; \
break; \
case VRM::RNE: \
if ((result & lsb_half) && ((result & (lsb_half - 1)) || (result & lsb))) \
result += lsb; \
break; \
case VRM::RDN: \
break; \
case VRM::ROD: \
if (result & (lsb - 1)) \
result |= lsb; \
break; \
case VRM::INVALID_RM: \
assert(true); \
} \
} while (0)
//
// vector: integer and masking operand access helper
//
#define VXI_PARAMS(x) \
type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
type_sew_t<x>::type vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \
type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)RS1; \
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)insn.v_simm5();
#define VV_U_PARAMS(x) \
type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \
type_usew_t<x>::type vs1 = P.VU.elt<type_usew_t<x>::type>(rs1_num, i); \
type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i);
#define V_U_PARAMS(x) \
type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \
type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i);
#define VX_U_PARAMS(x) \
type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \
type_usew_t<x>::type rs1 = (type_usew_t<x>::type)RS1; \
type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i);
#define VI_U_PARAMS(x) \
type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \
type_usew_t<x>::type UNUSED zimm5 = (type_usew_t<x>::type)insn.v_zimm5(); \
type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i);
#define VV_PARAMS(x) \
type_sew_t<x>::type UNUSED &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
type_sew_t<x>::type vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \
type_sew_t<x>::type UNUSED vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i);
#define VX_PARAMS(x) \
type_sew_t<x>::type UNUSED &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)RS1; \
type_sew_t<x>::type UNUSED vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i);
#define VI_PARAMS(x) \
type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)insn.v_simm5(); \
type_sew_t<x>::type UNUSED vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i);
#define XV_PARAMS(x) \
type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, RS1);
#define VV_SU_PARAMS(x) \
type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
type_usew_t<x>::type vs1 = P.VU.elt<type_usew_t<x>::type>(rs1_num, i); \
type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i);
#define VX_SU_PARAMS(x) \
type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
type_usew_t<x>::type rs1 = (type_usew_t<x>::type)RS1; \
type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i);
#define VV_UCMP_PARAMS(x) \
type_usew_t<x>::type vs1 = P.VU.elt<type_usew_t<x>::type>(rs1_num, i); \
type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i);
#define VX_UCMP_PARAMS(x) \
type_usew_t<x>::type rs1 = (type_usew_t<x>::type)RS1; \
type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i);
#define VI_UCMP_PARAMS(x) \
type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i);
#define VV_CMP_PARAMS(x) \
type_sew_t<x>::type vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \
type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i);
#define VX_CMP_PARAMS(x) \
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)RS1; \
type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i);
#define VI_CMP_PARAMS(x) \
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)insn.v_simm5(); \
type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i);
#define VI_XI_SLIDEDOWN_PARAMS(x, off) \
auto &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i + off);
#define VI_XI_SLIDEUP_PARAMS(x, offset) \
auto &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i - offset);
#define VI_NARROW_PARAMS(sew1, sew2) \
auto &vd = P.VU.elt<type_usew_t<sew1>::type>(rd_num, i, true); \
auto UNUSED vs2_u = P.VU.elt<type_usew_t<sew2>::type>(rs2_num, i); \
auto UNUSED vs2 = P.VU.elt<type_sew_t<sew2>::type>(rs2_num, i); \
auto zimm5 = (type_usew_t<sew1>::type)insn.v_zimm5();
#define VX_NARROW_PARAMS(sew1, sew2) \
auto &vd = P.VU.elt<type_usew_t<sew1>::type>(rd_num, i, true); \
auto UNUSED vs2_u = P.VU.elt<type_usew_t<sew2>::type>(rs2_num, i); \
auto UNUSED vs2 = P.VU.elt<type_sew_t<sew2>::type>(rs2_num, i); \
auto rs1 = (type_sew_t<sew1>::type)RS1;
#define VV_NARROW_PARAMS(sew1, sew2) \
auto &vd = P.VU.elt<type_usew_t<sew1>::type>(rd_num, i, true); \
auto UNUSED vs2_u = P.VU.elt<type_usew_t<sew2>::type>(rs2_num, i); \
auto UNUSED vs2 = P.VU.elt<type_sew_t<sew2>::type>(rs2_num, i); \
auto vs1 = P.VU.elt<type_sew_t<sew1>::type>(rs1_num, i);
#define XI_CARRY_PARAMS(x) \
auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \
auto UNUSED rs1 = (type_sew_t<x>::type)RS1; \
auto UNUSED simm5 = (type_sew_t<x>::type)insn.v_simm5(); \
#define VV_CARRY_PARAMS(x) \
auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \
auto vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \
#define XI_WITH_CARRY_PARAMS(x) \
auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \
auto UNUSED rs1 = (type_sew_t<x>::type)RS1; \
auto UNUSED simm5 = (type_sew_t<x>::type)insn.v_simm5(); \
auto &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true);
#define VV_WITH_CARRY_PARAMS(x) \
auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \
auto vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \
auto &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true);
#define VFP_V_PARAMS(width) \
float##width##_t &vd = P.VU.elt<float##width##_t>(rd_num, i, true); \
float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i);
#define VFP_VV_CMP_PARAMS(width) \
float##width##_t vs1 = P.VU.elt<float##width##_t>(rs1_num, i); \
float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i);
#define VFP_VV_PARAMS(width) \
float##width##_t &vd = P.VU.elt<float##width##_t>(rd_num, i, true); \
VFP_VV_CMP_PARAMS(width)
#define VFP_VF_CMP_PARAMS(width) \
float##width##_t rs1 = f##width(READ_FREG(rs1_num)); \
float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i);
#define VFP_VF_PARAMS(width) \
float##width##_t &vd = P.VU.elt<float##width##_t>(rd_num, i, true); \
VFP_VF_CMP_PARAMS(width)
#define CVT_FP_TO_FP_PARAMS(from_width, to_width) \
auto vs2 = P.VU.elt<float##from_width##_t>(rs2_num, i); \
auto &vd = P.VU.elt<float##to_width##_t>(rd_num, i, true);
#define CVT_INT_TO_FP_PARAMS(from_width, to_width, sign) \
auto vs2 = P.VU.elt<sign##from_width##_t>(rs2_num, i); \
auto &vd = P.VU.elt<float##to_width##_t>(rd_num, i, true);
#define CVT_FP_TO_INT_PARAMS(from_width, to_width, sign) \
auto vs2 = P.VU.elt<float##from_width##_t>(rs2_num, i); \
auto &vd = P.VU.elt<sign##to_width##_t>(rd_num, i, true);
//
// vector: integer and masking operation loop
//
#define INSNS_BASE(PARAMS, BODY) \
if (sew == e8) { \
PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
PARAMS(e64); \
BODY; \
}
// comparison result to masking register
#define VI_LOOP_CMP_BODY(PARAMS, BODY) \
VI_LOOP_CMP_BASE \
INSNS_BASE(PARAMS, BODY) \
VI_LOOP_CMP_END
#define VI_VV_LOOP_CMP(BODY) \
VI_CHECK_MSS(true); \
VI_LOOP_CMP_BODY(VV_CMP_PARAMS, BODY)
#define VI_VX_LOOP_CMP(BODY) \
VI_CHECK_MSS(false); \
VI_LOOP_CMP_BODY(VX_CMP_PARAMS, BODY)
#define VI_VI_LOOP_CMP(BODY) \
VI_CHECK_MSS(false); \
VI_LOOP_CMP_BODY(VI_CMP_PARAMS, BODY)
#define VI_VV_ULOOP_CMP(BODY) \
VI_CHECK_MSS(true); \
VI_LOOP_CMP_BODY(VV_UCMP_PARAMS, BODY)
#define VI_VX_ULOOP_CMP(BODY) \
VI_CHECK_MSS(false); \
VI_LOOP_CMP_BODY(VX_UCMP_PARAMS, BODY)
#define VI_VI_ULOOP_CMP(BODY) \
VI_CHECK_MSS(false); \
VI_LOOP_CMP_BODY(VI_UCMP_PARAMS, BODY)
// merge and copy loop
#define VI_MERGE_VARS \
VI_MASK_VARS \
bool UNUSED use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
#define VI_MERGE_LOOP_BASE \
VI_GENERAL_LOOP_BASE \
VI_MERGE_VARS
#define VI_VV_MERGE_LOOP(BODY) \
VI_CHECK_SSS(true); \
VI_MERGE_LOOP_BASE \
if (sew == e8) { \
VV_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VV_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VV_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VV_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_VX_MERGE_LOOP(BODY) \
VI_CHECK_SSS(false); \
VI_MERGE_LOOP_BASE \
if (sew == e8) { \
VX_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VX_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VX_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VX_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_VI_MERGE_LOOP(BODY) \
VI_CHECK_SSS(false); \
VI_MERGE_LOOP_BASE \
if (sew == e8) { \
VI_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VI_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VI_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VI_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_VF_MERGE_LOOP(BODY) \
VI_CHECK_SSS(false); \
VI_VFP_COMMON \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
VI_MERGE_VARS \
if (P.VU.vsew == e16) { \
VFP_VF_PARAMS(16); \
BODY; \
} else if (P.VU.vsew == e32) { \
VFP_VF_PARAMS(32); \
BODY; \
} else if (P.VU.vsew == e64) { \
VFP_VF_PARAMS(64); \
BODY; \
} \
VI_LOOP_END
// reduction loop - signed
#define VI_LOOP_REDUCTION_BASE(x) \
require(x >= e8 && x <= e64); \
reg_t vl = P.VU.vl->read(); \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \
auto &vd_0_des = P.VU.elt<type_sew_t<x>::type>(rd_num, 0, vl > 0); \
auto vd_0_res = P.VU.elt<type_sew_t<x>::type>(rs1_num, 0); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
VI_LOOP_ELEMENT_SKIP(); \
auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \
#define REDUCTION_LOOP(x, BODY) \
VI_LOOP_REDUCTION_BASE(x) \
BODY; \
VI_LOOP_REDUCTION_END(x)
#define VI_VV_LOOP_REDUCTION(BODY) \
VI_CHECK_REDUCTION(false); \
reg_t sew = P.VU.vsew; \
if (sew == e8) { \
REDUCTION_LOOP(e8, BODY) \
} else if (sew == e16) { \
REDUCTION_LOOP(e16, BODY) \
} else if (sew == e32) { \
REDUCTION_LOOP(e32, BODY) \
} else if (sew == e64) { \
REDUCTION_LOOP(e64, BODY) \
}
// reduction loop - unsigned
#define VI_ULOOP_REDUCTION_BASE(x) \
require(x >= e8 && x <= e64); \
reg_t vl = P.VU.vl->read(); \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \
auto &vd_0_des = P.VU.elt<type_usew_t<x>::type>(rd_num, 0, vl > 0); \
auto vd_0_res = P.VU.elt<type_usew_t<x>::type>(rs1_num, 0); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
VI_LOOP_ELEMENT_SKIP(); \
auto vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i);
#define REDUCTION_ULOOP(x, BODY) \
VI_ULOOP_REDUCTION_BASE(x) \
BODY; \
VI_LOOP_REDUCTION_END(x)
#define VI_VV_ULOOP_REDUCTION(BODY) \
VI_CHECK_REDUCTION(false); \
reg_t sew = P.VU.vsew; \
if (sew == e8) { \
REDUCTION_ULOOP(e8, BODY) \
} else if (sew == e16) { \
REDUCTION_ULOOP(e16, BODY) \
} else if (sew == e32) { \
REDUCTION_ULOOP(e32, BODY) \
} else if (sew == e64) { \
REDUCTION_ULOOP(e64, BODY) \
}
// genearl VXI signed/unsigned loop
#define VI_VV_ULOOP(BODY) \
VI_CHECK_SSS(true) \
VI_LOOP_BASE \
if (sew == e8) { \
VV_U_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VV_U_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VV_U_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VV_U_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_VV_LOOP(BODY) \
VI_CHECK_SSS(true) \
VI_LOOP_BASE \
if (sew == e8) { \
VV_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VV_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VV_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VV_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_V_ULOOP(BODY) \
VI_CHECK_SSS(false) \
VI_LOOP_BASE \
if (sew == e8) { \
V_U_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
V_U_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
V_U_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
V_U_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_VX_ULOOP(BODY) \
VI_CHECK_SSS(false) \
VI_LOOP_BASE \
if (sew == e8) { \
VX_U_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VX_U_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VX_U_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VX_U_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_VX_LOOP(BODY) \
VI_CHECK_SSS(false) \
VI_LOOP_BASE \
if (sew == e8) { \
VX_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VX_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VX_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VX_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_VI_ULOOP(BODY) \
VI_CHECK_SSS(false) \
VI_LOOP_BASE \
if (sew == e8) { \
VI_U_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VI_U_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VI_U_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VI_U_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_VI_LOOP(BODY) \
VI_CHECK_SSS(false) \
VI_LOOP_BASE \
if (sew == e8) { \
VI_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VI_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VI_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VI_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
// signed unsigned operation loop (e.g. mulhsu)
#define VI_VV_SU_LOOP(BODY) \
VI_CHECK_SSS(true) \
VI_LOOP_BASE \
if (sew == e8) { \
VV_SU_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VV_SU_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VV_SU_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VV_SU_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
#define VI_VX_SU_LOOP(BODY) \
VI_CHECK_SSS(false) \
VI_LOOP_BASE \
if (sew == e8) { \
VX_SU_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VX_SU_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VX_SU_PARAMS(e32); \
BODY; \
} else if (sew == e64) { \
VX_SU_PARAMS(e64); \
BODY; \
} \
VI_LOOP_END
// narrow operation loop
#define VI_VV_LOOP_NARROW(BODY) \
VI_CHECK_SDS(true); \
VI_LOOP_BASE \
if (sew == e8) { \
VV_NARROW_PARAMS(e8, e16) \
BODY; \
} else if (sew == e16) { \
VV_NARROW_PARAMS(e16, e32) \
BODY; \
} else if (sew == e32) { \
VV_NARROW_PARAMS(e32, e64) \
BODY; \
} \
VI_LOOP_END
#define VI_VX_LOOP_NARROW(BODY) \
VI_CHECK_SDS(false); \
VI_LOOP_BASE \
if (sew == e8) { \
VX_NARROW_PARAMS(e8, e16) \
BODY; \
} else if (sew == e16) { \
VX_NARROW_PARAMS(e16, e32) \
BODY; \
} else if (sew == e32) { \
VX_NARROW_PARAMS(e32, e64) \
BODY; \
} \
VI_LOOP_END
#define VI_VI_LOOP_NARROW(BODY) \
VI_CHECK_SDS(false); \
VI_LOOP_BASE \
if (sew == e8) { \
VI_NARROW_PARAMS(e8, e16) \
BODY; \
} else if (sew == e16) { \
VI_NARROW_PARAMS(e16, e32) \
BODY; \
} else if (sew == e32) { \
VI_NARROW_PARAMS(e32, e64) \
BODY; \
} \
VI_LOOP_END
#define VI_VI_LOOP_NSHIFT(BODY) \
VI_CHECK_SDS(false); \
VI_LOOP_NSHIFT_BASE \
if (sew == e8) { \
VI_NARROW_PARAMS(e8, e16) \
BODY; \
} else if (sew == e16) { \
VI_NARROW_PARAMS(e16, e32) \
BODY; \
} else if (sew == e32) { \
VI_NARROW_PARAMS(e32, e64) \
BODY; \
} \
VI_LOOP_END
#define VI_VX_LOOP_NSHIFT(BODY) \
VI_CHECK_SDS(false); \
VI_LOOP_NSHIFT_BASE \
if (sew == e8) { \
VX_NARROW_PARAMS(e8, e16) \
BODY; \
} else if (sew == e16) { \
VX_NARROW_PARAMS(e16, e32) \
BODY; \
} else if (sew == e32) { \
VX_NARROW_PARAMS(e32, e64) \
BODY; \
} \
VI_LOOP_END
#define VI_VV_LOOP_NSHIFT(BODY) \
VI_CHECK_SDS(true); \
VI_LOOP_NSHIFT_BASE \
if (sew == e8) { \
VV_NARROW_PARAMS(e8, e16) \
BODY; \
} else if (sew == e16) { \
VV_NARROW_PARAMS(e16, e32) \
BODY; \
} else if (sew == e32) { \
VV_NARROW_PARAMS(e32, e64) \
BODY; \
} \
VI_LOOP_END
// widen operation loop
#define VI_VV_LOOP_WIDEN(BODY) \
VI_LOOP_BASE \
if (sew == e8) { \
VV_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VV_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VV_PARAMS(e32); \
BODY; \
} \
VI_LOOP_END
#define VI_VX_LOOP_WIDEN(BODY) \
VI_LOOP_BASE \
if (sew == e8) { \
VX_PARAMS(e8); \
BODY; \
} else if (sew == e16) { \
VX_PARAMS(e16); \
BODY; \
} else if (sew == e32) { \
VX_PARAMS(e32); \
BODY; \
} \
VI_LOOP_END
#define VI_WIDE_OP_AND_ASSIGN(var0, var1, var2, op0, op1, sign) \
switch (P.VU.vsew) { \
case e8: { \
sign##16_t UNUSED vd_w = P.VU.elt<sign##16_t>(rd_num, i); \
P.VU.elt<uint16_t>(rd_num, i, true) = \
op1((sign##16_t)(sign##8_t)var0 op0 (sign##16_t)(sign##8_t)var1) + var2; \
} \
break; \
case e16: { \
sign##32_t UNUSED vd_w = P.VU.elt<sign##32_t>(rd_num, i); \
P.VU.elt<uint32_t>(rd_num, i, true) = \
op1((sign##32_t)(sign##16_t)var0 op0 (sign##32_t)(sign##16_t)var1) + var2; \
} \
break; \
default: { \
sign##64_t UNUSED vd_w = P.VU.elt<sign##64_t>(rd_num, i); \
P.VU.elt<uint64_t>(rd_num, i, true) = \
op1((sign##64_t)(sign##32_t)var0 op0 (sign##64_t)(sign##32_t)var1) + var2; \
} \
break; \
}
#define VI_WIDE_OP_AND_ASSIGN_MIX(var0, var1, var2, op0, op1, sign_d, sign_1, sign_2) \
switch (P.VU.vsew) { \
case e8: { \
sign_d##16_t UNUSED vd_w = P.VU.elt<sign_d##16_t>(rd_num, i); \
P.VU.elt<uint16_t>(rd_num, i, true) = \
op1((sign_1##16_t)(sign_1##8_t)var0 op0 (sign_2##16_t)(sign_2##8_t)var1) + var2; \
} \
break; \
case e16: { \
sign_d##32_t UNUSED vd_w = P.VU.elt<sign_d##32_t>(rd_num, i); \
P.VU.elt<uint32_t>(rd_num, i, true) = \
op1((sign_1##32_t)(sign_1##16_t)var0 op0 (sign_2##32_t)(sign_2##16_t)var1) + var2; \
} \
break; \
default: { \
sign_d##64_t UNUSED vd_w = P.VU.elt<sign_d##64_t>(rd_num, i); \
P.VU.elt<uint64_t>(rd_num, i, true) = \
op1((sign_1##64_t)(sign_1##32_t)var0 op0 (sign_2##64_t)(sign_2##32_t)var1) + var2; \
} \
break; \
}
#define VI_WIDE_WVX_OP(var0, op0, sign) \
switch (P.VU.vsew) { \
case e8: { \
sign##16_t &vd_w = P.VU.elt<sign##16_t>(rd_num, i, true); \
sign##16_t vs2_w = P.VU.elt<sign##16_t>(rs2_num, i); \
vd_w = vs2_w op0 (sign##16_t)(sign##8_t)var0; \
} \