From 5524fb54bab115c7428efc9c978eebd5c006e257 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Thu, 22 Feb 2024 03:36:16 +0500 Subject: [PATCH 1/3] Coverpoints for lr-sc added for 32 and 64 bit architecture --- coverage/rv_lr_sc_64.cgf | 211 ++++++++++++++++++++++++++++++++++++++ coverage/rvi_lr_sc_32.cgf | 211 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 422 insertions(+) create mode 100644 coverage/rv_lr_sc_64.cgf create mode 100644 coverage/rvi_lr_sc_32.cgf diff --git a/coverage/rv_lr_sc_64.cgf b/coverage/rv_lr_sc_64.cgf new file mode 100644 index 000000000..40a24d24d --- /dev/null +++ b/coverage/rv_lr_sc_64.cgf @@ -0,0 +1,211 @@ +#For lr-sc-01.S +lr-sc-01: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq != 0x1": 0 #no aq flag used + "mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used + val_comb: + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val: 0 + mnemonic == 'sc.d' and rs2_val == get_mem_val(rs1_val, 8) and rd_val == 0: 0 + +#For lr-sc-fail-01.S +lr-sc-fail-01: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq != 0x1": 0 #no aq flag used + "mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used + val_comb: + #reservation successfull + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val: 0 + #rd -> non-zero on sc + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs1_val and rd_val!=0: 0 + +#For lr-sc-fail-02.S +lr-sc-fail-02: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq != 0x1": 0 #no aq flag used + "mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #rd -> 1 on sc -- it should hit 8 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs2_val and rd_val!=0: 0 + +#For lr-sc-sw.S +lr-sc-sw: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + sw: 0 + op_comb: + "mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used + val_comb: + #reservation successfull - it should hit 2 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #check store word successfull? imm_val is zero. + mnemonic == 'sw' and get_mem_val(rs1_val, 8) == rs2_val : 0 + #rd -> 0 on sc -- it should hit 2 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0 + +#For lr-aq-sc-01.S +lr-aq-sc-01: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.d' and rl != 0x1": 0 #no rl flag used + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #rd -> 0 on sc -- it should hit 4 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0 + +#For lr-aq-sc-rl-01.S +lr-aq-sc-rl-01: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #rd -> 0 on sc -- it should hit 4 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0 + +#For lr-sc-constrained-loop-01.S +lr-sc-constrained-loop-01: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 1 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #rd -> 0 on sc -- it should hit 1 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0 + +#For lr-sc-constrained-loop-02.S +lr-sc-constrained-loop-02: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and rs1 == 'x31' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.d' and rs1 == 'x26' and rl == 0x1": 0 #rl flag used for some other register + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #rd -> 1 on sc -- it should hit 4 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs2_val and rd_val!=0: 0 + +#For lr-sc-constrained-loop-03.S +lr-sc-constrained-loop-03: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 1 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #rd -> 1 on sc -- it should hit 1 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0 + +#For lr-sc-constrained-loop-04.S +lr-sc-constrained-loop-04: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 1 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #rd -> 1 on sc -- it should hit 4 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs2_val and rd_val!=0: 0 + +#For lr-sc-unconstrained-loop-01.S +lr-sc-unconstrained-loop-01: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 2 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #rd -> 0 on sc -- it should hit 2 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0 + +#For lr-sc-rl-01.S +lr-sc-rl-01: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq == 0x0": 0 #no aq flag used + "mnemonic == 'sc.d' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) == rd_val : 0 + #rd -> 0 on sc -- it should hit 4 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) == rs2_val and rd_val==0: 0 + +#For lr-sc-misaligned-01.S +lr-sc-misaligned-01: + config: + - check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.d: 0 + sc.d: 0 + op_comb: + "mnemonic == 'lr.d' and aq == 0x0": 0 #no aq flag used + "mnemonic == 'sc.d' and rl == 0x0": 0 #no rl flag used + csr_comb: + #misaligned store/amo fault -- it should hit 3 times + mcause == 0x06: 0 + val_comb: + #reservation failed - it should hit 3 times + mnemonic == 'lr.d' and get_mem_val(rs1_val, 8) != rd_val : 0 + #rd -> 1 on sc -- it should hit 3 times + mnemonic == 'sc.d' and get_mem_val(rs1_val, 8) != rs2_val and rd_val!=0: 0 diff --git a/coverage/rvi_lr_sc_32.cgf b/coverage/rvi_lr_sc_32.cgf new file mode 100644 index 000000000..11e37aa23 --- /dev/null +++ b/coverage/rvi_lr_sc_32.cgf @@ -0,0 +1,211 @@ +#For lr-sc-01.S +lr-sc-01: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq != 0x1": 0 #no aq flag used + "mnemonic == 'sc.w' and rl != 0x1": 0 #no rl flag used + val_comb: + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val: 0 + mnemonic == 'sc.w' and rs2_val == get_mem_val(rs1_val, 4) and rd_val == 0: 0 + +#For lr-sc-fail-01.S +lr-sc-fail-01: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq != 0x1": 0 #no aq flag used + "mnemonic == 'sc.w' and rl != 0x1": 0 #no rl flag used + val_comb: + #reservation successfull + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val: 0 + #rd -> non-zero on sc + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) != rs1_val and rd_val!=0: 0 + +#For lr-sc-fail-02.S +lr-sc-fail-02: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq != 0x1": 0 #no aq flag used + "mnemonic == 'sc.w' and rl != 0x1": 0 #no rl flag used + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #rd -> 1 on sc -- it should hit 8 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) != rs2_val and rd_val!=0: 0 + +#For lr-sc-sw.S +lr-sc-sw: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + sw: 0 + op_comb: + "mnemonic == 'lr.w' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.w' and rl != 0x1": 0 #no rl flag used + val_comb: + #reservation successfull - it should hit 2 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #check store word successfull? imm_val is zero. + mnemonic == 'sw' and get_mem_val(rs1_val, 4) == rs2_val : 0 + #rd -> 0 on sc -- it should hit 2 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) == rs2_val and rd_val==0: 0 + +#For lr-aq-sc-01.S +lr-aq-sc-01: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.w' and rl != 0x1": 0 #no rl flag used + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #rd -> 0 on sc -- it should hit 4 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) == rs2_val and rd_val==0: 0 + +#For lr-aq-sc-rl-01.S +lr-aq-sc-rl-01: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.w' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #rd -> 0 on sc -- it should hit 4 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) == rs2_val and rd_val==0: 0 + +#For lr-sc-constrained-loop-01.S +lr-sc-constrained-loop-01: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.w' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 1 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #rd -> 0 on sc -- it should hit 1 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) == rs2_val and rd_val==0: 0 + +#For lr-sc-constrained-loop-02.S +lr-sc-constrained-loop-02: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and rs1 == 'x31' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.w' and rs1 == 'x26' and rl == 0x1": 0 #rl flag used for some other register + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #rd -> 1 on sc -- it should hit 4 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) != rs2_val and rd_val!=0: 0 + +#For lr-sc-constrained-loop-03.S +lr-sc-constrained-loop-03: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.w' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 1 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #rd -> 1 on sc -- it should hit 1 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) == rs2_val and rd_val==0: 0 + +#For lr-sc-constrained-loop-04.S +lr-sc-constrained-loop-04: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.w' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 1 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #rd -> 1 on sc -- it should hit 4 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) != rs2_val and rd_val!=0: 0 + +#For lr-sc-unconstrained-loop-01.S +lr-sc-unconstrained-loop-01: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq == 0x1": 0 #aq flag used + "mnemonic == 'sc.w' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 2 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #rd -> 0 on sc -- it should hit 2 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) == rs2_val and rd_val==0: 0 + +#For lr-sc-rl-01.S +lr-sc-rl-01: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq == 0x0": 0 #no aq flag used + "mnemonic == 'sc.w' and rl == 0x1": 0 #rl flag used + val_comb: + #reservation successfull - it should hit 4 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) == rd_val : 0 + #rd -> 0 on sc -- it should hit 4 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) == rs2_val and rd_val==0: 0 + +#For lr-sc-misaligned-01.S +lr-sc-misaligned-01: + config: + - check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + lr.w: 0 + sc.w: 0 + op_comb: + "mnemonic == 'lr.w' and aq == 0x0": 0 #no aq flag used + "mnemonic == 'sc.w' and rl == 0x0": 0 #no rl flag used + csr_comb: + #misaligned store/amo fault -- it should hit 3 times + mcause == 0x06: 0 + val_comb: + #reservation failed - it should hit 3 times + mnemonic == 'lr.w' and get_mem_val(rs1_val, 4) != rd_val : 0 + #rd -> 1 on sc -- it should hit 3 times + mnemonic == 'sc.w' and get_mem_val(rs1_val, 4) != rs2_val and rd_val!=0: 0 \ No newline at end of file From 27a9cc4367104f1883962f1d84ef421ec5e90c50 Mon Sep 17 00:00:00 2001 From: Muhammad Maarij Zeeshan Date: Thu, 22 Feb 2024 08:56:57 +0500 Subject: [PATCH 2/3] Added tests for LR/SC instructions of A extension for RV32 and RV64 --- riscv-test-suite/rv32i_m/A/src/lr-aq-sc-01.S | 105 ++++++++++++++ .../rv32i_m/A/src/lr-aq-sc-rl-01.S | 105 ++++++++++++++ riscv-test-suite/rv32i_m/A/src/lr-sc-01.S | 105 ++++++++++++++ .../rv32i_m/A/src/lr-sc-constrained-loop-01.S | 95 ++++++++++++ .../rv32i_m/A/src/lr-sc-constrained-loop-02.S | 98 +++++++++++++ .../rv32i_m/A/src/lr-sc-constrained-loop-03.S | 122 ++++++++++++++++ .../rv32i_m/A/src/lr-sc-constrained-loop-04.S | 117 +++++++++++++++ .../rv32i_m/A/src/lr-sc-fail-01.S | 113 +++++++++++++++ .../rv32i_m/A/src/lr-sc-fail-02.S | 114 +++++++++++++++ .../rv32i_m/A/src/lr-sc-misaligned-01.S | 104 ++++++++++++++ riscv-test-suite/rv32i_m/A/src/lr-sc-rl-01.S | 104 ++++++++++++++ riscv-test-suite/rv32i_m/A/src/lr-sc-sw.S | 96 +++++++++++++ .../A/src/lr-sc-unconstrained-loop-01.S | 113 +++++++++++++++ riscv-test-suite/rv64i_m/A/src/lr-aq-sc-01.S | 105 ++++++++++++++ .../rv64i_m/A/src/lr-aq-sc-rl-01.S | 105 ++++++++++++++ riscv-test-suite/rv64i_m/A/src/lr-sc-01.S | 105 ++++++++++++++ .../rv64i_m/A/src/lr-sc-constrained-loop-01.S | 95 ++++++++++++ .../rv64i_m/A/src/lr-sc-constrained-loop-02.S | 98 +++++++++++++ .../rv64i_m/A/src/lr-sc-constrained-loop-03.S | 122 ++++++++++++++++ .../rv64i_m/A/src/lr-sc-constrained-loop-04.S | 117 +++++++++++++++ .../rv64i_m/A/src/lr-sc-fail-01.S | 113 +++++++++++++++ .../rv64i_m/A/src/lr-sc-fail-02.S | 116 +++++++++++++++ .../rv64i_m/A/src/lr-sc-misaligned-01.S | 136 ++++++++++++++++++ riscv-test-suite/rv64i_m/A/src/lr-sc-rl-01.S | 104 ++++++++++++++ riscv-test-suite/rv64i_m/A/src/lr-sc-sw.S | 96 +++++++++++++ .../A/src/lr-sc-unconstrained-loop-01.S | 113 +++++++++++++++ 26 files changed, 2816 insertions(+) create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-aq-sc-01.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-aq-sc-rl-01.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-01.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-01.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-02.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-03.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-04.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-fail-01.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-fail-02.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-misaligned-01.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-rl-01.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-sw.S create mode 100644 riscv-test-suite/rv32i_m/A/src/lr-sc-unconstrained-loop-01.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-aq-sc-01.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-aq-sc-rl-01.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-01.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-01.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-02.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-03.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-04.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-fail-01.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-fail-02.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-misaligned-01.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-rl-01.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-sw.S create mode 100644 riscv-test-suite/rv64i_m/A/src/lr-sc-unconstrained-loop-01.S diff --git a/riscv-test-suite/rv32i_m/A/src/lr-aq-sc-01.S b/riscv-test-suite/rv32i_m/A/src/lr-aq-sc-01.S new file mode 100644 index 000000000..11665e70a --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-aq-sc-01.S @@ -0,0 +1,105 @@ +// +// This assembly file tests the lr.r.aq and sc.w instruction of the RISC-V RV32A extension for the lr-aq-sc covergroup. +// This test first acquires access through load reserve and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-aq-sc) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +lr.w.aq x30, (x31) # Load reserve and acquire the rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional on the same address + +inst_1: +addi x31, x31, 4 # Add 4 to go to next address +lr.w.aq x30, (x31) # Load reserve and acquire the rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional on the same address + +inst_2: +addi x31, x31, 4 # Add 4 to go to next address +lr.w.aq x30, (x31) # Load reserve and acquire the rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional on the same address + +inst_3: +addi x31, x31, 4 # Add 4 to go to next address +lr.w.aq x30, (x31) # Load reserve and acquire the rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional on the same address + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-aq-sc-rl-01.S b/riscv-test-suite/rv32i_m/A/src/lr-aq-sc-rl-01.S new file mode 100644 index 000000000..f1fd2fc25 --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-aq-sc-rl-01.S @@ -0,0 +1,105 @@ +// +// This assembly file tests the lr.r.aq and sc.w.rl instruction of the RISC-V RV32A extension for the lr-aq-sc-rl covergroup. +// This test first acquires access through load reserve and then it store reserve to the same reservation set and releases the access. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-aq-sc-rl) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +lr.w.aq x30, (x31) # Load reserve and aquire the rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_1: +addi x31, x31, 4 # Add 4 to go to next address +lr.w.aq x30, (x31) # Load reserve and aquire the rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_2: +addi x31, x31, 4 # Add 4 to go to next address +lr.w.aq x30, (x31) # Load reserve and aquire the rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_3: +addi x31, x31, 4 # Add 4 to go to next address +lr.w.aq x30, (x31) # Load reserve and aquire the rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release on the same address + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-01.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-01.S new file mode 100644 index 000000000..e0a9fe5fe --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-01.S @@ -0,0 +1,105 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-aq-sc covergroup. +// This test first does the load reserve and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +lr.w x30, (x31) # Load reserve the rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional on the same address + +inst_1: +addi x31, x31, 4 # Add 4 to go to next address +lr.w x30, (x31) # Load reserve the rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional on the same address + +inst_2: +addi x31, x31, 4 # Add 4 to go to next address +lr.w x30, (x31) # Load reserve the rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional on the same address + +inst_3: +addi x31, x31, 4 # Add 4 to go to next address +lr.w x30, (x31) # Load reserve the rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional on the same address + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-01.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-01.S new file mode 100644 index 000000000..91a034130 --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-01.S @@ -0,0 +1,95 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-sc-constrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs only I type instructions and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-constrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) +LI (x27, 0x4) + +inst_0: +beqz x27, stop_retry # If 4 retries have reached zero stop retrying +lr.w.aq x30, (x31) # Load reserve and acquire from rvtest_data +li x28, 0x0000FFFF # Mask the read data +and x30, x30, x28 +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-02.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-02.S new file mode 100644 index 000000000..a2f3b920d --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-02.S @@ -0,0 +1,98 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-sc-constrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs a sc to another address and then it store reserve to the reservation set, the store reserve fails and is retried 4 times and keeps on failing. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-constrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + + +LA (x31, rvtest_data) # Load address of rvtest_data in x31 +LA (x26, rvtest_data) # Load address of rvtest_data in x26 +addi x26, x26, 4 # Add 4 to address of rvtest_data +LI (x27, 0x4) # Load 4 in x27 for retries + +inst_0: +beqz x27, stop_retry # If 4 retries have reached zero stop retrying +lr.w.aq x30, (x31) # Load reserve and acquire from rvtest_data +li x28, 0x0000FFFF # Mask the read data +and x30, x30, x28 +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x26) # Store conditional and release to rvtest_data + 4 +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-03.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-03.S new file mode 100644 index 000000000..e75898ab6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-03.S @@ -0,0 +1,122 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-sc-constrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs 16 or less instructions and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-constrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data +LI (x27, 0x4) # Load 4 in x27 for retries + +inst_0: +beqz x27, stop_retry # If 4 retries have reached zero stop retrying +lr.w.aq x30, (x31) # Load reserve and acquire from rvtest_data + +# More than 16 instructions for LR/SC loop to fail + +li x28, 0x0000FFFF +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +li x30, 0 # Load zero to verify the changed value + +sc.w.rl x29, x30, (x31) # Store conditional and release to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-04.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-04.S new file mode 100644 index 000000000..809145814 --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-constrained-loop-04.S @@ -0,0 +1,117 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-sc-constrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs more than 16 instructions and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-constrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data +LI (x27, 0x4) # Load 4 in x27 for retries + +inst_0: +beqz x27, stop_retry # If 4 retries have reached zero stop retrying +lr.w.aq x30, (x31) # Load reserve and acquire from rvtest_data + +# More than 16 instructions for LR/SC loop to fail + +li x28, 0x0000FFFF +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +li x30, 0 # Load zero to verify the changed value + +sc.w.rl x29, x30, (x31) # Store conditional and release to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-fail-01.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-fail-01.S new file mode 100644 index 000000000..cf24a704e --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-fail-01.S @@ -0,0 +1,113 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-sc-fail covergroup. +// This test first does the load reserve and then it store reserve to the different reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-fail) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data in x31 +LA (x28, rvtest_data) # Load address of rvtest_data in x28 +addi x28, x28, 16 # Add 16 to address of rvtest_data + + +inst_0: +lr.w x30, (x31) # Load reserve from rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x28) # Store Conditional to rvtest_data + 16 + +inst_1: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.w x30, (x31) # Load reserve from rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x28) # Store Conditional to rvtest_data + 20 + + +inst_2: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.w x30, (x31) # Load reserve from rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x28) # Store Conditional to rvtest_data + 24 + + +inst_3: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.w x30, (x31) # Load reserve from rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x28) # Store Conditional to rvtest_data + 28 + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-fail-02.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-fail-02.S new file mode 100644 index 000000000..7c57ed4d3 --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-fail-02.S @@ -0,0 +1,114 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-sc-fail covergroup. +// This test first does the load reserve and before the store reserve to the reservation set it does another sc to a different address and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-fail) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data in x31 +LA (x28, rvtest_data) # Load address of rvtest_data in x28 +addi x28, x28, 16 # Add 16 to address of rvtest_data + +inst_0: +lr.w x30, (x31) # Load Reserve from rvtest_data +sc.w x29, x30, (x28) # Store Condtional to rvtest_data + 16 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store Conditional to rvtest_data + +inst_1: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.w x30, (x31) # Load reserve from rvtest_data + 4 +sc.w x29, x30, (x28) # Store Conditional to rvtest_data + 20 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store Conditional to rvtest_data + 4 + +inst_2: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.w x30, (x31) # Load reserve from rvtest_data + 8 +sc.w x29, x30, (x28) # Store Conditional to rvtest_data + 24 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store Conditional to rvtest_data + 8 + +inst_3: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.w x30, (x31) # Load reserve from rvtest_data + 12 +sc.w x29, x30, (x28) # Store Conditional to rvtest_data + 28 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store Conditional to rvtest_data + 12 + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-misaligned-01.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-misaligned-01.S new file mode 100644 index 000000000..831fe5b40 --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-misaligned-01.S @@ -0,0 +1,104 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-sc-misaligned covergroup. +//This test first does the load reserve and then it store reserve to the same reservation set, the address of the reservation set is misaligned by 1, 2 and 3 bytes. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-misaligned) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +addi x31, x31, 1 # Add 1 to rvtest_data +lr.w x30, (x31) # Load reserve rvtest_data by misaligned 1 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional to rvtest_data by misaligned 1 + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_1: +addi x31, x31, 2 # Add 2 to rvtest_data +lr.w x30, (x31) # Load reserve rvtest_data by misaligned 2 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional to rvtest_data by misaligned 2 + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_2: +addi x31, x31, 3 # Add 3 to rvtest_data +lr.w x30, (x31) # Load reserve rvtest_data by misaligned 3 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional to rvtest_data by misaligned 3 + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-rl-01.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-rl-01.S new file mode 100644 index 000000000..a7fb40fa4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-rl-01.S @@ -0,0 +1,104 @@ +// +// This assembly file tests the lr.r and sc.w.rl instruction of the RISC-V RV32A extension for the lr-sc-rl covergroup. +// This test first does the load reserve and then it store reserve to the same reservation set and releases the access. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-rl) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +lr.w x30, (x31) # Load reserve the rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_1: +addi x31, x31, 4 # Add 4 to go to next address +lr.w x30, (x31) # Load reserve the rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_2: +addi x31, x31, 4 # Add 4 to go to next address +lr.w x30, (x31) # Load reserve the rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_3: +addi x31, x31, 4 # Add 4 to go to next address +lr.w x30, (x31) # Load reserve the rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release on the same address +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-sw.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-sw.S new file mode 100644 index 000000000..143e68076 --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-sw.S @@ -0,0 +1,96 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-sc-fail covergroup. +// This test first acquires access through load reserve and before the store reserve to the reservation set it does another sw to the same address and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-sw) + +RVTEST_SIGBASE(x8,signature_x8) + +LA (x31, rvtest_data) # Load address of rvtest_data in 31 +addi x28, x31, 4 # Load address of rvtest_data + 4 in x28 +LI (x5, 0) # Initializing x5 with zero + +inst_0: +lr.w.aq x30, (x31) # Load reserve and acquire from rvtest_data +sw x5, (x31) # Store word to rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional to same address + +inst_1: +lr.w.aq x30, (x31) # Load reserve and acquire from rvtest_data +sw x30, (x28) # Store word to rvtest_data + 4 +li x5, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional to same address + + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +# signature_x1_0: +# .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +# signature_x1_1: +# .fill 50*((XLEN/8)/4),4,0xdeadbeef + +signature_x8: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/A/src/lr-sc-unconstrained-loop-01.S b/riscv-test-suite/rv32i_m/A/src/lr-sc-unconstrained-loop-01.S new file mode 100644 index 000000000..d98f178e4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/A/src/lr-sc-unconstrained-loop-01.S @@ -0,0 +1,113 @@ +// +// This assembly file tests the lr.r and sc.w instruction of the RISC-V RV32A extension for the lr-sc-unconstrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs only I type instructions and then it store reserve to the same reservation set. After that another LR/SC sequence is performed outside of the constrained loop. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-unconstrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data +LI (x27, 0x4) # Load 4 in x27 for retries + +inst_0: +beqz x27, stop_retry_inst_0 # If 4 retries have reached zero stop retrying +lr.w.aq x30, (x31) # Load reserve and acquire from rvtest_data +li x28, 0x0000FFFF # Mask the read data +and x30, x30, x28 +li x30, 0 # Load zero to verify the changed value +sc.w.rl x29, x30, (x31) # Store conditional and release to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry_inst_0: + +LA (x31, rvtest_data) # Load address of rvtest_data +addi x31, x31, 4 # Add 4 to go to next address +LI (x27, 0x4) # Load 4 in x27 for retries + +# LR/SC out of loop + +inst_1: +beqz x27, stop_retry_inst_1 # If 4 retries have reached zero stop retrying +lr.w x30, (x31) # Load reserve from rvtest_data +li x28, 0x0000FFFF # Mask the read data +and x30, x30, x28 +li x30, 0 # Load zero to verify the changed value +sc.w x29, x30, (x31) # Store conditional to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_1 # Check if store conditional passed otherwise retry + +stop_retry_inst_1: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-aq-sc-01.S b/riscv-test-suite/rv64i_m/A/src/lr-aq-sc-01.S new file mode 100644 index 000000000..10eb4e161 --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-aq-sc-01.S @@ -0,0 +1,105 @@ +// +// This assembly file tests the lr.r.aq and sc.d instruction of the RISC-V RV64A extension for the lr-aq-sc covergroup. +// This test first acquires access through load reserve and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-aq-sc) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +lr.d.aq x30, (x31) # Load reserve and acquire the rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional on the same address + +inst_1: +addi x31, x31, 4 # Add 4 to go to next address +lr.d.aq x30, (x31) # Load reserve and acquire the rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional on the same address + +inst_2: +addi x31, x31, 4 # Add 4 to go to next address +lr.d.aq x30, (x31) # Load reserve and acquire the rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional on the same address + +inst_3: +addi x31, x31, 4 # Add 4 to go to next address +lr.d.aq x30, (x31) # Load reserve and acquire the rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional on the same address + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-aq-sc-rl-01.S b/riscv-test-suite/rv64i_m/A/src/lr-aq-sc-rl-01.S new file mode 100644 index 000000000..d5240adfe --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-aq-sc-rl-01.S @@ -0,0 +1,105 @@ +// +// This assembly file tests the lr.r.aq and sc.d.rl instruction of the RISC-V RV64A extension for the lr-aq-sc-rl covergroup. +// This test first acquires access through load reserve and then it store reserve to the same reservation set and releases the access. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-aq-sc-rl) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +lr.d.aq x30, (x31) # Load reserve and aquire the rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_1: +addi x31, x31, 4 # Add 4 to go to next address +lr.d.aq x30, (x31) # Load reserve and aquire the rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_2: +addi x31, x31, 4 # Add 4 to go to next address +lr.d.aq x30, (x31) # Load reserve and aquire the rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_3: +addi x31, x31, 4 # Add 4 to go to next address +lr.d.aq x30, (x31) # Load reserve and aquire the rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release on the same address + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-01.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-01.S new file mode 100644 index 000000000..f5ad17bdb --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-01.S @@ -0,0 +1,105 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV64A extension for the lr-aq-sc covergroup. +// This test first does the load reserve and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +lr.d x30, (x31) # Load reserve the rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional on the same address + +inst_1: +addi x31, x31, 4 # Add 4 to go to next address +lr.d x30, (x31) # Load reserve the rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional on the same address + +inst_2: +addi x31, x31, 4 # Add 4 to go to next address +lr.d x30, (x31) # Load reserve the rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional on the same address + +inst_3: +addi x31, x31, 4 # Add 4 to go to next address +lr.d x30, (x31) # Load reserve the rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional on the same address + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-01.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-01.S new file mode 100644 index 000000000..3d98ea50c --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-01.S @@ -0,0 +1,95 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV64A extension for the lr-sc-constrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs only I type instructions and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-constrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) +LI (x27, 0x4) + +inst_0: +beqz x27, stop_retry # If 4 retries have reached zero stop retrying +lr.d.aq x30, (x31) # Load reserve and acquire from rvtest_data +li x28, 0x0000FFFF # Mask the read data +and x30, x30, x28 +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-02.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-02.S new file mode 100644 index 000000000..f88dce362 --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-02.S @@ -0,0 +1,98 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV64A extension for the lr-sc-constrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs a sc to another address and then it store reserve to the reservation set, the store reserve fails and is retried 4 times and keeps on failing. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-constrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + + +LA (x31, rvtest_data) # Load address of rvtest_data in x31 +LA (x26, rvtest_data) # Load address of rvtest_data in x26 +addi x28, x28, 4 # Add 4 to address of rvtest_data +LI (x27, 0x4) # Load 4 in x27 for retries + +inst_0: +beqz x27, stop_retry # If 4 retries have reached zero stop retrying +lr.d.aq x30, (x31) # Load reserve and acquire from rvtest_data +li x28, 0x0000FFFF # Mask the read data +and x30, x30, x28 +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x26) # Store conditional and release to rvtest_data + 4 +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-03.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-03.S new file mode 100644 index 000000000..a196b8ccb --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-03.S @@ -0,0 +1,122 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV64A extension for the lr-sc-constrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs 16 or less instructions and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-constrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data +LI (x27, 0x4) # Load 4 in x27 for retries + +inst_0: +beqz x27, stop_retry # If 4 retries have reached zero stop retrying +lr.d.aq x30, (x31) # Load reserve and acquire from rvtest_data + +# More than 16 instructions for LR/SC loop to fail + +li x28, 0x0000FFFF +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +li x30, 0 # Load zero to verify the changed value + +sc.d.rl x29, x30, (x31) # Store conditional and release to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-04.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-04.S new file mode 100644 index 000000000..d5c182577 --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-constrained-loop-04.S @@ -0,0 +1,117 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV32A extension for the lr-sc-constrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs more than 16 instructions and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-constrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data +LI (x27, 0x4) # Load 4 in x27 for retries + +inst_0: +beqz x27, stop_retry # If 4 retries have reached zero stop retrying +lr.d.aq x30, (x31) # Load reserve and acquire from rvtest_data + +# More than 16 instructions for LR/SC loop to fail + +li x28, 0x0000FFFF +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 +and x30, x30, x28 + +li x30, 0 # Load zero to verify the changed value + +sc.d.rl x29, x30, (x31) # Store conditional and release to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-fail-01.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-fail-01.S new file mode 100644 index 000000000..d7d78d3ed --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-fail-01.S @@ -0,0 +1,113 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV64A extension for the lr-sc-fail covergroup. +// This test first does the load reserve and then it store reserve to the different reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-fail) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data in x31 +LA (x28, rvtest_data) # Load address of rvtest_data in x28 +addi x28, x28, 16 # Add 16 to address of rvtest_data + + +inst_0: +lr.d x30, (x31) # Load reserve from rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x28) # Store Conditional to rvtest_data + 16 + +inst_1: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.d x30, (x31) # Load reserve from rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x28) # Store Conditional to rvtest_data + 20 + + +inst_2: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.d x30, (x31) # Load reserve from rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x28) # Store Conditional to rvtest_data + 24 + + +inst_3: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.d x30, (x31) # Load reserve from rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x28) # Store Conditional to rvtest_data + 28 + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-fail-02.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-fail-02.S new file mode 100644 index 000000000..6000077bf --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-fail-02.S @@ -0,0 +1,116 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV64A extension for the lr-sc-fail covergroup. +// This test first does the load reserve and before the store reserve to the reservation set it does another sc to a different address and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-fail) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data in x31 +LA (x28, rvtest_data) # Load address of rvtest_data in x28 +addi x28, x28, 16 # Add 16 to address of rvtest_data + +inst_0: +lr.d x30, (x31) # Load Reserve from rvtest_data +sc.d x29, x30, (x28) # Store Condtional to rvtest_data + 16 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store Conditional to rvtest_data + +inst_1: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.d x30, (x31) # Load reserve from rvtest_data + 4 +sc.d x29, x30, (x28) # Store Conditional to rvtest_data + 20 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store Conditional to rvtest_data + 4 + +inst_2: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.d x30, (x31) # Load reserve from rvtest_data + 8 +sc.d x29, x30, (x28) # Store Conditional to rvtest_data + 24 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store Conditional to rvtest_data + 8 + +inst_3: +addi x31, x31, 4 # Add 4 to rvtest_data in x31 +addi x28, x28, 4 # Add 4 to rvtest_data in x28 +lr.d x30, (x31) # Load reserve from rvtest_data + 12 +sc.d x29, x30, (x28) # Store Conditional to rvtest_data + 28 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store Conditional to rvtest_data + 12 + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.align 4 + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-misaligned-01.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-misaligned-01.S new file mode 100644 index 000000000..3f626ffdf --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-misaligned-01.S @@ -0,0 +1,136 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV64A extension for the lr-sc-misaligned covergroup. +//This test first does the load reserve and then it store reserve to the same reservation set, the address of the reservation set is misaligned by 1, 2 and 3 bytes. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-misaligned) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +addi x31, x31, 1 # Add 1 to rvtest_data +lr.d x30, (x31) # Load reserve rvtest_data by misaligned 1 +sc.d x29, x30, (x31) # Store conditional to rvtest_data by misaligned 1 + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_1: +addi x31, x31, 2 # Add 2 to rvtest_data +lr.d x30, (x31) # Load reserve rvtest_data by misaligned 2 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional to rvtest_data by misaligned 2 + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_2: +addi x31, x31, 3 # Add 3 to rvtest_data +lr.d x30, (x31) # Load reserve rvtest_data by misaligned 3 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional to rvtest_data by misaligned 3 + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_3: +addi x31, x31, 4 # Add 4 to rvtest_data +lr.d x30, (x31) # Load reserve rvtest_data by misaligned 4 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional to rvtest_data by misaligned 4 + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_4: +addi x31, x31, 5 # Add 5 to rvtest_data +lr.d x30, (x31) # Load reserve rvtest_data by misaligned 5 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional to rvtest_data by misaligned 5 + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_5: +addi x31, x31, 6 # Add 6 to rvtest_data +lr.d x30, (x31) # Load reserve rvtest_data by misaligned 6 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional to rvtest_data by misaligned 6 + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_6: +addi x31, x31, 7 # Add 7 to rvtest_data +lr.d x30, (x31) # Load reserve rvtest_data by misaligned 7 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional to rvtest_data by misaligned 7 + + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-rl-01.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-rl-01.S new file mode 100644 index 000000000..e2b011d1c --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-rl-01.S @@ -0,0 +1,104 @@ +// +// This assembly file tests the lr.r and sc.d.rl instruction of the RISC-V RV64A extension for the lr-sc-rl covergroup. +// This test first does the load reserve and then it store reserve to the same reservation set and releases the access. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-rl) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data + +inst_0: +lr.d x30, (x31) # Load reserve the rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_1: +addi x31, x31, 4 # Add 4 to go to next address +lr.d x30, (x31) # Load reserve the rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_2: +addi x31, x31, 4 # Add 4 to go to next address +lr.d x30, (x31) # Load reserve the rvtest_data + 8 +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release on the same address + +inst_3: +addi x31, x31, 4 # Add 4 to go to next address +lr.d x30, (x31) # Load reserve the rvtest_data + 12 +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release on the same address +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-sw.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-sw.S new file mode 100644 index 000000000..87b1df139 --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-sw.S @@ -0,0 +1,96 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV64A extension for the lr-sc-fail covergroup. +// This test first acquires access through load reserve and before the store reserve to the reservation set it does another sw to the same address and then it store reserve to the same reservation set. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-sw) + +RVTEST_SIGBASE(x8,signature_x8) + +LA (x31, rvtest_data) # Load address of rvtest_data in 31 +addi x28, x31, 4 # Load address of rvtest_data + 4 in x28 +LI (x5, 0) # Initializing x5 with zero + +inst_0: +lr.d.aq x30, (x31) # Load reserve and acquire from rvtest_data +sw x5, (x31) # Store word to rvtest_data +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional to same address + +inst_1: +lr.d.aq x30, (x31) # Load reserve and acquire from rvtest_data +sw x5, (x28) # Store word to rvtest_data + 4 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional to same address + + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +# signature_x1_0: +# .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +# signature_x1_1: +# .fill 50*((XLEN/8)/4),4,0xdeadbeef + +signature_x8: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/A/src/lr-sc-unconstrained-loop-01.S b/riscv-test-suite/rv64i_m/A/src/lr-sc-unconstrained-loop-01.S new file mode 100644 index 000000000..53b7286f1 --- /dev/null +++ b/riscv-test-suite/rv64i_m/A/src/lr-sc-unconstrained-loop-01.S @@ -0,0 +1,113 @@ +// +// This assembly file tests the lr.r and sc.d instruction of the RISC-V RV64A extension for the lr-sc-unconstrained-loop covergroup. +// This test first acquires access through load reserve and during the loop it performs only I type instructions and then it store reserve to the same reservation set. After that another LR/SC sequence is performed outside of the constrained loop. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IA_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True;",lr-sc-unconstrained-loop) + +RVTEST_SIGBASE(x1,signature_x1_1) + +LA (x31, rvtest_data) # Load address of rvtest_data +LI (x27, 0x4) # Load 4 in x27 for retries + +inst_0: +beqz x27, stop_retry_inst_0 # If 4 retries have reached zero stop retrying +lr.d.aq x30, (x31) # Load reserve and acquire from rvtest_data +li x28, 0x0000FFFF # Mask the read data +and x30, x30, x28 +li x30, 0 # Load zero to verify the changed value +sc.d.rl x29, x30, (x31) # Store conditional and release to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_0 # Check if store conditional passed otherwise retry + +stop_retry_inst_0: + +LA (x31, rvtest_data) # Load address of rvtest_data +addi x31, x31, 4 # Add 4 to go to next address +LI (x27, 0x4) # Load 4 in x27 for retries + +# LR/SC out of loop + +inst_1: +beqz x27, stop_retry_inst_1 # If 4 retries have reached zero stop retrying +lr.d x30, (x31) # Load reserve from rvtest_data +li x28, 0x0000FFFF # Mask the read data +and x30, x30, x28 +li x30, 0 # Load zero to verify the changed value +sc.d x29, x30, (x31) # Store conditional to same address +addi x27, x27, -1 # Decrease counter for retries +bnez x29, inst_1 # Check if store conditional passed otherwise retry + +stop_retry_inst_1: + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +.word 0xffffffff +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 50*((XLEN/8)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 88*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From 7925ef06972ac250ceb43006188afa2777a38019 Mon Sep 17 00:00:00 2001 From: muhammad-maarij-zeeshan <142016896+muhammad-maarij-zeeshan@users.noreply.github.com> Date: Mon, 26 Feb 2024 16:35:06 +0500 Subject: [PATCH 3/3] Update CHANGELOG.md Signed-off-by: muhammad-maarij-zeeshan <142016896+muhammad-maarij-zeeshan@users.noreply.github.com> --- CHANGELOG.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index a5bd6dbfa..127003aac 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,8 @@ # CHANGELOG +## [3.8.10] -- 2024-02-21 +- Adds tests for LR/SC instructions in Atomic (A) Extension. + ## [3.8.9] -- 2024-01-12 - Fixed Check ISA fields to include 32/64 in Zicond tests. Note that the riscv-ctg CGFs have not been updated.