From 2e8019ef8ddacd042ee2a4758551989a43fe89dd Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Tue, 19 Dec 2023 16:27:59 +0000 Subject: [PATCH 1/8] first attempt at CSRs and encodings for CHERI --- csrs.csv | 10 +++++++++ unratified/rv64_cheri | 51 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 unratified/rv64_cheri diff --git a/csrs.csv b/csrs.csv index 3c6328b9..ade506ee 100644 --- a/csrs.csv +++ b/csrs.csv @@ -240,7 +240,14 @@ 0x3ed, "pmpaddr61" 0x3ee, "pmpaddr62" 0x3ef, "pmpaddr63" +0x417, "jvtc" +0x505, "stvecc" +0x540, "sscratchc" +0x541, "sepcc" 0x747, "mseccfg" +0x760, "mscratchc" +0x761, "mepcc" +0x765, "mtvecc" 0x7a0, "tselect" 0x7a1, "tdata1" 0x7a2, "tdata2" @@ -253,6 +260,9 @@ 0x7b1, "dpc" 0x7b2, "dscratch0" 0x7b3, "dscratch1" +0x7b9, "dpcc" +0x7ba, "dscratch0c" +0x7bb, "dscratch1c" 0xB00, "mcycle" 0xB02, "minstret" 0xB03, "mhpmcounter3" diff --git a/unratified/rv64_cheri b/unratified/rv64_cheri new file mode 100644 index 00000000..cc60f7fc --- /dev/null +++ b/unratified/rv64_cheri @@ -0,0 +1,51 @@ +lc rd rs1 imm12 14..12=4 6..2=0x03 1..0=3 +sc imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3 + +#maybe doesn't need full 12-bit immediate +cincoffsetimm rd rs1 imm12 14..12=1 6..2=0x04 1..0=3 +#can trim to 5-bit immediate +csetboundsimm rd rs1 imm12 14..12=5 6..2=0x04 1..0=3 + +cincoffset rd rs1 rs2 31..25=6 14..12=0 6..2=0x0C 1..0=3 +csetaddr rd rs1 rs2 31..25=6 14..12=1 6..2=0x0C 1..0=3 +candperm rd rs1 rs2 31..25=6 14..12=2 6..2=0x0C 1..0=3 +csethigh rd rs1 rs2 31..25=6 14..12=3 6..2=0x0C 1..0=3 +csetequalexact rd rs1 rs2 31..25=6 14..12=4 6..2=0x0C 1..0=3 +cbuildcap rd rs1 rs2 31..25=6 14..12=5 6..2=0x0C 1..0=3 +ctestsubset rd rs1 rs2 31..25=6 14..12=6 6..2=0x0C 1..0=3 + +csetbounds rd rs1 rs2 31..25=7 14..12=0 6..2=0x0C 1..0=3 +csetboundsinexact rd rs1 rs2 31..25=7 14..12=1 6..2=0x0C 1..0=3 + +cgettag rd rs1 31..25=8 24..20=0 14..12=0 6..2=0x0C 1..0=3 +cgetperm rd rs1 31..25=8 24..20=1 14..12=0 6..2=0x0C 1..0=3 +cmove rd rs1 31..25=8 24..20=2 14..12=0 6..2=0x0C 1..0=3 +csetmode rd rs1 31..25=8 24..20=3 14..12=0 6..2=0x0C 1..0=3 +cgethigh rd rs1 31..25=8 24..20=4 14..12=0 6..2=0x0C 1..0=3 +cgetbase rd rs1 31..25=8 24..20=5 14..12=0 6..2=0x0C 1..0=3 +cgetlen rd rs1 31..25=8 24..20=6 14..12=0 6..2=0x0C 1..0=3 +cram rd rs1 31..25=8 24..20=7 14..12=0 6..2=0x0C 1..0=3 +cseal rd rs1 31..25=8 24..20=8 14..12=0 6..2=0x0C 1..0=3 + +cmodeswitch 31..25=9 24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3 + +#adjacent to c.not +c.cmodeswitch 15..13=4 12..10=7 9..7=0 6..5=3 4..2=7 1..0=1 + +#adjacent to JALR +jalr.pcc rd rs1 31..20=0 14..12=1 6..2=0x19 1..0=3 + +#adjacent to sh[123]add +sh4add rd rs1 rs2 31..25=16 14..12=7 6..2=0x0C 1..0=3 + +#adjacent to sh[123]add.uw +sh4add.uw rd rs1 rs2 31..25=16 14..12=7 6..2=0x0E 1..0=3 + +#regular encodings +lr.b rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=0 6..2=0x0B 1..0=3 +lr.h rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=1 6..2=0x0B 1..0=3 +sc.b rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=0 6..2=0x0B 1..0=3 +sc.h rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=1 6..2=0x0B 1..0=3 + +#regular encoding +amoswap.c rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=4 6..2=0x0B 1..0=3 From 5a54e195fdfdd5bda35333a36a5073564bdc1223 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Tue, 19 Dec 2023 16:40:54 +0000 Subject: [PATCH 2/8] note that lr/b etc will be a separate extension eventually --- unratified/rv64_cheri | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/unratified/rv64_cheri b/unratified/rv64_cheri index cc60f7fc..ee76f405 100644 --- a/unratified/rv64_cheri +++ b/unratified/rv64_cheri @@ -41,7 +41,7 @@ sh4add rd rs1 rs2 31..25=16 14..12=7 6..2=0x0C 1..0=3 #adjacent to sh[123]add.uw sh4add.uw rd rs1 rs2 31..25=16 14..12=7 6..2=0x0E 1..0=3 -#regular encodings +#regular encodings - will become a separate extension lr.b rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=0 6..2=0x0B 1..0=3 lr.h rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=1 6..2=0x0B 1..0=3 sc.b rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=0 6..2=0x0B 1..0=3 From 17a3dd72c7f143c004dde7c81b498a4c694f26b8 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Thu, 4 Jan 2024 15:43:54 +0000 Subject: [PATCH 3/8] resolve overlapping encodings --- unratified/rv64_cheri | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/unratified/rv64_cheri b/unratified/rv64_cheri index ee76f405..5ade1bd5 100644 --- a/unratified/rv64_cheri +++ b/unratified/rv64_cheri @@ -1,10 +1,10 @@ lc rd rs1 imm12 14..12=4 6..2=0x03 1..0=3 sc imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3 -#maybe doesn't need full 12-bit immediate -cincoffsetimm rd rs1 imm12 14..12=1 6..2=0x04 1..0=3 -#can trim to 5-bit immediate -csetboundsimm rd rs1 imm12 14..12=5 6..2=0x04 1..0=3 +#6-bit immediate fits, should hopefully be enough? +cincoffsetimm rd rs1 imm6 31..26=1 14..12=1 6..2=0x04 1..0=3 +#5-bit immediate and 25 says whether to shift it +csetboundsimm rd rs1 imm5 31..26=1 14..12=5 6..2=0x04 1..0=3 cincoffset rd rs1 rs2 31..25=6 14..12=0 6..2=0x0C 1..0=3 csetaddr rd rs1 rs2 31..25=6 14..12=1 6..2=0x0C 1..0=3 From a9c455170460478310de1f68c1642b610e894250 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Mon, 8 Jan 2024 11:59:54 +0000 Subject: [PATCH 4/8] remap cincoffsetimm to op-imm-32 and make cincoffset with rs2=x0 decode as cmove --- unratified/rv64_cheri | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/unratified/rv64_cheri b/unratified/rv64_cheri index 5ade1bd5..dec08bec 100644 --- a/unratified/rv64_cheri +++ b/unratified/rv64_cheri @@ -1,12 +1,14 @@ lc rd rs1 imm12 14..12=4 6..2=0x03 1..0=3 sc imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3 -#6-bit immediate fits, should hopefully be enough? -cincoffsetimm rd rs1 imm6 31..26=1 14..12=1 6..2=0x04 1..0=3 +#need to ADDIW +cincoffsetimm rd rs1 imm12 14..12=2 6..2=0x06 1..0=3 #5-bit immediate and 25 says whether to shift it -csetboundsimm rd rs1 imm5 31..26=1 14..12=5 6..2=0x04 1..0=3 +csetboundsimm rd rs1 imm5 31..26=1 14..12=5 6..2=0x04 1..0=3 -cincoffset rd rs1 rs2 31..25=6 14..12=0 6..2=0x0C 1..0=3 +#if rs2=x0 decode as cmove +cincoffset rd rs1 rs2 31..25=6 14..12=0 6..2=0x06 1..0=3 +cmove rd rs1 24..20=0 31..25=6 14..12=0 6..2=0x06 1..0=3 csetaddr rd rs1 rs2 31..25=6 14..12=1 6..2=0x0C 1..0=3 candperm rd rs1 rs2 31..25=6 14..12=2 6..2=0x0C 1..0=3 csethigh rd rs1 rs2 31..25=6 14..12=3 6..2=0x0C 1..0=3 @@ -19,7 +21,6 @@ csetboundsinexact rd rs1 rs2 31..25=7 14..12=1 6..2=0x0C 1..0=3 cgettag rd rs1 31..25=8 24..20=0 14..12=0 6..2=0x0C 1..0=3 cgetperm rd rs1 31..25=8 24..20=1 14..12=0 6..2=0x0C 1..0=3 -cmove rd rs1 31..25=8 24..20=2 14..12=0 6..2=0x0C 1..0=3 csetmode rd rs1 31..25=8 24..20=3 14..12=0 6..2=0x0C 1..0=3 cgethigh rd rs1 31..25=8 24..20=4 14..12=0 6..2=0x0C 1..0=3 cgetbase rd rs1 31..25=8 24..20=5 14..12=0 6..2=0x0C 1..0=3 From 2c62d98fa3176031d6dc6636e0832a7236766c62 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Wed, 24 Jan 2024 13:26:45 +0100 Subject: [PATCH 5/8] add rs2 to csetmode --- unratified/rv64_cheri | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/unratified/rv64_cheri b/unratified/rv64_cheri index dec08bec..5f02206a 100644 --- a/unratified/rv64_cheri +++ b/unratified/rv64_cheri @@ -15,13 +15,13 @@ csethigh rd rs1 rs2 31..25=6 14..12=3 6..2=0x0C 1..0=3 csetequalexact rd rs1 rs2 31..25=6 14..12=4 6..2=0x0C 1..0=3 cbuildcap rd rs1 rs2 31..25=6 14..12=5 6..2=0x0C 1..0=3 ctestsubset rd rs1 rs2 31..25=6 14..12=6 6..2=0x0C 1..0=3 +csetmode rd rs1 rs2 31..25=6 14..12=7 6..2=0x0C 1..0=3 csetbounds rd rs1 rs2 31..25=7 14..12=0 6..2=0x0C 1..0=3 csetboundsinexact rd rs1 rs2 31..25=7 14..12=1 6..2=0x0C 1..0=3 cgettag rd rs1 31..25=8 24..20=0 14..12=0 6..2=0x0C 1..0=3 cgetperm rd rs1 31..25=8 24..20=1 14..12=0 6..2=0x0C 1..0=3 -csetmode rd rs1 31..25=8 24..20=3 14..12=0 6..2=0x0C 1..0=3 cgethigh rd rs1 31..25=8 24..20=4 14..12=0 6..2=0x0C 1..0=3 cgetbase rd rs1 31..25=8 24..20=5 14..12=0 6..2=0x0C 1..0=3 cgetlen rd rs1 31..25=8 24..20=6 14..12=0 6..2=0x0C 1..0=3 From 6fefa7defd297765f4705059ebdb8b57682ec5d6 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Tue, 13 Feb 2024 16:04:53 +0000 Subject: [PATCH 6/8] instruction renaming to match latest spec --- unratified/rv64_cheri | 47 +++++++++++++++++++++---------------------- 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/unratified/rv64_cheri b/unratified/rv64_cheri index 5f02206a..fe2e62cf 100644 --- a/unratified/rv64_cheri +++ b/unratified/rv64_cheri @@ -2,39 +2,38 @@ lc rd rs1 imm12 14..12=4 6..2=0x03 1..0=3 sc imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3 #need to ADDIW -cincoffsetimm rd rs1 imm12 14..12=2 6..2=0x06 1..0=3 +caddi rd rs1 imm12 14..12=2 6..2=0x06 1..0=3 #5-bit immediate and 25 says whether to shift it -csetboundsimm rd rs1 imm5 31..26=1 14..12=5 6..2=0x04 1..0=3 +scbndsi rd rs1 imm5 31..26=1 14..12=5 6..2=0x04 1..0=3 #if rs2=x0 decode as cmove -cincoffset rd rs1 rs2 31..25=6 14..12=0 6..2=0x06 1..0=3 -cmove rd rs1 24..20=0 31..25=6 14..12=0 6..2=0x06 1..0=3 -csetaddr rd rs1 rs2 31..25=6 14..12=1 6..2=0x0C 1..0=3 -candperm rd rs1 rs2 31..25=6 14..12=2 6..2=0x0C 1..0=3 -csethigh rd rs1 rs2 31..25=6 14..12=3 6..2=0x0C 1..0=3 -csetequalexact rd rs1 rs2 31..25=6 14..12=4 6..2=0x0C 1..0=3 -cbuildcap rd rs1 rs2 31..25=6 14..12=5 6..2=0x0C 1..0=3 -ctestsubset rd rs1 rs2 31..25=6 14..12=6 6..2=0x0C 1..0=3 -csetmode rd rs1 rs2 31..25=6 14..12=7 6..2=0x0C 1..0=3 - -csetbounds rd rs1 rs2 31..25=7 14..12=0 6..2=0x0C 1..0=3 -csetboundsinexact rd rs1 rs2 31..25=7 14..12=1 6..2=0x0C 1..0=3 - -cgettag rd rs1 31..25=8 24..20=0 14..12=0 6..2=0x0C 1..0=3 -cgetperm rd rs1 31..25=8 24..20=1 14..12=0 6..2=0x0C 1..0=3 -cgethigh rd rs1 31..25=8 24..20=4 14..12=0 6..2=0x0C 1..0=3 -cgetbase rd rs1 31..25=8 24..20=5 14..12=0 6..2=0x0C 1..0=3 -cgetlen rd rs1 31..25=8 24..20=6 14..12=0 6..2=0x0C 1..0=3 +cadd rd rs1 rs2 31..25=6 14..12=0 6..2=0x06 1..0=3 +scaddr rd rs1 rs2 31..25=6 14..12=1 6..2=0x0C 1..0=3 +acperm rd rs1 rs2 31..25=6 14..12=2 6..2=0x0C 1..0=3 +schi rd rs1 rs2 31..25=6 14..12=3 6..2=0x0C 1..0=3 +sceq rd rs1 rs2 31..25=6 14..12=4 6..2=0x0C 1..0=3 +cbld rd rs1 rs2 31..25=6 14..12=5 6..2=0x0C 1..0=3 +cscc rd rs1 rs2 31..25=6 14..12=6 6..2=0x0C 1..0=3 +scmode rd rs1 rs2 31..25=6 14..12=7 6..2=0x0C 1..0=3 + +scbnds rd rs1 rs2 31..25=7 14..12=0 6..2=0x0C 1..0=3 +scbndsr rd rs1 rs2 31..25=7 14..12=1 6..2=0x0C 1..0=3 + +gctag rd rs1 31..25=8 24..20=0 14..12=0 6..2=0x0C 1..0=3 +gcperm rd rs1 31..25=8 24..20=1 14..12=0 6..2=0x0C 1..0=3 +gchi rd rs1 31..25=8 24..20=4 14..12=0 6..2=0x0C 1..0=3 +gcbase rd rs1 31..25=8 24..20=5 14..12=0 6..2=0x0C 1..0=3 +gclen rd rs1 31..25=8 24..20=6 14..12=0 6..2=0x0C 1..0=3 cram rd rs1 31..25=8 24..20=7 14..12=0 6..2=0x0C 1..0=3 -cseal rd rs1 31..25=8 24..20=8 14..12=0 6..2=0x0C 1..0=3 +sentry rd rs1 31..25=8 24..20=8 14..12=0 6..2=0x0C 1..0=3 -cmodeswitch 31..25=9 24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3 +modesw 31..25=9 24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3 #adjacent to c.not -c.cmodeswitch 15..13=4 12..10=7 9..7=0 6..5=3 4..2=7 1..0=1 +c.modesw 15..13=4 12..10=7 9..7=0 6..5=3 4..2=7 1..0=1 #adjacent to JALR -jalr.pcc rd rs1 31..20=0 14..12=1 6..2=0x19 1..0=3 +jalr.mode rd rs1 31..20=0 14..12=1 6..2=0x19 1..0=3 #adjacent to sh[123]add sh4add rd rs1 rs2 31..25=16 14..12=7 6..2=0x0C 1..0=3 From 92a41e407265d125dcf3c98c3e7932eba1ed2a55 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Wed, 14 Feb 2024 14:44:23 +0000 Subject: [PATCH 7/8] add extra debug CSRs --- csrs.csv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/csrs.csv b/csrs.csv index ade506ee..985a0ddf 100644 --- a/csrs.csv +++ b/csrs.csv @@ -263,6 +263,8 @@ 0x7b9, "dpcc" 0x7ba, "dscratch0c" 0x7bb, "dscratch1c" +0x7bc, "dddc" +0x7bd, "dinfcap" 0xB00, "mcycle" 0xB02, "minstret" 0xB03, "mhpmcounter3" From b003eddc51bf588d48e8fd340ade541720a47f33 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Mon, 19 Feb 2024 17:37:05 +0000 Subject: [PATCH 8/8] put cadd into OP --- unratified/rv64_cheri | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/unratified/rv64_cheri b/unratified/rv64_cheri index fe2e62cf..da31ea12 100644 --- a/unratified/rv64_cheri +++ b/unratified/rv64_cheri @@ -7,7 +7,7 @@ caddi rd rs1 imm12 14..12=2 6..2=0x06 1..0=3 scbndsi rd rs1 imm5 31..26=1 14..12=5 6..2=0x04 1..0=3 #if rs2=x0 decode as cmove -cadd rd rs1 rs2 31..25=6 14..12=0 6..2=0x06 1..0=3 +cadd rd rs1 rs2 31..25=6 14..12=0 6..2=0x0C 1..0=3 scaddr rd rs1 rs2 31..25=6 14..12=1 6..2=0x0C 1..0=3 acperm rd rs1 rs2 31..25=6 14..12=2 6..2=0x0C 1..0=3 schi rd rs1 rs2 31..25=6 14..12=3 6..2=0x0C 1..0=3