From 80d0154b7435b555af03592be6a485a954cf0f0a Mon Sep 17 00:00:00 2001 From: Tim Hutt Date: Thu, 2 Jan 2025 13:11:05 +0000 Subject: [PATCH] Implement CMake build system This is a draft of a CMake build system. It doesn't yet include RVFI, JSON docs, formal stuff, etc. --- .gitignore | 5 +- CMakeLists.txt | 76 +++++ Makefile | 428 -------------------------- build_simulators.sh | 14 - cmake/extra_fast.cmake | 28 ++ cmake/modules/FindGMP.cmake | 46 +++ dependencies/softfloat/CMakeLists.txt | 44 +++ emulator/CMakeLists.txt | 44 +++ model/CMakeLists.txt | 268 ++++++++++++++++ sail-riscv.install | 2 - sail_runtime/CMakeLists.txt | 23 ++ test/get_perf.py | 42 --- test/riscv-tests/.gitignore | 2 - test/riscv-tests/CMakeLists.txt | 46 +++ test/run_fp_tests.sh | 97 ------ test/run_tests.sh | 125 -------- 16 files changed, 579 insertions(+), 711 deletions(-) create mode 100644 CMakeLists.txt delete mode 100644 Makefile delete mode 100755 build_simulators.sh create mode 100644 cmake/extra_fast.cmake create mode 100644 cmake/modules/FindGMP.cmake create mode 100644 dependencies/softfloat/CMakeLists.txt create mode 100644 emulator/CMakeLists.txt create mode 100644 model/CMakeLists.txt delete mode 100644 sail-riscv.install create mode 100644 sail_runtime/CMakeLists.txt delete mode 100755 test/get_perf.py delete mode 100644 test/riscv-tests/.gitignore create mode 100644 test/riscv-tests/CMakeLists.txt delete mode 100755 test/run_fp_tests.sh delete mode 100755 test/run_tests.sh diff --git a/.gitignore b/.gitignore index 0079a6798..72da15507 100644 --- a/.gitignore +++ b/.gitignore @@ -6,4 +6,7 @@ _build/ _sbuild/ *.o *.a -/z3_problems +z3_problems + +# Typical CMake build directory. +/build diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 000000000..4ff7aaee5 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,76 @@ +cmake_minimum_required(VERSION 3.22) + +project(sail_riscv) + +# Enable CTest +enable_testing() + +# We technically require C++20 since the C generated by Sail - which we compile +# as C++ - uses designated initialisers, a C++20 feature. However in practice +# much older compilers support this feature so everything does work with C++17, +# but you get lots of warnings on compilers that support C++20 if you use +# this feature without -std=c++20. +if (cxx_std_20 IN_LIST CMAKE_CXX_COMPILE_FEATURES) + set(CMAKE_CXX_STANDARD 20) +else() + set(CMAKE_CXX_STANDARD 17) +endif() +set(CMAKE_CXX_STANDARD_REQUIRED TRUE) + +# Export compile_commands.json for IDE support. +set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE) + +# Always use Position Independent Code. By default it is only used for +# shared libraries (which require it), but you also need it for static +# libraries if you link them into shared libraries. +# Generally it just simplifies everything for a negligable performance cost. +set(CMAKE_POSITION_INDEPENDENT_CODE TRUE) + +# Don't allow undefined symbols in shared libraries. This is generally a pain. +if (UNIX) + set(CMAKE_SHARED_LINKER_FLAGS "-Wl,--no-undefined") +endif() + +# Optional faster binary. Increases compilation time a lot though due to LTO. +option(EXTRA_FAST "Enable aggressive optimisation flags (-march=native, -flto, etc)" FALSE) + +if (EXTRA_FAST) + include("cmake/extra_fast.cmake") +endif() + +# Extra CMake files. +set(CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules") + +# These are the main requirements. +# Don't use `REQUIRED` so that we can print custom help messages. +find_package(ZLIB) +if (NOT ZLIB_FOUND) + message(FATAL_ERROR "Zlib not found. Try 'sudo apt install zlib1g-dev' or 'sudo dnf install zlib-devel'.") +endif() + +find_package(GMP) +if (NOT GMP_FOUND) + message(FATAL_ERROR "GMP not found. Try 'sudo apt install libgmp3-dev' or 'sudo dnf install gmp-devel'.") +endif() + +find_program(SAIL_BIN "sail") +if (NOT SAIL_BIN) + message(FATAL_ERROR "Sail not found. See README.md for installation instructions.") +endif() + +set(ENABLED_ARCHITECTURES "rv32;rv64" CACHE STRING "Enabled architectures to build (rv32, rv64, rv32d, rv64f)" ) + +# Softfloat support. +add_subdirectory("dependencies/softfloat") + +# Sail C runtime. +add_subdirectory("sail_runtime") + +# Sail model generated C code. +add_subdirectory("model") + +# Emulator binary. +add_subdirectory("emulator") + +# Old pre-compiled riscv-tests. +add_subdirectory("test/riscv-tests") diff --git a/Makefile b/Makefile deleted file mode 100644 index c1f3e4e14..000000000 --- a/Makefile +++ /dev/null @@ -1,428 +0,0 @@ -# Select architecture: RV32 or RV64. -ARCH ?= RV64 - -ifeq ($(ARCH),32) - override ARCH := RV32 -else ifeq ($(ARCH),64) - override ARCH := RV64 -endif - -ifeq ($(ARCH),RV32) - SAIL_XLEN := riscv_xlen32.sail -else ifeq ($(ARCH),RV64) - SAIL_XLEN := riscv_xlen64.sail -else - $(error '$(ARCH)' is not a valid architecture, must be one of: RV32, RV64) -endif - -SAIL_XLEN += riscv_xlen.sail -SAIL_FLEN := riscv_flen_D.sail -SAIL_FLEN += riscv_flen.sail -SAIL_VLEN := riscv_vlen.sail - -# Instruction sources, depending on target -SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail -SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_zifencei.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_hints.sail -SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_zcf.sail -SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_zcd.sail - -SAIL_DEFAULT_INST += riscv_insts_svinval.sail - -SAIL_DEFAULT_INST += riscv_insts_zba.sail -SAIL_DEFAULT_INST += riscv_insts_zbb.sail -SAIL_DEFAULT_INST += riscv_insts_zbc.sail -SAIL_DEFAULT_INST += riscv_insts_zbs.sail - -SAIL_DEFAULT_INST += riscv_insts_zcb.sail - -SAIL_DEFAULT_INST += riscv_insts_zfh.sail -# Zfa needs to be added after fext, dext and Zfh (as it needs -# definitions from those) -SAIL_DEFAULT_INST += riscv_insts_zfa.sail - -SAIL_DEFAULT_INST += riscv_insts_zkn.sail -SAIL_DEFAULT_INST += riscv_insts_zks.sail - -SAIL_DEFAULT_INST += riscv_insts_zbkb.sail -SAIL_DEFAULT_INST += riscv_insts_zbkx.sail - -SAIL_DEFAULT_INST += riscv_insts_zicond.sail - -SAIL_DEFAULT_INST += riscv_insts_vext_utils.sail -SAIL_DEFAULT_INST += riscv_insts_vext_fp_utils.sail -SAIL_DEFAULT_INST += riscv_insts_vext_vset.sail -SAIL_DEFAULT_INST += riscv_insts_vext_arith.sail -SAIL_DEFAULT_INST += riscv_insts_vext_fp.sail -SAIL_DEFAULT_INST += riscv_insts_vext_mem.sail -SAIL_DEFAULT_INST += riscv_insts_vext_mask.sail -SAIL_DEFAULT_INST += riscv_insts_vext_vm.sail -SAIL_DEFAULT_INST += riscv_insts_vext_fp_vm.sail -SAIL_DEFAULT_INST += riscv_insts_vext_red.sail -SAIL_DEFAULT_INST += riscv_insts_vext_fp_red.sail -SAIL_DEFAULT_INST += riscv_insts_zicbom.sail -SAIL_DEFAULT_INST += riscv_insts_zicboz.sail - -SAIL_SEQ_INST = $(SAIL_DEFAULT_INST) riscv_jalr_seq.sail -SAIL_RMEM_INST = $(SAIL_DEFAULT_INST) riscv_jalr_rmem.sail riscv_insts_rmem.sail - -# TODO: riscv_csr_end.sail here temporarily until the scattered definitions -# are moved from riscv_insts_zicsr.sail to more appropriate places. -SAIL_SEQ_INST_SRCS = riscv_insts_begin.sail $(SAIL_SEQ_INST) riscv_insts_end.sail riscv_csr_end.sail -SAIL_RMEM_INST_SRCS = riscv_insts_begin.sail $(SAIL_RMEM_INST) riscv_insts_end.sail riscv_csr_end.sail - -# System and platform sources -SAIL_SYS_SRCS += riscv_vext_control.sail # helpers for the 'V' extension -SAIL_SYS_SRCS += riscv_sys_exceptions.sail # default basic helpers for exception handling -SAIL_SYS_SRCS += riscv_sync_exception.sail # define the exception structure used in the model -SAIL_SYS_SRCS += riscv_zihpm.sail -SAIL_SYS_SRCS += riscv_zkr_control.sail -SAIL_SYS_SRCS += riscv_zicntr_control.sail -SAIL_SYS_SRCS += riscv_softfloat_interface.sail riscv_fdext_regs.sail riscv_fdext_control.sail -SAIL_SYS_SRCS += riscv_sys_control.sail # general exception handling - -# SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail -# SAIL_RV64_VM_SRCS = riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_vmem_rv64.sail - -# SAIL_VM_SRCS = riscv_pte.sail riscv_ptw.sail riscv_vmem_common.sail riscv_vmem_tlb.sail -# ifeq ($(ARCH),RV32) -# SAIL_VM_SRCS += $(SAIL_RV32_VM_SRCS) -# else -# SAIL_VM_SRCS += $(SAIL_RV64_VM_SRCS) -# endif - -SAIL_VM_SRCS += riscv_vmem_common.sail -SAIL_VM_SRCS += riscv_vmem_pte.sail -SAIL_VM_SRCS += riscv_vmem_ptw.sail -SAIL_VM_SRCS += riscv_vmem_tlb.sail -SAIL_VM_SRCS += riscv_vmem.sail - -# Non-instruction sources -PRELUDE = prelude.sail riscv_errors.sail $(SAIL_XLEN) $(SAIL_FLEN) $(SAIL_VLEN) prelude_mem_addrtype.sail prelude_mem_metadata.sail prelude_mem.sail - -SAIL_REGS_SRCS = riscv_csr_begin.sail # Start of CSR scattered definitions. -SAIL_REGS_SRCS += riscv_reg_type.sail riscv_freg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail -SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail -SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS) -SAIL_REGS_SRCS += riscv_vreg_type.sail riscv_vext_regs.sail - -SAIL_ARCH_SRCS = $(PRELUDE) -SAIL_ARCH_SRCS += riscv_extensions.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail -SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail -SAIL_ARCH_SRCS += riscv_sstc.sail -SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) -SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_extensions.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail -SAIL_ARCH_SRCS += riscv_types_kext.sail # Shared/common code for the cryptography extension. - -SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail -RVFI_STEP_SRCS = riscv_step_common.sail riscv_step_rvfi.sail riscv_decode_ext.sail riscv_fetch_rvfi.sail riscv_step.sail - -SAIL_OTHER_SRCS = $(SAIL_STEP_SRCS) -ifeq ($(ARCH),RV32) -SAIL_OTHER_COQ_SRCS = riscv_termination_common.sail riscv_termination_rv32.sail -else -SAIL_OTHER_COQ_SRCS = riscv_termination_common.sail riscv_termination_rv64.sail -endif - -PRELUDE_SRCS = $(addprefix model/,$(PRELUDE)) -SAIL_SRCS = $(addprefix model/,$(SAIL_ARCH_SRCS) $(SAIL_SEQ_INST_SRCS) $(SAIL_OTHER_SRCS)) -SAIL_RMEM_SRCS = $(addprefix model/,$(SAIL_ARCH_SRCS) $(SAIL_RMEM_INST_SRCS) $(SAIL_OTHER_SRCS)) -SAIL_RVFI_SRCS = $(addprefix model/,$(SAIL_ARCH_RVFI_SRCS) $(SAIL_SEQ_INST_SRCS) $(RVFI_STEP_SRCS)) -SAIL_COQ_SRCS = $(addprefix model/,$(SAIL_ARCH_SRCS) $(SAIL_SEQ_INST_SRCS) $(SAIL_OTHER_COQ_SRCS)) - -SAIL_FLAGS += --require-version 0.18 -SAIL_FLAGS += --strict-var -SAIL_FLAGS += -dno_cast -SAIL_DOC_FLAGS ?= -doc_embed plain - -# Sail command to use. -SAIL := sail - -# /share/sail -SAIL_DIR := $(shell $(SAIL) --dir) -SAIL_LIB_DIR := $(SAIL_DIR)/lib -SAIL_SRC_DIR := $(SAIL_DIR)/src - -LEM_DIR := $(SAIL_DIR)/../lem -export LEM_DIR - -C_WARNINGS ?= -#-Wall -Wextra -Wno-unused-label -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-unused-function -C_INCS = $(addprefix emulator/,riscv_prelude.h riscv_platform_impl.h riscv_platform.h riscv_softfloat.h) -C_SRCS = $(addprefix emulator/,riscv_prelude.c riscv_platform_impl.c riscv_platform.c riscv_softfloat.c riscv_sim.c) - -SOFTFLOAT_DIR = dependencies/softfloat/berkeley-softfloat-3 -SOFTFLOAT_INCDIR = $(SOFTFLOAT_DIR)/source/include -SOFTFLOAT_LIBDIR = $(SOFTFLOAT_DIR)/build/Linux-RISCV64-GCC -SOFTFLOAT_FLAGS = -I $(SOFTFLOAT_INCDIR) -SOFTFLOAT_LIBS = $(SOFTFLOAT_LIBDIR)/softfloat.a -SOFTFLOAT_SPECIALIZE_TYPE = RISCV - -GMP_FLAGS = $(shell pkg-config --cflags gmp) -# N.B. GMP does not have pkg-config metadata on Ubuntu 18.04 so default to -lgmp -GMP_LIBS = $(shell pkg-config --libs gmp || echo -lgmp) - -# TODO: Remove Zlib when upgrading to Sail 0.19; it is no longer a requirement. -ZLIB_FLAGS = $(shell pkg-config --cflags zlib) -ZLIB_LIBS = $(shell pkg-config --libs zlib) - -C_FLAGS = -I $(SAIL_LIB_DIR) -I emulator $(GMP_FLAGS) $(ZLIB_FLAGS) $(SOFTFLOAT_FLAGS) -C_LIBS = $(GMP_LIBS) $(ZLIB_LIBS) $(SOFTFLOAT_LIBS) - -# The C simulator can be built to be linked against Spike for tandem-verification. -# This needs the C bindings to Spike from https://github.com/SRI-CSL/l3riscv -# TV_SPIKE_DIR in the environment should point to the top-level dir of the L3 -# RISC-V, containing the built C bindings to Spike. -# RISCV should be defined if TV_SPIKE_DIR is. -ifneq (,$(TV_SPIKE_DIR)) -C_FLAGS += -I $(TV_SPIKE_DIR)/src/cpp -DENABLE_SPIKE -C_LIBS += -L $(TV_SPIKE_DIR) -ltv_spike -Wl,-rpath=$(TV_SPIKE_DIR) -C_LIBS += -L $(RISCV)/lib -lfesvr -lriscv -Wl,-rpath=$(RISCV)/lib -endif - -# SAIL_FLAGS = -dtc_verbose 4 - -ifneq (,$(COVERAGE)) -C_FLAGS += --coverage -O1 -SAIL_FLAGS += -Oconstant_fold -else -C_FLAGS += -O3 -flto=auto -endif - -ifneq (,$(SAILCOV)) -ALL_BRANCHES = generated_definitions/c/all_branches -C_FLAGS += -DSAILCOV -SAIL_FLAGS += -c_coverage $(ALL_BRANCHES) -c_include sail_coverage.h -C_LIBS += $(SAIL_LIB_DIR)/coverage/libsail_coverage.a -lm -lpthread -ldl -endif - -# Optionally link C_LIBS statically. Unlike -static this will not -# link glibc statically which is generally a bad idea. -ifneq (,$(STATIC)) - UNAME_S := $(shell sh -c 'uname -s 2>/dev/null || echo not') - ifeq ($(UNAME_S),Darwin) - # Unfortunately the Mac linker does not support -Bstatic. - GMP_LIBS = $(shell pkg-config --variable=libdir gmp)/libgmp.a - C_LIBS_WRAPPED = $(C_LIBS) - else - C_LIBS_WRAPPED = -Wl,--push-state -Wl,-Bstatic $(C_LIBS) -Wl,--pop-state - endif -else - C_LIBS_WRAPPED = $(C_LIBS) -endif - -RISCV_EXTRAS_LEM_FILES = riscv_extras.lem mem_metadata.lem riscv_extras_fdext.lem -RISCV_EXTRAS_LEM = $(addprefix handwritten_support/,$(RISCV_EXTRAS_LEM_FILES)) - -.PHONY: - -all: emulator/riscv_sim_$(ARCH) -.PHONY: all - -# the following ensures empty sail-generated .c files don't hang around and -# break future builds if sail exits badly -.DELETE_ON_ERROR: generated_definitions/c/%.c - -check: $(SAIL_SRCS) model/main.sail Makefile - $(SAIL) $(SAIL_FLAGS) $(SAIL_SRCS) model/main.sail - -interpret: $(SAIL_SRCS) model/main.sail - $(SAIL) -i $(SAIL_FLAGS) $(SAIL_SRCS) model/main.sail - -sail_doc/riscv_$(ARCH).json: $(SAIL_SRCS) model/main.sail - $(SAIL) -doc -doc_bundle riscv_$(ARCH).json -o sail_doc $(SAIL_FLAGS) $(SAIL_DOC_FLAGS) $(SAIL_SRCS) model/main.sail - -riscv.smt_model: $(SAIL_SRCS) - $(SAIL) -smt_serialize $(SAIL_FLAGS) $(SAIL_SRCS) -o riscv - -cloc: - cloc --by-file --force-lang C,sail $(SAIL_SRCS) - -gcovr: - gcovr -r . --html --html-detail -o index.html - -generated_definitions/c/riscv_model_$(ARCH).c: $(SAIL_SRCS) model/main.sail Makefile - mkdir -p generated_definitions/c - $(SAIL) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_SRCS) model/main.sail -o $(basename $@) - -$(SOFTFLOAT_LIBS): - $(MAKE) SPECIALIZE_TYPE=$(SOFTFLOAT_SPECIALIZE_TYPE) -C $(SOFTFLOAT_LIBDIR) - -# convenience target -.PHONY: csim -csim: emulator/riscv_sim_$(ARCH) -.PHONY: rvfi -rvfi: emulator/riscv_rvfi_$(ARCH) - -emulator/riscv_sim_$(ARCH): generated_definitions/c/riscv_model_$(ARCH).c $(C_INCS) $(C_SRCS) $(SOFTFLOAT_LIBS) Makefile - $(CC) -g $(C_WARNINGS) $(C_FLAGS) $< $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS_WRAPPED) -o $@ - -# Note: We have to add -c_preserve since the functions might be optimized out otherwise -rvfi_preserve_fns=-c_preserve rvfi_set_instr_packet \ - -c_preserve rvfi_get_cmd \ - -c_preserve rvfi_get_insn \ - -c_preserve rvfi_get_v2_trace_size \ - -c_preserve rvfi_get_v2_support_packet \ - -c_preserve rvfi_get_exec_packet_v1 \ - -c_preserve rvfi_get_exec_packet_v2 \ - -c_preserve rvfi_get_mem_data \ - -c_preserve rvfi_get_int_data \ - -c_preserve rvfi_zero_exec_packet \ - -c_preserve rvfi_halt_exec_packet \ - -c_preserve print_instr_packet \ - -c_preserve print_rvfi_exec - -# sed -i isn't posix compliant, unfortunately -generated_definitions/c/riscv_rvfi_model_$(ARCH).c: $(SAIL_RVFI_SRCS) model/main.sail Makefile - mkdir -p generated_definitions/c - $(SAIL) $(rvfi_preserve_fns) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_RVFI_SRCS) model/main.sail -o $(basename $@) - sed -e '/^[[:space:]]*$$/d' $@ > $@.new - mv $@.new $@ - -emulator/riscv_rvfi_$(ARCH): generated_definitions/c/riscv_rvfi_model_$(ARCH).c $(C_INCS) $(C_SRCS) $(SOFTFLOAT_LIBS) Makefile - $(CC) -g $(C_WARNINGS) $(C_FLAGS) $< -DRVFI_DII $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS_WRAPPED) -o $@ - -latex: $(SAIL_SRCS) Makefile - mkdir -p generated_definitions/latex - $(SAIL) -latex -latex_prefix sail -o generated_definitions/latex $(SAIL_SRCS) - -generated_definitions/isabelle/$(ARCH)/ROOT: handwritten_support/ROOT - mkdir -p generated_definitions/isabelle/$(ARCH) - cp handwritten_support/ROOT generated_definitions/isabelle/$(ARCH)/ - -riscv_isa: generated_definitions/isabelle/$(ARCH)/Riscv.thy -riscv_isa_build: riscv_isa -ifeq ($(wildcard $(LEM_DIR)/isabelle-lib),) - $(error Lem directory not found. Please set the LEM_DIR environment variable) -endif -ifeq ($(wildcard $(SAIL_LIB_DIR)/isabelle),) - $(error lib directory of Sail not found. Please set the SAIL_LIB_DIR environment variable) -endif - isabelle build -b -d $(LEM_DIR)/isabelle-lib -d $(SAIL_LIB_DIR)/isabelle -d generated_definitions/isabelle/$(ARCH) Sail-RISC-V - -.PHONY: riscv_isa riscv_isa_build - -generated_definitions/lem/$(ARCH)/riscv.lem: $(SAIL_SRCS) Makefile - mkdir -p generated_definitions/lem/$(ARCH) generated_definitions/isabelle/$(ARCH) - $(SAIL) $(SAIL_FLAGS) -lem -lem_output_dir generated_definitions/lem/$(ARCH) -isa_output_dir generated_definitions/isabelle/$(ARCH) -o riscv -lem_lib Riscv_extras -lem_lib Riscv_extras_fdext -lem_lib Mem_metadata $(SAIL_SRCS) - echo "declare {isabelle} rename field sync_exception_ext = sync_exception_ext_exception" >> generated_definitions/lem/$(ARCH)/riscv_types.lem - -# sed -i isn't posix compliant, unfortunately -generated_definitions/isabelle/$(ARCH)/Riscv.thy: generated_definitions/isabelle/$(ARCH)/ROOT generated_definitions/lem/$(ARCH)/riscv.lem $(RISCV_EXTRAS_LEM) Makefile - lem -wl ign -isa -outdir generated_definitions/isabelle/$(ARCH) -lib Sail=$(SAIL_SRC_DIR)/lem_interp -lib Sail=$(SAIL_SRC_DIR)/gen_lib \ - $(RISCV_EXTRAS_LEM) \ - generated_definitions/lem/$(ARCH)/riscv_types.lem \ - generated_definitions/lem/$(ARCH)/riscv.lem - sed 's/datatype ast/datatype (plugins only: size) ast/' generated_definitions/isabelle/$(ARCH)/Riscv_types.thy > generated_definitions/isabelle/$(ARCH)/Riscv_types.thy.new - mv generated_definitions/isabelle/$(ARCH)/Riscv_types.thy.new generated_definitions/isabelle/$(ARCH)/Riscv_types.thy - sed "s/record( 'asidlen, 'valen, 'palen, 'ptelen) TLB_Entry/record (overloaded) ( 'asidlen, 'valen, 'palen, 'ptelen) TLB_Entry/" generated_definitions/isabelle/$(ARCH)/Riscv_types.thy > generated_definitions/isabelle/$(ARCH)/Riscv_types.thy.new - mv generated_definitions/isabelle/$(ARCH)/Riscv_types.thy.new generated_definitions/isabelle/$(ARCH)/Riscv_types.thy - sed "s/by pat_completeness auto/by pat_completeness (auto intro!: let_cong bind_cong MemoryOpResult.case_cong)/" generated_definitions/isabelle/$(ARCH)/Riscv.thy > generated_definitions/isabelle/$(ARCH)/Riscv.thy.new - mv generated_definitions/isabelle/$(ARCH)/Riscv.thy.new generated_definitions/isabelle/$(ARCH)/Riscv.thy - -generated_definitions/hol4/$(ARCH)/Holmakefile: handwritten_support/Holmakefile - mkdir -p generated_definitions/hol4/$(ARCH) - cp handwritten_support/Holmakefile generated_definitions/hol4/$(ARCH) - -generated_definitions/hol4/$(ARCH)/riscvScript.sml: generated_definitions/hol4/$(ARCH)/Holmakefile generated_definitions/lem/$(ARCH)/riscv.lem $(RISCV_EXTRAS_LEM) - lem -hol -outdir generated_definitions/hol4/$(ARCH) -lib $(SAIL_LIB_DIR)/hol -i $(SAIL_LIB_DIR)/hol/sail2_prompt_monad.lem -i $(SAIL_LIB_DIR)/hol/sail2_prompt.lem \ - -lib $(SAIL_DIR)/src/lem_interp -lib $(SAIL_DIR)/src/gen_lib \ - $(RISCV_EXTRAS_LEM) \ - generated_definitions/lem/$(ARCH)/riscv_types.lem \ - generated_definitions/lem/$(ARCH)/riscv.lem - -$(addprefix generated_definitions/hol4/$(ARCH)/,riscvTheory.uo riscvTheory.ui): generated_definitions/hol4/$(ARCH)/Holmakefile generated_definitions/hol4/$(ARCH)/riscvScript.sml -ifeq ($(wildcard $(LEM_DIR)/hol-lib),) - $(error Lem directory not found. Please set the LEM_DIR environment variable) -endif -ifeq ($(wildcard $(SAIL_LIB_DIR)/hol),) - $(error lib directory of Sail not found. Please set the SAIL_LIB_DIR environment variable) -endif - (cd generated_definitions/hol4/$(ARCH) && Holmake riscvTheory.uo) - -riscv_hol: generated_definitions/hol4/$(ARCH)/riscvScript.sml -riscv_hol_build: generated_definitions/hol4/$(ARCH)/riscvTheory.uo -.PHONY: riscv_hol riscv_hol_build - - -COQ_LIBS = -R generated_definitions/coq Riscv -R generated_definitions/coq/$(ARCH) $(ARCH) -R handwritten_support Riscv_common -COQ_LIBS += -Q $(BBV_DIR)/src/bbv bbv -COQ_LIBS += -Q $(SAIL_LIB_DIR)/coq Sail - -riscv_coq: $(addprefix generated_definitions/coq/$(ARCH)/,riscv.v riscv_types.v) -riscv_coq_build: generated_definitions/coq/$(ARCH)/riscv.vo -.PHONY: riscv_coq riscv_coq_build - -$(addprefix generated_definitions/coq/$(ARCH)/,riscv.v riscv_types.v): $(SAIL_COQ_SRCS) Makefile - mkdir -p generated_definitions/coq/$(ARCH) - $(SAIL) $(SAIL_FLAGS) -dcoq_undef_axioms -coq -coq_output_dir generated_definitions/coq/$(ARCH) -o riscv -coq_lib riscv_extras -coq_lib mem_metadata $(SAIL_COQ_SRCS) - -%.vo: %.v -ifeq ($(wildcard $(BBV_DIR)/src),) - $(error BBV directory not found. Please set the BBV_DIR environment variable) -endif -ifeq ($(wildcard $(SAIL_LIB_DIR)/coq),) - $(error lib directory of Sail not found. Please set the SAIL_LIB_DIR environment variable) -endif - coqc $(COQ_LIBS) $< - -generated_definitions/coq/$(ARCH)/riscv.vo: generated_definitions/coq/$(ARCH)/riscv_types.vo handwritten_support/riscv_extras.vo handwritten_support/mem_metadata.vo - -riscv_coq_install: - if [ ! -f generated_definitions/coq/RV64/riscv.v ]; then echo RV64 has not been built; false; fi - if [ ! -f generated_definitions/coq/RV32/riscv.v ]; then echo RV32 has not been built; false; fi - install -d `coqc -where`/user-contrib/Riscv_common - install -d `coqc -where`/user-contrib/RV64 - install -d `coqc -where`/user-contrib/RV32 - install handwritten_support/*.v* `coqc -where`/user-contrib/Riscv_common - install generated_definitions/coq/RV64/* `coqc -where`/user-contrib/RV64 - install generated_definitions/coq/RV32/* `coqc -where`/user-contrib/RV32 -.PHONY: riscv_coq_install - -echo_rmem_srcs: - echo $(SAIL_RMEM_SRCS) - -RMEM_FILES = generated_definitions/for-rmem/riscv.lem generated_definitions/for-rmem/riscv_types.lem generated_definitions/for-rmem/riscv_toFromInterp2.ml generated_definitions/for-rmem/riscv.defs - -riscv_rmem: generated_definitions/for-rmem/riscv.lem -riscv_rmem: generated_definitions/for-rmem/riscv_toFromInterp2.ml -riscv_rmem: generated_definitions/for-rmem/riscv.defs -.PHONY: riscv_rmem - -generated_definitions/for-rmem/riscv.lem: SAIL_FLAGS += -lem_lib Riscv_extras -lem_lib Riscv_extras_fdext -lem_lib Mem_metadata -generated_definitions/for-rmem/riscv.lem: $(SAIL_RMEM_SRCS) - mkdir -p $(dir $@) -# We do not need the isabelle .thy files, but sail always generates them - $(SAIL) $(SAIL_FLAGS) -lem -lem_mwords -lem_output_dir $(dir $@) -isa_output_dir $(dir $@) -o $(notdir $(basename $@)) $^ - -generated_definitions/for-rmem/riscv_toFromInterp2.ml: $(SAIL_RMEM_SRCS) - mkdir -p $(dir $@) - $(SAIL) $(SAIL_FLAGS) -tofrominterp -tofrominterp_lem -tofrominterp_mwords -tofrominterp_output_dir $(dir $@) -o riscv $^ - -generated_definitions/for-rmem/riscv.defs: $(SAIL_RMEM_SRCS) - mkdir -p $(dir $@) - $(SAIL) $(SAIL_FLAGS) -marshal -o $(basename $@) $^ - -# we exclude prelude.sail here, most code there should move to sail lib -#LOC_FILES:=$(SAIL_SRCS) main.sail -#include $(SAIL_DIR)/etc/loc.mk - -FORCE: - -SHARE_FILES:=$(sort $(wildcard model/*.sail)) $(sort $(wildcard emulator/*.c)) $(sort $(wildcard emulator/*.h)) $(sort $(wildcard handwritten_support/*.lem)) $(sort $(wildcard handwritten_support/hgen/*.hgen)) $(RMEM_FILES) -sail-riscv.install: FORCE - echo 'bin: ["emulator/riscv_sim_RV64" "emulator/riscv_sim_RV32"]' > sail-riscv.install - echo 'share: [ $(foreach f,$(SHARE_FILES),"$f" {"$f"}) ]' >> sail-riscv.install - -clean: - -rm -rf generated_definitions/c/* generated_definitions/latex/* - -rm -rf generated_definitions/lem/* generated_definitions/isabelle/* generated_definitions/hol4/* generated_definitions/coq/* - -rm -rf generated_definitions/for-rmem/* - -$(MAKE) -C $(SOFTFLOAT_LIBDIR) clean - -rm -f emulator/riscv_sim_RV32 emulator/riscv_sim_RV64 emulator/riscv_rvfi_RV32 emulator/riscv_rvfi_RV64 - -rm -f *.gcno *.gcda - -rm -f z3_problems - -Holmake cleanAll - -rm -f handwritten_support/riscv_extras.vo handwritten_support/riscv_extras.vos handwritten_support/riscv_extras.vok handwritten_support/riscv_extras.glob handwritten_support/.riscv_extras.aux - -rm -f handwritten_support/mem_metadata.vo handwritten_support/mem_metadata.vos handwritten_support/mem_metadata.vok handwritten_support/mem_metadata.glob handwritten_support/.mem_metadata.aux - -rm -f sail_doc/riscv_RV32.json - -rm -f sail_doc/riscv_RV64.json diff --git a/build_simulators.sh b/build_simulators.sh deleted file mode 100755 index 73fd5d206..000000000 --- a/build_simulators.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -function test_build () { - declare -i rc=0 - eval $* - rc=$? - if [ $rc -ne 0 ]; then - echo "Failure to execute: $*" - exit $rc - fi -} - -test_build make ARCH=RV32 emulator/riscv_sim_RV32 -test_build make ARCH=RV64 emulator/riscv_sim_RV64 diff --git a/cmake/extra_fast.cmake b/cmake/extra_fast.cmake new file mode 100644 index 000000000..745d52d0c --- /dev/null +++ b/cmake/extra_fast.cmake @@ -0,0 +1,28 @@ +include(CheckCXXCompilerFlag) + +# Enable agressive optimisation flags. + +# Try to use -march=x86-64-v3, but fall back to -march=native if we are +# using an old compiler that doesn't support that flag. +check_cxx_compiler_flag("-march=x86-64-v3" COMPILER_SUPPORTS_MARCH_X86_V3) +if (COMPILER_SUPPORTS_MARCH_X86_V3) + message(STATUS "Enabling -march=x86-64-v3") + add_compile_options("-march=x86-64-v3") +else() + # Must be quite old so try -march=native. + check_cxx_compiler_flag("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE) + if (COMPILER_SUPPORTS_MARCH_NATIVE) + message(STATUS "Enabling -march=native") + add_compile_options("-march=native") + endif() +endif() + +# This makes a measurable difference. +check_cxx_compiler_flag("-fomit-frame-pointer" COMPILER_SUPPORTS_FOMIT_FRAME_POINTER) +if (COMPILER_SUPPORTS_FOMIT_FRAME_POINTER) + message(STATUS "Enabling -fomit-frame-pointer") + add_compile_options("-fomit-frame-pointer") +endif() + +# LTO +set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE) diff --git a/cmake/modules/FindGMP.cmake b/cmake/modules/FindGMP.cmake new file mode 100644 index 000000000..7c2c8ca2b --- /dev/null +++ b/cmake/modules/FindGMP.cmake @@ -0,0 +1,46 @@ +# From https://github.com/Z3Prover/z3/blob/7f8e2a9f75f6c8b4b8ab05b87ea6a343d9a0b88d/cmake/modules/FindGMP.cmake +# with minor simplication to remove gmp++ and try pkg-config. + +# Tries to find an install of the GNU multiple precision library +# +# Once done this will define +# GMP_FOUND - BOOL: System has the GMP library installed +# GMP_C_LIBRARIES - LIST: The libraries needed to use GMP via it's C interface +# GMP_C_INCLUDES - LIST: The GMP include directories + +include(FindPackageHandleStandardArgs) + +find_package(PkgConfig) +if (PKG_CONFIG_FOUND) + pkg_check_modules(PC_GMP QUIET gmp) +endif() + +# Try to find libraries +find_library(GMP_C_LIBRARIES + NAMES gmp + PATHS ${PC_GMP_LIBRARY_DIRS} + DOC "GMP C libraries" +) + +# Try to find headers +find_path(GMP_C_INCLUDES + NAMES gmp.h + PATHS ${PC_GMP_INCLUDE_DIRS} + DOC "GMP C header" +) + +# TODO: We should check we can link some simple code against libgmp + +# Handle QUIET and REQUIRED and check the necessary variables were set and if so +# set ``GMP_FOUND`` +find_package_handle_standard_args(GMP + REQUIRED_VARS GMP_C_LIBRARIES GMP_C_INCLUDES) + +if (GMP_FOUND) + if (NOT TARGET GMP::GMP) + add_library(GMP::GMP UNKNOWN IMPORTED) + set_target_properties(GMP::GMP PROPERTIES + INTERFACE_INCLUDE_DIRECTORIES "${GMP_C_INCLUDES}" + IMPORTED_LOCATION "${GMP_C_LIBRARIES}") + endif() +endif() diff --git a/dependencies/softfloat/CMakeLists.txt b/dependencies/softfloat/CMakeLists.txt new file mode 100644 index 000000000..8a731f49f --- /dev/null +++ b/dependencies/softfloat/CMakeLists.txt @@ -0,0 +1,44 @@ +SET(source_dir "${CMAKE_CURRENT_SOURCE_DIR}/berkeley-softfloat-3") + +# Generic source plus RISC-V specific source. +file(GLOB riscv_source + "${source_dir}/source/*.c" + "${source_dir}/source/include/*.h" + "${source_dir}/source/RISCV/*.c" + "${source_dir}/source/RISCV/*.h" + "${source_dir}/build/Linux-RISCV-GCC/platform.h" +) + +# Some files do not work with SOFTFLOAT_FAST_INT64 +list(REMOVE_ITEM riscv_source + "${source_dir}/source/s_addExtF80M.c" + "${source_dir}/source/s_addF128M.c" + "${source_dir}/source/s_compareNonnormExtF80M.c" + "${source_dir}/source/s_invalidF128M.c" + "${source_dir}/source/s_mulAddF128M.c" + "${source_dir}/source/s_normRoundPackMToExtF80M.c" + "${source_dir}/source/s_normRoundPackMToF128M.c" + "${source_dir}/source/s_normSubnormalF128SigM.c" + "${source_dir}/source/s_roundPackMToExtF80M.c" + "${source_dir}/source/s_roundPackMToF128M.c" + "${source_dir}/source/s_shiftLeftM.c" + "${source_dir}/source/s_shiftNormSigF128M.c" + "${source_dir}/source/s_shiftRightJamM.c" + "${source_dir}/source/s_shiftRightM.c" + "${source_dir}/source/s_tryPropagateNaNExtF80M.c" + "${source_dir}/source/s_tryPropagateNaNF128M.c" + "${source_dir}/source/RISCV/s_propagateNaNF128M.c" + "${source_dir}/source/RISCV/s_commonNaNToF128M.c" +) + +add_library(softfloat + ${riscv_source} +) + +target_include_directories(softfloat PUBLIC + "${source_dir}/source/include" + "${source_dir}/source/RISCV" + "${source_dir}/build/Linux-RISCV64-GCC" +) + +target_compile_options(softfloat PRIVATE "-Werror=implicit-function-declaration" "-DSOFTFLOAT_ROUND_ODD") diff --git a/emulator/CMakeLists.txt b/emulator/CMakeLists.txt new file mode 100644 index 000000000..764163a20 --- /dev/null +++ b/emulator/CMakeLists.txt @@ -0,0 +1,44 @@ +set(EMULATOR_COMMON_SRCS + riscv_config.h + riscv_platform.c + riscv_platform.h + riscv_platform_impl.c + riscv_platform_impl.h + riscv_prelude.c + riscv_prelude.h + riscv_sail.h + riscv_sim.c + riscv_softfloat.c + riscv_softfloat.h +) + +foreach (arch IN LISTS ENABLED_ARCHITECTURES) + add_executable(emulator_${arch} + "${CMAKE_BINARY_DIR}/riscv_model_${arch}.c" + ${EMULATOR_COMMON_SRCS} + ) + + add_dependencies(emulator_${arch} generated_model_${arch}) + + target_link_libraries(emulator_${arch} + PRIVATE softfloat sail_runtime GMP::GMP ZLIB::ZLIB + ) + + target_include_directories(emulator_${arch} + # So the generated C can find riscv_platform/prelude.h" + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}" + ) + + # TODO: Enable warnings when we use the #include trick + # to include the generated Sail code. Currently it + # generates too many warnings to turn these on globally. + + # target_compile_options(emulator_${arch} PRIVATE + # -Wall -Wextra + # # Too annoying at the moment. + # -Wno-unused-parameter + # ) + + install(TARGETS emulator_${arch}) + +endforeach() diff --git a/model/CMakeLists.txt b/model/CMakeLists.txt new file mode 100644 index 000000000..1df6c937b --- /dev/null +++ b/model/CMakeLists.txt @@ -0,0 +1,268 @@ +foreach (arch IN LISTS ENABLED_ARCHITECTURES) + if (arch STREQUAL "rv32") + set(xlen 32) + set(flen 32) + elseif (arch STREQUAL "rv64") + set(xlen 64) + set(flen 64) + elseif (arch STREQUAL "rv32d") + set(xlen 32) + set(flen 64) + elseif (arch STREQUAL "rv64f") + set(xlen 64) + set(flen 32) + else() + message(FATAL_ERROR "Invalid architecture: ${arch}") + endif() + + set(sail_xlen + "riscv_xlen${xlen}.sail" + "riscv_xlen.sail" + ) + + # TODO: Unfortunately 32 or 64 bit float support is a compile time. + # See https://github.com/riscv/sail-riscv/issues/348 + if (flen EQUAL 64) + set(sail_flen "riscv_flen_D.sail") + else() + set(sail_flen "riscv_flen_F.sail") + endif() + list(APPEND sail_flen "riscv_flen.sail") + + set(sail_vlen "riscv_vlen.sail") + + # Instruction sources, depending on target + set(sail_check_srcs + "riscv_addr_checks_common.sail" + "riscv_addr_checks.sail" + "riscv_misa_ext.sail" + ) + + set(vext_srcs + "riscv_insts_vext_utils.sail" + "riscv_insts_vext_fp_utils.sail" + "riscv_insts_vext_vset.sail" + "riscv_insts_vext_arith.sail" + "riscv_insts_vext_fp.sail" + "riscv_insts_vext_mem.sail" + "riscv_insts_vext_mask.sail" + "riscv_insts_vext_vm.sail" + "riscv_insts_vext_fp_vm.sail" + "riscv_insts_vext_red.sail" + "riscv_insts_vext_fp_red.sail" + ) + + set(sail_default_inst + "riscv_insts_base.sail" + "riscv_insts_zifencei.sail" + "riscv_insts_aext.sail" + "riscv_insts_zca.sail" + "riscv_insts_mext.sail" + "riscv_insts_zicsr.sail" + "riscv_insts_hints.sail" + "riscv_insts_fext.sail" + "riscv_insts_zcf.sail" + "riscv_insts_dext.sail" + "riscv_insts_zcd.sail" + "riscv_insts_svinval.sail" + "riscv_insts_zba.sail" + "riscv_insts_zbb.sail" + "riscv_insts_zbc.sail" + "riscv_insts_zbs.sail" + "riscv_insts_zcb.sail" + "riscv_insts_zfh.sail" + # Zfa needs to be added after fext, dext and Zfh (as it needs + # definitions from those) + "riscv_insts_zfa.sail" + "riscv_insts_zkn.sail" + "riscv_insts_zks.sail" + "riscv_insts_zbkb.sail" + "riscv_insts_zbkx.sail" + "riscv_insts_zicond.sail" + ${vext_srcs} + "riscv_insts_zicbom.sail" + "riscv_insts_zicboz.sail" + ) + + set(sail_seq_inst + ${sail_default_inst} + "riscv_jalr_seq.sail" + ) + + set(sail_seq_inst_srcs + "riscv_insts_begin.sail" + ${sail_seq_inst} + "riscv_insts_end.sail" + "riscv_csr_end.sail" + ) + + set(sail_sys_srcs + "riscv_vext_control.sail" + "riscv_sys_exceptions.sail" + "riscv_sync_exception.sail" + "riscv_zihpm.sail" + "riscv_zkr_control.sail" + "riscv_zicntr_control.sail" + "riscv_softfloat_interface.sail" + "riscv_fdext_regs.sail" + "riscv_fdext_control.sail" + "riscv_sys_control.sail" + ) + + set(sail_vm_srcs + "riscv_vmem_common.sail" + "riscv_vmem_pte.sail" + "riscv_vmem_ptw.sail" + "riscv_vmem_tlb.sail" + "riscv_vmem.sail" + ) + + set(prelude + "prelude.sail" + "riscv_errors.sail" + ${sail_xlen} + ${sail_flen} + ${sail_vlen} + "prelude_mem_addrtype.sail" + "prelude_mem_metadata.sail" + "prelude_mem.sail" + ) + + set(sail_regs_srcs + "riscv_csr_begin.sail" + "riscv_reg_type.sail" + "riscv_freg_type.sail" + "riscv_regs.sail" + "riscv_pc_access.sail" + "riscv_sys_regs.sail" + "riscv_pmp_regs.sail" + "riscv_pmp_control.sail" + "riscv_ext_regs.sail" + ${sail_check_srcs} + "riscv_vreg_type.sail" + "riscv_vext_regs.sail" + ) + + set(sail_arch_srcs + ${prelude} + "riscv_extensions.sail" + "riscv_types_common.sail" + "riscv_types_ext.sail" + "riscv_types.sail" + "riscv_vmem_types.sail" + ${sail_regs_srcs} + ${sail_sys_srcs} + "riscv_platform.sail" + "riscv_mem.sail" + ${sail_vm_srcs} + # Shared/common code for the cryptography extension. + "riscv_types_kext.sail" + ) + + set(sail_step_srcs + "riscv_step_common.sail" + "riscv_step_ext.sail" + "riscv_decode_ext.sail" + "riscv_fetch.sail" + "riscv_step.sail" + ) + + # Final file list. + set(sail_srcs + ${sail_arch_srcs} + ${sail_seq_inst_srcs} + ${sail_step_srcs} + "main.sail" + ) + + # The list above can be compared with the ones you get from + # + # VERBOSE=1 make ARCH=RV32 c_emulator/riscv_sim_RV32 + # VERBOSE=1 make ARCH=RV64 c_emulator/riscv_sim_RV64 + # VERBOSE=1 make ARCH=RV32 c_emulator/cheri_riscv_sim_rv32 + # VERBOSE=1 make ARCH=RV64 c_emulator/cheri_riscv_sim_rv64 + # + # The order is sometimes important because Sail is single pass. Code can't + # see declarations that come later. + + # Generate C code from Sail model. This is a single C file. + set(c_model_no_ext "${CMAKE_BINARY_DIR}/riscv_model_${arch}") + set(c_model "${c_model_no_ext}.c") + set(branch_info_file "${c_model_no_ext}.branch_info") + + add_custom_command( + DEPENDS ${sail_srcs} + OUTPUT ${c_model} ${branch_info_file} + VERBATIM + COMMENT "Building C code from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + sail + # Output file (without extension). + -o ${c_model_no_ext} + # Generate a file containing information about all possible branches. + # See https://github.com/rems-project/sail/blob/sail2/sailcov/README.md + # --c-coverage ${branch_info_file} + # Don't allow implicit var declaration (like Python). This is + # deprecated because it is error-prone. + --strict-var + # Optimisations. + -O --Oconstant-fold + # Cache Z3 results in z3_problems file to speed up incremental compilation. + --memo-z3 + # Output C code. + -c + # Don't generate a main() function. + --c-no-main + # Extra #include's. + --c-include riscv_prelude.h + --c-include riscv_platform.h + # Don't dead-code eliminate these functions. These should match the + # ones used from riscv_sail.h + --c-preserve init_model + --c-preserve step + --c-preserve tick_clock + --c-preserve tick_platform + --c-preserve _set_Misa_C + --c-preserve _set_Misa_D + --c-preserve _set_Misa_F + # Input files. + ${sail_srcs} + ) + + add_custom_target(generated_model_${arch} DEPENDS ${c_model}) + + set(model_doc "riscv_model_${arch}.json") + + # JSON code snippets output. + add_custom_command( + DEPENDS ${sail_srcs} + OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/${model_doc}" + VERBATIM + COMMENT "Building documentation JSON from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + # Generate JSON documentation file. + -doc + # Format to interpret comments as. You can also use 'asciidoc' + # in which case it will interpret them as Markdown and output them + # as Asciidoc, but there's a bug in the Sail compiler so it can't + # parse the Markdown and it doesn't seem to output the comments + # anyway. + -doc_format identity + # Don't pretty-print the JSON output. It's too big to be readable anyway. + -doc_compact + # Actually embed the code snippets in the JSON as plain text rather + # than referencing them. The other option is base64. + -doc_embed plain + # The directory that the JSON will be saved in. + -o ${CMAKE_CURRENT_BINARY_DIR} + # The name of the JSON file. + -doc_bundle ${model_doc} + # Input files. + ${sail_srcs} + ) + + add_custom_target(generated_docs_${arch} DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/${model_doc}") +endforeach() diff --git a/sail-riscv.install b/sail-riscv.install deleted file mode 100644 index 3a7673e29..000000000 --- a/sail-riscv.install +++ /dev/null @@ -1,2 +0,0 @@ -bin: ["emulator/riscv_sim_RV64" "emulator/riscv_sim_RV32"] -share: [ "model/main.sail" {"model/main.sail"} "model/prelude.sail" {"model/prelude.sail"} "model/prelude_mem.sail" {"model/prelude_mem.sail"} "model/prelude_mem_metadata.sail" {"model/prelude_mem_metadata.sail"} "model/riscv_addr_checks.sail" {"model/riscv_addr_checks.sail"} "model/riscv_addr_checks_common.sail" {"model/riscv_addr_checks_common.sail"} "model/riscv_analysis.sail" {"model/riscv_analysis.sail"} "model/riscv_csr_ext.sail" {"model/riscv_csr_ext.sail"} "model/riscv_csr_map.sail" {"model/riscv_csr_map.sail"} "model/riscv_decode_ext.sail" {"model/riscv_decode_ext.sail"} "model/riscv_ext_regs.sail" {"model/riscv_ext_regs.sail"} "model/riscv_fdext_control.sail" {"model/riscv_fdext_control.sail"} "model/riscv_fdext_regs.sail" {"model/riscv_fdext_regs.sail"} "model/riscv_fetch.sail" {"model/riscv_fetch.sail"} "model/riscv_fetch_rvfi.sail" {"model/riscv_fetch_rvfi.sail"} "model/riscv_flen_D.sail" {"model/riscv_flen_D.sail"} "model/riscv_flen_F.sail" {"model/riscv_flen_F.sail"} "model/riscv_freg_type.sail" {"model/riscv_freg_type.sail"} "model/riscv_insts_aext.sail" {"model/riscv_insts_aext.sail"} "model/riscv_insts_base.sail" {"model/riscv_insts_base.sail"} "model/riscv_insts_begin.sail" {"model/riscv_insts_begin.sail"} "model/riscv_insts_cdext.sail" {"model/riscv_insts_cdext.sail"} "model/riscv_insts_cext.sail" {"model/riscv_insts_cext.sail"} "model/riscv_insts_cfext.sail" {"model/riscv_insts_cfext.sail"} "model/riscv_insts_dext.sail" {"model/riscv_insts_dext.sail"} "model/riscv_insts_end.sail" {"model/riscv_insts_end.sail"} "model/riscv_insts_fext.sail" {"model/riscv_insts_fext.sail"} "model/riscv_insts_hints.sail" {"model/riscv_insts_hints.sail"} "model/riscv_insts_mext.sail" {"model/riscv_insts_mext.sail"} "model/riscv_insts_next.sail" {"model/riscv_insts_next.sail"} "model/riscv_insts_rmem.sail" {"model/riscv_insts_rmem.sail"} "model/riscv_insts_zba.sail" {"model/riscv_insts_zba.sail"} "model/riscv_insts_zbb.sail" {"model/riscv_insts_zbb.sail"} "model/riscv_insts_zbc.sail" {"model/riscv_insts_zbc.sail"} "model/riscv_insts_zbkb.sail" {"model/riscv_insts_zbkb.sail"} "model/riscv_insts_zbkx.sail" {"model/riscv_insts_zbkx.sail"} "model/riscv_insts_zbs.sail" {"model/riscv_insts_zbs.sail"} "model/riscv_insts_zfh.sail" {"model/riscv_insts_zfh.sail"} "model/riscv_insts_zicsr.sail" {"model/riscv_insts_zicsr.sail"} "model/riscv_insts_zkn.sail" {"model/riscv_insts_zkn.sail"} "model/riscv_insts_zks.sail" {"model/riscv_insts_zks.sail"} "model/riscv_jalr_rmem.sail" {"model/riscv_jalr_rmem.sail"} "model/riscv_jalr_seq.sail" {"model/riscv_jalr_seq.sail"} "model/riscv_mem.sail" {"model/riscv_mem.sail"} "model/riscv_misa_ext.sail" {"model/riscv_misa_ext.sail"} "model/riscv_next_control.sail" {"model/riscv_next_control.sail"} "model/riscv_next_regs.sail" {"model/riscv_next_regs.sail"} "model/riscv_pc_access.sail" {"model/riscv_pc_access.sail"} "model/riscv_platform.sail" {"model/riscv_platform.sail"} "model/riscv_pmp_control.sail" {"model/riscv_pmp_control.sail"} "model/riscv_pmp_regs.sail" {"model/riscv_pmp_regs.sail"} "model/riscv_pte.sail" {"model/riscv_pte.sail"} "model/riscv_ptw.sail" {"model/riscv_ptw.sail"} "model/riscv_reg_type.sail" {"model/riscv_reg_type.sail"} "model/riscv_regs.sail" {"model/riscv_regs.sail"} "model/riscv_softfloat_interface.sail" {"model/riscv_softfloat_interface.sail"} "model/riscv_step.sail" {"model/riscv_step.sail"} "model/riscv_step_common.sail" {"model/riscv_step_common.sail"} "model/riscv_step_ext.sail" {"model/riscv_step_ext.sail"} "model/riscv_step_rvfi.sail" {"model/riscv_step_rvfi.sail"} "model/riscv_sync_exception.sail" {"model/riscv_sync_exception.sail"} "model/riscv_sys_control.sail" {"model/riscv_sys_control.sail"} "model/riscv_sys_exceptions.sail" {"model/riscv_sys_exceptions.sail"} "model/riscv_sys_regs.sail" {"model/riscv_sys_regs.sail"} "model/riscv_termination_common.sail" {"model/riscv_termination_common.sail"} "model/riscv_termination_rv32.sail" {"model/riscv_termination_rv32.sail"} "model/riscv_termination_rv64.sail" {"model/riscv_termination_rv64.sail"} "model/riscv_types.sail" {"model/riscv_types.sail"} "model/riscv_types_common.sail" {"model/riscv_types_common.sail"} "model/riscv_types_ext.sail" {"model/riscv_types_ext.sail"} "model/riscv_types_kext.sail" {"model/riscv_types_kext.sail"} "model/riscv_vmem_common.sail" {"model/riscv_vmem_common.sail"} "model/riscv_vmem_rv32.sail" {"model/riscv_vmem_rv32.sail"} "model/riscv_vmem_rv64.sail" {"model/riscv_vmem_rv64.sail"} "model/riscv_vmem_sv32.sail" {"model/riscv_vmem_sv32.sail"} "model/riscv_vmem_sv39.sail" {"model/riscv_vmem_sv39.sail"} "model/riscv_vmem_sv48.sail" {"model/riscv_vmem_sv48.sail"} "model/riscv_vmem_tlb.sail" {"model/riscv_vmem_tlb.sail"} "model/riscv_vmem_types.sail" {"model/riscv_vmem_types.sail"} "model/riscv_xlen32.sail" {"model/riscv_xlen32.sail"} "model/riscv_xlen64.sail" {"model/riscv_xlen64.sail"} "model/rvfi_dii.sail" {"model/rvfi_dii.sail"} "emulator/riscv_platform.c" {"emulator/riscv_platform.c"} "emulator/riscv_platform_impl.c" {"emulator/riscv_platform_impl.c"} "emulator/riscv_prelude.c" {"emulator/riscv_prelude.c"} "emulator/riscv_sim.c" {"emulator/riscv_sim.c"} "emulator/riscv_softfloat.c" {"emulator/riscv_softfloat.c"} "emulator/riscv_config.h" {"emulator/riscv_config.h"} "emulator/riscv_platform.h" {"emulator/riscv_platform.h"} "emulator/riscv_platform_impl.h" {"emulator/riscv_platform_impl.h"} "emulator/riscv_prelude.h" {"emulator/riscv_prelude.h"} "emulator/riscv_sail.h" {"emulator/riscv_sail.h"} "emulator/riscv_softfloat.h" {"emulator/riscv_softfloat.h"} "handwritten_support/mem_metadata.lem" {"handwritten_support/mem_metadata.lem"} "handwritten_support/riscv_extras.lem" {"handwritten_support/riscv_extras.lem"} "handwritten_support/riscv_extras_fdext.lem" {"handwritten_support/riscv_extras_fdext.lem"} "handwritten_support/riscv_extras_sequential.lem" {"handwritten_support/riscv_extras_sequential.lem"} "handwritten_support/hgen/ast.hgen" {"handwritten_support/hgen/ast.hgen"} "handwritten_support/hgen/fold.hgen" {"handwritten_support/hgen/fold.hgen"} "handwritten_support/hgen/herdtools_ast_to_shallow_ast.hgen" {"handwritten_support/hgen/herdtools_ast_to_shallow_ast.hgen"} "handwritten_support/hgen/herdtools_types_to_shallow_types.hgen" {"handwritten_support/hgen/herdtools_types_to_shallow_types.hgen"} "handwritten_support/hgen/lexer.hgen" {"handwritten_support/hgen/lexer.hgen"} "handwritten_support/hgen/lexer_regexps.hgen" {"handwritten_support/hgen/lexer_regexps.hgen"} "handwritten_support/hgen/map.hgen" {"handwritten_support/hgen/map.hgen"} "handwritten_support/hgen/parser.hgen" {"handwritten_support/hgen/parser.hgen"} "handwritten_support/hgen/pretty.hgen" {"handwritten_support/hgen/pretty.hgen"} "handwritten_support/hgen/pretty_xml.hgen" {"handwritten_support/hgen/pretty_xml.hgen"} "handwritten_support/hgen/sail_trans_out.hgen" {"handwritten_support/hgen/sail_trans_out.hgen"} "handwritten_support/hgen/shallow_ast_to_herdtools_ast.hgen" {"handwritten_support/hgen/shallow_ast_to_herdtools_ast.hgen"} "handwritten_support/hgen/shallow_types_to_herdtools_types.hgen" {"handwritten_support/hgen/shallow_types_to_herdtools_types.hgen"} "handwritten_support/hgen/token_types.hgen" {"handwritten_support/hgen/token_types.hgen"} "handwritten_support/hgen/tokens.hgen" {"handwritten_support/hgen/tokens.hgen"} "handwritten_support/hgen/trans_sail.hgen" {"handwritten_support/hgen/trans_sail.hgen"} "handwritten_support/hgen/types.hgen" {"handwritten_support/hgen/types.hgen"} "handwritten_support/hgen/types_sail_trans_out.hgen" {"handwritten_support/hgen/types_sail_trans_out.hgen"} "handwritten_support/hgen/types_trans_sail.hgen" {"handwritten_support/hgen/types_trans_sail.hgen"} "handwritten_support/0.11/mem_metadata.lem" {"handwritten_support/0.11/mem_metadata.lem"} "handwritten_support/0.11/riscv_extras.lem" {"handwritten_support/0.11/riscv_extras.lem"} "handwritten_support/0.11/riscv_extras_fdext.lem" {"handwritten_support/0.11/riscv_extras_fdext.lem"} "handwritten_support/0.11/riscv_extras_sequential.lem" {"handwritten_support/0.11/riscv_extras_sequential.lem"} "generated_definitions/for-rmem/riscv.lem" {"generated_definitions/for-rmem/riscv.lem"} "generated_definitions/for-rmem/riscv_types.lem" {"generated_definitions/for-rmem/riscv_types.lem"} "generated_definitions/for-rmem/riscv_toFromInterp2.ml" {"generated_definitions/for-rmem/riscv_toFromInterp2.ml"} "generated_definitions/for-rmem/riscv.defs" {"generated_definitions/for-rmem/riscv.defs"} ] diff --git a/sail_runtime/CMakeLists.txt b/sail_runtime/CMakeLists.txt new file mode 100644 index 000000000..dd7f9275f --- /dev/null +++ b/sail_runtime/CMakeLists.txt @@ -0,0 +1,23 @@ +execute_process( + COMMAND ${SAIL_BIN} --dir + OUTPUT_VARIABLE sail_dir + OUTPUT_STRIP_TRAILING_WHITESPACE + COMMAND_ERROR_IS_FATAL ANY +) + +add_library(sail_runtime + "${sail_dir}/lib/elf.c" + "${sail_dir}/lib/elf.h" + "${sail_dir}/lib/rts.c" + "${sail_dir}/lib/rts.h" + "${sail_dir}/lib/sail.c" + "${sail_dir}/lib/sail.h" + "${sail_dir}/lib/sail_failure.c" + "${sail_dir}/lib/sail_failure.h" + "${sail_dir}/lib/sail_coverage.h" + "${sail_dir}/lib/sail_state.h" +) + +target_include_directories(sail_runtime + PUBLIC "${sail_dir}/lib" +) diff --git a/test/get_perf.py b/test/get_perf.py deleted file mode 100755 index 1570cac4f..000000000 --- a/test/get_perf.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/python -# Estimates the performance of the C backend based on aggregating the unit-tests. -# Assumes a complete run over the unit-tests has been done. - -import os, glob - -def test_perf(d, test_pat, test_type): - couts = glob.glob(os.path.join(d, test_pat)) - if len(couts) == 0: return - - total_insts = 0 - total_msecs = 0 - for c in couts: - with open(c, "r") as f: - insts = 0 - msecs = 0 - perf = None - for l in f.readlines(): - if l.startswith("Instructions:"): insts = int(l.split()[1]) - if l.startswith("Execution:"): msecs = int(l.split()[1]) - if l.startswith("Perf:"): perf = l - #print("Test {0}: {1} insts, {2} msecs".format(c, insts, msecs)) - #if perf: print(perf) - total_insts += insts - total_msecs += msecs - - Kips = total_insts/total_msecs if total_msecs != 0 else float("nan") - print("Average {0} performance: {1} Kips".format(test_type, Kips)) - -def get_test_pat(iset, emode): - return "rv64{0}-{1}-*.cout".format(iset, emode) - -if __name__ == '__main__': - test_dir = os.path.join(os.path.dirname(__file__), "riscv-tests") - for mode in ["p", "v"]: - test_perf(test_dir, get_test_pat("ui", mode), "ui-{0}".format(mode)) - test_perf(test_dir, get_test_pat("um", mode), "um-{0}".format(mode)) - test_perf(test_dir, get_test_pat("ua", mode), "ua-{0}".format(mode)) - test_perf(test_dir, get_test_pat("uc", mode), "uc-{0}".format(mode)) - test_perf(test_dir, get_test_pat("si", mode), "si-{0}".format(mode)) - test_perf(test_dir, get_test_pat("mi", mode), "mi-{0}".format(mode)) - test_perf(test_dir, get_test_pat("*", mode), mode) diff --git a/test/riscv-tests/.gitignore b/test/riscv-tests/.gitignore deleted file mode 100644 index 72a5e441e..000000000 --- a/test/riscv-tests/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.out -*.cout diff --git a/test/riscv-tests/CMakeLists.txt b/test/riscv-tests/CMakeLists.txt new file mode 100644 index 000000000..c5304284f --- /dev/null +++ b/test/riscv-tests/CMakeLists.txt @@ -0,0 +1,46 @@ +# Run the emulator with all the ELF files in lib/sail-riscv/test/riscv-tests/rv32*.elf etc. +# +# On success or failure they write to the `tohost` symbol. See this code: +# https://github.com/riscv/riscv-test-env/blob/4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46/p/riscv_test.h#L200 + +file(GLOB elfs_rv32 CONFIGURE_DEPENDS "${CMAKE_CURRENT_SOURCE_DIR}/rv32*.elf") +file(GLOB elfs_rv64 CONFIGURE_DEPENDS "${CMAKE_CURRENT_SOURCE_DIR}/rv64*.elf") + +foreach (arch IN LISTS ENABLED_ARCHITECTURES) + set(elfs) + if (arch STREQUAL "rv32") + list(APPEND elfs ${elfs_rv32}) + endif() + if (arch STREQUAL "rv64") + list(APPEND elfs ${elfs_rv64}) + endif() + + foreach(elf IN LISTS elfs) + file(RELATIVE_PATH elf_name "${CMAKE_CURRENT_SOURCE_DIR}" ${elf}) + + if (elf_name MATCHES "breakpoint") + continue() + endif() + + # rv64mi-p-access jumps to an address with the top bit set. It expects an + # access fault, but that isn't necessarily the case. + if (elf_name STREQUAL "rv64mi-p-access.elf") + continue() + endif() + # These test RV32 with the D extension, but we have disabled D on RV32. + if (elf_name MATCHES "rv32ud") + continue() + endif() + + # These tests assume that certain bits of medeleg are writable, which + # isn't necessarily the case. + if (elf_name MATCHES "rv(32|64)si-p-(csr|ma_fetch|sbreak|scall).elf") + continue() + endif() + + add_test( + NAME "${arch}_${elf_name}" + COMMAND $ ${elf} + ) + endforeach() +endforeach() diff --git a/test/run_fp_tests.sh b/test/run_fp_tests.sh deleted file mode 100755 index 6d48fdb5c..000000000 --- a/test/run_fp_tests.sh +++ /dev/null @@ -1,97 +0,0 @@ -#!/usr/bin/env bash -set -e - -DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" -cd $DIR -RISCVDIR="$DIR/.." - -RED='\033[0;91m' -GREEN='\033[0;92m' -YELLOW='\033[0;93m' -NC='\033[0m' - -rm -f $DIR/tests.xml - -pass=0 -fail=0 -all_pass=0 -all_fail=0 -SUITE_XML="" -SUITES_XML="" - -function green { - (( pass += 1 )) - printf "$1: ${GREEN}$2${NC}\n" - SUITE_XML+=" \n" -} - -function yellow { - (( fail += 1 )) - printf "$1: ${YELLOW}$2${NC}\n" - SUITE_XML+=" \n $2\n \n" -} - -function red { - (( fail += 1 )) - printf "$1: ${RED}$2${NC}\n" - SUITE_XML+=" \n $2\n \n" -} - -function finish_suite { - printf "$1: Passed ${pass} out of $(( pass + fail ))\n\n" - SUITES_XML+=" \n$SUITE_XML \n" - SUITE_XML="" - (( all_pass += pass )) || : - (( all_fail += fail )) || : - pass=0 - fail=0 -} - -SAILLIBDIR="$DIR/../../lib/" - -cd $RISCVDIR - -# Do 'make clean' to avoid cross-arch pollution. -make clean - -if make emulator/riscv_sim_RV64; -then - green "Building 64-bit RISCV C emulator" "ok" -else - red "Building 64-bit RISCV C emulator" "fail" -fi -for test in $DIR/riscv-tests/rv64u{f,d}*.elf $DIR/riscv-tests/rv64mi-p-csr.elf; do - if timeout 5 $RISCVDIR/emulator/riscv_sim_RV64 -p $test > ${test%.elf}.cout 2>&1 && grep -q SUCCESS ${test%.elf}.cout - then - green "C-64 $(basename $test)" "ok" - else - red "C-64 $(basename $test)" "fail" - fi -done -finish_suite "64-bit RISCV C tests" - - -if ARCH=RV32 make emulator/riscv_sim_RV32; -then - green "Building 32-bit RISCV C emulator" "ok" -else - red "Building 32-bit RISCV C emulator" "fail" -fi -for test in $DIR/riscv-tests/rv32u{f,d}*.elf $DIR/riscv-tests/rv32mi-p-csr.elf; do - if timeout 5 $RISCVDIR/emulator/riscv_sim_RV32 -p $test > ${test%.elf}.cout 2>&1 && grep -q SUCCESS ${test%.elf}.cout - then - green "C-32 $(basename $test)" "ok" - else - red "C-32 $(basename $test)" "fail" - fi -done -finish_suite "32-bit RISCV C tests" - -printf "Passed ${all_pass} out of $(( all_pass + all_fail ))\n\n" -XML="\n$SUITES_XML\n" -printf "$XML" > $DIR/tests.xml - -if [ $all_fail -gt 0 ] -then - exit 1 -fi diff --git a/test/run_tests.sh b/test/run_tests.sh deleted file mode 100755 index 106bbc9bb..000000000 --- a/test/run_tests.sh +++ /dev/null @@ -1,125 +0,0 @@ -#!/usr/bin/env bash -set -e - -DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" -cd $DIR -RISCVDIR="$DIR/.." - -RED='\033[0;91m' -GREEN='\033[0;92m' -YELLOW='\033[0;93m' -NC='\033[0m' - -rm -f $DIR/tests.xml - -pass=0 -fail=0 -all_pass=0 -all_fail=0 -SUITE_XML="" -SUITES_XML="" - -function green { - (( pass += 1 )) - printf "$1: ${GREEN}$2${NC}\n" - SUITE_XML+=" \n" -} - -function yellow { - (( fail += 1 )) - printf "$1: ${YELLOW}$2${NC}\n" - SUITE_XML+=" \n $2\n \n" -} - -function red { - (( fail += 1 )) - printf "$1: ${RED}$2${NC}\n" - SUITE_XML+=" \n $2\n \n" -} - -function finish_suite { - printf "$1: Passed ${pass} out of $(( pass + fail ))\n\n" - SUITES_XML+=" \n$SUITE_XML \n" - SUITE_XML="" - (( all_pass += pass )) || : - (( all_fail += fail )) || : - pass=0 - fail=0 -} - -SAILLIBDIR="$DIR/../../lib/" - -cd $RISCVDIR - -# Do 'make clean' to avoid cross-arch pollution. -make clean - -printf "Building 32-bit RISCV specification...\n" - -if ARCH=RV32 make emulator/riscv_sim_RV32; -then - green "Building 32-bit RISCV C emulator" "ok" -else - red "Building 32-bit RISCV C emulator" "fail" -fi -for test in $DIR/riscv-tests/rv32*.elf; do - if timeout 5 $RISCVDIR/emulator/riscv_sim_RV32 -p $test > ${test%.elf}.cout 2>&1 && grep -q SUCCESS ${test%.elf}.cout - then - green "C-32 $(basename $test)" "ok" - else - red "C-32 $(basename $test)" "fail" - fi -done -finish_suite "32-bit RISCV C tests" - -# Do 'make clean' to avoid cross-arch pollution. -make clean - -printf "Building 64-bit RISCV specification...\n" - -if make emulator/riscv_sim_RV64; -then - green "Building 64-bit RISCV C emulator" "ok" -else - red "Building 64-bit RISCV C emulator" "fail" -fi -for test in $DIR/riscv-tests/rv64*.elf; do - if timeout 5 $RISCVDIR/emulator/riscv_sim_RV64 -p $test > ${test%.elf}.cout 2>&1 && grep -q SUCCESS ${test%.elf}.cout - then - green "C-64 $(basename $test)" "ok" - else - red "C-64 $(basename $test)" "fail" - fi -done -finish_suite "64-bit RISCV C tests" - -# Do 'make clean' to avoid cross-arch pollution. -make clean - -if ARCH=RV32 make emulator/riscv_rvfi_RV32; -then - green "Building 32-bit RISCV RVFI C emulator" "ok" -else - red "Building 32-bit RISCV RVFI C emulator" "fail" -fi -finish_suite "32-bit RISCV RVFI C tests" - -# Do 'make clean' to avoid cross-arch pollution. -make clean - -if ARCH=RV64 make emulator/riscv_rvfi_RV64; -then - green "Building 64-bit RISCV RVFI C emulator" "ok" -else - red "Building 64-bit RISCV RVFI C emulator" "fail" -fi -finish_suite "64-bit RISCV RVFI C tests" - -printf "Passed ${all_pass} out of $(( all_pass + all_fail ))\n\n" -XML="\n$SUITES_XML\n" -printf "$XML" > $DIR/tests.xml - -if [ $all_fail -gt 0 ] -then - exit 1 -fi