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This repository has been archived by the owner on Mar 20, 2024. It is now read-only.
I have a question about issue #602. This issue mentions that the "renamed implementations" will be simplified when the agnostic approach is adopted. #602
I believe that the tail agnostic scheme simplifies a scenario when LMUL=8, SEW=8. In other cases, since the result does not overwrite a full vector register, bits beyond VLMAX should retain their original value, right? I believe we need to optimize mask register implementations and provide further details about the bits beyond VLMAX. If we wish to keep the current specification definition, the mask instruction must merge the result with the original data when VLMAX ≠ VLENB.
VLEN=64, SEW=16, LMUL=2, VLMAX=8, vl=4. vta=1
va = 'h00000000_12345678
vmseq va, vb, vc # bit[3:0] will be updated according to setting. let 4-bit result to 4'he
va = 'h00000000_123456FX # 8'b78->8'hfe, bits beyond VLMAX retain their original value. Is it correct for bits beyond VLMAX?
Thanks,
Larry
The text was updated successfully, but these errors were encountered:
Hello,
I have a question about issue #602. This issue mentions that the "renamed implementations" will be simplified when the agnostic approach is adopted.
#602
I believe that the tail agnostic scheme simplifies a scenario when LMUL=8, SEW=8. In other cases, since the result does not overwrite a full vector register, bits beyond VLMAX should retain their original value, right? I believe we need to optimize mask register implementations and provide further details about the bits beyond VLMAX. If we wish to keep the current specification definition, the mask instruction must merge the result with the original data when VLMAX ≠ VLENB.
Thanks,
Larry
The text was updated successfully, but these errors were encountered: