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alt_dma.c
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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
/*
* $Id: //acds/rel/19.1std/embedded/ip/hps/altera_hps/hwlib/src/hwmgr/alt_dma.c#1 $
*/
#include <stdio.h>
#include <stdlib.h>
#include <inttypes.h>
#include "alt_printf.h"
#include "alt_cache.h"
#include "alt_dma.h"
#include "alt_mmu.h"
#include "socal/alt_rstmgr.h"
#include "socal/alt_sysmgr.h"
#if ALT_DMA_PERIPH_PROVISION_I2C_SUPPORT
#include "socal/alt_i2c.h"
#endif
#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT
#include "socal/alt_qspi.h"
#endif
#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT
#include "alt_16550_uart.h"
#include "socal/alt_uart.h"
#endif
#if defined(soc_a10)
#include "socal/alt_ecc_dmac.h"
#endif
#include "socal/socal.h"
#include "socal/hps.h"
#ifndef ARRAY_COUNT
#define ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0]))
#endif
#ifdef DEBUG_ALT_DMA
#define dprintf printf
#else
#define dprintf null_printf
#endif
/*
* SoCAL stand in for DMA Controller registers
*
* The base can be one of the following:
* - ALT_DMANONSECURE_ADDR
* - ALT_DMASECURE_ADDR
*
* Macros which have a channel parameter does no validation.
* */
#if defined(soc_a10)
#define ALT_DMASECURE_ADDR ALT_DMA_SCTL_ADDR
#define ALT_DMANONSECURE_ADDR ALT_DMA_NSCTL_ADDR
#endif
/* DMA Manager Status Register */
#define ALT_DMA_DSR_OFST 0x0
#define ALT_DMA_DSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DSR_OFST))
#define ALT_DMA_DSR_DMASTATUS_SET_MSK 0x0000000f
#define ALT_DMA_DSR_DMASTATUS_GET(value) ((value) & 0x0000000f)
/* DMA Program Counter Register */
#define ALT_DMA_DPC_OFST 0x4
#define ALT_DMA_DPC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DPC_OFST))
/* Interrupt Enable Register */
#define ALT_DMA_INTEN_OFST 0x20
#define ALT_DMA_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTEN_OFST))
/* Event-Interrupt Raw Status Register */
#define ALT_DMA_INT_EVENT_RIS_OFST 0x24
#define ALT_DMA_INT_EVENT_RIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INT_EVENT_RIS_OFST))
/* Interrupt Status Register */
#define ALT_DMA_INTMIS_OFST 0x28
#define ALT_DMA_INTMIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTMIS_OFST))
/* Interrupt Clear Register */
#define ALT_DMA_INTCLR_OFST 0x2c
#define ALT_DMA_INTCLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTCLR_OFST))
/* Fault Status DMA Manager Register */
#define ALT_DMA_FSRD_OFST 0x30
#define ALT_DMA_FSRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST))
/* Fault Status DMA Channel Register */
#define ALT_DMA_FSRC_OFST 0x34
#define ALT_DMA_FSRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRC_OFST))
/* Fault Type DMA Manager Register */
#define ALT_DMA_FTRD_OFST 0x38
#define ALT_DMA_FTRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST))
/* Fault Type DMA Channel Registers */
#define ALT_DMA_FTRx_OFST(channel) (0x40 + 0x4 * (channel))
#define ALT_DMA_FTRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FTRx_OFST(channel)))
/* Channel Status Registers */
#define ALT_DMA_CSRx_OFST(channel) (0x100 + 0x8 * (channel))
#define ALT_DMA_CSRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CSRx_OFST(channel)))
#define ALT_DMA_CSRx_CHANNELSTATUS_SET_MSK 0x0000000f
#define ALT_DMA_CSRx_CHANNELSTATUS_GET(value) ((value) & 0x0000000f)
/* Channel Program Counter Registers */
#define ALT_DMA_CPCx_OFST(channel) (0x104 + 0x8 * (channel))
#define ALT_DMA_CPCx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CPCx_OFST(channel)))
/* Source Address Registers */
#define ALT_DMA_SARx_OFST(channel) (0x400 + 0x20 * (channel))
#define ALT_DMA_SARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_SARx_OFST(channel)))
/* Destination Address Registers */
#define ALT_DMA_DARx_OFST(channel) (0x404 + 0x20 * (channel))
#define ALT_DMA_DARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DARx_OFST(channel)))
/* Channel Control Registers */
#define ALT_DMA_CCRx_OFST(channel) (0x408 + 0x20 * (channel))
#define ALT_DMA_CCRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CCRx_OFST(channel)))
/* Loop Counter 0 Registers */
#define ALT_DMA_LC0_x_OFST(channel) (0x40c + 0x20 * (channel))
#define ALT_DMA_LC0_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC0_x_OFST(channel)))
/* Loop Counter 1 Registers */
#define ALT_DMA_LC1_x_OFST(channel) (0x410 + 0x20 * (channel))
#define ALT_DMA_LC1_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC1_x_OFST(channel)))
/* Debug Status Register */
#define ALT_DMA_DBGSTATUS_OFST 0xd00
#define ALT_DMA_DBGSTATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGSTATUS_OFST))
/* Debug Command Register */
#define ALT_DMA_DBGCMD_OFST 0xd04
#define ALT_DMA_DBGCMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGCMD_OFST))
/* Debug Instruction-0 Register */
#define ALT_DMA_DBGINST0_OFST 0xd08
#define ALT_DMA_DBGINST0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST0_OFST))
#define ALT_DMA_DBGINST0_CHANNELNUMBER_SET(value) (((value) & 0x7) << 8)
#define ALT_DMA_DBGINST0_DEBUGTHREAD_SET(value) ((value) & 0x1)
#define ALT_DMA_DBGINST0_DEBUGTHREAD_E_MANAGER 0
#define ALT_DMA_DBGINST0_DEBUGTHREAD_E_CHANNEL 1
#define ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(value) (((value) & 0xff) << 16)
#define ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(value) (((value) & 0xff) << 24)
/* Debug Instruction-1 Register */
#define ALT_DMA_DBGINST1_OFST 0xd0c
#define ALT_DMA_DBGINST1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST1_OFST))
/* Configuration Registers 0 - 4 */
#define ALT_DMA_CR0_OFST 0xe00
#define ALT_DMA_CR1_OFST 0xe04
#define ALT_DMA_CR2_OFST 0xe08
#define ALT_DMA_CR3_OFST 0xe0c
#define ALT_DMA_CR4_OFST 0xe10
#define ALT_DMA_CR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR0_OFST))
#define ALT_DMA_CR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR1_OFST))
#define ALT_DMA_CR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR2_OFST))
#define ALT_DMA_CR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR3_OFST))
#define ALT_DMA_CR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR4_OFST))
/* DMA Configuration Register */
#define ALT_DMA_CRD_OFST 0xe14
#define ALT_DMA_CRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CRD_OFST))
/* Watchdog Register */
#define ALT_DMA_WD_OFST 0xe80
#define ALT_DMA_WD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_WD_OFST))
/*
* Internal Data structures
* */
/* This flag marks the channel as being allocated. */
#define ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED (1 << 0)
typedef struct ALT_DMA_CHANNEL_INFO_s
{
uint8_t flag;
}
ALT_DMA_CHANNEL_INFO_t;
static struct
{
/* State information fo each DMA channel. */
ALT_DMA_CHANNEL_INFO_t channel_info[8];
#if defined(soc_cv_av)
/* This variable is true if CAN is available in the HPS. */
bool can_exist;
#elif defined(soc_a10)
#else
#error Unsupported SoCFPGA device.
#endif
} g_dmaState;
/*
* If users are not using the MMU (and not including alt_mmu.c), this function
* will resolve to translating a flat memory mapping. This is needed to
* decouple the MMU from the DMA modules.
* */
__attribute__((weak)) uintptr_t alt_mmu_va_to_pa(const void * va, uint32_t * seglength, uint32_t * dfsr)
{
*seglength = 0xffffffff;
*dfsr = 0;
return (uintptr_t)va;
}
__attribute__((weak)) ALT_STATUS_CODE alt_mmu_va_to_pa_coalesce_begin(ALT_MMU_VA_TO_PA_COALESCE_t * coalesce, const void * va, size_t size)
{
if ((uintptr_t)va + size - 1 < (uintptr_t)va)
{
return ALT_E_ERROR;
}
coalesce->va = va;
coalesce->size = size;
coalesce->nextsegpa = (uintptr_t)va;
coalesce->nextsegsize = size;
return ALT_E_SUCCESS;
}
__attribute__((weak)) ALT_STATUS_CODE alt_mmu_va_to_pa_coalesce_next(ALT_MMU_VA_TO_PA_COALESCE_t * coalesce, uintptr_t * segpa, uint32_t * segsize)
{
if (coalesce->size == 0)
{
return ALT_E_ERROR;
}
coalesce->size = 0;
*segpa = coalesce->nextsegpa;
*segsize = coalesce->nextsegsize;
coalesce->nextsegpa = 0;
coalesce->nextsegsize = 0;
return ALT_E_SUCCESS;
}
__attribute__((weak)) ALT_STATUS_CODE alt_mmu_va_to_pa_coalesce_end(ALT_MMU_VA_TO_PA_COALESCE_t * coalesce)
{
if (coalesce->size)
{
return ALT_E_ERROR;
}
else
{
return ALT_E_SUCCESS;
}
}
/*
* If users are not using the cache (and not including alt_cache.c) this
* function will resolve to a no-op. This is needed to decouple DMA from cache.
* */
__attribute__((weak)) ALT_STATUS_CODE alt_cache_system_clean(void * address, size_t length)
{
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg)
{
int i;
#if defined(soc_cv_av)
/* Update the System Manager DMA configuration items */
uint32_t dmactrl = 0;
/* Update the System Manager DMA peripheral security items */
uint32_t dmapersecurity = 0;
/* Initialize the channel information array */
for (i = 0; i < ARRAY_COUNT(g_dmaState.channel_info); ++i)
{
g_dmaState.channel_info[i].flag = 0;
}
/* See if CAN is available on the system. */
g_dmaState.can_exist = ALT_SYSMGR_HPSINFO_CAN_GET(alt_read_word(ALT_SYSMGR_HPSINFO_ADDR))
== ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE;
/* Handle FPGA / CAN muxing */
for (i = 0; i < ARRAY_COUNT(dma_cfg->periph_mux); ++i)
{
/* The default is FPGA. */
switch (dma_cfg->periph_mux[i])
{
case ALT_DMA_PERIPH_MUX_DEFAULT:
case ALT_DMA_PERIPH_MUX_FPGA:
break;
case ALT_DMA_PERIPH_MUX_CAN:
if (!g_dmaState.can_exist)
{
return ALT_E_BAD_ARG;
}
dmactrl |= (ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK << i);
break;
default:
return ALT_E_ERROR;
}
}
/* Handle Manager security */
/* Default is Secure state. */
switch (dma_cfg->manager_sec)
{
case ALT_DMA_SECURITY_DEFAULT:
case ALT_DMA_SECURITY_SECURE:
break;
case ALT_DMA_SECURITY_NONSECURE:
dmactrl |= ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK;
break;
default:
return ALT_E_ERROR;
}
/* Handle IRQ security */
for (i = 0; i < ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH; ++i)
{
/* Default is Secure state. */
switch (dma_cfg->irq_sec[i])
{
case ALT_DMA_SECURITY_DEFAULT:
case ALT_DMA_SECURITY_SECURE:
break;
case ALT_DMA_SECURITY_NONSECURE:
dmactrl |= (1 << (i + ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB));
break;
default:
return ALT_E_ERROR;
}
}
alt_write_word(ALT_SYSMGR_DMA_CTL_ADDR, dmactrl);
for (i = 0; i < ARRAY_COUNT(dma_cfg->periph_sec); ++i)
{
/* Default is Secure state. */
switch (dma_cfg->periph_sec[i])
{
case ALT_DMA_SECURITY_DEFAULT:
case ALT_DMA_SECURITY_SECURE:
break;
case ALT_DMA_SECURITY_NONSECURE:
dmapersecurity |= (1 << i);
break;
default:
return ALT_E_ERROR;
}
}
alt_write_word(ALT_SYSMGR_DMA_PERSECURITY_ADDR, dmapersecurity);
/* Take DMA out of reset. */
alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_DMA_SET_MSK);
#elif defined(soc_a10)
/* Update the System Manager DMA configuration items */
uint32_t sysmgrdma = 0;
uint32_t sysmgrdmaperiph = 0;
/* Initialize the channel information array */
for (i = 0; i < ARRAY_COUNT(g_dmaState.channel_info); ++i)
{
g_dmaState.channel_info[i].flag = 0;
}
/* Handle FPGA / {Security Manager / I2C4} muxing */
switch (dma_cfg->periph_mux[0]) /* For index 0, default is security manager. */
{
case ALT_DMA_PERIPH_MUX_DEFAULT:
case ALT_DMA_PERIPH_MUX_SECMGR:
sysmgrdma |= ALT_SYSMGR_DMA_CHANSEL_2_SET(ALT_SYSMGR_DMA_CHANSEL_2_E_SECMGR);
break;
case ALT_DMA_PERIPH_MUX_FPGA:
sysmgrdma |= ALT_SYSMGR_DMA_CHANSEL_2_SET(ALT_SYSMGR_DMA_CHANSEL_2_E_FPGA);
break;
default:
return ALT_E_ERROR;
}
switch (dma_cfg->periph_mux[1]) /* For index 1, default is FPGA. */
{
case ALT_DMA_PERIPH_MUX_DEFAULT:
case ALT_DMA_PERIPH_MUX_FPGA:
sysmgrdma |= ALT_SYSMGR_DMA_CHANSEL_1_SET(ALT_SYSMGR_DMA_CHANSEL_1_E_FPGA);
break;
case ALT_DMA_PERIPH_MUX_I2C:
sysmgrdma |= ALT_SYSMGR_DMA_CHANSEL_1_SET(ALT_SYSMGR_DMA_CHANSEL_1_E_I2C4_RX);
break;
default:
return ALT_E_ERROR;
}
switch (dma_cfg->periph_mux[2]) /* For index 2, default is FPGA. */
{
case ALT_DMA_PERIPH_MUX_DEFAULT:
case ALT_DMA_PERIPH_MUX_FPGA:
sysmgrdma |= ALT_SYSMGR_DMA_CHANSEL_0_SET(ALT_SYSMGR_DMA_CHANSEL_0_E_FPGA);
break;
case ALT_DMA_PERIPH_MUX_I2C:
sysmgrdma |= ALT_SYSMGR_DMA_CHANSEL_0_SET(ALT_SYSMGR_DMA_CHANSEL_0_E_I2C4_TX);
break;
default:
return ALT_E_ERROR;
}
/* Handle Manager security */
switch (dma_cfg->manager_sec)
{
case ALT_DMA_SECURITY_DEFAULT:
case ALT_DMA_SECURITY_SECURE:
break;
case ALT_DMA_SECURITY_NONSECURE:
sysmgrdma |= ALT_SYSMGR_DMA_MGR_NS_SET_MSK;
break;
default:
return ALT_E_ERROR;
}
/* Handle IRQ Security */
for (i = 0; i < ALT_SYSMGR_DMA_IRQ_NS_WIDTH; ++i)
{
switch (dma_cfg->irq_sec[i])
{
case ALT_DMA_SECURITY_DEFAULT:
case ALT_DMA_SECURITY_SECURE:
break;
case ALT_DMA_SECURITY_NONSECURE:
sysmgrdma |= (1 << (i + ALT_SYSMGR_DMA_IRQ_NS_LSB));
break;
default:
return ALT_E_ERROR;
}
}
/* Write out the sysmgrdma value. */
alt_write_word(ALT_SYSMGR_DMA_ADDR, sysmgrdma);
/* Update System Manager DMA peripheral security items */
for (i = 0; i < ALT_SYSMGR_DMA_PERIPH_NS_WIDTH; ++i)
{
/* Default is Secure state. */
switch (dma_cfg->periph_sec[i])
{
case ALT_DMA_SECURITY_DEFAULT:
case ALT_DMA_SECURITY_SECURE:
break;
case ALT_DMA_SECURITY_NONSECURE:
sysmgrdmaperiph |= (1 << i);
break;
default:
return ALT_E_ERROR;
}
}
alt_write_word(ALT_SYSMGR_DMA_PERIPH_ADDR, sysmgrdmaperiph);
/* Take DMA out of reset. */
alt_clrbits_word(ALT_RSTMGR_PER0MODRST_ADDR, ALT_RSTMGR_PER0MODRST_DMA_SET_MSK);
#endif
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_uninit(void)
{
int i;
/* DMAKILL all channel and free all allocated channels. */
for (i = 0; i < ARRAY_COUNT(g_dmaState.channel_info); ++i)
{
if (g_dmaState.channel_info[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)
{
alt_dma_channel_kill((ALT_DMA_CHANNEL_t)i);
alt_dma_channel_free((ALT_DMA_CHANNEL_t)i);
}
}
/* Put DMA into reset. */
#if defined(soc_cv_av)
alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_DMA_SET_MSK);
#elif defined(soc_a10)
alt_setbits_word(ALT_RSTMGR_PER0MODRST_ADDR, ALT_RSTMGR_PER0MODRST_DMA_SET_MSK);
#endif
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel)
{
/* Validate channel */
switch (channel)
{
case ALT_DMA_CHANNEL_0:
case ALT_DMA_CHANNEL_1:
case ALT_DMA_CHANNEL_2:
case ALT_DMA_CHANNEL_3:
case ALT_DMA_CHANNEL_4:
case ALT_DMA_CHANNEL_5:
case ALT_DMA_CHANNEL_6:
case ALT_DMA_CHANNEL_7:
break;
default:
return ALT_E_BAD_ARG;
}
/* Verify channel is unallocated */
if (g_dmaState.channel_info[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)
{
return ALT_E_ERROR;
}
/* Mark channel as allocated */
g_dmaState.channel_info[channel].flag |= ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED;
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated)
{
/* Sweep channel array for unallocated channel */
int i;
for (i = 0; i < ARRAY_COUNT(g_dmaState.channel_info); ++i)
{
if (!(g_dmaState.channel_info[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED))
{
/* Allocate that free channel. */
ALT_STATUS_CODE status = alt_dma_channel_alloc((ALT_DMA_CHANNEL_t)i);
if (status == ALT_E_SUCCESS)
{
*allocated = (ALT_DMA_CHANNEL_t)i;
}
return status;
}
}
/* No free channels found. */
return ALT_E_ERROR;
}
ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel)
{
ALT_DMA_CHANNEL_STATE_t state;
ALT_STATUS_CODE status;
/* Validate channel */
switch (channel)
{
case ALT_DMA_CHANNEL_0:
case ALT_DMA_CHANNEL_1:
case ALT_DMA_CHANNEL_2:
case ALT_DMA_CHANNEL_3:
case ALT_DMA_CHANNEL_4:
case ALT_DMA_CHANNEL_5:
case ALT_DMA_CHANNEL_6:
case ALT_DMA_CHANNEL_7:
break;
default:
return ALT_E_BAD_ARG;
}
/* Verify channel is allocated */
if (!(g_dmaState.channel_info[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED))
{
return ALT_E_ERROR;
}
/* Verify channel is stopped */
status = alt_dma_channel_state_get(channel, &state);
if (status != ALT_E_SUCCESS)
{
return status;
}
if (state != ALT_DMA_CHANNEL_STATE_STOPPED)
{
return ALT_E_ERROR;
}
/* Mark channel as unallocated. */
g_dmaState.channel_info[channel].flag &= ~ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED;
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t * pgm)
{
ALT_STATUS_CODE status = ALT_E_SUCCESS;
uintptr_t pgmpa = 0;
/* Validate channel */
switch (channel)
{
case ALT_DMA_CHANNEL_0:
case ALT_DMA_CHANNEL_1:
case ALT_DMA_CHANNEL_2:
case ALT_DMA_CHANNEL_3:
case ALT_DMA_CHANNEL_4:
case ALT_DMA_CHANNEL_5:
case ALT_DMA_CHANNEL_6:
case ALT_DMA_CHANNEL_7:
break;
default:
return ALT_E_BAD_ARG;
}
/* Verify channel is allocated */
if (!(g_dmaState.channel_info[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED))
{
return ALT_E_ERROR;
}
/* Verify channel is stopped */
if (status == ALT_E_SUCCESS)
{
ALT_DMA_CHANNEL_STATE_t state;
status = alt_dma_channel_state_get(channel, &state);
if (state != ALT_DMA_CHANNEL_STATE_STOPPED)
{
return ALT_E_ERROR;
}
}
/* Validate the program */
if (status == ALT_E_SUCCESS)
{
status = alt_dma_program_validate(pgm);
}
/* Sync the DMA program to RAM. */
if (status == ALT_E_SUCCESS)
{
void * vaddr = (void *)((uintptr_t)(pgm->program + pgm->buffer_start) & ~(ALT_CACHE_LINE_SIZE - 1));
void * vend = (void *)(((uintptr_t)(pgm->program + pgm->buffer_start + pgm->code_size) + (ALT_CACHE_LINE_SIZE - 1)) & ~(ALT_CACHE_LINE_SIZE - 1));
size_t length = (uintptr_t)vend - (uintptr_t)vaddr;
status = alt_cache_system_clean(vaddr, length);
}
/*
* Get the PA of the program buffer.
* */
if (status == ALT_E_SUCCESS)
{
uint32_t dfsr;
uint32_t seglength;
pgmpa = alt_mmu_va_to_pa(pgm->program + pgm->buffer_start, &seglength, &dfsr);
if (dfsr)
{
dprintf("DMA[exec]: ERROR: Cannot get VA-to-PA of pgm->program + pgm->buffer_start= %p.\n", pgm->program + pgm->buffer_start);
status = ALT_E_ERROR;
}
}
/*
* Execute the program
* */
/* Configure DBGINST0 and DBGINST1 to execute DMAGO targetting the requested channel. */
/* For information on APB Interface, see PL330, section 2.5.1.
* For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21.
* For information on DMAGO, see PL330, section 4.3.5. */
if (status == ALT_E_SUCCESS)
{
dprintf("DMA[exec]: program = 0x%x (PA).\n", pgmpa);
alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR),
ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0xa0) |
ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(channel));
alt_write_word(ALT_DMA_DBGINST1_ADDR(ALT_DMASECURE_ADDR), pgmpa);
/* Execute the instruction held in DBGINST{0,1} */
/* For information on DBGCMD, see PL330, section 3.3.19. */
alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0);
}
return status;
}
ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel)
{
ALT_STATUS_CODE status = ALT_E_SUCCESS;
ALT_DMA_CHANNEL_STATE_t current;
uint32_t i = 20000;
/* Validate channel */
switch (channel)
{
case ALT_DMA_CHANNEL_0:
case ALT_DMA_CHANNEL_1:
case ALT_DMA_CHANNEL_2:
case ALT_DMA_CHANNEL_3:
case ALT_DMA_CHANNEL_4:
case ALT_DMA_CHANNEL_5:
case ALT_DMA_CHANNEL_6:
case ALT_DMA_CHANNEL_7:
break;
default:
return ALT_E_BAD_ARG;
}
/* Verify channel is allocated */
if (!(g_dmaState.channel_info[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED))
{
return ALT_E_ERROR;
}
/* NOTE: Don't worry about the current channel state. Just issue DMAKILL
* instruction. The channel state cannot move from from Stopped back to
* Killing. */
/* Configure DBGINST0 to execute DMAKILL on the requested channel thread.
* DMAKILL is short enough not to use DBGINST1 register. */
/* For information on APB Interface, see PL330, section 2.5.1.
* For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21.
* For information on DMAKILL, see PL330, section 4.3.6. */
alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR),
ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0x1) |
ALT_DMA_DBGINST0_CHANNELNUMBER_SET(channel) |
ALT_DMA_DBGINST0_DEBUGTHREAD_SET(ALT_DMA_DBGINST0_DEBUGTHREAD_E_CHANNEL));
/* Execute the instruction held in DBGINST0 */
/* For information on DBGCMD, see PL330, section 3.3.19. */
alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0);
/* Wait for channel to move to KILLING or STOPPED state. Do not wait for
* the STOPPED only. If the AXI transaction hangs permanently, it can be
* waiting indefinately. */
while (--i)
{
status = alt_dma_channel_state_get(channel, ¤t);
if (status != ALT_E_SUCCESS)
{
break;
}
if ( (current == ALT_DMA_CHANNEL_STATE_KILLING)
|| (current == ALT_DMA_CHANNEL_STATE_STOPPED))
{
break;
}
}
if (i == 0)
{
status = ALT_E_TMO;
}
return status;
}
ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel,
ALT_DMA_PROGRAM_REG_t reg, uint32_t * val)
{
/* Validate channel */
switch (channel)
{
case ALT_DMA_CHANNEL_0:
case ALT_DMA_CHANNEL_1:
case ALT_DMA_CHANNEL_2:
case ALT_DMA_CHANNEL_3:
case ALT_DMA_CHANNEL_4:
case ALT_DMA_CHANNEL_5:
case ALT_DMA_CHANNEL_6:
case ALT_DMA_CHANNEL_7:
break;
default:
return ALT_E_BAD_ARG;
}
/* For information on SAR, see PL330, section 3.3.13.
* For information on DAR, see PL330, section 3.3.14.
* For information on CCR, see PL330, section 3.3.15. */
switch (reg)
{
case ALT_DMA_PROGRAM_REG_SAR:
*val = alt_read_word(ALT_DMA_SARx_ADDR(ALT_DMASECURE_ADDR, channel));
break;
case ALT_DMA_PROGRAM_REG_DAR:
*val = alt_read_word(ALT_DMA_DARx_ADDR(ALT_DMASECURE_ADDR, channel));
break;
case ALT_DMA_PROGRAM_REG_CCR:
*val = alt_read_word(ALT_DMA_CCRx_ADDR(ALT_DMASECURE_ADDR, channel));
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num)
{
/* Validate evt_num */
switch (evt_num)
{
case ALT_DMA_EVENT_0:
case ALT_DMA_EVENT_1:
case ALT_DMA_EVENT_2:
case ALT_DMA_EVENT_3:
case ALT_DMA_EVENT_4:
case ALT_DMA_EVENT_5:
case ALT_DMA_EVENT_6:
case ALT_DMA_EVENT_7:
case ALT_DMA_EVENT_ABORT:
break;
default:
return ALT_E_BAD_ARG;
}
/* Issue the DMASEV on the DMA manager thread.
* DMASEV is short enough not to use DBGINST1 register. */
/* For information on APB Interface, see PL330, section 2.5.1.
* For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21.
* For information on DMASEV, see PL330, section 4.3.15. */
alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR),
ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0x34) | /* opcode for DMASEV */
ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(evt_num << 3) |
ALT_DMA_DBGINST0_DEBUGTHREAD_SET(ALT_DMA_DBGINST0_DEBUGTHREAD_E_MANAGER)
);
/* Execute the instruction held in DBGINST0 */
/* For information on DBGCMD, see PL330, section 3.3.19. */
alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state)
{
/* For information on DSR, see PL330, section 3.3.1. */
uint32_t raw_state = alt_read_word(ALT_DMA_DSR_ADDR(ALT_DMASECURE_ADDR));
*state = (ALT_DMA_MANAGER_STATE_t)ALT_DMA_DSR_DMASTATUS_GET(raw_state);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel,
ALT_DMA_CHANNEL_STATE_t * state)
{
uint32_t raw_state;
/* Validate channel */
switch (channel)
{
case ALT_DMA_CHANNEL_0:
case ALT_DMA_CHANNEL_1:
case ALT_DMA_CHANNEL_2:
case ALT_DMA_CHANNEL_3:
case ALT_DMA_CHANNEL_4:
case ALT_DMA_CHANNEL_5:
case ALT_DMA_CHANNEL_6:
case ALT_DMA_CHANNEL_7:
break;
default:
return ALT_E_BAD_ARG;
}
/* For information on CSR, see PL330, section 3.3.11. */
raw_state = alt_read_word(ALT_DMA_CSRx_ADDR(ALT_DMASECURE_ADDR, channel));
*state = (ALT_DMA_CHANNEL_STATE_t)ALT_DMA_CSRx_CHANNELSTATUS_GET(raw_state);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault)
{
/* For information on FTRD, see PL330, section 3.3.9. */
*fault = (ALT_DMA_MANAGER_FAULT_t)alt_read_word(ALT_DMA_FTRD_ADDR(ALT_DMASECURE_ADDR));
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel,
ALT_DMA_CHANNEL_FAULT_t * fault)
{
/* Validate channel */
switch (channel)
{
case ALT_DMA_CHANNEL_0:
case ALT_DMA_CHANNEL_1:
case ALT_DMA_CHANNEL_2:
case ALT_DMA_CHANNEL_3:
case ALT_DMA_CHANNEL_4:
case ALT_DMA_CHANNEL_5:
case ALT_DMA_CHANNEL_6:
case ALT_DMA_CHANNEL_7:
break;
default:
return ALT_E_BAD_ARG;
}
/* For information on FTR, see PL330, section 3.3.10. */
*fault = (ALT_DMA_CHANNEL_FAULT_t)alt_read_word(ALT_DMA_FTRx_ADDR(ALT_DMASECURE_ADDR, channel));
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num,
ALT_DMA_EVENT_SELECT_t opt)
{
/* Validate evt_num */
switch (evt_num)
{
case ALT_DMA_EVENT_0:
case ALT_DMA_EVENT_1:
case ALT_DMA_EVENT_2:
case ALT_DMA_EVENT_3:
case ALT_DMA_EVENT_4: