From 2524a2fa19b95f736e3827d79846e4c6b8843c67 Mon Sep 17 00:00:00 2001 From: AinsleySnow <772571228@qq.com> Date: Fri, 12 Jan 2024 16:01:14 +0800 Subject: [PATCH] [LLVM][XTHeadVector] Implement intrinsics for vwadd/vwsub. (#51) * [LLVM][XTHeadVector] Define intrinsic function for vwadd/vwsub, etc. * [LLVM][XTHeadVector] Redefine MxList and AllWidenableVectors for xtheadvector. * [LLVM][XTHeadVector] Define pseudos for vwadd, etc. * [LLVM][XTHeadVector] Define TiedBinary Pseudos. This is in reference of https://reviews.llvm.org/D103211 and https://reviews.llvm.org/D103552. * [LLVM][XTHeadVector] Define patterns and map intrinsics to pseudos. The defination and usage of TiedBinary Pat reference https://reviews.llvm.org/D103211 and https://reviews.llvm.org/D103552 as well. * [LLVM][XTHeadVector] Update the convertToThreeAddress method, to convert xtheadvector pseudos. * [LLVM][XTHeadVector] Add test cases for vwadd{u}/vwsub{u}. * [LLVM][XTHeadVector] Add test cases for vwadd{u}.{wv/wx}/vwsub{u}.{wv/wx}. * [NFC][XTHeadVector] Update README. --- README.md | 4 + .../include/llvm/IR/IntrinsicsRISCVXTHeadV.td | 27 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 45 +- .../RISCV/RISCVInstrInfoXTHeadVPseudos.td | 251 ++ llvm/test/CodeGen/RISCV/rvv0p71/vwadd.ll | 1497 +++++++++++ llvm/test/CodeGen/RISCV/rvv0p71/vwadd.w.ll | 2305 +++++++++++++++++ llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.ll | 1497 +++++++++++ llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.w.ll | 2304 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv0p71/vwsub.ll | 1497 +++++++++++ llvm/test/CodeGen/RISCV/rvv0p71/vwsub.w.ll | 2304 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.ll | 1497 +++++++++++ llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.w.ll | 2304 ++++++++++++++++ 12 files changed, 15525 insertions(+), 7 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vwadd.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vwadd.w.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.w.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vwsub.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vwsub.w.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.w.ll diff --git a/README.md b/README.md index f07eaaf96ffcf..2d93585f64b0b 100644 --- a/README.md +++ b/README.md @@ -27,6 +27,10 @@ Any feature not listed below but present in the specification should be consider - (Done) `vadd.{vv,vx,vi}` - (Done) `vsub.{vv,vx}` - (Done) `vrsub.{vx,vi}` + - (Done) `12.2. Vector Widening Integer Add/Subtract` + - (Done) `vwadd{u}.{vv,vx,wv,wx}` + - (Done) `vwsub{u}.{vv,vx,wv,wx}` + - (WIP) Clang intrinsics related to the `XTHeadVector` extension: - (WIP) `6. Configuration-Setting and Utility` - (Done) `6.1. Set vl and vtype` diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td b/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td index 03fd643434fdf..0485a7a7e83d5 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td @@ -574,10 +574,27 @@ let TargetPrefix = "riscv" in { let VLOperand = 4; } + // For destination vector type is NOT the same as + // first source vector (with mask but no policy). + // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl) + class XVBinaryABXMasked + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], + [IntrNoMem]>, RISCVVIntrinsic { + let ScalarOperand = 2; + let VLOperand = 4; + } + multiclass XVBinaryAAX { def "int_riscv_" # NAME : RISCVBinaryAAXUnMasked; def "int_riscv_" # NAME # "_mask" : XVBinaryAAXMasked; } + + multiclass XVBinaryABX { + def "int_riscv_" # NAME : RISCVBinaryABXUnMasked; + def "int_riscv_" # NAME # "_mask" : XVBinaryABXMasked; + } } let TargetPrefix = "riscv" in { @@ -586,6 +603,16 @@ let TargetPrefix = "riscv" in { defm th_vadd : XVBinaryAAX; defm th_vsub : XVBinaryAAX; defm th_vrsub : XVBinaryAAX; + + // 12.2. Vector Widening Integer Add/Subtract + defm th_vwaddu : XVBinaryABX; + defm th_vwadd : XVBinaryABX; + defm th_vwaddu_w : XVBinaryAAX; + defm th_vwadd_w : XVBinaryAAX; + defm th_vwsubu : XVBinaryABX; + defm th_vwsub : XVBinaryABX; + defm th_vwsubu_w : XVBinaryAAX; + defm th_vwsub_w : XVBinaryAAX; } // TargetPrefix = "riscv" let TargetPrefix = "riscv" in { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 4706df8d3ee66..d6d3b6235c14d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2550,6 +2550,9 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI, #define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL) \ RISCV::PseudoV##OP##_##LMUL##_TIED +#define CASE_TH_WIDEOP_OPCODE_COMMON(OP, LMUL) \ + RISCV::PseudoTH_V##OP##_##LMUL##_TIED + #define CASE_WIDEOP_OPCODE_LMULS_MF4(OP) \ CASE_WIDEOP_OPCODE_COMMON(OP, MF4): \ case CASE_WIDEOP_OPCODE_COMMON(OP, MF2): \ @@ -2560,6 +2563,11 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI, #define CASE_WIDEOP_OPCODE_LMULS(OP) \ CASE_WIDEOP_OPCODE_COMMON(OP, MF8): \ case CASE_WIDEOP_OPCODE_LMULS_MF4(OP) + +#define CASE_TH_WIDEOP_OPCODE_LMULS(OP) \ + CASE_TH_WIDEOP_OPCODE_COMMON(OP, M1): \ + case CASE_TH_WIDEOP_OPCODE_COMMON(OP, M2): \ + case CASE_TH_WIDEOP_OPCODE_COMMON(OP, M4) // clang-format on #define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL) \ @@ -2567,6 +2575,11 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI, NewOpc = RISCV::PseudoV##OP##_##LMUL; \ break; +#define CASE_TH_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL) \ + case RISCV::PseudoTH_V##OP##_##LMUL##_TIED: \ + NewOpc = RISCV::PseudoTH_V##OP##_##LMUL; \ + break; + #define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP) \ CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4) \ CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \ @@ -2578,6 +2591,11 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI, CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8) \ CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP) +#define CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(OP) \ + CASE_TH_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \ + CASE_TH_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2) \ + CASE_TH_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4) + MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const { @@ -2619,12 +2637,20 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI, case CASE_WIDEOP_OPCODE_LMULS(WADD_WV): case CASE_WIDEOP_OPCODE_LMULS(WADDU_WV): case CASE_WIDEOP_OPCODE_LMULS(WSUB_WV): - case CASE_WIDEOP_OPCODE_LMULS(WSUBU_WV): { + case CASE_WIDEOP_OPCODE_LMULS(WSUBU_WV): + case CASE_TH_WIDEOP_OPCODE_LMULS(WADD_WV): + case CASE_TH_WIDEOP_OPCODE_LMULS(WADDU_WV): + case CASE_TH_WIDEOP_OPCODE_LMULS(WSUB_WV): + case CASE_TH_WIDEOP_OPCODE_LMULS(WSUBU_WV): { // If the tail policy is undisturbed we can't convert. - assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) && - MI.getNumExplicitOperands() == 6); - if ((MI.getOperand(5).getImm() & 1) == 0) - return nullptr; + // We can always do the conversion in RVV 0.7.1, since + // it is always tail agnostic. + if (!STI.hasVendorXTHeadV()) { + assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) && + MI.getNumExplicitOperands() == 6); + if ((MI.getOperand(5).getImm() & 1) == 0) + return nullptr; + } // clang-format off unsigned NewOpc; @@ -2635,6 +2661,10 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI, CASE_WIDEOP_CHANGE_OPCODE_LMULS(WADDU_WV) CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUB_WV) CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUBU_WV) + CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(WADD_WV) + CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(WADDU_WV) + CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(WSUB_WV) + CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(WSUBU_WV) } // clang-format on @@ -2645,8 +2675,9 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI, .add(MI.getOperand(1)) .add(MI.getOperand(2)) .add(MI.getOperand(3)) - .add(MI.getOperand(4)) - .add(MI.getOperand(5)); + .add(MI.getOperand(4)); + if (!STI.hasVendorXTHeadV()) + MIB.add(MI.getOperand(5)); } } MIB.copyImplicitOps(MI); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td index e9fc9e53606fd..d9cbdbc106053 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td @@ -18,6 +18,9 @@ // Used to iterate over all possible LMULs in RVV 0.7.1 defvar MxListXTHeadV = [V_M1, V_M2, V_M4, V_M8]; +// Used to iterate over all possible extendable LMULs in RVV 0.7.1. +defvar MxListWXTHeadV = [V_M1, V_M2, V_M4]; + // Redefine `AllIntegerVectors` from RISCVInstrInfoVPseudos.td to remove fractionally-grouped register groups // like MF2, MF4, MF8, which are not supported by the 'V' extension 0.7.1. defset list AllXVectors = { @@ -79,6 +82,22 @@ defset list AllXVectors = { } } +// Redefine `AllWidenableIntVectors` from RISCVInstrInfoVPseudos.td to remove fractionally-grouped +// register groups like MF2, MF4, MF8, which are not supported by the 'V' extension 0.7.1. +defset list AllWidenableIntXVectors = { + def : VTypeInfoToWide; + def : VTypeInfoToWide; + def : VTypeInfoToWide; + + def : VTypeInfoToWide; + def : VTypeInfoToWide; + def : VTypeInfoToWide; + + def : VTypeInfoToWide; + def : VTypeInfoToWide; + def : VTypeInfoToWide; +} + class GetXVTypePredicates { // TODO: distinguish different types (like F16, F32, F64, AnyF)? Is it needed? list Predicates = !cond(!eq(vti.Scalar, f16) : [HasVendorXTHeadV], @@ -1532,6 +1551,39 @@ class XVPseudoBinaryNoMask : + Pseudo<(outs RetClass:$rd), + (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>, + RISCVVPseudo { + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; + let Constraints = !interleave([Constraint, "$rd = $rs2"], ","); + let HasVLOp = 1; + let HasSEWOp = 1; + let isConvertibleToThreeAddress = 1; + let IsTiedPseudo = 1; +} + +class XVPseudoTiedBinaryMask : + Pseudo<(outs GetVRegNoV0.R:$rd), + (ins GetVRegNoV0.R:$merge, + Op2Class:$rs1, + VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>, + RISCVVPseudo { + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; + let Constraints = !interleave([Constraint, "$rd = $merge"], ","); + let HasVLOp = 1; + let HasSEWOp = 1; + let IsTiedPseudo = 1; +} + multiclass XVPseudoBinary { + let VLMul = MInfo.value in { + def "_" # MInfo.MX # "_TIED": XVPseudoTiedBinaryNoMask; + def "_" # MInfo.MX # "_MASK_TIED" : XVPseudoTiedBinaryMask; + } +} + multiclass XVPseudoBinaryV_VV { defm _VV : XVPseudoBinary; } @@ -1560,6 +1624,27 @@ multiclass XVPseudoBinaryV_VI; } +multiclass XVPseudoBinaryW_VV { + defm _VV : XVPseudoBinary; +} + +multiclass XVPseudoBinaryW_VX { + defm _VX : XVPseudoBinary; +} + +multiclass XVPseudoBinaryW_WV { + defm _WV : XVPseudoBinary; + defm _WV : XVPseudoTiedBinary; +} + +multiclass XVPseudoBinaryW_WX { + defm _WX : XVPseudoBinary; +} + multiclass XVPseudoVALU_VV_VX_VI { foreach m = MxListXTHeadV in { defvar mx = m.MX; @@ -1608,6 +1693,36 @@ multiclass XVPseudoVALU_VX_VI { } } +multiclass XVPseudoVWALU_VV_VX { + foreach m = MxListWXTHeadV in { + defvar mx = m.MX; + defvar WriteVIWALUV_MX = !cast("WriteVIWALUV_" # mx); + defvar WriteVIWALUX_MX = !cast("WriteVIWALUX_" # mx); + defvar ReadVIWALUV_MX = !cast("ReadVIWALUV_" # mx); + defvar ReadVIWALUX_MX = !cast("ReadVIWALUX_" # mx); + + defm "" : XVPseudoBinaryW_VV, + Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>; + defm "" : XVPseudoBinaryW_VX, + Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>; + } +} + +multiclass XVPseudoVWALU_WV_WX { + foreach m = MxListWXTHeadV in { + defvar mx = m.MX; + defvar WriteVIWALUV_MX = !cast("WriteVIWALUV_" # mx); + defvar WriteVIWALUX_MX = !cast("WriteVIWALUX_" # mx); + defvar ReadVIWALUV_MX = !cast("ReadVIWALUV_" # mx); + defvar ReadVIWALUX_MX = !cast("ReadVIWALUX_" # mx); + + defm "" : XVPseudoBinaryW_WV, + Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>; + defm "" : XVPseudoBinaryW_WX, + Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>; + } +} + //===----------------------------------------------------------------------===// // Helpers to define the intrinsic patterns for the XTHeadVector extension. //===----------------------------------------------------------------------===// @@ -1632,6 +1747,40 @@ class XVPatBinaryNoMask; +class XVPatTiedBinaryNoMask : + Pat<(result_type (!cast(intrinsic_name) + (result_type (undef)), + (result_type result_reg_class:$rs1), + (op2_type op2_kind:$rs2), VLOpFrag)), + (!cast(inst#"_TIED") + (result_type result_reg_class:$rs1), + (op2_type op2_kind:$rs2), + GPR:$vl, sew)>; + +class XVPatTiedBinaryMask : + Pat<(result_type (!cast(intrinsic_name#"_mask") + (result_type result_reg_class:$merge), + (result_type result_reg_class:$merge), + (op2_type op2_kind:$rs2), + (mask_type V0), VLOpFrag)), + (!cast(inst#"_MASK_TIED") + (result_type result_reg_class:$merge), + (op2_type op2_kind:$rs2), + (mask_type V0), GPR:$vl, sew)>; + multiclass XVPatBinary; } +multiclass XVPatBinaryW_VV vtilist> { + foreach VtiToWti = vtilist in { + defvar Vti = VtiToWti.Vti; + defvar Wti = VtiToWti.Wti; + let Predicates = !listconcat(GetXVTypePredicates.Predicates, + GetXVTypePredicates.Predicates) in + defm : XVPatBinary; + } +} + +multiclass XVPatBinaryW_VX vtilist> { + foreach VtiToWti = vtilist in { + defvar Vti = VtiToWti.Vti; + defvar Wti = VtiToWti.Wti; + defvar kind = "V"#Vti.ScalarSuffix; + let Predicates = !listconcat(GetXVTypePredicates.Predicates, + GetXVTypePredicates.Predicates) in + defm : XVPatBinary; + } +} + +multiclass XVPatBinaryW_WV vtilist> { + foreach VtiToWti = vtilist in { + defvar Vti = VtiToWti.Vti; + defvar Wti = VtiToWti.Wti; + let Predicates = !listconcat(GetXVTypePredicates.Predicates, + GetXVTypePredicates.Predicates) in { + def : XVPatTiedBinaryNoMask; + let AddedComplexity = 1 in { + def : XVPatTiedBinaryMask; + } + def : VPatBinaryMask; + } + } +} + +multiclass XVPatBinaryW_WX vtilist> { + foreach VtiToWti = vtilist in { + defvar Vti = VtiToWti.Vti; + defvar Wti = VtiToWti.Wti; + defvar kind = "W"#Vti.ScalarSuffix; + let Predicates = !listconcat(GetXVTypePredicates.Predicates, + GetXVTypePredicates.Predicates) in + defm : XVPatBinary; + } +} + multiclass XVPatBinaryV_VV_VX_VI vtilist, Operand ImmType = simm5> : XVPatBinaryV_VV, @@ -1703,6 +1919,16 @@ multiclass XVPatBinaryV_VX_VI, XVPatBinaryV_VI; +multiclass XVPatBinaryW_VV_VX vtilist> + : XVPatBinaryW_VV, + XVPatBinaryW_VX; + +multiclass XVPatBinaryW_WV_WX vtilist> + : XVPatBinaryW_WV, + XVPatBinaryW_WX; + //===----------------------------------------------------------------------===// // 12.1. Vector Single-Width Saturating Add and Subtract //===----------------------------------------------------------------------===// @@ -1772,6 +1998,31 @@ let Predicates = [HasVendorXTHeadV] in { defm : XVPatBinaryV_VX_VI<"int_riscv_th_vrsub", "PseudoTH_VRSUB", AllIntegerXVectors>; } // Predicates = [HasVendorXTHeadV] +//===----------------------------------------------------------------------===// +// 12.2. Vector Widening Integer Add/Subtract +//===----------------------------------------------------------------------===// +let Predicates = [HasVendorXTHeadV] in { + defm PseudoTH_VWADDU : XVPseudoVWALU_VV_VX; + defm PseudoTH_VWSUBU : XVPseudoVWALU_VV_VX; + defm PseudoTH_VWADD : XVPseudoVWALU_VV_VX; + defm PseudoTH_VWSUB : XVPseudoVWALU_VV_VX; + defm PseudoTH_VWADDU : XVPseudoVWALU_WV_WX; + defm PseudoTH_VWSUBU : XVPseudoVWALU_WV_WX; + defm PseudoTH_VWADD : XVPseudoVWALU_WV_WX; + defm PseudoTH_VWSUB : XVPseudoVWALU_WV_WX; +} + +let Predicates = [HasVendorXTHeadV] in { + defm : XVPatBinaryW_VV_VX<"int_riscv_th_vwaddu", "PseudoTH_VWADDU", AllWidenableIntXVectors>; + defm : XVPatBinaryW_VV_VX<"int_riscv_th_vwsubu", "PseudoTH_VWSUBU", AllWidenableIntXVectors>; + defm : XVPatBinaryW_VV_VX<"int_riscv_th_vwadd", "PseudoTH_VWADD", AllWidenableIntXVectors>; + defm : XVPatBinaryW_VV_VX<"int_riscv_th_vwsub", "PseudoTH_VWSUB", AllWidenableIntXVectors>; + defm : XVPatBinaryW_WV_WX<"int_riscv_th_vwaddu_w", "PseudoTH_VWADDU", AllWidenableIntXVectors>; + defm : XVPatBinaryW_WV_WX<"int_riscv_th_vwsubu_w", "PseudoTH_VWSUBU", AllWidenableIntXVectors>; + defm : XVPatBinaryW_WV_WX<"int_riscv_th_vwadd_w", "PseudoTH_VWADD", AllWidenableIntXVectors>; + defm : XVPatBinaryW_WV_WX<"int_riscv_th_vwsub_w", "PseudoTH_VWSUB", AllWidenableIntXVectors>; +} + //===----------------------------------------------------------------------===// // 12.14. Vector Integer Merge and Move Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vwadd.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vwadd.ll new file mode 100644 index 0000000000000..2d7ef42e4c931 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vwadd.ll @@ -0,0 +1,1497 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT + +declare @llvm.riscv.th.vwadd.nxv8i16.nxv8i8.nxv8i8( + , + , + , + iXLen); + +define @intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwadd.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv8i16.nxv8i8.nxv8i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv8i16.nxv8i8.nxv8i8( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv8i16.nxv8i8.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv8i16.nxv8i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwadd.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv8i16.nxv8i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv8i16.nxv8i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwadd_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv8i16.nxv8i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv16i16.nxv16i8.nxv16i8( + , + , + , + iXLen); + +define @intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwadd.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv16i16.nxv16i8.nxv16i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv16i16.nxv16i8.nxv16i8( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv16i16.nxv16i8.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv16i16.nxv16i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwadd.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv16i16.nxv16i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv16i16.nxv16i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwadd_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv16i16.nxv16i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv32i16.nxv32i8.nxv32i8( + , + , + , + iXLen); + +define @intrinsic_vwadd_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwadd.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv32i16.nxv32i8.nxv32i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv32i16.nxv32i8.nxv32i8( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv32i16.nxv32i8.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv32i16.nxv32i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwadd_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwadd.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv32i16.nxv32i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv32i16.nxv32i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwadd_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv32i16.nxv32i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv4i32.nxv4i16.nxv4i16( + , + , + , + iXLen); + +define @intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwadd.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv4i32.nxv4i16.nxv4i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv4i32.nxv4i16.nxv4i16( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv4i32.nxv4i16.nxv4i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv4i32.nxv4i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwadd.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv4i32.nxv4i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv4i32.nxv4i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwadd_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv4i32.nxv4i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv8i32.nxv8i16.nxv8i16( + , + , + , + iXLen); + +define @intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwadd.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv8i32.nxv8i16.nxv8i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv8i32.nxv8i16.nxv8i16( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv8i32.nxv8i16.nxv8i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv8i32.nxv8i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwadd.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv8i32.nxv8i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv8i32.nxv8i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwadd_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv8i32.nxv8i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv16i32.nxv16i16.nxv16i16( + , + , + , + iXLen); + +define @intrinsic_vwadd_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwadd.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv16i32.nxv16i16.nxv16i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv16i32.nxv16i16.nxv16i16( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv16i32.nxv16i16.nxv16i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv16i32.nxv16i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwadd_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwadd.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv16i32.nxv16i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv16i32.nxv16i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwadd_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv16i32.nxv16i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv2i64.nxv2i32.nxv2i32( + , + , + , + iXLen); + +define @intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwadd.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv2i64.nxv2i32.nxv2i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv2i64.nxv2i32.nxv2i32( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv2i64.nxv2i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwadd.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv2i64.nxv2i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv2i64.nxv2i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwadd_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv2i64.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv4i64.nxv4i32.nxv4i32( + , + , + , + iXLen); + +define @intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwadd.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv4i64.nxv4i32.nxv4i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv4i64.nxv4i32.nxv4i32( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv4i64.nxv4i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwadd.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv4i64.nxv4i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv4i64.nxv4i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwadd_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv4i64.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv8i64.nxv8i32.nxv8i32( + , + , + , + iXLen); + +define @intrinsic_vwadd_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwadd.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv8i64.nxv8i32.nxv8i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv8i64.nxv8i32.nxv8i32( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.nxv8i64.nxv8i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwadd_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwadd.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.nxv8i64.nxv8i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.mask.nxv8i64.nxv8i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwadd_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.mask.nxv8i64.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-LABEL: {{.*}} +; CHECK-NEXT: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vwadd.w.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vwadd.w.ll new file mode 100644 index 0000000000000..e1b64d39d1db4 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vwadd.w.ll @@ -0,0 +1,2305 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s + +declare @llvm.riscv.th.vwadd.w.nxv8i16.nxv8i16.nxv8i8( + , + , + , + iXLen); + +define @intrinsic_vwadd_w_wv_nxv8i16_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv8i16.nxv8i16.nxv8i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv8i16.nxv8i16.nxv8i8( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_w_mask_wv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i16.nxv8i16.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv8i16.nxv8i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwadd_w_wx_nxv8i16_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv8i16.nxv8i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv8i16.nxv8i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwadd_w_mask_wx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwadd.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i16.nxv8i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv16i16.nxv16i16.nxv16i8( + , + , + , + iXLen); + +define @intrinsic_vwadd_w_wv_nxv16i16_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv16i16.nxv16i16.nxv16i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv16i16.nxv16i16.nxv16i8( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_w_mask_wv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv16i16.nxv16i16.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv16i16.nxv16i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwadd_w_wx_nxv16i16_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv16i16.nxv16i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv16i16.nxv16i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwadd_w_mask_wx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwadd.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv16i16.nxv16i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv32i16.nxv32i16.nxv32i8( + , + , + , + iXLen); + +define @intrinsic_vwadd_w_wv_nxv32i16_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv32i16.nxv32i16.nxv32i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv32i16.nxv32i16.nxv32i8( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_w_mask_wv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwadd.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv32i16.nxv32i16.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv32i16.nxv32i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwadd_w_wx_nxv32i16_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv32i16.nxv32i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv32i16.nxv32i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwadd_w_mask_wx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwadd.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv32i16.nxv32i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv4i32.nxv4i32.nxv4i16( + , + , + , + iXLen); + +define @intrinsic_vwadd_w_wv_nxv4i32_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv4i32.nxv4i32.nxv4i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv4i32.nxv4i32.nxv4i16( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_w_mask_wv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv4i32.nxv4i32.nxv4i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv4i32.nxv4i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwadd_w_wx_nxv4i32_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv4i32.nxv4i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv4i32.nxv4i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwadd_w_mask_wx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwadd.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv4i32.nxv4i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv8i32.nxv8i32.nxv8i16( + , + , + , + iXLen); + +define @intrinsic_vwadd_w_wv_nxv8i32_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv8i32.nxv8i32.nxv8i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv8i32.nxv8i32.nxv8i16( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_w_mask_wv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i32.nxv8i32.nxv8i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv8i32.nxv8i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwadd_w_wx_nxv8i32_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv8i32.nxv8i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv8i32.nxv8i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwadd_w_mask_wx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwadd.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i32.nxv8i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv16i32.nxv16i32.nxv16i16( + , + , + , + iXLen); + +define @intrinsic_vwadd_w_wv_nxv16i32_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv16i32.nxv16i32.nxv16i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv16i32.nxv16i32.nxv16i16( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_w_mask_wv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e16, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwadd.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv16i32.nxv16i32.nxv16i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv16i32.nxv16i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwadd_w_wx_nxv16i32_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv16i32.nxv16i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv16i32.nxv16i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwadd_w_mask_wx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwadd.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv16i32.nxv16i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv2i64.nxv2i64.nxv2i32( + , + , + , + iXLen); + +define @intrinsic_vwadd_w_wv_nxv2i64_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv2i64.nxv2i64.nxv2i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv2i64.nxv2i64.nxv2i32( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_w_mask_wv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv2i64.nxv2i64.nxv2i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv2i64.nxv2i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwadd_w_wx_nxv2i64_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv2i64.nxv2i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv2i64.nxv2i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwadd_w_mask_wx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwadd.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv2i64.nxv2i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv4i64.nxv4i64.nxv4i32( + , + , + , + iXLen); + +define @intrinsic_vwadd_w_wv_nxv4i64_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv4i64.nxv4i64.nxv4i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv4i64.nxv4i64.nxv4i32( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_w_mask_wv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv4i64.nxv4i64.nxv4i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv4i64.nxv4i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwadd_w_wx_nxv4i64_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv4i64.nxv4i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv4i64.nxv4i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwadd_w_mask_wx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwadd.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv4i64.nxv4i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv8i64.nxv8i64.nxv8i32( + , + , + , + iXLen); + +define @intrinsic_vwadd_w_wv_nxv8i64_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv8i64.nxv8i64.nxv8i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv8i64.nxv8i64.nxv8i32( + , + , + , + , + iXLen); + +define @intrinsic_vwadd_w_mask_wv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e32, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwadd.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i64.nxv8i64.nxv8i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.nxv8i64.nxv8i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwadd_w_wx_nxv8i64_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv8i64.nxv8i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwadd.w.mask.nxv8i64.nxv8i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwadd_w_mask_wx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwadd.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i64.nxv8i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i16.nxv8i16.nxv8i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv16i16.nxv16i16.nxv16i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv32i16.nxv32i16.nxv32i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv4i32.nxv4i32.nxv4i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i32.nxv8i32.nxv8i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv16i32.nxv16i32.nxv16i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv2i64.nxv2i64.nxv2i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv4i64.nxv4i64.nxv4i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwadd.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i64.nxv8i64.nxv8i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wx_tie_nxv8i16_nxv8i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_tie_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i16.nxv8i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wx_tie_nxv16i16_nxv16i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_tie_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv16i16.nxv16i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wx_tie_nxv32i16_nxv32i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_tie_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv32i16.nxv32i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wx_tie_nxv4i32_nxv4i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_tie_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv4i32.nxv4i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wx_tie_nxv8i32_nxv8i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_tie_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i32.nxv8i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wx_tie_nxv16i32_nxv16i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_tie_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv16i32.nxv16i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wx_tie_nxv2i64_nxv2i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_tie_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv2i64.nxv2i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wx_tie_nxv4i64_nxv4i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_tie_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv4i64.nxv4i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_mask_wx_tie_nxv8i64_nxv8i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_mask_wx_tie_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwadd.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.mask.nxv8i64.nxv8i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwadd_w_wv_untie_nxv8i16_nxv8i16_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_untie_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwadd.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv8i16.nxv8i16.nxv8i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwadd_w_wv_untie_nxv16i16_nxv16i16_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_untie_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwadd.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv16i16.nxv16i16.nxv16i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwadd_w_wv_untie_nxv32i16_nxv32i16_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_untie_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwadd.wv v24, v16, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: th.vmv.v.v v9, v25 +; CHECK-NEXT: th.vmv.v.v v10, v26 +; CHECK-NEXT: th.vmv.v.v v11, v27 +; CHECK-NEXT: th.vmv.v.v v12, v28 +; CHECK-NEXT: th.vmv.v.v v13, v29 +; CHECK-NEXT: th.vmv.v.v v14, v30 +; CHECK-NEXT: th.vmv.v.v v15, v31 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv32i16.nxv32i16.nxv32i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwadd_w_wv_untie_nxv4i32_nxv4i32_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_untie_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwadd.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv4i32.nxv4i32.nxv4i16( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwadd_w_wv_untie_nxv8i32_nxv8i32_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_untie_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwadd.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv8i32.nxv8i32.nxv8i16( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwadd_w_wv_untie_nxv2i64_nxv2i64_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_untie_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwadd.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv2i64.nxv2i64.nxv2i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwadd_w_wv_untie_nxv4i64_nxv4i64_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_untie_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwadd.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv4i64.nxv4i64.nxv4i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwadd_w_wv_untie_nxv8i64_nxv8i64_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_w_wv_untie_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwadd.wv v24, v16, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: th.vmv.v.v v9, v25 +; CHECK-NEXT: th.vmv.v.v v10, v26 +; CHECK-NEXT: th.vmv.v.v v11, v27 +; CHECK-NEXT: th.vmv.v.v v12, v28 +; CHECK-NEXT: th.vmv.v.v v13, v29 +; CHECK-NEXT: th.vmv.v.v v14, v30 +; CHECK-NEXT: th.vmv.v.v v15, v31 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwadd.w.nxv8i64.nxv8i64.nxv8i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.ll new file mode 100644 index 0000000000000..85ada393e06a3 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.ll @@ -0,0 +1,1497 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT + +declare @llvm.riscv.th.vwaddu.nxv8i16.nxv8i8.nxv8i8( + , + , + , + iXLen); + +define @intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv8i16.nxv8i8.nxv8i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv8i16.nxv8i8.nxv8i8( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv8i16.nxv8i8.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv8i16.nxv8i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv8i16.nxv8i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv8i16.nxv8i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwaddu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv8i16.nxv8i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv16i16.nxv16i8.nxv16i8( + , + , + , + iXLen); + +define @intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv16i16.nxv16i8.nxv16i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv16i16.nxv16i8.nxv16i8( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv16i16.nxv16i8.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv16i16.nxv16i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv16i16.nxv16i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv16i16.nxv16i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwaddu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv16i16.nxv16i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv32i16.nxv32i8.nxv32i8( + , + , + , + iXLen); + +define @intrinsic_vwaddu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv32i16.nxv32i8.nxv32i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv32i16.nxv32i8.nxv32i8( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv32i16.nxv32i8.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv32i16.nxv32i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwaddu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv32i16.nxv32i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv32i16.nxv32i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwaddu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv32i16.nxv32i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv4i32.nxv4i16.nxv4i16( + , + , + , + iXLen); + +define @intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv4i32.nxv4i16.nxv4i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv4i32.nxv4i16.nxv4i16( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv4i32.nxv4i16.nxv4i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv4i32.nxv4i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv4i32.nxv4i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv4i32.nxv4i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwaddu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv4i32.nxv4i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv8i32.nxv8i16.nxv8i16( + , + , + , + iXLen); + +define @intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv8i32.nxv8i16.nxv8i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv8i32.nxv8i16.nxv8i16( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv8i32.nxv8i16.nxv8i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv8i32.nxv8i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv8i32.nxv8i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv8i32.nxv8i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwaddu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv8i32.nxv8i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv16i32.nxv16i16.nxv16i16( + , + , + , + iXLen); + +define @intrinsic_vwaddu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv16i32.nxv16i16.nxv16i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv16i32.nxv16i16.nxv16i16( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv16i32.nxv16i16.nxv16i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv16i32.nxv16i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwaddu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv16i32.nxv16i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv16i32.nxv16i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwaddu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv16i32.nxv16i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv2i64.nxv2i32.nxv2i32( + , + , + , + iXLen); + +define @intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv2i64.nxv2i32.nxv2i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv2i64.nxv2i32.nxv2i32( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv2i64.nxv2i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv2i64.nxv2i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv2i64.nxv2i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwaddu_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv2i64.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv4i64.nxv4i32.nxv4i32( + , + , + , + iXLen); + +define @intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv4i64.nxv4i32.nxv4i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv4i64.nxv4i32.nxv4i32( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv4i64.nxv4i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv4i64.nxv4i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv4i64.nxv4i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwaddu_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv4i64.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv8i64.nxv8i32.nxv8i32( + , + , + , + iXLen); + +define @intrinsic_vwaddu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv8i64.nxv8i32.nxv8i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv8i64.nxv8i32.nxv8i32( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.nxv8i64.nxv8i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwaddu_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.nxv8i64.nxv8i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.mask.nxv8i64.nxv8i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwaddu_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.mask.nxv8i64.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-LABEL: {{.*}} +; CHECK-NEXT: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.w.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.w.ll new file mode 100644 index 0000000000000..d610a81357be5 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vwaddu.w.ll @@ -0,0 +1,2304 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s + +declare @llvm.riscv.th.vwaddu.w.nxv8i16.nxv8i16.nxv8i8( + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_wv_nxv8i16_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv8i16.nxv8i16.nxv8i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv8i16.nxv8i16.nxv8i8( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i16.nxv8i16.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv8i16.nxv8i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwaddu_w_wx_nxv8i16_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv8i16.nxv8i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv8i16.nxv8i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i16.nxv8i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv16i16.nxv16i16.nxv16i8( + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_wv_nxv16i16_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv16i16.nxv16i16.nxv16i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv16i16.nxv16i16.nxv16i8( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv16i16.nxv16i16.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv16i16.nxv16i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwaddu_w_wx_nxv16i16_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv16i16.nxv16i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv16i16.nxv16i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv16i16.nxv16i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv32i16.nxv32i16.nxv32i8( + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_wv_nxv32i16_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv32i16.nxv32i16.nxv32i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv32i16.nxv32i16.nxv32i8( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv32i16.nxv32i16.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv32i16.nxv32i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwaddu_w_wx_nxv32i16_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv32i16.nxv32i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv32i16.nxv32i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv32i16.nxv32i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv4i32.nxv4i32.nxv4i16( + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_wv_nxv4i32_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv4i32.nxv4i32.nxv4i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv4i32.nxv4i32.nxv4i16( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv4i32.nxv4i32.nxv4i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv4i32.nxv4i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwaddu_w_wx_nxv4i32_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv4i32.nxv4i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv4i32.nxv4i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv4i32.nxv4i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv8i32.nxv8i32.nxv8i16( + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_wv_nxv8i32_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv8i32.nxv8i32.nxv8i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv8i32.nxv8i32.nxv8i16( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i32.nxv8i32.nxv8i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv8i32.nxv8i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwaddu_w_wx_nxv8i32_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv8i32.nxv8i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv8i32.nxv8i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i32.nxv8i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv16i32.nxv16i32.nxv16i16( + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_wv_nxv16i32_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv16i32.nxv16i32.nxv16i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv16i32.nxv16i32.nxv16i16( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e16, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv16i32.nxv16i32.nxv16i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv16i32.nxv16i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwaddu_w_wx_nxv16i32_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv16i32.nxv16i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv16i32.nxv16i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv16i32.nxv16i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv2i64.nxv2i64.nxv2i32( + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_wv_nxv2i64_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv2i64.nxv2i64.nxv2i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv2i64.nxv2i64.nxv2i32( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv2i64.nxv2i64.nxv2i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv2i64.nxv2i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwaddu_w_wx_nxv2i64_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv2i64.nxv2i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv2i64.nxv2i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv2i64.nxv2i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv4i64.nxv4i64.nxv4i32( + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_wv_nxv4i64_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv4i64.nxv4i64.nxv4i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv4i64.nxv4i64.nxv4i32( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv4i64.nxv4i64.nxv4i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv4i64.nxv4i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwaddu_w_wx_nxv4i64_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv4i64.nxv4i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv4i64.nxv4i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv4i64.nxv4i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv8i64.nxv8i64.nxv8i32( + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_wv_nxv8i64_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv8i64.nxv8i64.nxv8i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv8i64.nxv8i64.nxv8i32( + , + , + , + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e32, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i64.nxv8i64.nxv8i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.nxv8i64.nxv8i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwaddu_w_wx_nxv8i64_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv8i64.nxv8i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwaddu.w.mask.nxv8i64.nxv8i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwaddu_w_mask_wx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i64.nxv8i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i16.nxv8i16.nxv8i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv16i16.nxv16i16.nxv16i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv32i16.nxv32i16.nxv32i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv4i32.nxv4i32.nxv4i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i32.nxv8i32.nxv8i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv16i32.nxv16i32.nxv16i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv2i64.nxv2i64.nxv2i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv4i64.nxv4i64.nxv4i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i64.nxv8i64.nxv8i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wx_tie_nxv8i16_nxv8i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_tie_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i16.nxv8i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wx_tie_nxv16i16_nxv16i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_tie_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv16i16.nxv16i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wx_tie_nxv32i16_nxv32i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_tie_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv32i16.nxv32i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wx_tie_nxv4i32_nxv4i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_tie_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv4i32.nxv4i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wx_tie_nxv8i32_nxv8i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_tie_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i32.nxv8i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wx_tie_nxv16i32_nxv16i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_tie_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv16i32.nxv16i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wx_tie_nxv2i64_nxv2i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_tie_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv2i64.nxv2i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wx_tie_nxv4i64_nxv4i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_tie_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv4i64.nxv4i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_mask_wx_tie_nxv8i64_nxv8i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_mask_wx_tie_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.mask.nxv8i64.nxv8i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwaddu_w_wv_untie_nxv8i16_nxv8i16_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_untie_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv8i16.nxv8i16.nxv8i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwaddu_w_wv_untie_nxv16i16_nxv16i16_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_untie_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv16i16.nxv16i16.nxv16i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwaddu_w_wv_untie_nxv32i16_nxv32i16_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_untie_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v24, v16, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: th.vmv.v.v v9, v25 +; CHECK-NEXT: th.vmv.v.v v10, v26 +; CHECK-NEXT: th.vmv.v.v v11, v27 +; CHECK-NEXT: th.vmv.v.v v12, v28 +; CHECK-NEXT: th.vmv.v.v v13, v29 +; CHECK-NEXT: th.vmv.v.v v14, v30 +; CHECK-NEXT: th.vmv.v.v v15, v31 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv32i16.nxv32i16.nxv32i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwaddu_w_wv_untie_nxv4i32_nxv4i32_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_untie_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv4i32.nxv4i32.nxv4i16( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwaddu_w_wv_untie_nxv8i32_nxv8i32_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_untie_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv8i32.nxv8i32.nxv8i16( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwaddu_w_wv_untie_nxv2i64_nxv2i64_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_untie_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwaddu.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv2i64.nxv2i64.nxv2i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwaddu_w_wv_untie_nxv4i64_nxv4i64_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_untie_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwaddu.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv4i64.nxv4i64.nxv4i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwaddu_w_wv_untie_nxv8i64_nxv8i64_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_w_wv_untie_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwaddu.wv v24, v16, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: th.vmv.v.v v9, v25 +; CHECK-NEXT: th.vmv.v.v v10, v26 +; CHECK-NEXT: th.vmv.v.v v11, v27 +; CHECK-NEXT: th.vmv.v.v v12, v28 +; CHECK-NEXT: th.vmv.v.v v13, v29 +; CHECK-NEXT: th.vmv.v.v v14, v30 +; CHECK-NEXT: th.vmv.v.v v15, v31 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwaddu.w.nxv8i64.nxv8i64.nxv8i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vwsub.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vwsub.ll new file mode 100644 index 0000000000000..4a64164f27471 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vwsub.ll @@ -0,0 +1,1497 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT + +declare @llvm.riscv.th.vwsub.nxv8i16.nxv8i8.nxv8i8( + , + , + , + iXLen); + +define @intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsub.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv8i16.nxv8i8.nxv8i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv8i16.nxv8i8.nxv8i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv8i16.nxv8i8.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv8i16.nxv8i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsub.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv8i16.nxv8i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv8i16.nxv8i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsub_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv8i16.nxv8i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv16i16.nxv16i8.nxv16i8( + , + , + , + iXLen); + +define @intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsub.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv16i16.nxv16i8.nxv16i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv16i16.nxv16i8.nxv16i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv16i16.nxv16i8.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv16i16.nxv16i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsub.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv16i16.nxv16i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv16i16.nxv16i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsub_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv16i16.nxv16i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv32i16.nxv32i8.nxv32i8( + , + , + , + iXLen); + +define @intrinsic_vwsub_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsub.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv32i16.nxv32i8.nxv32i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv32i16.nxv32i8.nxv32i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv32i16.nxv32i8.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv32i16.nxv32i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsub_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsub.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv32i16.nxv32i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv32i16.nxv32i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsub_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv32i16.nxv32i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv4i32.nxv4i16.nxv4i16( + , + , + , + iXLen); + +define @intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsub.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv4i32.nxv4i16.nxv4i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv4i32.nxv4i16.nxv4i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv4i32.nxv4i16.nxv4i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv4i32.nxv4i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsub.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv4i32.nxv4i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv4i32.nxv4i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsub_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv4i32.nxv4i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv8i32.nxv8i16.nxv8i16( + , + , + , + iXLen); + +define @intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsub.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv8i32.nxv8i16.nxv8i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv8i32.nxv8i16.nxv8i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv8i32.nxv8i16.nxv8i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv8i32.nxv8i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsub.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv8i32.nxv8i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv8i32.nxv8i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsub_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv8i32.nxv8i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv16i32.nxv16i16.nxv16i16( + , + , + , + iXLen); + +define @intrinsic_vwsub_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwsub.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv16i32.nxv16i16.nxv16i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv16i32.nxv16i16.nxv16i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv16i32.nxv16i16.nxv16i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv16i32.nxv16i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsub_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsub.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv16i32.nxv16i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv16i32.nxv16i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsub_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv16i32.nxv16i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv2i64.nxv2i32.nxv2i32( + , + , + , + iXLen); + +define @intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsub.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv2i64.nxv2i32.nxv2i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv2i64.nxv2i32.nxv2i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv2i64.nxv2i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsub.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv2i64.nxv2i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv2i64.nxv2i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsub_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv2i64.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv4i64.nxv4i32.nxv4i32( + , + , + , + iXLen); + +define @intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsub.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv4i64.nxv4i32.nxv4i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv4i64.nxv4i32.nxv4i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv4i64.nxv4i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsub.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv4i64.nxv4i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv4i64.nxv4i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsub_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv4i64.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv8i64.nxv8i32.nxv8i32( + , + , + , + iXLen); + +define @intrinsic_vwsub_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsub.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv8i64.nxv8i32.nxv8i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv8i64.nxv8i32.nxv8i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.nxv8i64.nxv8i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsub_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsub.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.nxv8i64.nxv8i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.mask.nxv8i64.nxv8i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsub_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.mask.nxv8i64.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-LABEL: {{.*}} +; CHECK-NEXT: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vwsub.w.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vwsub.w.ll new file mode 100644 index 0000000000000..05d5f07e79655 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vwsub.w.ll @@ -0,0 +1,2304 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s + +declare @llvm.riscv.th.vwsub.w.nxv8i16.nxv8i16.nxv8i8( + , + , + , + iXLen); + +define @intrinsic_vwsub_w_wv_nxv8i16_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv8i16.nxv8i16.nxv8i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv8i16.nxv8i16.nxv8i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_w_mask_wv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i16.nxv8i16.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv8i16.nxv8i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsub_w_wx_nxv8i16_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv8i16.nxv8i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv8i16.nxv8i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsub_w_mask_wx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsub.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i16.nxv8i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv16i16.nxv16i16.nxv16i8( + , + , + , + iXLen); + +define @intrinsic_vwsub_w_wv_nxv16i16_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv16i16.nxv16i16.nxv16i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv16i16.nxv16i16.nxv16i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_w_mask_wv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv16i16.nxv16i16.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv16i16.nxv16i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsub_w_wx_nxv16i16_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv16i16.nxv16i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv16i16.nxv16i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsub_w_mask_wx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsub.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv16i16.nxv16i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv32i16.nxv32i16.nxv32i8( + , + , + , + iXLen); + +define @intrinsic_vwsub_w_wv_nxv32i16_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv32i16.nxv32i16.nxv32i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv32i16.nxv32i16.nxv32i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_w_mask_wv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsub.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv32i16.nxv32i16.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv32i16.nxv32i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsub_w_wx_nxv32i16_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv32i16.nxv32i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv32i16.nxv32i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsub_w_mask_wx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsub.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv32i16.nxv32i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv4i32.nxv4i32.nxv4i16( + , + , + , + iXLen); + +define @intrinsic_vwsub_w_wv_nxv4i32_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv4i32.nxv4i32.nxv4i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv4i32.nxv4i32.nxv4i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_w_mask_wv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv4i32.nxv4i32.nxv4i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv4i32.nxv4i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsub_w_wx_nxv4i32_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv4i32.nxv4i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv4i32.nxv4i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsub_w_mask_wx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsub.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv4i32.nxv4i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv8i32.nxv8i32.nxv8i16( + , + , + , + iXLen); + +define @intrinsic_vwsub_w_wv_nxv8i32_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv8i32.nxv8i32.nxv8i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv8i32.nxv8i32.nxv8i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_w_mask_wv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i32.nxv8i32.nxv8i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv8i32.nxv8i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsub_w_wx_nxv8i32_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv8i32.nxv8i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv8i32.nxv8i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsub_w_mask_wx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsub.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i32.nxv8i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv16i32.nxv16i32.nxv16i16( + , + , + , + iXLen); + +define @intrinsic_vwsub_w_wv_nxv16i32_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv16i32.nxv16i32.nxv16i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv16i32.nxv16i32.nxv16i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_w_mask_wv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e16, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsub.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv16i32.nxv16i32.nxv16i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv16i32.nxv16i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsub_w_wx_nxv16i32_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv16i32.nxv16i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv16i32.nxv16i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsub_w_mask_wx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsub.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv16i32.nxv16i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv2i64.nxv2i64.nxv2i32( + , + , + , + iXLen); + +define @intrinsic_vwsub_w_wv_nxv2i64_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv2i64.nxv2i64.nxv2i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv2i64.nxv2i64.nxv2i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_w_mask_wv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv2i64.nxv2i64.nxv2i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv2i64.nxv2i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsub_w_wx_nxv2i64_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv2i64.nxv2i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv2i64.nxv2i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsub_w_mask_wx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsub.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv2i64.nxv2i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv4i64.nxv4i64.nxv4i32( + , + , + , + iXLen); + +define @intrinsic_vwsub_w_wv_nxv4i64_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv4i64.nxv4i64.nxv4i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv4i64.nxv4i64.nxv4i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_w_mask_wv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv4i64.nxv4i64.nxv4i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv4i64.nxv4i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsub_w_wx_nxv4i64_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv4i64.nxv4i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv4i64.nxv4i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsub_w_mask_wx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsub.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv4i64.nxv4i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv8i64.nxv8i64.nxv8i32( + , + , + , + iXLen); + +define @intrinsic_vwsub_w_wv_nxv8i64_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv8i64.nxv8i64.nxv8i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv8i64.nxv8i64.nxv8i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsub_w_mask_wv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e32, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsub.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i64.nxv8i64.nxv8i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.nxv8i64.nxv8i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsub_w_wx_nxv8i64_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv8i64.nxv8i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsub.w.mask.nxv8i64.nxv8i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsub_w_mask_wx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsub.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i64.nxv8i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i16.nxv8i16.nxv8i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv16i16.nxv16i16.nxv16i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv32i16.nxv32i16.nxv32i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv4i32.nxv4i32.nxv4i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i32.nxv8i32.nxv8i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv16i32.nxv16i32.nxv16i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv2i64.nxv2i64.nxv2i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv4i64.nxv4i64.nxv4i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsub.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i64.nxv8i64.nxv8i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wx_tie_nxv8i16_nxv8i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_tie_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i16.nxv8i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wx_tie_nxv16i16_nxv16i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_tie_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv16i16.nxv16i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wx_tie_nxv32i16_nxv32i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_tie_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv32i16.nxv32i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wx_tie_nxv4i32_nxv4i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_tie_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv4i32.nxv4i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wx_tie_nxv8i32_nxv8i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_tie_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i32.nxv8i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wx_tie_nxv16i32_nxv16i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_tie_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv16i32.nxv16i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wx_tie_nxv2i64_nxv2i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_tie_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv2i64.nxv2i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wx_tie_nxv4i64_nxv4i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_tie_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv4i64.nxv4i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_mask_wx_tie_nxv8i64_nxv8i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_mask_wx_tie_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsub.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.mask.nxv8i64.nxv8i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsub_w_wv_untie_nxv8i16_nxv8i16_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_untie_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsub.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv8i16.nxv8i16.nxv8i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsub_w_wv_untie_nxv16i16_nxv16i16_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_untie_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsub.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv16i16.nxv16i16.nxv16i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsub_w_wv_untie_nxv32i16_nxv32i16_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_untie_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsub.wv v24, v16, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: th.vmv.v.v v9, v25 +; CHECK-NEXT: th.vmv.v.v v10, v26 +; CHECK-NEXT: th.vmv.v.v v11, v27 +; CHECK-NEXT: th.vmv.v.v v12, v28 +; CHECK-NEXT: th.vmv.v.v v13, v29 +; CHECK-NEXT: th.vmv.v.v v14, v30 +; CHECK-NEXT: th.vmv.v.v v15, v31 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv32i16.nxv32i16.nxv32i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsub_w_wv_untie_nxv4i32_nxv4i32_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_untie_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsub.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv4i32.nxv4i32.nxv4i16( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsub_w_wv_untie_nxv8i32_nxv8i32_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_untie_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsub.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv8i32.nxv8i32.nxv8i16( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsub_w_wv_untie_nxv2i64_nxv2i64_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_untie_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsub.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv2i64.nxv2i64.nxv2i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsub_w_wv_untie_nxv4i64_nxv4i64_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_untie_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsub.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv4i64.nxv4i64.nxv4i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsub_w_wv_untie_nxv8i64_nxv8i64_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_w_wv_untie_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsub.wv v24, v16, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: th.vmv.v.v v9, v25 +; CHECK-NEXT: th.vmv.v.v v10, v26 +; CHECK-NEXT: th.vmv.v.v v11, v27 +; CHECK-NEXT: th.vmv.v.v v12, v28 +; CHECK-NEXT: th.vmv.v.v v13, v29 +; CHECK-NEXT: th.vmv.v.v v14, v30 +; CHECK-NEXT: th.vmv.v.v v15, v31 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsub.w.nxv8i64.nxv8i64.nxv8i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.ll new file mode 100644 index 0000000000000..cae96e879bf36 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.ll @@ -0,0 +1,1497 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT + +declare @llvm.riscv.th.vwsubu.nxv8i16.nxv8i8.nxv8i8( + , + , + , + iXLen); + +define @intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv8i16.nxv8i8.nxv8i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv8i16.nxv8i8.nxv8i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv8i16.nxv8i8.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv8i16.nxv8i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv8i16.nxv8i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv8i16.nxv8i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsubu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv8i16.nxv8i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv16i16.nxv16i8.nxv16i8( + , + , + , + iXLen); + +define @intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv16i16.nxv16i8.nxv16i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv16i16.nxv16i8.nxv16i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv16i16.nxv16i8.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv16i16.nxv16i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv16i16.nxv16i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv16i16.nxv16i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsubu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv16i16.nxv16i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv32i16.nxv32i8.nxv32i8( + , + , + , + iXLen); + +define @intrinsic_vwsubu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv32i16.nxv32i8.nxv32i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv32i16.nxv32i8.nxv32i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv32i16.nxv32i8.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv32i16.nxv32i8.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsubu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv32i16.nxv32i8.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv32i16.nxv32i8.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsubu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv32i16.nxv32i8.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv4i32.nxv4i16.nxv4i16( + , + , + , + iXLen); + +define @intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv4i32.nxv4i16.nxv4i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv4i32.nxv4i16.nxv4i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv4i32.nxv4i16.nxv4i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv4i32.nxv4i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv4i32.nxv4i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv4i32.nxv4i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsubu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv4i32.nxv4i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv8i32.nxv8i16.nxv8i16( + , + , + , + iXLen); + +define @intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv8i32.nxv8i16.nxv8i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv8i32.nxv8i16.nxv8i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv8i32.nxv8i16.nxv8i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv8i32.nxv8i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv8i32.nxv8i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv8i32.nxv8i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsubu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv8i32.nxv8i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv16i32.nxv16i16.nxv16i16( + , + , + , + iXLen); + +define @intrinsic_vwsubu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv16i32.nxv16i16.nxv16i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv16i32.nxv16i16.nxv16i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv16i32.nxv16i16.nxv16i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv16i32.nxv16i16.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsubu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv16i32.nxv16i16.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv16i32.nxv16i16.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsubu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv16i32.nxv16i16.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv2i64.nxv2i32.nxv2i32( + , + , + , + iXLen); + +define @intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.vv v10, v8, v9 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv2i64.nxv2i32.nxv2i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv2i64.nxv2i32.nxv2i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.vv v8, v10, v11, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv2i64.nxv2i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.vx v10, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: th.vmv.v.v v9, v11 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv2i64.nxv2i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv2i64.nxv2i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsubu_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv2i64.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv4i64.nxv4i32.nxv4i32( + , + , + , + iXLen); + +define @intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.vv v12, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv4i64.nxv4i32.nxv4i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv4i64.nxv4i32.nxv4i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.vv v8, v12, v14, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv4i64.nxv4i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.vx v12, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vmv.v.v v10, v14 +; CHECK-NEXT: th.vmv.v.v v11, v15 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv4i64.nxv4i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv4i64.nxv4i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsubu_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv4i64.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv8i64.nxv8i32.nxv8i32( + , + , + , + iXLen); + +define @intrinsic_vwsubu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.vv v16, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv8i64.nxv8i32.nxv8i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv8i64.nxv8i32.nxv8i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.vv v8, v16, v20, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.nxv8i64.nxv8i32.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsubu_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.vx v16, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vmv.v.v v12, v20 +; CHECK-NEXT: th.vmv.v.v v13, v21 +; CHECK-NEXT: th.vmv.v.v v14, v22 +; CHECK-NEXT: th.vmv.v.v v15, v23 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.nxv8i64.nxv8i32.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.mask.nxv8i64.nxv8i32.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsubu_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.mask.nxv8i64.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-LABEL: {{.*}} +; CHECK-NEXT: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.w.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.w.ll new file mode 100644 index 0000000000000..d423f7fad908d --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vwsubu.w.ll @@ -0,0 +1,2304 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \ +; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s + +declare @llvm.riscv.th.vwsubu.w.nxv8i16.nxv8i16.nxv8i8( + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_wv_nxv8i16_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv8i16.nxv8i16.nxv8i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv8i16.nxv8i16.nxv8i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i16.nxv8i16.nxv8i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv8i16.nxv8i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsubu_w_wx_nxv8i16_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv8i16.nxv8i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv8i16.nxv8i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i16.nxv8i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv16i16.nxv16i16.nxv16i8( + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_wv_nxv16i16_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv16i16.nxv16i16.nxv16i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv16i16.nxv16i16.nxv16i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv16i16.nxv16i16.nxv16i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv16i16.nxv16i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsubu_w_wx_nxv16i16_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv16i16.nxv16i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv16i16.nxv16i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv16i16.nxv16i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv32i16.nxv32i16.nxv32i8( + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_wv_nxv32i16_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv32i16.nxv32i16.nxv32i8( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv32i16.nxv32i16.nxv32i8( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv32i16.nxv32i16.nxv32i8( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv32i16.nxv32i16.i8( + , + , + i8, + iXLen); + +define @intrinsic_vwsubu_w_wx_nxv32i16_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv32i16.nxv32i16.i8( + undef, + %0, + i8 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv32i16.nxv32i16.i8( + , + , + i8, + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv32i16.nxv32i16.i8( + %0, + %1, + i8 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv4i32.nxv4i32.nxv4i16( + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_wv_nxv4i32_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv4i32.nxv4i32.nxv4i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv4i32.nxv4i32.nxv4i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv4i32.nxv4i32.nxv4i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv4i32.nxv4i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsubu_w_wx_nxv4i32_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv4i32.nxv4i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv4i32.nxv4i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv4i32.nxv4i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv8i32.nxv8i32.nxv8i16( + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_wv_nxv8i32_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv8i32.nxv8i32.nxv8i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv8i32.nxv8i32.nxv8i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i32.nxv8i32.nxv8i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv8i32.nxv8i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsubu_w_wx_nxv8i32_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv8i32.nxv8i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv8i32.nxv8i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i32.nxv8i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv16i32.nxv16i32.nxv16i16( + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_wv_nxv16i32_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv16i32.nxv16i32.nxv16i16( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv16i32.nxv16i32.nxv16i16( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e16, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv16i32.nxv16i32.nxv16i16( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv16i32.nxv16i32.i16( + , + , + i16, + iXLen); + +define @intrinsic_vwsubu_w_wx_nxv16i32_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv16i32.nxv16i32.i16( + undef, + %0, + i16 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv16i32.nxv16i32.i16( + , + , + i16, + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv16i32.nxv16i32.i16( + %0, + %1, + i16 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv2i64.nxv2i64.nxv2i32( + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_wv_nxv2i64_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v10 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv2i64.nxv2i64.nxv2i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv2i64.nxv2i64.nxv2i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v10, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv2i64.nxv2i64.nxv2i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv2i64.nxv2i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsubu_w_wx_nxv2i64_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv2i64.nxv2i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv2i64.nxv2i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v10, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv2i64.nxv2i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv4i64.nxv4i64.nxv4i32( + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_wv_nxv4i64_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v12 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv4i64.nxv4i64.nxv4i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv4i64.nxv4i64.nxv4i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v12, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv4i64.nxv4i64.nxv4i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv4i64.nxv4i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsubu_w_wx_nxv4i64_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv4i64.nxv4i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv4i64.nxv4i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v12, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv4i64.nxv4i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv8i64.nxv8i64.nxv8i32( + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_wv_nxv8i64_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v16 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv8i64.nxv8i64.nxv8i32( + undef, + %0, + %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv8i64.nxv8i64.nxv8i32( + , + , + , + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e32, m4, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a2 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v16, v24, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i64.nxv8i64.nxv8i32( + %0, + %1, + %2, + %3, + iXLen %4) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.nxv8i64.nxv8i64.i32( + , + , + i32, + iXLen); + +define @intrinsic_vwsubu_w_wx_nxv8i64_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv8i64.nxv8i64.i32( + undef, + %0, + i32 %1, + iXLen %2) + + ret %a +} + +declare @llvm.riscv.th.vwsubu.w.mask.nxv8i64.nxv8i64.i32( + , + , + i32, + , + iXLen); + +define @intrinsic_vwsubu_w_mask_wx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v16, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i64.nxv8i64.i32( + %0, + %1, + i32 %2, + %3, + iXLen %4) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i16.nxv8i16.nxv8i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv16i16.nxv16i16.nxv16i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv32i16.nxv32i16.nxv32i8( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv4i32.nxv4i32.nxv4i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i32.nxv8i32.nxv8i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv16i32.nxv16i32.nxv16i16( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v10, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv2i64.nxv2i64.nxv2i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v12, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv4i64.nxv4i64.nxv4i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v8, v8, v16, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i64.nxv8i64.nxv8i32( + %0, + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wx_tie_nxv8i16_nxv8i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_tie_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i16.nxv8i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wx_tie_nxv16i16_nxv16i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_tie_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv16i16.nxv16i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wx_tie_nxv32i16_nxv32i16_i8( %0, i8 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_tie_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv32i16.nxv32i16.i8( + %0, + %0, + i8 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wx_tie_nxv4i32_nxv4i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_tie_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv4i32.nxv4i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wx_tie_nxv8i32_nxv8i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_tie_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i32.nxv8i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wx_tie_nxv16i32_nxv16i32_i16( %0, i16 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_tie_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv16i32.nxv16i32.i16( + %0, + %0, + i16 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wx_tie_nxv2i64_nxv2i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_tie_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv2i64.nxv2i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wx_tie_nxv4i64_nxv4i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_tie_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv4i64.nxv4i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_mask_wx_tie_nxv8i64_nxv8i64_i32( %0, i32 %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_mask_wx_tie_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.wx v8, v8, a0, v0.t +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.mask.nxv8i64.nxv8i64.i32( + %0, + %0, + i32 %1, + %2, + iXLen %3) + + ret %a +} + +define @intrinsic_vwsubu_w_wv_untie_nxv8i16_nxv8i16_nxv8i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_untie_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv8i16.nxv8i16.nxv8i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsubu_w_wv_untie_nxv16i16_nxv16i16_nxv16i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_untie_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv16i16.nxv16i16.nxv16i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsubu_w_wv_untie_nxv32i16_nxv32i16_nxv32i8( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_untie_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v24, v16, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: th.vmv.v.v v9, v25 +; CHECK-NEXT: th.vmv.v.v v10, v26 +; CHECK-NEXT: th.vmv.v.v v11, v27 +; CHECK-NEXT: th.vmv.v.v v12, v28 +; CHECK-NEXT: th.vmv.v.v v13, v29 +; CHECK-NEXT: th.vmv.v.v v14, v30 +; CHECK-NEXT: th.vmv.v.v v15, v31 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv32i16.nxv32i16.nxv32i8( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsubu_w_wv_untie_nxv4i32_nxv4i32_nxv4i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_untie_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv4i32.nxv4i32.nxv4i16( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsubu_w_wv_untie_nxv8i32_nxv8i32_nxv8i16( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_untie_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv8i32.nxv8i32.nxv8i16( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsubu_w_wv_untie_nxv2i64_nxv2i64_nxv2i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_untie_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vwsubu.wv v12, v10, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: th.vmv.v.v v9, v13 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv2i64.nxv2i64.nxv2i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsubu_w_wv_untie_nxv4i64_nxv4i64_nxv4i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_untie_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vwsubu.wv v16, v12, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: th.vmv.v.v v9, v17 +; CHECK-NEXT: th.vmv.v.v v10, v18 +; CHECK-NEXT: th.vmv.v.v v11, v19 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv4i64.nxv4i64.nxv4i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +} + +define @intrinsic_vwsubu_w_wv_untie_nxv8i64_nxv8i64_nxv8i32( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_w_wv_untie_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: csrr a1, vl +; CHECK-NEXT: csrr a2, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vsetvl zero, a1, a2 +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vwsubu.wv v24, v16, v8 +; CHECK-NEXT: csrr a0, vl +; CHECK-NEXT: csrr a1, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: th.vmv.v.v v9, v25 +; CHECK-NEXT: th.vmv.v.v v10, v26 +; CHECK-NEXT: th.vmv.v.v v11, v27 +; CHECK-NEXT: th.vmv.v.v v12, v28 +; CHECK-NEXT: th.vmv.v.v v13, v29 +; CHECK-NEXT: th.vmv.v.v v14, v30 +; CHECK-NEXT: th.vmv.v.v v15, v31 +; CHECK-NEXT: th.vsetvl zero, a0, a1 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vwsubu.w.nxv8i64.nxv8i64.nxv8i32( + undef, + %1, + %0, + iXLen %2) + + ret %a +}