diff --git a/.github/workflows/testbench.yml b/.github/workflows/testbench.yml
new file mode 100644
index 0000000..f376656
--- /dev/null
+++ b/.github/workflows/testbench.yml
@@ -0,0 +1,36 @@
+name: hdmi
+
+on: [push, pull_request]
+
+jobs:
+  test:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          fetch-depth: 0
+      - uses: actions/setup-python@v2
+        with:
+          python-version: '3.x'
+      - name: Install hdlmake
+        run: pip install -r requirements.txt
+      - name: Install ModelSim dependencies
+        run: |
+          sudo dpkg --add-architecture i386
+          sudo apt-get update
+          sudo apt-get install lib32z1 lib32stdc++6 libexpat1:i386 libc6:i386 libsm6:i386 libncurses5:i386 libx11-6:i386 zlib1g:i386 libxext6:i386 libxft2:i386
+      - name: Cache ModelSim
+        uses: actions/cache@v2
+        with:
+          path: $HOME/intelFPGA
+          key: ${{ runner.os }}-modelsim
+      - name: Install ModelSim if not cached
+        run: stat $HOME/intelFPGA/20.1/modelsim_ase || (curl 'https://download.altera.com/akdlm/software/acdsinst/20.1std.1/720/ib_installers/ModelSimSetup-20.1.1.720-linux.run' -o ModelSimSetup.run && chmod +x ModelSimSetup.run && ./ModelSimSetup.run --mode unattended --accept_eula 1 && sed -i 's/linux_rh60/linux/g' $HOME/intelFPGA/20.1/modelsim_ase/vco )
+      - name: Add ModelSim to PATH
+        run: echo "$HOME/intelFPGA/20.1/modelsim_ase/bin" >> $GITHUB_PATH
+      - name: Top Testbench
+        run: cd $GITHUB_WORKSPACE/sim/top_tb/ && hdlmake fetch && hdlmake && make
+      - name: Audio Param Testbench
+        run: cd $GITHUB_WORKSPACE/sim/audio_param_tb/ && hdlmake fetch && hdlmake && make
+      - name: Audio Clock Testbench
+        run: cd $GITHUB_WORKSPACE/sim/audio_param_tb/ && hdlmake fetch && hdlmake && make
\ No newline at end of file
diff --git a/.travis.yml b/.travis.yml
deleted file mode 100644
index 3bbd200..0000000
--- a/.travis.yml
+++ /dev/null
@@ -1,31 +0,0 @@
-sudo: required
-language: python
-os: linux
-addons:
-  apt:
-    update: false
-    packages:
-      - lib32z1
-      - lib32stdc++6
-      - libexpat1:i386
-      - libc6:i386
-      - libsm6:i386
-      - libncurses5:i386
-      - libx11-6:i386
-      - zlib1g:i386
-      - libxext6:i386
-      - libxft2:i386
-
-install:
-    - pip install -r requirements.txt
-    - stat /home/travis/intelFPGA/19.1/modelsim_ase || (curl 'http://download.altera.com/akdlm/software/acdsinst/19.1std/670/ib_installers/ModelSimSetup-19.1.0.670-linux.run' -o ModelSimSetup.run && chmod +x ModelSimSetup.run && travis_wait 30 ./ModelSimSetup.run --mode unattended --accept_eula 1 && sed -i 's/linux_rh60/linux/g' /home/travis/intelFPGA/19.1/modelsim_ase/vco )
-script:
-    - export PATH=$PATH:/home/travis/intelFPGA/19.1/modelsim_ase/bin
-    - cd ./sim/top_tb/ && hdlmake fetch && hdlmake && make
-    - cd -
-    - cd ./sim/audio_param_tb/ && hdlmake fetch && hdlmake && make
-    - cd -
-    - cd ./sim/audio_clock_tb/ && hdlmake fetch && hdlmake && make
-cache:
-    directories:
-        - /home/travis/intelFPGA/
diff --git a/README.md b/README.md
index 5601936..b65d9c9 100644
--- a/README.md
+++ b/README.md
@@ -2,7 +2,7 @@
 
 [English](./README.md) | [Français](./README_fr.md) | [Help translate](https://github.com/hdl-util/hdmi/issues/11)
 
-[![Build Status](https://travis-ci.com/hdl-util/hdmi.svg?branch=master)](https://travis-ci.com/hdl-util/hdmi)
+![hdmi](https://github.com/hdl-util/hdmi/workflows/hdmi/badge.svg)
 
 SystemVerilog code for HDMI 1.4b video/audio output on an [FPGA](https://simple.wikipedia.org/wiki/Field-programmable_gate_array).
 
diff --git a/README_fr.md b/README_fr.md
index b7b90a9..cb7ecca 100644
--- a/README_fr.md
+++ b/README_fr.md
@@ -1,8 +1,8 @@
 # hdmi
 
-[English](./README.md) | [Français](./README_fr.md) | [Help translate](https://github.com/hdl-util/hdmi/issues/11)
+[English](./README.md) | [Français](./README_fr.md) | [Nous aider avec la traduction](https://github.com/hdl-util/hdmi/issues/11)
 
-[![Statut de Construction](https://travis-ci.com/hdl-util/hdmi.svg?branch=master)](https://travis-ci.com/hdl-util/hdmi)
+![hdmi](https://github.com/hdl-util/hdmi/workflows/hdmi/badge.svg)
 
 SystemVerilog code pour transmettre vidéo/audio HDMI 1.4a sur un [FPGA](https://fr.wikipedia.org/wiki/Circuit_logique_programmable#FPGA).
 
diff --git a/sim/audio_clock_tb/Manifest.py b/sim/audio_clock_tb/Manifest.py
index 6ff86bc..f3a2747 100644
--- a/sim/audio_clock_tb/Manifest.py
+++ b/sim/audio_clock_tb/Manifest.py
@@ -2,7 +2,7 @@
 sim_tool = "modelsim"
 sim_top = "audio_clock_tb"
 
-sim_post_cmd = "vsim -novopt -do ../vsim.do -c audio_clock_tb"
+sim_post_cmd = "vsim -do ../vsim.do -c audio_clock_tb"
 
 modules = {
   "local" : [ "../../test/audio_clock_tb" ],
diff --git a/sim/audio_param_tb/Manifest.py b/sim/audio_param_tb/Manifest.py
index d19a55e..4aa9a99 100644
--- a/sim/audio_param_tb/Manifest.py
+++ b/sim/audio_param_tb/Manifest.py
@@ -2,7 +2,7 @@
 sim_tool = "modelsim"
 sim_top = "audio_param_tb"
 
-sim_post_cmd = "vsim -novopt -do ../vsim.do -c audio_param_tb"
+sim_post_cmd = "vsim -do ../vsim.do -c audio_param_tb"
 
 modules = {
   "local" : [ "../../test/audio_param_tb" ],
diff --git a/sim/spd_tb/Manifest.py b/sim/spd_tb/Manifest.py
index c0e3813..3ccc671 100644
--- a/sim/spd_tb/Manifest.py
+++ b/sim/spd_tb/Manifest.py
@@ -2,7 +2,7 @@
 sim_tool = "modelsim"
 sim_top = "spd_tb"
 
-sim_post_cmd = "vsim -novopt -do ../vsim.do -c spd_tb"
+sim_post_cmd = "vsim -do ../vsim.do -c spd_tb"
 
 modules = {
   "local" : [ "../../test/spd_tb" ],