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Half duplex SPI #75
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I'm trying to enable SPI1 in RCC.APB2ENR from the consuming crate. I'm unable to do that since the RCC rb has been moved in |
In general, HALs attempt to provide an API that protects the user from making mistakes (although in practice, all that I know fall short in various ways). One such mistake would be to, for example, to initialize a UART at 115200 baud, then invalidating that configuration by changing the clocks in RCC, which this HAL prevents by freezing the clock configuration.
I don't know if it's frowned upon, but I think HALs generally assume that they are in control. You are free to work around that by accessing the PAC API directly (see |
Thanks. I then got stuck on figuring out the receiving part. Let's say we'd have some blocking:: API with roughly: fn read(&mut self, words: &mut [u8]) -> Result<(), Error>;
fn write(&mut self, words: &[u8]) -> Result<(), Error>; The write impl is pretty straightforward, but with read one has to actively manage the half duplex: BIDIMODE=1 & BIDIOE=0 causes infinite SCK train to be produced. We don't want that, SCK should be disabled after receiving N words.
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SPI would benefit from half-duplex comms (SPI control register 1: BIDIMODE).
I realize this trait is missing in embedded-hal. I could potentially try to figure this out and bodge a prototype. But that ain't gonna be easy since I'm rather new to Rust.
Any pointers appreciated.
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