-
Main Changes
+
Main Changes
- First official release of STM32L4xx HAL Drivers for STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx and STM32L486xx devices
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
index 87385fc504..9d0c69301e 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
@@ -53,7 +53,7 @@
*/
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
-#define STM32L4XX_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
+#define STM32L4XX_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
index 9c51e6fb2d..c0d18e4a4e 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
@@ -33,7 +33,7 @@
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
- (+++) Configure CAN pins as alternate function open-drain
+ (+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
@@ -235,6 +235,7 @@
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
+#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
@@ -248,8 +249,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@@ -814,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
- * @brief Configuration functions.
- *
+ * @brief Configuration functions.
+ *
@verbatim
==============================================================================
##### Configuration functions #####
@@ -868,7 +869,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
-#endif
+#endif /* CAN3 */
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
@@ -878,7 +879,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
-#endif
+#endif /* CAN3 */
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
@@ -970,8 +971,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
+ * @brief Control functions
+ *
@verbatim
==============================================================================
##### Control functions #####
@@ -1143,7 +1144,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
- uint32_t timeout = 1000000U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@@ -1159,15 +1159,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
count++;
/* Check if timeout is reached */
- if (count > timeout)
+ if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
- }
- while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
+ } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@@ -1608,8 +1607,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFi
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
- * @brief Interrupts management
- *
+ * @brief Interrupts management
+ *
@verbatim
==============================================================================
##### Interrupts management #####
@@ -2074,8 +2073,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
- * @brief CAN Callback functions
- *
+ * @brief CAN Callback functions
+ *
@verbatim
==============================================================================
##### Callback functions #####
@@ -2324,8 +2323,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
+ * @brief CAN Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c
index 9af2683998..80650672d0 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c
@@ -351,7 +351,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
#else
MODIFY_REG(hcomp->Instance->CSR,
COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL |
- COMP_CSR_POLARITY | COMP_CSR_HYST |
+ COMP_CSR_POLARITY | COMP_CSR_HYST |
COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL,
tmp_csr
);
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
index 8b4ef7d8f9..c529a48ef0 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
@@ -451,6 +451,37 @@ void HAL_MPU_Disable(void)
MPU->CTRL = 0;
}
+/**
+ * @brief Enable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Disable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
/**
* @brief Initialize and configure the Region and the memory to be protected.
@@ -463,38 +494,31 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
- if ((MPU_Init->Enable) != RESET)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00;
- MPU->RASR = 0x00;
- }
+/* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+
+ /* Apply configuration */
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c
index 0382661ccb..cdf1f2638e 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c
@@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
#else
/* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+ CLEAR_REG(hcrc->Instance->IDR);
#endif /* CRC_IDR32BITSLENGTH_SUPPORT */
/* DeInit the low level hardware */
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c
index ffe13b1f12..c876bb6be3 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c
@@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
}
-
-
/**
* @}
*/
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c
index 223c614395..8fe7662c88 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c
@@ -529,7 +529,7 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
==============================================================================
[..] This section provides functions allowing to:
(+) Encrypt plaintext using AES algorithm in different chaining modes
- (+) Decrypt cyphertext using AES algorithm in different chaining modes
+ (+) Decrypt ciphertext using AES algorithm in different chaining modes
[..] Three processing functions are available:
(+) Polling mode
(+) Interrupt mode
@@ -546,7 +546,7 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
* the configuration information for CRYP module
* @param pPlainData Pointer to the plaintext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Timeout Specify Timeout value
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
* resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
@@ -577,7 +577,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
* the configuration information for CRYP module
* @param pPlainData Pointer to the plaintext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Timeout Specify Timeout value
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
* resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
@@ -608,7 +608,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
* the configuration information for CRYP module
* @param pPlainData Pointer to the plaintext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Timeout Specify Timeout value
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
* resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
@@ -634,10 +634,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Decrypt pCypherData in AES ECB decryption mode with key derivation,
- * the decyphered data are available in pPlainData.
+ * the deciphered data are available in pPlainData.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
* @param pPlainData Pointer to the plaintext buffer
* @param Timeout Specify Timeout value
@@ -665,10 +665,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
/**
* @brief Decrypt pCypherData in AES ECB decryption mode with key derivation,
- * the decyphered data are available in pPlainData.
+ * the deciphered data are available in pPlainData.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
* @param pPlainData Pointer to the plaintext buffer
* @param Timeout Specify Timeout value
@@ -696,10 +696,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
/**
* @brief Decrypt pCypherData in AES CTR decryption mode,
- * the decyphered data are available in pPlainData.
+ * the deciphered data are available in pPlainData.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
* @param pPlainData Pointer to the plaintext buffer
* @param Timeout Specify Timeout value
@@ -732,7 +732,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
* the configuration information for CRYP module
* @param pPlainData Pointer to the plaintext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
* resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
* @retval HAL status
@@ -762,7 +762,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
* the configuration information for CRYP module
* @param pPlainData Pointer to the plaintext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
* resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
* @retval HAL status
@@ -793,7 +793,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
* the configuration information for CRYP module
* @param pPlainData Pointer to the plaintext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
* resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
* @retval HAL status
@@ -818,10 +818,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt,
- * the decyphered data are available in pPlainData.
+ * the deciphered data are available in pPlainData.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
* @param pPlainData Pointer to the plaintext buffer.
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
@@ -848,10 +848,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt,
- * the decyphered data are available in pPlainData.
+ * the deciphered data are available in pPlainData.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
* @param pPlainData Pointer to the plaintext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
@@ -878,10 +878,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt,
- * the decyphered data are available in pPlainData.
+ * the deciphered data are available in pPlainData.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
* @param pPlainData Pointer to the plaintext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
@@ -913,7 +913,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
* the configuration information for CRYP module
* @param pPlainData Pointer to the plaintext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
* resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
* @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
@@ -946,7 +946,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
* the configuration information for CRYP module
* @param pPlainData Pointer to the plaintext buffer
* @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
* resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
* @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
@@ -977,7 +977,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
* the configuration information for CRYP module
* @param pPlainData Pointer to the plaintext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer.
+ * @param pCypherData Pointer to the ciphertext buffer.
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
* resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
* @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
@@ -1003,10 +1003,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Decrypt pCypherData in AES ECB decryption mode using DMA,
- * the decyphered data are available in pPlainData.
+ * the deciphered data are available in pPlainData.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
* @param pPlainData Pointer to the plaintext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
@@ -1034,10 +1034,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Decrypt pCypherData in AES CBC decryption mode using DMA,
- * the decyphered data are available in pPlainData.
+ * the deciphered data are available in pPlainData.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
* @param pPlainData Pointer to the plaintext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
@@ -1065,10 +1065,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Decrypt pCypherData in AES CTR decryption mode using DMA,
- * the decyphered data are available in pPlainData.
+ * the deciphered data are available in pPlainData.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param pCypherData Pointer to the ciphertext buffer
* @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
* @param pPlainData Pointer to the plaintext buffer
* @note This API is provided only to maintain compatibility with legacy software. Users should directly
@@ -1687,7 +1687,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
}
else /* Process the rest of input data */
{
- /* Get the Intput data address */
+ /* Get the Input data address */
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Increment/decrement instance pointer/counter */
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c
index 9a9394e865..b74bef585b 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c
@@ -264,7 +264,7 @@
and a pointer to the user callback function.
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
@@ -279,9 +279,9 @@
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
+ reset to the legacy weak (overridden) functions in the HAL_DAC_Init
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -296,7 +296,7 @@
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
@@ -1445,7 +1445,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1554,7 +1554,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
/**
* @brief Unregister a User DAC Callback
- * DAC Callback is redirected to the weak (surcharged) predefined callback
+ * DAC Callback is redirected to the weak (overridden) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c
index 994811f930..db05de93da 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c
@@ -425,10 +425,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
- /* OPAMP_CSR_OUTCAL is actually one value more */
- trimmingvalue++;
- /* Set right trimming */
- MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+ /* Check trimming value below maximum */
+ if (trimmingvalue < 0x1FU)
+ {
+ /* Trimming is actually one value more */
+ trimmingvalue++;
+
+ /* Set right trimming */
+ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+ }
}
/* Disable the selected DAC channel calibration */
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
index d476444acb..c9927db559 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
@@ -895,7 +895,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA Channel.
* @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @param pCallback pointer to private callbacsk function which has pointer to
+ * @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c
index bee68498f7..d0f03db532 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c
@@ -118,7 +118,7 @@
and a pointer to the user callback function.
(#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
- weak (overridden) function.
+ weak (surcharged) function.
@ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -130,16 +130,16 @@
(+) MspDeInitCallback : DMA2D MspDeInit.
(#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (overridden) functions:
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
- as weak (overridden) functions. They must be defined by the user to be resorted to.
+ as weak (surcharged) functions. They must be defined by the user to be resorted to.
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
@@ -151,7 +151,7 @@
When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (overridden) callbacks are used.
+ and weak (surcharged) callbacks are used.
[..]
(@) You can refer to the DMA2D HAL driver header file for more useful macros
@@ -335,7 +335,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
/* Before aborting any DMA2D transfer or CLUT loading, check
first whether or not DMA2D clock is enabled */
- if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
+ if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U)
{
/* Abort DMA2D transfer if any */
if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
@@ -443,7 +443,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DMA2D Callback
- * To be used instead of the weak (overridden) predefined callback
+ * To be used instead of the weak (surcharged) predefined callback
* @param hdma2d DMA2D handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -542,7 +542,7 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM
/**
* @brief Unregister a DMA2D Callback
- * DMA2D Callback is redirected to the weak (overridden) predefined callback
+ * DMA2D Callback is redirected to the weak (surcharged) predefined callback
* @param hdma2d DMA2D handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -583,11 +583,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
break;
case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
break;
default :
@@ -603,11 +603,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
switch (CallbackID)
{
case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
break;
default :
@@ -1043,7 +1043,8 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
@@ -1097,7 +1098,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
uint32_t LayerIdx)
{
/* Check the parameters */
@@ -1800,7 +1801,7 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
- DMA2D_LayerCfgTypeDef *pLayerCfg;
+ const DMA2D_LayerCfgTypeDef *pLayerCfg;
uint32_t regMask;
uint32_t regValue;
@@ -2082,7 +2083,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
* the configuration information for the DMA2D.
* @retval HAL state
*/
-HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d)
{
return hdma2d->State;
}
@@ -2093,7 +2094,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
* the configuration information for DMA2D.
* @retval DMA2D Error Code
*/
-uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
+uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d)
{
return hdma2d->ErrorCode;
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c
index ddb64423a9..8c3dd6d2e9 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c
@@ -130,7 +130,7 @@
all callbacks are set to the corresponding weak functions:
examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
+ reset to the legacy weak (overridden) functions in the HAL_DSI_Init()
and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -395,24 +395,53 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
}
}
- /*************************** Set the PHY parameters ***************************/
+ __HAL_DSI_ENABLE(hdsi);
+
+ /************************ Set the DSI clock parameters ************************/
+ /* Set the TX escape clock division factor */
+ hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
+ hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+ /*************************** Set the PHY parameters ***************************/
/* D-PHY clock and digital enable*/
- hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+ hdsi->Instance->PCTLR |= DSI_PCTLR_DEN;
+
+ hdsi->Instance->PCTLR |= DSI_PCTLR_CKE;
- /* Clock lane configuration */
- hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
- hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
/* Configure the number of active data lanes */
hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
- /************************ Set the DSI clock parameters ************************/
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | DSI_PSR_PSSC))
+ {
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
- /* Set the TX escape clock division factor */
- hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
- hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | \
+ DSI_PSR_PSS1 | DSI_PSR_PSSC))
+ {
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
/* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
/* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
@@ -431,6 +460,12 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
hdsi->Instance->IER[1U] = 0U;
hdsi->ErrorMsk = 0U;
+ __HAL_DSI_DISABLE(hdsi);
+
+ /* Clock lane configuration */
+ hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
+ hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
+
/* Initialize the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
@@ -1628,14 +1663,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
- uint8_t *ParametersTable)
+ const uint8_t *ParametersTable)
{
uint32_t uicounter;
uint32_t nbBytes;
uint32_t count;
uint32_t tickstart;
uint32_t fifoword;
- uint8_t *pparams = ParametersTable;
+ const uint8_t *pparams = ParametersTable;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -3099,7 +3134,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
* the configuration information for the DSI.
* @retval HAL state
*/
-HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
+HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi)
{
return hdsi->State;
}
@@ -3110,7 +3145,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
* the configuration information for the DSI.
* @retval DSI Error Code
*/
-uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
+uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi)
{
/* Get the error code */
return hdsi->ErrorCode;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
index 6ba7d60e81..5933b2d20c 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
@@ -301,7 +301,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
@@ -387,7 +387,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
* @brief Read the specified input port pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to read.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@@ -417,7 +417,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
*
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
@@ -468,7 +468,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* until the next reset.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bits to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c
index 8eede1343c..2d17a9a297 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c
@@ -123,7 +123,7 @@
(#) HAL in interruption mode (interruptions driven)
(##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
- This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+ This is why, for driver implementation simplicity s sake, user is requested to enter a message the
length of which is a multiple of 4 bytes.
(##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
@@ -1825,8 +1825,9 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
{
uint32_t buffercounter;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t tmp;
- for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U)
+ for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++)
{
/* Write input data 4 bytes at a time */
HASH->DIN = *(uint32_t *)inputaddr;
@@ -1834,8 +1835,16 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
- if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size))
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size))
{
+ /* wait for flag BUSY not set before Wait for DINIS = 1*/
+ if ((buffercounter * 4U) >= 64U)
+ {
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
/* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
in the input buffer */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
@@ -1850,14 +1859,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashInCount = Size - (buffercounter + 4U);
+ hhash->HashInCount = Size - ((buffercounter * 4U) + 4U);
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashKeyCount = Size - (buffercounter + 4U);
+ hhash->HashKeyCount = Size - ((buffercounter * 4U) + 4U);
}
else
{
@@ -1876,6 +1885,52 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
} /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
/* At this point, all the data have been entered to the Peripheral: exit */
+
+ if ((Size % 4U) != 0U)
+ {
+ if (hhash->Init.DataType == HASH_DATATYPE_16B)
+ {
+ /* Write remaining input data */
+
+ if ((Size % 4U) <= 2U)
+ {
+ HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+ }
+ if ((Size % 4U) == 3U)
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ }
+
+ }
+ else if ((hhash->Init.DataType == HASH_DATATYPE_8B)
+ || (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */
+ {
+ /* Write remaining input data */
+ if ((Size % 4U) == 1U)
+ {
+ HASH->DIN = (uint32_t) * (uint8_t *)inputaddr;
+ }
+ if ((Size % 4U) == 2U)
+ {
+ HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+ }
+ if ((Size % 4U) == 3U)
+ {
+ tmp = *(uint8_t *)inputaddr;
+ tmp |= (uint32_t)*(uint8_t *)(inputaddr + 1U) << 8U;
+ tmp |= (uint32_t)*(uint8_t *)(inputaddr + 2U) << 16U;
+ HASH->DIN = tmp;
+ }
+
+ }
+ else
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ }
+ /*hhash->HashInCount += 4U;*/
+ }
+
+
return HAL_OK;
}
@@ -2963,11 +3018,11 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
HAL_StatusTypeDef status ;
HAL_HASH_StateTypeDef State_tmp = hhash->State;
-#if defined (HASH_CR_MDMAT)
+ #if defined (HASH_CR_MDMAT)
/* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
(case of multi-buffer HASH processing) */
assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
-#endif /* MDMA defined*/
+ #endif /* MDMA defined*/
/* If State is ready or suspended, start or resume polling-based HASH processing */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
@@ -3446,7 +3501,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
/* Enable the DMA In DMA channel */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
(((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \
- : (inputSize / 4U)));
+ : (inputSize / 4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c
index b3eb1c62fc..6592b2c946 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c
@@ -106,8 +106,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx;
-
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
@@ -117,8 +115,6 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
- USBx = hhcd->Instance;
-
if (hhcd->State == HAL_HCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -148,22 +144,31 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
hhcd->State = HAL_HCD_STATE_BUSY;
/* Disable DMA mode for FS instance */
- if ((USBx->CID & (0x1U << 8)) == 0U)
- {
- hhcd->Init.dma_enable = 0U;
- }
+ hhcd->Init.dma_enable = 0U;
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */
- (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
+ if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
- /* Force Host Mode*/
- (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
+ /* Force Host Mode */
+ if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init Host */
- (void)USB_HostInit(hhcd->Instance, hhcd->Init);
+ if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
hhcd->State = HAL_HCD_STATE_READY;
@@ -1201,7 +1206,7 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1417,7 +1422,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
*/
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
uint32_t num_packets;
@@ -1558,7 +1563,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts;
uint32_t pktcnt;
@@ -1624,7 +1629,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
*/
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0;
__IO uint32_t hprt0_dup;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
index 30bea1ec62..f2a44238cb 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
@@ -90,7 +90,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@@ -156,7 +156,7 @@
HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
@@ -214,7 +214,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@@ -1288,7 +1288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_READ);
}
@@ -1379,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
uint32_t Timeout)
{
uint32_t tickstart;
+ uint16_t tmpXferCount;
+ HAL_StatusTypeDef error;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1405,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
/* Preload TX data if no stretch enable */
if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
{
@@ -1426,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
hi2c->XferCount--;
}
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ return HAL_ERROR;
+ }
+
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
@@ -1437,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
return HAL_ERROR;
}
@@ -1449,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
return HAL_ERROR;
}
@@ -1472,31 +1486,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Wait until AF flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
+
+ if (error != HAL_OK)
{
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+
+ tmpXferCount = hi2c->XferCount;
+ if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+ {
+ /* Reset ErrorCode to NONE */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
}
+ else
+ {
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
- return HAL_ERROR;
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
@@ -1778,7 +1809,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
xfermode = I2C_RELOAD_MODE;
}
else
@@ -2127,7 +2158,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
xfermode = I2C_RELOAD_MODE;
}
else
@@ -2674,7 +2705,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_READ);
}
@@ -2712,7 +2743,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
}
@@ -3322,22 +3353,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials == Trials)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
/* Increment Trials */
I2C_Trials++;
} while (I2C_Trials < Trials);
@@ -4549,7 +4564,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@@ -4558,7 +4573,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
- if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
+
+ if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -4983,7 +5000,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
@@ -5138,7 +5163,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
{
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@@ -5172,7 +5205,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
@@ -5229,9 +5270,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
-
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -5394,7 +5434,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
xfermode = I2C_RELOAD_MODE;
}
else
@@ -5542,7 +5590,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@@ -5589,7 +5645,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
@@ -5659,9 +5723,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
-
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -6260,6 +6323,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
+ uint32_t tmpoptions = hi2c->XferOptions;
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
@@ -6347,6 +6411,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hi2c->XferCount == 0U)
+ {
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, tmpITFlags);
+ }
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ }
+ }
+
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -6764,7 +6879,15 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
/* Set the XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
}
else
{
@@ -6875,6 +6998,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
@@ -6986,16 +7115,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ HAL_StatusTypeDef status = HAL_OK;
+
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
/* Check if a STOPF is detected */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
{
/* Check if an RXNE is pending */
/* Store Last receive data if any */
@@ -7003,19 +7134,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
- return HAL_OK;
+ status = HAL_OK;
}
- else
+
+ /* Check a no-acknowledge have been detected */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- {
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -7029,12 +7155,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
}
/* Check for the Timeout */
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
{
@@ -7044,11 +7174,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ status = HAL_ERROR;
}
}
}
- return HAL_OK;
+ return status;
}
/**
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
index 51d12928df..08550b316f 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
@@ -126,7 +126,8 @@
The timeout value is multiplied by 1000 to be converted in milliseconds.
LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
+#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
+ ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c
index 00a41fc8da..9b5b3d49a1 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c
@@ -388,10 +388,10 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
}
else
{
- /* Check LPTIM2 Input1 source */
+ /* Check LPTIM Input1 source */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
- /* Configure LPTIM2 Input1 source */
+ /* Configure LPTIM Input1 source */
hlptim->Instance->OR = hlptim->Init.Input1Source;
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c
index 27c55f6f94..aa088a6ef7 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c
@@ -279,24 +279,20 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
/* Set Synchronization size */
- hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
tmp = (hltdc->Init.HorizontalSync << 16U);
- hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
+ WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync));
/* Set Accumulated Back porch */
- hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
tmp = (hltdc->Init.AccumulatedHBP << 16U);
- hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
+ WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP));
/* Set Accumulated Active Width */
- hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
- hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
+ WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH));
/* Set Total Width */
- hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
tmp = (hltdc->Init.TotalWidth << 16U);
- hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
+ WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh));
/* Set the background color value */
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
@@ -916,11 +912,12 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize,
+ uint32_t LayerIdx)
{
uint32_t tmp;
uint32_t counter;
- uint32_t *pcolorlut = pCLUT;
+ const uint32_t *pcolorlut = pCLUT;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
@@ -2092,7 +2089,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3
* the configuration information for the LTDC.
* @retval HAL state
*/
-HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc)
{
return hltdc->State;
}
@@ -2103,7 +2100,7 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
* the configuration information for the LTDC.
* @retval LTDC Error Code
*/
-uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
+uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc)
{
return hltdc->ErrorCode;
}
@@ -2154,9 +2151,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
tmp2 = (pLayerCfg->Alpha0 << 24U);
- LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED |
- LTDC_LxDCCR_DCALPHA);
- LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
+ WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2));
/* Specifies the constant alpha value */
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
@@ -2167,8 +2162,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
/* Configure the color frame buffer start address */
- LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
- LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
+ WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress);
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c
index b977ac3be6..6fe2e03c7d 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c
@@ -75,7 +75,7 @@
SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
- (#) Initialize the SDMMC peripheral interface with defaullt configuration.
+ (#) Initialize the SDMMC peripheral interface with default configuration.
The initialization process is done at 400KHz. You can change or adapt
this frequency by adjusting the "ClockDiv" field.
The MMC Card frequency (SDMMC_CK) is computed as follows:
@@ -305,7 +305,7 @@
#define MMC_EXT_CSD_S_A_TIMEOUT_POS 8
/* Frequencies used in the driver for clock divider calculation */
-#define MMC_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
+#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */
/**
* @}
@@ -4365,7 +4365,14 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
}
else
{
- Init.ClockDiv = sdmmc_clk/(2U*MMC_HIGH_SPEED_FREQ);
+ if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = 0;
+ }
+ else
+ {
+ Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U;
+ }
(void)SDMMC_Init(hmmc->Instance, Init);
SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c
index d5e378d2b9..8da9bd02b0 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c
@@ -493,7 +493,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
* @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig)
{
hnand->Config.PageSize = pDeviceConfig->PageSize;
hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c
index f92a91efb5..bf3e07c3c7 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c
@@ -1145,7 +1145,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u
*((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;
hospi->pBuffPtr++;
hospi->XferCount--;
- } while (hospi->XferCount > 0U);
+ }
+ while (hospi->XferCount > 0U);
if (status == HAL_OK)
{
@@ -1238,7 +1239,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui
*hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
hospi->pBuffPtr++;
hospi->XferCount--;
- } while (hospi->XferCount > 0U);
+ }
+ while (hospi->XferCount > 0U);
if (status == HAL_OK)
{
@@ -2596,8 +2598,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
#endif
/********************* Deactivation of other instance *********************/
- if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) ||
- (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
+ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) ||
+ ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) ||
+ (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
#if defined (OCTOSPIM_CR_MUXEN)
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c
index f6c0695f7b..fef5e99d13 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c
@@ -130,9 +130,6 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
-#if defined (USB_OTG_FS)
- USB_OTG_GlobalTypeDef *USBx;
-#endif /* defined (USB_OTG_FS) */
uint8_t i;
/* Check the PCD handle allocation */
@@ -144,10 +141,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-#if defined (USB_OTG_FS)
- USBx = hpcd->Instance;
-#endif /* defined (USB_OTG_FS) */
-
if (hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -183,13 +176,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State = HAL_PCD_STATE_BUSY;
-#if defined (USB_OTG_FS)
/* Disable DMA mode for FS instance */
- if ((USBx->CID & (0x1U << 8)) == 0U)
- {
- hpcd->Init.dma_enable = 0U;
- }
-#endif /* defined (USB_OTG_FS) */
+ hpcd->Init.dma_enable = 0U;
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@@ -201,8 +189,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
return HAL_ERROR;
}
- /* Force Device Mode*/
- (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+ /* Force Device Mode */
+ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
@@ -1930,7 +1922,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
- HAL_StatusTypeDef ret = HAL_OK;
+ HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
@@ -1945,7 +1937,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
ep->num = ep_addr & EP_ADDR_MSK;
- ep->maxpacket = ep_mps;
+ ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
ep->type = ep_type;
#if defined (USB_OTG_FS)
@@ -2322,9 +2314,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
*/
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (gSNPSiD == USB_OTG_CORE_ID_310A)
@@ -2369,9 +2361,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
@@ -2501,7 +2493,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
{
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
}
}
@@ -2622,7 +2613,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
/* Manage Single Buffer Transaction */
if ((wEPVal & USB_EP_KIND) == 0U)
{
- /* multi-packet on the NON control IN endpoint */
+ /* Multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len > TxPctSize)
@@ -2698,7 +2689,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
if (ep->xfer_len == 0U)
{
- /* set NAK to OUT endpoint since double buffer is enabled */
+ /* Set NAK to OUT endpoint since double buffer is enabled */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
@@ -2730,11 +2721,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
if (ep->xfer_len == 0U)
{
- /* set NAK on the current endpoint */
+ /* Set NAK on the current endpoint */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
- /*Need to FreeUser Buffer*/
+ /* Need to FreeUser Buffer */
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
@@ -2784,6 +2775,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ if (ep->type == EP_TYPE_BULK)
+ {
+ /* Set Bulk endpoint in NAK state */
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
+ }
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2795,10 +2792,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
+
+ return HAL_OK;
}
else /* Transfer is not yet Done */
{
- /* need to Free USB Buff */
+ /* Need to Free USB Buffer */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
@@ -2829,7 +2828,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
}
/* Write remaining Data to Buffer */
- /* Set the Double buffer counter for pma buffer1 */
+ /* Set the Double buffer counter for pma buffer0 */
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
/* Copy user buffer to USB PMA */
@@ -2857,6 +2856,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ if (ep->type == EP_TYPE_BULK)
+ {
+ /* Set Bulk endpoint in NAK state */
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
+ }
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2869,10 +2874,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
+
+ return HAL_OK;
}
else /* Transfer is not yet Done */
{
- /* need to Free USB Buff */
+ /* Need to Free USB Buffer */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
@@ -2902,7 +2909,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
ep->xfer_fill_db = 0;
}
- /* Set the Double buffer counter for pmabuffer1 */
+ /* Set the Double buffer counter for pma buffer1 */
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
/* Copy the user buffer to USB PMA */
@@ -2911,13 +2918,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
}
}
- /*enable endpoint IN*/
+ /* Enable endpoint IN */
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
return HAL_OK;
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
#endif /* defined (USB) */
/**
@@ -2925,7 +2931,6 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#endif /* HAL_PCD_MODULE_ENABLED */
-
/**
* @}
*/
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c
index 5d7a0bff46..94c487e5df 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c
@@ -178,7 +178,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
/* Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
- USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
+ USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
@@ -470,7 +470,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
}
}
-
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
@@ -505,7 +504,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
return HAL_OK;
}
-
#endif /* defined (USB) */
/**
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pka.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pka.c
index 101d091dc3..be900a87c4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pka.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pka.c
@@ -277,9 +277,9 @@
/** @defgroup PKA_Private_Functions PKA Private Functions
* @{
*/
-uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka);
-HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
-uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode);
+uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka);
+HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
+uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode);
uint32_t PKA_GetBitSize_u8(uint32_t byteNumber);
uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb);
uint32_t PKA_GetBitSize_u32(uint32_t wordNumber);
@@ -787,7 +787,6 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i
{
/* Set input parameter in PKA RAM */
PKA_ModExp_Set(hpka, in);
-
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout);
}
@@ -802,7 +801,6 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef
{
/* Set input parameter in PKA RAM */
PKA_ModExp_Set(hpka, in);
-
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP);
}
@@ -818,7 +816,6 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast
{
/* Set input parameter in PKA RAM */
PKA_ModExpFastMode_Set(hpka, in);
-
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout);
}
@@ -833,7 +830,6 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF
{
/* Set input parameter in PKA RAM */
PKA_ModExpFastMode_Set(hpka, in);
-
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
}
@@ -867,7 +863,6 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType
{
/* Set input parameter in PKA RAM */
PKA_ECDSASign_Set(hpka, in);
-
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout);
}
@@ -882,7 +877,6 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT
{
/* Set input parameter in PKA RAM */
PKA_ECDSASign_Set(hpka, in);
-
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE);
}
@@ -1059,7 +1053,6 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i
{
/* Set input parameter in PKA RAM */
PKA_ECCMul_Set(hpka, in);
-
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
}
@@ -1074,7 +1067,6 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef
{
/* Set input parameter in PKA RAM */
PKA_ECCMul_Set(hpka, in);
-
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
}
@@ -1571,12 +1563,11 @@ void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka)
void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
{
uint32_t mode = PKA_GetMode(hpka);
- FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR);
- FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR);
- FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND);
+ uint32_t itsource = READ_REG(hpka->Instance->CR);
+ uint32_t flag = READ_REG(hpka->Instance->SR);
/* Address error interrupt occurred */
- if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET))
+ if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR))
{
hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR;
@@ -1585,7 +1576,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
}
/* RAM access error interrupt occurred */
- if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET))
+ if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR))
{
hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR;
@@ -1613,7 +1604,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
}
/* End Of Operation interrupt occurred */
- if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET))
+ if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND))
{
/* Clear PROCEND flag */
__HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND);
@@ -1682,7 +1673,7 @@ __weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka)
* @param hpka PKA handle
* @retval HAL status
*/
-HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka)
+HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka)
{
/* Return PKA handle state */
return hpka->State;
@@ -1693,7 +1684,7 @@ HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka)
* @param hpka PKA handle
* @retval PKA error code
*/
-uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka)
+uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka)
{
/* Return PKA handle error code */
return hpka->ErrorCode;
@@ -1716,7 +1707,7 @@ uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka)
* @param hpka PKA handle
* @retval Return the current mode
*/
-uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka)
+uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka)
{
/* return the shifted PKA_CR_MODE value */
return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
@@ -1729,7 +1720,7 @@ uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka)
* @param Tickstart Tick start value
* @retval HAL status
*/
-HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
+HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
{
/* Wait for the end of operation or timeout */
while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL)
@@ -1752,7 +1743,7 @@ HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeo
* @param mode PKA operating mode
* @retval error code
*/
-uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode)
+uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode)
{
uint32_t err = HAL_PKA_ERROR_NONE;
@@ -2109,6 +2100,8 @@ void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
+ * @note If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash
+ * for example)the hash value should be written at the end of the buffer with zeros padding at beginning.
*/
void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
{
@@ -2321,7 +2314,6 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
}
-
/**
* @brief Set input parameters.
* @param hpka PKA handle
@@ -2401,7 +2393,7 @@ void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
/* Move the input parameters modulus value n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + ((in->modSize + 3UL) / 4UL));
}
/**
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pssi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pssi.c
index eb9c00d87e..d6ef96fcb6 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pssi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pssi.c
@@ -53,7 +53,6 @@
(#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
(GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.
-
(#) For PSSI IO operations, two operation modes are available within this driver :
*** Polling mode IO operation ***
@@ -179,11 +178,12 @@
* @{
*/
/* Private functions to handle DMA transfer */
+#if defined(HAL_DMA_MODULE_ENABLED)
void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
void PSSI_DMAError(DMA_HandleTypeDef *hdma);
void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
-
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Private functions to handle IT transfer */
static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
@@ -264,6 +264,7 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
/* Allocate lock resource and initialize it */
hpssi->Lock = HAL_UNLOCKED;
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/* Init the PSSI Callback settings */
hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
@@ -277,7 +278,10 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hpssi->MspInitCallback(hpssi);
-
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_PSSI_MspInit(hpssi);
+#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/
}
hpssi->State = HAL_PSSI_STATE_BUSY;
@@ -320,6 +324,7 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi)
/* Disable the PSSI Peripheral Clock */
HAL_PSSI_DISABLE(hpssi);
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
if (hpssi->MspDeInitCallback == NULL)
{
hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
@@ -327,6 +332,10 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi)
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
hpssi->MspDeInitCallback(hpssi);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_PSSI_MspDeInit(hpssi);
+#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/
hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
hpssi->State = HAL_PSSI_STATE_RESET;
@@ -369,6 +378,7 @@ __weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi)
*/
}
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User PSSI Callback
* To be used instead of the weak predefined callback
@@ -563,6 +573,7 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS
return status;
}
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
@@ -639,10 +650,13 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
HAL_PSSI_DISABLE(hpssi);
/* Configure transfer parameters */
- hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL);
+ MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
+ (PSSI_CR_OUTEN_OUTPUT |((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
/* DMA Disable */
hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Enable the selected PSSI peripheral */
HAL_PSSI_ENABLE(hpssi);
@@ -696,7 +710,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
/* Increment Buffer pointer */
pbuffer++;
transfer_size -= 2U;
-
}
}
else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
@@ -722,7 +735,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
pbuffer++;
transfer_size -= 4U;
}
-
}
else
{
@@ -758,7 +770,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
}
}
-
/**
* @brief Receives an amount of data in blocking mode.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -792,11 +803,13 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
/* Configure transfer parameters */
- hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL);
+ MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
+ (PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL)));
+#if defined(HAL_DMA_MODULE_ENABLED)
/* DMA Disable */
hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Enable the selected PSSI peripheral */
HAL_PSSI_ENABLE(hpssi);
@@ -846,7 +859,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
*pbuffer = *dr;
pbuffer++;
transfer_size -= 2U;
-
}
}
else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
@@ -871,7 +883,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
*pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR);
pbuffer++;
transfer_size -= 4U;
-
}
}
else
@@ -892,7 +903,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
return HAL_ERROR;
}
-
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
@@ -906,6 +916,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Transmit an amount of data in non-blocking mode with DMA
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -949,18 +960,18 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa
{
/* Configure BusWidth */
- if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
- {
- MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
- PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
- }
- else
- {
- MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
- PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
- }
+ if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+ {
+ MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+ PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
+ }
+ else
+ {
+ MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+ PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
+ }
/* Set the PSSI DMA transfer complete callback */
hpssi->hdmatx->XferCpltCallback = PSSI_DMATransmitCplt;
@@ -992,8 +1003,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa
if (dmaxferstatus == HAL_OK)
{
-
-
/* Update XferCount value */
hpssi->XferCount -= hpssi->XferSize;
@@ -1038,7 +1047,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa
HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
}
-
return HAL_OK;
}
else
@@ -1088,19 +1096,18 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
{
if (hpssi->hdmarx != NULL)
{
-
/* Configure BusWidth */
- if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
- {
- MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
- }
- else
- {
- MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
- PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
- }
+ if (hpssi->hdmarx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+ {
+ MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
+ }
+ else
+ {
+ MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+ PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
+ }
/* Set the PSSI DMA transfer complete callback */
hpssi->hdmarx->XferCpltCallback = PSSI_DMAReceiveCplt;
@@ -1165,7 +1172,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
}
else
{
-
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
@@ -1181,8 +1187,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
}
}
-
-
/**
* @brief Abort a DMA process communication with Interrupt.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -1191,7 +1195,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
*/
HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
{
-
/* Process Locked */
__HAL_LOCK(hpssi);
@@ -1206,7 +1209,6 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
{
if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
{
-
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmatx != NULL)
@@ -1222,12 +1224,10 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
}
}
-
}
/* Abort DMA RX transfer if any */
else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
{
-
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmarx != NULL)
@@ -1246,12 +1246,16 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
}
else
{
+
/* Call the error callback */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->ErrorCallback(hpssi);
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
}
-
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
@@ -1261,8 +1265,8 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
return HAL_OK;
-
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @}
@@ -1284,13 +1288,12 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U)
{
/* Reset handle parameters */
-
hpssi->XferCount = 0U;
/* Disable all interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort DMA TX transfer if any */
if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
{
@@ -1317,7 +1320,6 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
}
}
-
}
/* Abort DMA RX transfer if any */
else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
@@ -1346,10 +1348,15 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
}
else
{
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/* Call the corresponding callback to inform upper layer of the error */
hpssi->ErrorCallback(hpssi);
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* If state is an abort treatment on going, don't change state */
if (hpssi->State == HAL_PSSI_STATE_ABORT)
@@ -1359,9 +1366,12 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->AbortCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
else
{
@@ -1370,15 +1380,16 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->ErrorCallback(hpssi);
-
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
-
}
}
-
/**
* @brief Tx Transfer complete callback.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -1411,7 +1422,6 @@ __weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi)
*/
}
-
/**
* @brief PSSI error callback.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -1469,20 +1479,19 @@ __weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi)
* the configuration information for the specified PSSI.
* @retval HAL state
*/
-HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi)
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi)
{
/* Return PSSI handle state */
return hpssi->State;
}
-
/**
* @brief Return the PSSI error code.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval PSSI Error Code
*/
-uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi)
+uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi)
{
return hpssi->ErrorCode;
}
@@ -1507,9 +1516,7 @@ uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi)
*/
static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
{
-
/* Reset handle parameters */
-
hpssi->XferCount = 0U;
/* Set new error code */
@@ -1518,7 +1525,7 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
/* Disable all interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort DMA TX transfer if any */
if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
{
@@ -1542,7 +1549,6 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
}
}
-
}
/* Abort DMA RX transfer if any */
else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
@@ -1571,6 +1577,7 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
/*Nothing to do*/
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* If state is an abort treatment on going, don't change state */
if (hpssi->State == HAL_PSSI_STATE_ABORT)
@@ -1581,9 +1588,11 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->AbortCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
else
{
@@ -1594,11 +1603,15 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->ErrorCallback(hpssi);
-
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief DMA PSSI slave transmit process complete callback.
* @param hdma DMA handle
@@ -1611,7 +1624,6 @@ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
uint32_t tmperror;
-
/* Disable Interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
@@ -1633,12 +1645,12 @@ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->TxCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_TxCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
-
-
}
/**
@@ -1653,7 +1665,6 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
uint32_t tmperror;
-
/* Disable Interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
@@ -1675,11 +1686,12 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->RxCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_RxCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
-
-
}
/**
@@ -1703,16 +1715,23 @@ void PSSI_DMAAbort(DMA_HandleTypeDef *hdma)
hpssi->State = HAL_PSSI_STATE_READY;
/* Call the corresponding callback to inform upper layer of End of Transfer */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->AbortCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
else
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->ErrorCallback(hpssi);
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @brief This function handles PSSI Communication Timeout.
@@ -1746,6 +1765,8 @@ static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi
}
return HAL_OK;
}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
void PSSI_DMAError(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
@@ -1753,7 +1774,6 @@ void PSSI_DMAError(DMA_HandleTypeDef *hdma)
uint32_t tmperror;
-
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
@@ -1777,12 +1797,14 @@ void PSSI_DMAError(DMA_HandleTypeDef *hdma)
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->ErrorCallback(hpssi);
-
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
-
}
-
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c
index 4eb20ad220..44f35e133d 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c
@@ -581,7 +581,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))
/* Clear Busy bit */
- HAL_QSPI_Abort_IT(hqspi);
+ (void)HAL_QSPI_Abort_IT(hqspi);
#endif
/* Change state of QSPI */
@@ -626,7 +626,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx))
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
- HAL_QSPI_Abort_IT(hqspi);
+ (void)HAL_QSPI_Abort_IT(hqspi);
#endif
/* Change state of QSPI */
@@ -2255,7 +2255,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS
* @param hqspi QSPI handle
* @retval HAL state
*/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi)
{
/* Return QSPI handle state */
return hqspi->State;
@@ -2266,7 +2266,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
* @param hqspi QSPI handle
* @retval QSPI Error Code
*/
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi)
{
return hqspi->ErrorCode;
}
@@ -2446,7 +2446,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t
* @param hqspi QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
+uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi)
{
return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
}
@@ -2706,6 +2706,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->AlternateBytesSize | cmd->AlternateByteMode |
cmd->AddressMode | cmd->InstructionMode |
cmd->Instruction | FunctionalMode));
+
+ /* Clear AR register */
+ CLEAR_REG(hqspi->Instance->AR);
}
}
else
@@ -2733,6 +2736,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
cmd->AlternateByteMode | cmd->AddressMode |
cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+
+ /* Clear AR register */
+ CLEAR_REG(hqspi->Instance->AR);
}
}
}
@@ -2767,6 +2773,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
cmd->AlternateBytesSize | cmd->AlternateByteMode |
cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+
+ /* Clear AR register */
+ CLEAR_REG(hqspi->Instance->AR);
}
}
else
@@ -2796,6 +2805,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
cmd->AlternateByteMode | cmd->AddressMode |
cmd->InstructionMode | FunctionalMode));
+
+ /* Clear AR register */
+ CLEAR_REG(hqspi->Instance->AR);
}
}
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
index e5a52f81f2..a4fe06f447 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
@@ -1854,7 +1854,11 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
/* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
}
- /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
+ else
+ {
+ /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
+ /* nothing to do */
+ }
}
#endif
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
index 738b417e37..6ab96aa46a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
@@ -675,6 +675,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
status = ret;
}
}
+ else
+ {
+ /* nothing to do */
+ }
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
@@ -2542,7 +2546,7 @@ void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2)
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming.
(+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
- directly reload value with target and sychronization frequencies values
+ directly reload value with target and synchronization frequencies values
(##) Call function HAL_RCCEx_CRSConfig which
(+++) Resets CRS registers to their default values.
(+++) Configures CRS registers with synchronization configuration
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c
index 52a92837b3..bccf40f68b 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c
@@ -116,9 +116,9 @@
/* Health test control register information to use in CCM algorithm */
#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */
#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
-#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */
+#define RNG_HTCFG 0x000CAA74U /*!< Recommended value for NIST compliance, refer to application note AN4230 */
#else /* RNG_VER_3_2 */
-#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */
+#define RNG_HTCFG 0x00007274U /*!< Recommended value for NIST compliance, refer to application note AN4230 */
#endif /* RNG_VER_3_1 || RNG_VER_3_0 */
/**
* @}
@@ -229,7 +229,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
/*!< magic number must be written immediately before to RNG_HTCRG */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
- /* for best latency and to be compliant with NIST */
+ /* Recommended value for NIST compliance, refer to application note AN4230 */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */
@@ -272,12 +272,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
/* Get tick */
tickstart = HAL_GetTick();
/* Check if data register contains valid random data */
- while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
+ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET)
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
/* New check to avoid false timeout detection in case of preemption */
- if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET)
{
hrng->State = HAL_RNG_STATE_ERROR;
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng_ex.c
index ec6096eb6e..61d0317de6 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng_ex.c
@@ -30,7 +30,7 @@
#if defined(RNG)
-/** @addtogroup RNG_Ex
+/** @addtogroup RNGEx
* @brief RNG Extended HAL module driver.
* @{
*/
@@ -53,7 +53,7 @@
#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RNG_Ex_Private_Constants
+/** @addtogroup RNGEx_Private_Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2U
@@ -65,11 +65,11 @@
/* Private functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
+/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions
* @{
*/
-/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions
+/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions
* @brief Configuration functions
*
@verbatim
@@ -140,7 +140,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT
#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
/*!< magic number must be written immediately before to RNG_HTCRG */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
- /* for best latency and to be compliant with NIST */
+ /* Recommended value for NIST compliance, refer to application note AN4230 */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */
@@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
* @}
*/
-/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function
+/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function
* @brief Recover from seed error function
*
@verbatim
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c
index d13157fcf1..3d52e1e68f 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c
@@ -1930,7 +1930,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
/* Clear the bits that are going to be configured and leave the others unchanged */
tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
- if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
{
tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c
index eca1eca7c8..87198fee78 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c
@@ -170,7 +170,7 @@
[..]
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
@@ -185,10 +185,10 @@
[..]
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ all callbacks are reset to the corresponding legacy weak functions:
examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+ reset to the legacy weak functions in the HAL_SAI_Init
and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -205,7 +205,7 @@
[..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
*/
@@ -1451,6 +1451,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
/* Process Locked */
__HAL_LOCK(hsai);
+ /* Disable SAI peripheral */
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+
/* Disable the SAI DMA request */
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
@@ -1470,12 +1476,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
(void) HAL_DMA_Abort(hsai->hdmarx);
}
- /* Disable SAI peripheral */
- if (SAI_Disable(hsai) != HAL_OK)
- {
- status = HAL_ERROR;
- }
-
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@@ -1501,6 +1501,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
/* Process Locked */
__HAL_LOCK(hsai);
+ /* Disable SAI peripheral */
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+
/* Check SAI DMA is enabled or not */
if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
{
@@ -1528,12 +1534,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
hsai->Instance->IMR = 0;
hsai->Instance->CLRFR = 0xFFFFFFFFU;
- /* Disable SAI peripheral */
- if (SAI_Disable(hsai) != HAL_OK)
- {
- status = HAL_ERROR;
- }
-
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c
index 6262126192..a15f8f8491 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c
@@ -461,6 +461,12 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
}
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
+ /* Configure the bus wide with the specified value in the SD_HandleTypeDef */
+ if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
/* Initialize the error code */
hsd->ErrorCode = HAL_SD_ERROR_NONE;
@@ -3468,11 +3474,6 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
return errorstate;
}
-#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
- /* Configure SDMMC peripheral interface */
- (void)SDMMC_Init(hsd->Instance, hsd->Init);
-#endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
-
/* All cards are initialized */
return HAL_SD_ERROR_NONE;
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c
index f871a470d8..e0ca908695 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c
@@ -2524,7 +2524,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
}
- MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
+ WRITE_REG(hsmartcard->Instance->RTOR, tmpreg);
/*-------------------------- USART BRR Configuration -----------------------*/
SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c
index ec68cb2bf4..cfbbcb2bb8 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c
@@ -2619,8 +2619,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
- /* Flush TX register */
- SMBUS_Flush_TXDR(hsmbus);
+ if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+ {
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+ }
/* Store current volatile hsmbus->ErrorCode, misra rule */
tmperror = hsmbus->ErrorCode;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus_ex.c
index 5b66c80d02..56c79eb678 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus_ex.c
@@ -6,6 +6,8 @@
* This file provides firmware functions to manage the following
* functionalities of SMBUS Extended peripheral:
* + Extended features functions
+ * + WakeUp Mode Functions
+ * + FastModePlus Functions
*
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
index 1474176a50..4875c0f024 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
@@ -44,7 +44,8 @@
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream/Channel
(+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
+ or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
@@ -190,7 +191,8 @@
@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
@note
- (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and
+ HAL_SPI_TransmitReceive_DMA()
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
@@ -818,38 +820,35 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
uint16_t initial_TxXferCount;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
initial_TxXferCount = Size;
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -888,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
@@ -898,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
@@ -907,9 +906,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -922,13 +921,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
if (hspi->TxXferCount > 1U)
{
/* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr ++;
hspi->TxXferCount--;
}
@@ -941,13 +940,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
if (hspi->TxXferCount > 1U)
{
/* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
@@ -957,9 +956,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -984,19 +983,18 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1016,12 +1014,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
}
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
@@ -1031,17 +1032,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
+ /* Process Locked */
+ __HAL_LOCK(hspi);
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1113,9 +1108,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1137,9 +1132,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1156,8 +1151,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* the latest data has not been received */
- errorcode = HAL_TIMEOUT;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Receive last data in 16 Bit mode */
@@ -1175,8 +1170,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read CRC to Flush DR and RXNE flag */
@@ -1202,8 +1198,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
tmpreg8 = *ptmpreg8;
@@ -1229,18 +1226,17 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
}
#endif /* USE_SPI_CRC */
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1253,8 +1249,8 @@ error :
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
{
uint16_t initial_TxXferCount;
uint16_t initial_RxXferCount;
@@ -1271,14 +1267,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -1293,18 +1285,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
#endif /* USE_SPI_CRC */
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1316,7 +1310,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferCount = Size;
hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferCount = Size;
hspi->TxXferSize = Size;
@@ -1356,7 +1350,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -1379,7 +1373,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
@@ -1410,9 +1404,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1423,13 +1417,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
@@ -1454,13 +1448,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
@@ -1506,9 +1500,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1522,8 +1516,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read CRC */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
@@ -1548,8 +1543,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
tmpreg8 = *ptmpreg8;
@@ -1565,30 +1561,32 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Clear CRC Flag */
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
- errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- errorcode = HAL_ERROR;
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1599,9 +1597,8 @@ error :
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
@@ -1609,14 +1606,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
/* Process Locked */
@@ -1625,7 +1620,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -1673,8 +1668,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Enable TXE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-error :
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1687,13 +1681,15 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
@@ -1704,12 +1700,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
}
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
/* Process Locked */
__HAL_LOCK(hspi);
@@ -1781,8 +1771,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
/* Enable RXNE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-error :
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1794,11 +1783,11 @@ error :
* @param Size amount of data to be sent and received
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
@@ -1808,16 +1797,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
/* Process locked */
@@ -1831,7 +1819,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
@@ -1892,8 +1880,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Enable TXE, RXNE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-error :
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1904,9 +1891,8 @@ error :
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
@@ -1914,25 +1900,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -1994,9 +1978,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -2006,16 +1990,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
__HAL_SPI_ENABLE(hspi);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -2030,15 +2014,17 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
/* Check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
@@ -2055,12 +2041,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Process Locked */
__HAL_LOCK(hspi);
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -2138,9 +2118,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -2150,16 +2130,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -2172,12 +2152,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check rx & tx dma handles */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
@@ -2186,26 +2165,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
- __HAL_LOCK(hspi);
-
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) ||
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -2214,7 +2192,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
@@ -2305,9 +2283,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Enable Rx DMA Request */
@@ -2326,9 +2304,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -2337,16 +2315,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -2439,7 +2418,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
__HAL_SPI_DISABLE(hspi);
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -2472,7 +2452,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
}
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -2727,9 +2708,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
+ HAL_SPI_TxRxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
+ HAL_SPI_TxRxCpltCallback()
*/
/* Abort the SPI DMA tx Stream/Channel */
@@ -3019,7 +3002,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
* the configuration information for SPI module.
* @retval SPI state
*/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
{
/* Return SPI handle state */
return hspi->State;
@@ -3031,7 +3014,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
* the configuration information for SPI module.
* @retval SPI error code in bitmap format
*/
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
{
/* Return SPI ErrorCode */
return hspi->ErrorCode;
@@ -3058,7 +3041,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
/* Init tickstart for timeout management*/
@@ -3115,7 +3098,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
@@ -3232,7 +3215,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
@@ -3270,7 +3253,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
}
else
{
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
@@ -3332,7 +3316,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Tx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -3350,7 +3334,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Rx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -3368,7 +3352,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user TxRx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -3386,7 +3370,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
@@ -3409,7 +3393,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
@@ -3431,7 +3415,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
hspi->hdmatx->XferAbortCallback = NULL;
@@ -3447,7 +3431,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
__HAL_SPI_DISABLE(hspi);
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -3497,7 +3482,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
@@ -3514,7 +3499,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
}
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -3650,14 +3636,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/* Transmit data in packing Bit mode */
if (hspi->TxXferCount >= 2U)
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
/* Transmit data in 8 Bit mode */
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
@@ -3751,7 +3737,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -3904,7 +3890,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
@@ -3930,7 +3916,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -4032,7 +4018,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
- __IO uint8_t *ptmpreg8;
+ __IO const uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Adjust Timeout value in case of end of transfer */
@@ -4387,7 +4373,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
}
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -4430,7 +4417,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
__HAL_SPI_DISABLE(hspi);
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -4459,7 +4447,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
}
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
index ad50589b8d..241ff98a9b 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
@@ -76,7 +76,7 @@
* the configuration information for the specified SPI module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg;
uint8_t count = 0U;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c
index 81bf276a8b..dccd6c4997 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c
@@ -1038,6 +1038,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
*/
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
{
+ /* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
@@ -1060,6 +1061,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
*/
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
{
+ /* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
@@ -1082,6 +1084,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
*/
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
{
+ /* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
index f302ed1f4f..2ce0df7321 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
@@ -3842,7 +3842,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
@@ -3874,7 +3874,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@@ -3904,7 +3904,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@@ -3934,7 +3934,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@@ -3964,7 +3964,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
@@ -3973,11 +3973,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Break input event */
- if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
+ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+ ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
@@ -4003,7 +4004,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
@@ -4016,7 +4017,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
@@ -4567,7 +4568,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@@ -6970,6 +6972,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
+
+ /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ {
+ /* Clear the update flag */
+ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ }
}
/**
@@ -7094,7 +7103,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
-
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
index d4c52fcbfe..6ddded092b 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
@@ -837,7 +837,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1083,17 +1083,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
(+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
@endverbatim
* @{
*/
@@ -1319,7 +1308,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -2105,7 +2094,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
uint32_t BreakInput,
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmporx;
@@ -2547,7 +2535,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/**
- * @brief Hall commutation changed callback in non-blocking mode
+ * @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2561,7 +2549,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
*/
}
/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @brief Commutation half complete callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2576,7 +2564,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
}
/**
- * @brief Hall Break detection callback in non-blocking mode
+ * @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2591,7 +2579,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
}
/**
- * @brief Hall Break2 detection callback in non blocking mode
+ * @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
@@ -2742,15 +2730,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
else
{
/* nothing to do */
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
index a3e3faa838..c5c33c7c35 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
@@ -999,10 +999,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = pCallback;
}
@@ -1013,9 +1010,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(huart);
-
return status;
}
@@ -1029,10 +1023,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
}
@@ -1043,8 +1034,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(huart);
return status;
}
@@ -2540,6 +2529,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
+ else
+ {
+ /* If DMA is in Circular mode, Idle event is to be reported to user
+ even if occurring after a Transfer Complete event from DMA */
+ if (nb_remaining_rx_data == huart->RxXferSize)
+ {
+ if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+ {
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ }
+ }
return;
}
else
@@ -3554,7 +3565,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
return HAL_TIMEOUT;
}
- if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
{
@@ -4699,6 +4710,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
+ break;
}
}
@@ -4863,6 +4875,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
+ break;
}
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
index 39bdd6066c..9d8a60a346 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
@@ -629,7 +629,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
/* Disable UART */
__HAL_UART_DISABLE(huart);
- /* Enable FIFO mode */
+ /* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
huart->FifoMode = UART_FIFOMODE_DISABLE;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c
index 71a3e41b3c..2ed5c53029 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c
@@ -144,7 +144,7 @@
*/
/** @defgroup USART USART
- * @brief HAL USART Synchronous module driver
+ * @brief HAL USART Synchronous SPI module driver
* @{
*/
@@ -236,8 +236,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
+ in synchronous SPI master/slave mode.
+ (+) For the synchronous SPI mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length
(++) Stop Bit
@@ -249,7 +249,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
(++) Receiver/transmitter modes
[..]
- The HAL_USART_Init() function follows the USART synchronous configuration
+ The HAL_USART_Init() function follows the USART synchronous SPI configuration
procedure (details for the procedure are available in reference manual).
@endverbatim
@@ -327,7 +327,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
return HAL_ERROR;
}
- /* In Synchronous mode, the following bits must be kept cleared:
+ /* In Synchronous SPI mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.
*/
@@ -672,11 +672,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
===============================================================================
##### IO operation functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART synchronous
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI
data transfers.
- [..] The USART supports master mode only: it cannot receive or send data related to an input
- clock (SCLK is always an output).
+ [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input).
[..]
@@ -3030,7 +3029,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
/* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
* set CPOL bit according to husart->Init.CLKPolarity value
* set CPHA bit according to husart->Init.CLKPhase value
- * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
+ * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only)
* set STOP[13:12] bits according to husart->Init.StopBits value */
tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
tmpreg |= (uint32_t)husart->Init.CLKLastBit;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c
index 647c80edaf..6314dab528 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c
@@ -373,7 +373,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
/* Disable USART */
__HAL_USART_DISABLE(husart);
- /* Enable FIFO mode */
+ /* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
husart->FifoMode = USART_FIFOMODE_DISABLE;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c
index 8fde353e3a..0244f02da6 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c
@@ -465,11 +465,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
/* Disable ADC instance if not already disabled. */
if (LL_ADC_IsEnabled(ADCx) == 1UL)
{
- /* Set ADC group regular trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-
/* Stop potential ADC conversion on going on ADC group regular. */
if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
{
@@ -479,11 +474,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
}
}
- /* Set ADC group injected trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-
/* Stop potential ADC conversion on going on ADC group injected. */
if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
{
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c
index c9b6f6a400..0a8711a040 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c
@@ -58,7 +58,7 @@
/* Note: On this STM32 series, comparator input plus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
-/* compatibility with other STM32 families. */
+/* compatibility with other STM32 series. */
#if defined(COMP_CSR_INPSEL_1)
#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
(((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
@@ -75,7 +75,7 @@
/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
-/* compatibility with other STM32 families. */
+/* compatibility with other STM32 series. */
#if defined(COMP_CSR_INMESEL_1)
#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
@@ -92,7 +92,7 @@
)
#else
#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
- (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c
index 3790c24998..41b56c9128 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c
@@ -144,7 +144,7 @@
* - SUCCESS: DMA2D registers are de-initialized
* - ERROR: DMA2D registers are not de-initialized
*/
-ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx)
+ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx)
{
ErrorStatus status = SUCCESS;
@@ -458,7 +458,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
* @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF
*/
-uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
uint32_t color;
@@ -502,7 +502,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
* @retval Output Green color value between Min_Data=0 and Max_Data=0xFF
*/
-uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
uint32_t color;
@@ -546,7 +546,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
* @retval Output Red color value between Min_Data=0 and Max_Data=0xFF
*/
-uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
uint32_t color;
@@ -590,7 +590,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
* @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF
*/
-uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
uint32_t color;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c
index 32bd5f6250..8fe8dc4eb0 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c
@@ -59,7 +59,7 @@
* @{
*/
#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) \
- || defined(HAL_SRAM_MODULE_ENABLED)
+ || defined(HAL_SRAM_MODULE_ENABLED)
/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
@@ -189,7 +189,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
- FMC_NORSRAM_InitTypeDef *Init)
+ const FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
uint32_t btcr_reg;
@@ -397,7 +397,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
- FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+ const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr;
@@ -417,22 +417,24 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
/* Set FMC_NORSRAM device timing parameters */
#if defined(FMC_BTRx_DATAHLD)
- MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
- ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
- ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
- ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
- ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
- (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
- (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
- (Timing->AccessMode)));
+ Device->BTCR[Bank + 1U] =
+ (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) |
+ (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) |
+ (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) |
+ (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) |
+ (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) |
+ ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) |
+ ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) |
+ Timing->AccessMode;
#else /* FMC_BTRx_DATAHLD */
- MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
- ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
- ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
- ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
- (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
- (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
- (Timing->AccessMode)));
+ Device->BTCR[Bank + 1U] =
+ (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) |
+ (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) |
+ (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) |
+ (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) |
+ ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) |
+ ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) |
+ Timing->AccessMode;
#endif /* FMC_BTRx_DATAHLD */
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
@@ -459,7 +461,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
- FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
uint32_t ExtendedMode)
{
/* Check the parameters */
@@ -618,7 +620,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device
* @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -651,7 +653,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
- FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+ const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -665,10 +667,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
UNUSED(Bank);
/* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
- ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
- ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
- ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)));
+ Device->PMEM = (Timing->SetupTime |
+ ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
+ ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
+ ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos));
return HAL_OK;
}
@@ -682,7 +684,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
- FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+ const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -696,10 +698,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
UNUSED(Bank);
/* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
- ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
- ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
- ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)));
+ Device->PATT = (Timing->SetupTime |
+ ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
+ ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
+ ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos));
return HAL_OK;
}
@@ -803,7 +805,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
* @param Timeout Timeout wait value
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
uint32_t Timeout)
{
uint32_t tickstart;
@@ -843,7 +845,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui
#endif /* FMC_BANK3 */
-
/**
* @}
*/
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pka.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pka.c
index 910a620210..187b6df640 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pka.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pka.c
@@ -84,7 +84,7 @@
* - SUCCESS: PKA registers are de-initialized
* - ERROR: PKA registers are not de-initialized
*/
-ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx)
+ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx)
{
ErrorStatus status = SUCCESS;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c
index f7f6d0849d..36d724f172 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c
@@ -1284,7 +1284,7 @@ uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)
switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource))
{
case LL_RCC_SWPMI1_CLKSOURCE_HSI: /* SWPMI1 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady())
+ if (LL_RCC_HSI_IsReady() != 0UL)
{
swpmi_frequency = HSI_VALUE;
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c
index 7fa1d79974..cdfcd300ab 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c
@@ -115,7 +115,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx)
* - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
* - ERROR: not applicable
*/
-ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct)
{
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(RNGx));
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c
index 89cc53f83b..bbc1e54826 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c
@@ -129,7 +129,7 @@
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
{
ErrorStatus status = ERROR;
@@ -178,8 +178,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in SPI configuration registers can only be written when the
+ * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior
+ * calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c
index 1ce1776ddf..9d7a8dd812 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c
@@ -66,8 +66,8 @@
|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
@@ -733,6 +733,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T
assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
@@ -745,7 +746,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
if (IS_TIM_BKIN2_INSTANCE(TIMx))
@@ -796,8 +796,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
@@ -825,8 +823,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
@@ -875,8 +875,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
@@ -904,8 +902,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
@@ -954,8 +954,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 3: Reset the CC3E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
@@ -983,8 +981,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
@@ -1033,8 +1033,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
/* Disable the Channel 4: Reset the CC4E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
@@ -1062,7 +1060,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
/* Set the Output Idle state */
@@ -1329,7 +1326,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM
(TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
- /* Select the Polarity and set the CC2E Bit */
+ /* Select the Polarity and set the CC4E Bit */
MODIFY_REG(TIMx->CCER,
(TIM_CCER_CC4P | TIM_CCER_CC4NP),
((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c
index e50e78759e..117c2ee65a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c
@@ -229,9 +229,9 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDe
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else if (mode == USB_DEVICE_MODE)
{
@@ -239,16 +239,16 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDe
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else
{
return HAL_ERROR;
}
- if (ms == 50U)
+ if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
{
return HAL_ERROR;
}
@@ -406,7 +406,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -420,7 +420,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -443,7 +443,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -457,7 +457,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -475,7 +475,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @retval Hal status
*/
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -490,7 +490,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
* This parameter can be one of these values:
* @arg USBD_FS_SPEED: Full speed mode
*/
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint8_t speed;
@@ -515,7 +515,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -553,7 +553,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -592,7 +592,7 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -639,7 +639,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -714,17 +714,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
}
else
{
- USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
- (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+ pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19));
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (pktcnt << 29));
+ }
}
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
- if (ep->type == EP_TYPE_ISOC)
- {
- USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
- USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
- }
}
/* EP enable, IN data in FIFO */
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
@@ -815,7 +815,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
__IO uint32_t count = 0U;
HAL_StatusTypeDef ret = HAL_OK;
@@ -875,7 +875,7 @@ HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
* @param len Number of bytes to write
* @retval HAL status
*/
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -903,7 +903,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
* @param len Number of bytes to read
* @retval pointer to destination buffer
*/
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint8_t *pDest = dest;
@@ -945,7 +945,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -976,7 +976,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -1046,7 +1046,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1061,7 +1061,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1078,7 +1078,7 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1111,7 +1111,7 @@ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
* @param chnum Channel number
* @retval USB Channel Interrupt status
*/
-uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
+uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1127,7 +1127,7 @@ uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
* @param USBx Selected device
* @retval USB Device OUT EP interrupt status
*/
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1143,7 +1143,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval USB Device IN EP interrupt status
*/
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1161,7 +1161,7 @@ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1179,7 +1179,7 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1213,7 +1213,7 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
* 0 : Host
* 1 : Device
*/
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
return ((USBx->GINTSTS) & 0x1U);
}
@@ -1223,7 +1223,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1241,10 +1241,10 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
* @param psetup pointer to setup packet
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, const uint8_t *psetup)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
UNUSED(psetup);
if (gSNPSiD > USB_OTG_CORE_ID_300A)
@@ -1277,7 +1277,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1291,7 +1291,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1375,7 +1375,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
*/
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1405,7 +1405,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
* @note (1)The application must wait at least 10 ms
* before clearing the reset bit.
*/
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1432,7 +1432,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
* 1 : Activate VBUS
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state)
{
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0 = 0U;
@@ -1730,7 +1730,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
* @param USBx Selected device
* @retval HAL state
*/
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1744,7 +1744,7 @@ uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t hcnum = (uint32_t)hc_num;
@@ -1828,7 +1828,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t chnum = (uint32_t)ch_num;
@@ -1917,7 +1917,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1935,7 +1935,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -2212,6 +2212,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ /* Set endpoint RX count */
+ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
+
+ /* Set endpoint RX to valid state */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
@@ -2316,7 +2320,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/* IN endpoint */
if (ep->is_in == 1U)
{
- /*Multi packet transfer*/
+ /* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
@@ -2418,9 +2422,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}
- else /* manage isochronous double buffer IN mode */
+ else /* Manage isochronous double buffer IN mode */
{
- /* each Time to write in PMA xfer_len_db will */
+ /* Each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
/* Fill the data buffer */
@@ -2452,19 +2456,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
if (ep->doublebuffer == 0U)
{
+ if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL))
+ {
+ /* This is a status out stage set the OUT_STATUS */
+ PCD_SET_OUT_STATUS(USBx, ep->num);
+ }
+ else
+ {
+ PCD_CLEAR_OUT_STATUS(USBx, ep->num);
+ }
+
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
- len = ep->maxpacket;
- ep->xfer_len -= len;
+ ep->xfer_len -= ep->maxpacket;
}
else
{
- len = ep->xfer_len;
ep->xfer_len = 0U;
}
- /* configure and validate Rx endpoint */
- PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
@@ -2473,15 +2483,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
{
- PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
-
/* Coming from ISR */
if (ep->xfer_count != 0U)
{
- /* update last value to check if there is blocking state */
+ /* Update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
- /*Blocking State */
+ /* Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
{
@@ -2492,18 +2500,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/* iso out double */
else if (ep->type == EP_TYPE_ISOC)
{
- /* Multi packet transfer */
- if (ep->xfer_len > ep->maxpacket)
- {
- len = ep->maxpacket;
- ep->xfer_len -= len;
- }
- else
- {
- len = ep->xfer_len;
- ep->xfer_len = 0U;
- }
- PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
+ /* Only single packet transfer supported in FS */
+ ep->xfer_len = 0U;
}
else
{
@@ -2547,26 +2545,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
- if (ep->doublebuffer == 0U)
+ if (ep->is_in != 0U)
{
- if (ep->is_in != 0U)
- {
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
- if (ep->type != EP_TYPE_ISOC)
- {
- /* Configure NAK status for the Endpoint */
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
- }
- }
- else
+ if (ep->type != EP_TYPE_ISOC)
{
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
- /* Configure VALID status for the Endpoint */
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
}
}
+ else
+ {
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+ /* Configure VALID status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
return HAL_OK;
}
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
index 9ec13821e6..f80f46ba22 100644
--- a/system/Drivers/STM32YYxx_HAL_Driver_version.md
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -13,7 +13,7 @@
* STM32H7: 1.11.3
* STM32L0: 1.10.6
* STM32L1: 1.4.5
- * STM32L4: 1.13.4
+ * STM32L4: 1.13.5
* STM32L5: 1.0.6
* STM32MP1: 1.6.0
* STM32U5: 1.6.0
diff --git a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c
index 7bc16550df..32c0368502 100644
--- a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c
+++ b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c
@@ -14,7 +14,7 @@
* Automatically generated from STM32L412C8Tx.xml, STM32L412C8Ux.xml
* STM32L412CBTx.xml, STM32L412CBUx.xml
* STM32L422CBTx.xml, STM32L422CBUx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c
index 747d362785..7a9ca1db5e 100644
--- a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c
+++ b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L412CBTxP.xml, STM32L412CBUxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c
index 3aea1023f1..d74f23fa9f 100644
--- a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c
+++ b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c
@@ -14,7 +14,7 @@
* Automatically generated from STM32L412K8Tx.xml, STM32L412K8Ux.xml
* STM32L412KBTx.xml, STM32L412KBUx.xml
* STM32L422KBTx.xml, STM32L422KBUx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c
index 4f37e74e9f..d3ed64a6ee 100644
--- a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c
+++ b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c
@@ -14,7 +14,7 @@
* Automatically generated from STM32L412R8Ix.xml, STM32L412R8Tx.xml
* STM32L412RBIx.xml, STM32L412RBTx.xml
* STM32L422RBIx.xml, STM32L422RBTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c
index 2fae449ad0..443be5aa42 100644
--- a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c
+++ b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L412RBIxP.xml, STM32L412RBTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c
index 856241f12d..c56017f824 100644
--- a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c
+++ b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L412T8Yx.xml, STM32L412TBYx.xml
* STM32L422TBYx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c
index d5dd540102..68d4981fbb 100644
--- a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L412TBYxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c
index 34dc30e962..35a1475199 100644
--- a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c
+++ b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L431C(B-C)Tx.xml, STM32L431C(B-C)Ux.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c
index b7e6f87941..eed840c330 100644
--- a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c
+++ b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L431C(B-C)Yx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c
index e20d491fba..5f820d224f 100644
--- a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c
+++ b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L431K(B-C)Ux.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c
index 8d7aa9fa82..fb48a85477 100644
--- a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c
+++ b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L431R(B-C)Ix.xml, STM32L431R(B-C)Tx.xml
* STM32L431R(B-C)Yx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c
index 0f90062c07..c43f5de2e6 100644
--- a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c
+++ b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L431VCIx.xml, STM32L431VCTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c
index 6c8f7c3224..98a8727910 100644
--- a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c
+++ b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L432K(B-C)Ux.xml, STM32L442KCUx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c
index 3a584e3d0c..a15f090088 100644
--- a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c
+++ b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L433C(B-C)Tx.xml, STM32L433C(B-C)Ux.xml
* STM32L443CCTx.xml, STM32L443CCUx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c
index 15f2f25d7d..e67dc95d6b 100644
--- a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c
+++ b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L433C(B-C)Yx.xml, STM32L443CCFx.xml
* STM32L443CCYx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c
index eb5eabe3cf..a6d03e307d 100644
--- a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c
+++ b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c
@@ -14,7 +14,7 @@
* Automatically generated from STM32L433R(B-C)Ix.xml, STM32L433R(B-C)Tx.xml
* STM32L433R(B-C)Yx.xml, STM32L443RCIx.xml
* STM32L443RCTx.xml, STM32L443RCYx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c
index 63035e74d8..6e93047656 100644
--- a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L433RCTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c
index 8d5635f586..348b921d56 100644
--- a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c
+++ b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L433VCIx.xml, STM32L433VCTx.xml
* STM32L443VCIx.xml, STM32L443VCTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c
index 05576957f5..621665b849 100644
--- a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c
+++ b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L451C(C-E)Ux.xml, STM32L451CETx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c
index a3b74f94e5..ba39a04354 100644
--- a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c
+++ b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L451R(C-E)Ix.xml, STM32L451R(C-E)Tx.xml
* STM32L451R(C-E)Yx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c
index 59e4192303..6e34d200e4 100644
--- a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c
+++ b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L451V(C-E)Ix.xml, STM32L451V(C-E)Tx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c
index ea57a441a5..7ad9a1acab 100644
--- a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c
+++ b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c
@@ -14,7 +14,7 @@
* Automatically generated from STM32L452C(C-E)Ux.xml, STM32L452CETx.xml
* STM32L452CETxP.xml, STM32L462CETx.xml
* STM32L462CEUx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c
index d4f218ddf4..4437d82ded 100644
--- a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c
+++ b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c
@@ -15,7 +15,7 @@
* STM32L452R(C-E)Yx.xml, STM32L452REYxP.xml
* STM32L462REIx.xml, STM32L462RETx.xml
* STM32L462REYx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L452RETxP/PeripheralPins.c b/variants/STM32L4xx/L452RETxP/PeripheralPins.c
index e8ff8372d8..281aaedd5c 100644
--- a/variants/STM32L4xx/L452RETxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L452RETxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L452RETxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c
index afc5633b41..864f1d706f 100644
--- a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c
+++ b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L452V(C-E)Ix.xml, STM32L452V(C-E)Tx.xml
* STM32L462VEIx.xml, STM32L462VETx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c
index 04da65d790..3ff22d95a2 100644
--- a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c
+++ b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L471Q(E-G)Ix.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c
index dad8815616..8171795b89 100644
--- a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c
+++ b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L471R(E-G)Tx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c
index a24e2980c0..8b1f1c9435 100644
--- a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c
+++ b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L471V(E-G)Tx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c
index 6e70eaa154..78c4c5b702 100644
--- a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c
+++ b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L471Z(E-G)Jx.xml, STM32L471Z(E-G)Tx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c
index 496a913b2d..fa069681cb 100644
--- a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c
+++ b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L475R(C-E-G)Tx.xml, STM32L476R(C-E-G)Tx.xml
* STM32L486RGTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c
index 7c326f5554..32505b71b8 100644
--- a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c
+++ b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L475V(C-E-G)Tx.xml, STM32L476V(C-E-G)Tx.xml
* STM32L486VGTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c
index fe67fc77d2..5b98653bc8 100644
--- a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c
+++ b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L476J(E-G)Yx.xml, STM32L485J(C-E)Yx.xml
* STM32L486JGYx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c
index 87afb4327a..3e5893767b 100644
--- a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L476JGYxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c
index c92708b112..e9756bee9d 100644
--- a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c
+++ b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L476M(E-G)Yx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c
index 901b5e222f..de839cd9b8 100644
--- a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c
+++ b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L476Q(E-G)Ix.xml, STM32L476QGIxP.xml
* STM32L486QGIx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c
index 418af906b0..84f2ec18ab 100644
--- a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L476VGYxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c
index 9ed455c7d5..46ec52fccb 100644
--- a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c
+++ b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L476Z(E-G)Tx.xml, STM32L476ZGJx.xml
* STM32L486ZGTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c
index 4742f096f5..eb7dcb2323 100644
--- a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L476ZGTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c
index f961d5f7ab..f0b05b6511 100644
--- a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c
+++ b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496A(E-G)Ix.xml, STM32L4A6AGIx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c
index f0e37da01c..00e7b91e0c 100644
--- a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496AGIxP.xml, STM32L4A6AGIxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c
index 175e2c9955..eb39c72dff 100644
--- a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c
+++ b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L496Q(E-G)Ix.xml, STM32L496QGIxS.xml
* STM32L4A6QGIx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/boards_entry.txt b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/boards_entry.txt
index 0d8aa77e4e..bb2790e408 100644
--- a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/boards_entry.txt
+++ b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/boards_entry.txt
@@ -26,7 +26,7 @@ GenL4.menu.pnum.GENERIC_L496QGIXS=Generic L496QGIxS
GenL4.menu.pnum.GENERIC_L496QGIXS.upload.maximum_size=1048576
GenL4.menu.pnum.GENERIC_L496QGIXS.upload.maximum_data_size=327680
GenL4.menu.pnum.GENERIC_L496QGIXS.build.board=GENERIC_L496QGIXS
-GenL4.menu.pnum.GENERIC_L496QGIXS.build.product_line=STM32L4A6xx
+GenL4.menu.pnum.GENERIC_L496QGIXS.build.product_line=STM32L496xx
GenL4.menu.pnum.GENERIC_L496QGIXS.build.variant=STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI
GenL4.menu.pnum.GENERIC_L496QGIXS.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L496.svd
diff --git a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c
index 7b16fbf838..4aa9d55c19 100644
--- a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496QGIxP.xml, STM32L4A6QGIxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c
index ea30e461d8..374c3e6b13 100644
--- a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c
+++ b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496R(E-G)Tx.xml, STM32L4A6RGTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c
index 3ce67d95c3..4f0f68850a 100644
--- a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496RGTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c
index 58651040bd..1320e982e8 100644
--- a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c
+++ b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496V(E-G)Tx.xml, STM32L4A6VGTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c
index bcb9ea4f57..89cc39ed3b 100644
--- a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496VGTxP.xml, STM32L4A6VGTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c
index 0123184048..879c564a55 100644
--- a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c
+++ b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496VGYx.xml, STM32L4A6VGYx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c
index 3450648f96..4684de3c00 100644
--- a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496VGYxP.xml, STM32L4A6VGYxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c
index 759c2dbf38..66c8a33130 100644
--- a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496WGYxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c
index edea5f8b3b..c575098073 100644
--- a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c
+++ b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496Z(E-G)Tx.xml, STM32L4A6ZGTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c
index fef1b9c5e6..595c7221ed 100644
--- a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L496ZGTxP.xml, STM32L4A6ZGTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c
index 28b517a244..112ad590ae 100644
--- a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4A6RGTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c
index 0dd192b8ea..8ab93bbfe8 100644
--- a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5A(G-E)Ix.xml, STM32L4Q5AGIx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c
index 23b5b95715..86e3140be9 100644
--- a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5AGIxP.xml, STM32L4Q5AGIxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c
index c21e945b01..44e9c664b2 100644
--- a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L4P5C(G-E)Tx.xml, STM32L4P5C(G-E)Ux.xml
* STM32L4Q5CGTx.xml, STM32L4Q5CGUx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c
index c416ae76fc..9ff6270da4 100644
--- a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L4P5CGTxP.xml, STM32L4P5CGUxP.xml
* STM32L4Q5CGTxP.xml, STM32L4Q5CGUxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c
index 1aa3328f3e..5e2568e0cb 100644
--- a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5Q(G-E)Ix.xml, STM32L4Q5QGIx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c
index c732684470..be7a4009c1 100644
--- a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L4P5QGIxP.xml, STM32L4P5QGIxS.xml
* STM32L4Q5QGIxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/boards_entry.txt b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/boards_entry.txt
index a82d5be62d..3610c296ba 100644
--- a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/boards_entry.txt
+++ b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/boards_entry.txt
@@ -17,7 +17,7 @@ GenL4.menu.pnum.GENERIC_L4P5QGIXS=Generic L4P5QGIxS
GenL4.menu.pnum.GENERIC_L4P5QGIXS.upload.maximum_size=1048576
GenL4.menu.pnum.GENERIC_L4P5QGIXS.upload.maximum_data_size=327680
GenL4.menu.pnum.GENERIC_L4P5QGIXS.build.board=GENERIC_L4P5QGIXS
-GenL4.menu.pnum.GENERIC_L4P5QGIXS.build.product_line=STM32L4Q5xx
+GenL4.menu.pnum.GENERIC_L4P5QGIXS.build.product_line=STM32L4P5xx
GenL4.menu.pnum.GENERIC_L4P5QGIXS.build.variant=STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP
GenL4.menu.pnum.GENERIC_L4P5QGIXS.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4P5.svd
diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c
index 3796e7db11..195f2e1871 100644
--- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5R(G-E)Tx.xml, STM32L4Q5RGTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c
index 89b00ebd9a..c213d75fbd 100644
--- a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5RGTxP.xml, STM32L4Q5RGTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c
index 888460f72b..a4c1b94421 100644
--- a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5V(G-E)Tx.xml, STM32L4Q5VGTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c
index 23484f7c6f..06e19e0de4 100644
--- a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5V(G-E)Yx.xml, STM32L4Q5VGYx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c
index e15468cfb7..23c3e6ee55 100644
--- a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5VGTxP.xml, STM32L4Q5VGTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c
index 66d7936975..ab1bf1d52b 100644
--- a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5VGYxP.xml, STM32L4Q5VGYxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c
index 7cb0d1129f..1ec9fbfce6 100644
--- a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5Z(G-E)Tx.xml, STM32L4Q5ZGTx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c
index bed2d0f879..0c1535cedd 100644
--- a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4P5ZGTxP.xml, STM32L4Q5ZGTxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c
index 10d046940a..f28dab5f87 100644
--- a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c
@@ -14,7 +14,7 @@
* Automatically generated from STM32L4R5A(G-I)Ix.xml, STM32L4R5AIIxP.xml
* STM32L4R7AIIx.xml, STM32L4S5AIIx.xml
* STM32L4S7AIIx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c
index 9cc1aaceac..beb0ba8071 100644
--- a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L4R5Q(G-I)Ix.xml, STM32L4R5QGIxS.xml
* STM32L4R5QIIxP.xml, STM32L4S5QIIx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/boards_entry.txt b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/boards_entry.txt
index e3adba2048..08feb8bca3 100644
--- a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/boards_entry.txt
+++ b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/boards_entry.txt
@@ -26,7 +26,7 @@ GenL4.menu.pnum.GENERIC_L4R5QGIXS=Generic L4R5QGIxS
GenL4.menu.pnum.GENERIC_L4R5QGIXS.upload.maximum_size=1048576
GenL4.menu.pnum.GENERIC_L4R5QGIXS.upload.maximum_data_size=655360
GenL4.menu.pnum.GENERIC_L4R5QGIXS.build.board=GENERIC_L4R5QGIXS
-GenL4.menu.pnum.GENERIC_L4R5QGIXS.build.product_line=STM32L4R7xx
+GenL4.menu.pnum.GENERIC_L4R5QGIXS.build.product_line=STM32L4R5xx
GenL4.menu.pnum.GENERIC_L4R5QGIXS.build.variant=STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII
GenL4.menu.pnum.GENERIC_L4R5QGIXS.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4R5.svd
diff --git a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c
index 0fb53f1548..ecb6d534c7 100644
--- a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L4R5V(G-I)Tx.xml, STM32L4R7VITx.xml
* STM32L4S5VITx.xml, STM32L4S7VITx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c
index 40baefa0e0..63846e250b 100644
--- a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L4R5Z(G-I)Tx.xml, STM32L4R7ZITx.xml
* STM32L4S5ZITx.xml, STM32L4S7ZITx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c
index 593f49e82a..a1d4368fc1 100644
--- a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c
@@ -13,7 +13,7 @@
/*
* Automatically generated from STM32L4R5Z(G-I)Yx.xml, STM32L4R9Z(G-I)Yx.xml
* STM32L4S5ZIYx.xml, STM32L4S9ZIYx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c
index 81a7ef4906..e14b3926d1 100644
--- a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4R5ZITxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c
index 21809be9e4..668d114dd6 100644
--- a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4R9A(G-I)Ix.xml, STM32L4S9AIIx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c
index 32a95941d2..e4ad7cfd7c 100644
--- a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4R9V(G-I)Tx.xml, STM32L4S9VITx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c
index 14ef489895..7245c19cd0 100644
--- a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4R9Z(G-I)Jx.xml, STM32L4S9ZIJx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c
index 3dbcbec2b5..b2510e97bb 100644
--- a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4R9Z(G-I)Tx.xml, STM32L4S9ZITx.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"
diff --git a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c
index b683f1622e..3b8ee79403 100644
--- a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c
+++ b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c
@@ -12,7 +12,7 @@
*/
/*
* Automatically generated from STM32L4R9ZIYxP.xml
- * CubeMX DB release 6.0.110
+ * CubeMX DB release 6.0.120
*/
#if !defined(CUSTOM_PERIPHERAL_PINS)
#include "Arduino.h"