From 0fb3eff98c4d64c57acefb2ebee29fd0911b40f2 Mon Sep 17 00:00:00 2001 From: yp05327 <576951401@qq.com> Date: Fri, 15 Sep 2023 10:50:31 +0900 Subject: [PATCH 01/83] variant(H7): add support for NUCLEO-H753ZI Signed-off-by: yp05327 <576951401@qq.com> --- README.md | 1 + boards.txt | 14 + .../CMakeLists.txt | 1 + .../variant_NUCLEO_H753ZI.cpp | 272 +++++++++++++++++ .../variant_NUCLEO_H753ZI.h | 279 ++++++++++++++++++ 5 files changed, 567 insertions(+) create mode 100644 variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.cpp create mode 100644 variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h diff --git a/README.md b/README.md index 6160441674..7e348625c9 100644 --- a/README.md +++ b/README.md @@ -99,6 +99,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H563ZI | [Nucleo H563ZI](https://www.st.com/en/evaluation-tools/nucleo-h563zi.html) | *2.6.0* | | | :green_heart: | STM32H723ZG | [Nucleo H723ZG](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html) | *2.4.0* | | | :green_heart: | STM32H743ZI | [Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) | *1.5.0* | Nucleo H743ZI2 since 1.6.0 | +| :yellow_heart: | STM32H753ZI | [Nucleo H753ZI](https://www.st.com/en/evaluation-tools/nucleo-h753zi.html) | **2.7.0** | | | :green_heart: | STM32L496ZG | [Nucleo L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) | *1.3.0* | | | :green_heart: | STM32L496ZG-P | [Nucleo L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) | *1.3.0* | | | :green_heart: | STM32L4R5ZI | [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) | *1.4.0* | | diff --git a/boards.txt b/boards.txt index e9aec9dab1..eb421f6be6 100644 --- a/boards.txt +++ b/boards.txt @@ -195,6 +195,20 @@ Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.product_line=STM32H743xx Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.variant_h=variant_NUCLEO_H743ZI.h +# NUCLEO_H753ZI board +Nucleo_144.menu.pnum.NUCLEO_H753ZI=Nucleo H753ZI +Nucleo_144.menu.pnum.NUCLEO_H753ZI.node=NODE_H753ZI +Nucleo_144.menu.pnum.NUCLEO_H753ZI.upload.maximum_size=2097152 +Nucleo_144.menu.pnum.NUCLEO_H753ZI.upload.maximum_data_size=524288 +Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.mcu=cortex-m7 +Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.float-abi=-mfloat-abi=hard +Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.board=NUCLEO_H753ZI +Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.series=STM32H7xx +Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.product_line=STM32H753xx +Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT +Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.variant_h=variant_NUCLEO_H753ZI.h + # NUCLEO_L496ZG board Nucleo_144.menu.pnum.NUCLEO_L496ZG=Nucleo L496ZG Nucleo_144.menu.pnum.NUCLEO_L496ZG.node=NODE_L496ZG diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/CMakeLists.txt b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/CMakeLists.txt index de8d28df0c..0f323ce3dc 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/CMakeLists.txt +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/CMakeLists.txt @@ -23,6 +23,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL PeripheralPins.c variant_generic.cpp variant_NUCLEO_H743ZI.cpp + variant_NUCLEO_H753ZI.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.cpp b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.cpp new file mode 100644 index 0000000000..f8446f7a6d --- /dev/null +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.cpp @@ -0,0 +1,272 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_NUCLEO_H753ZI) +#include "pins_arduino.h" + +// Pin number +const PinName digitalPin[] = { + PB_7, + PB_6, + PG_14, + PE_13, + PE_14, + PE_11, + PE_9, + PG_12, + PF_3, + PD_15, + PD_14, + PB_5, + PA_6, + PA_5, + PB_9, + PB_8, + PC_6, + PB_15, + PB_13, + PB_12, + PA_15, + PC_7, + PB_5, + PB_3, + PA_4, + PB_4, + PG_6, + PB_2, + PD_13, + PD_12, + PD_11, + PE_2, + PA_0, + PB_0, + PE_0, + PB_11, + PB_10, + PE_15, + PE_6, + PE_12, + PE_10, + PE_7, + PE_8, + PC_8, + PC_9, + PC_10, + PC_11, + PC_12, + PD_2, + PG_2, + PG_3, + PD_7, + PD_6, + PD_5, + PD_4, + PD_3, + PE_2, + PE_4, + PE_5, + PE_6, + PE_3, + PF_8, + PF_7, + PF_9, + PG_1, + PG_0, + PD_1, + PD_0, + PF_0, + PF_1, + PF_2, + PE_9, + PB_2, + PA_3, + PC_0, + PC_3_C, + PB_1, + PC_2_C, + PF_10, + PF_4, + PF_5, + PF_6, + PF_11, + PA_1, + PA_2, + PA_7, + PA_8, + PA_9, + PA_10, + PA_11, + PA_12, + PA_13, + PA_14, + PB_14, + PC_1, + PC_4, + PC_5, + PC_13, + PC_14, + PC_15, + PD_8, + PD_9, + PD_10, + PE_1, + PF_12, + PF_13, + PF_14, + PF_15, + PG_4, + PG_5, + PG_7, + PG_8, + PG_9, + PG_10, + PG_11, + PG_13, + PG_15, + PH_0, + PH_1 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 73, // A0 + 74, // A1 + 75, // A2 + 76, // A3 + 77, // A4 + 78, // A5 + 79, // A6 + 80, // A7 + 81, // A8 + 82, // A9 + 83, // A10 + 84, // A11 + 85, // A12 + 94, // A13 + 95, // A14 + 96, // A15 + 104, // A16 + 105, // A17 + 106, // A18 + 8, // A19 + 12, // A20 + 13, // A21 + 24, // A22 + 32, // A23 + 33, // A24 + 61, // A25 + 62, // A26 + 63 // A27 +}; + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /* Supply configuration update enable */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + /* Macro to configure the PLL clock source */ + __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 120; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 8; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + /* Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_QSPI + | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_ADC + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USART16 + | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_I2C123 + | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI123 + | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6; + PeriphClkInitStruct.PLL2.PLL2M = 1; + PeriphClkInitStruct.PLL2.PLL2N = 20; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 2; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0; + PeriphClkInitStruct.PLL3.PLL3M = 1; + PeriphClkInitStruct.PLL3.PLL3N = 24; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 6; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0; + PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; + PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3; + PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_D3PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_ */ diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h new file mode 100644 index 0000000000..bb4424b7ec --- /dev/null +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h @@ -0,0 +1,279 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PB7 0 // USART_A_RX +#define PB6 1 // USART_A_TX +#define PG14 2 +#define PE13 3 // TIMER_A_PWM3 +#define PE14 4 +#define PE11 5 // TIMER_A_PWM2 +#define PE9 6 // TIMER_A_PWM1 +#define PG12 7 +#define PF3 PIN_A19 +#define PD15 9 // TIMER_B_PWM2 +#define PD14 10 // SPI_A_CS/ TIM_B_PWM3 +#define PB5 11 // SPI_A_MOSI/ PA7 if SB33 ON and SB35 OFF +#define PA6 PIN_A20 // SPI_A_MISO +#define PA5 PIN_A21 // SPI_A_SCK +#define PB9 14 // I2C_A_SDA +#define PB8 15 // I2C_A_SCL +#define PC6 16 // I2S_A_MCK +#define PB15 17 // I2S_A_SD +#define PB13 18 // I2S_A_CK / RMII TXD1 - JP6 ON (default) +#define PB12 19 // I2S_A_WS +#define PA15 20 // I2S_B_WS +#define PC7 21 // I2S_B_MCK +// 22 is PB5 (11) +#define PB3 23 // I2S_B_CK/SPI_B_SCK - SWO +#define PA4 PIN_A22 // SPI_B_NSS +#define PB4 25 // SPI_B_MISO +#define PG6 26 // QSPI_CS +#define PB2 27 // QSPI_CLK +#define PD13 28 // QSPI_BK1_IO3 +#define PD12 29 // QSPI_BK1_IO1 +#define PD11 30 // QSPI_BK1_IO0 +#define PE2 31 // SAI_A_MCLK/QSPI_BK1_IO2 +#define PA0 PIN_A23 // TIMER_C_PWM1 +#define PB0 PIN_A24 // TIMER_D_PWM1 - LD1 LED_GREEN +#define PE0 34 // TIMER_B_ETR +#define PB11 35 // TIMER_C_PWM3 +#define PB10 36 // TIMER_C_PWM2 +#define PE15 37 // TIMER_A_BKIN1 +#define PE6 38 +#define PE12 39 // TIMER_A_PWM3N +#define PE10 40 // TIMER_A_PWM2N +#define PE7 41 // TIMER_A_ETR +#define PE8 42 // TIMER_A_PWM1N +#define PC8 43 // SDMMC1_D0 +#define PC9 44 // SDMMC1_D1/I2S_A_CKIN +#define PC10 45 // SDMMC1_D2 +#define PC11 46 // SDMMC1_D3 +#define PC12 47 // SDMMC1_CK +#define PD2 48 // SDMMC1_CMD +#define PG2 49 +#define PG3 50 +#define PD7 51 // USART_B_SCLK +#define PD6 52 // USART_B_RX +#define PD5 53 // USART_B_TX +#define PD4 54 // USART_B_RTS +#define PD3 55 // USART_B_CTS +// 56 is PE2 (31) +#define PE4 57 // SAI_A_FS +#define PE5 58 // SAI_A_SCK +// 59 is PE6 (38) +#define PE3 60 // SAI_B_SD +#define PF8 PIN_A25 // SAI_B_SCK +#define PF7 PIN_A26 // SAI_B_MCLK +#define PF9 PIN_A27 // SAI_B_FS +#define PG1 64 +#define PG0 65 +#define PD1 66 // CAN_TX +#define PD0 67 // CAN_RX +#define PF0 68 // I2C_B_SDA +#define PF1 69 // I2C_B_SCL +#define PF2 70 // I2C_B_SMBA +// 71 is PE9 (6) +// 72 is PB2 (27) +#define PA3 PIN_A0 +#define PC0 PIN_A1 +#define PC3_C PIN_A2 +#define PB1 PIN_A3 +#define PC2_C PIN_A4 +#define PF10 PIN_A5 +#define PF4 PIN_A6 +#define PF5 PIN_A7 +#define PF6 PIN_A8 +#define PF11 PIN_A9 +#define PA1 PIN_A10 // RMII Reference Clock - SB57 ON (default) +#define PA2 PIN_A11 // RMII MDIO - SB72 ON (default) +#define PA7 PIN_A12 // RMII RX Data Valid - SB31 ON (default) +#define PA8 86 +#define PA9 87 +#define PA10 88 +#define PA11 89 +#define PA12 90 +#define PA13 91 +#define PA14 92 +#define PB14 93 // LD3 LED_RED +#define PC1 PIN_A13 +#define PC4 PIN_A14 // RMII RXD0 - SB36 ON (default) +#define PC5 PIN_A15 // RMII RXD1 - SB29 ON (default) +#define PC13 97 +#define PC14 98 +#define PC15 99 // USER_BTN +#define PD8 100 +#define PD9 101 +#define PD10 102 // Serial Tx +#define PE1 103 // Serial Rx +#define PF12 PIN_A16 +#define PF13 PIN_A17 // LD2 LED_BLUE +#define PF14 PIN_A18 +#define PF15 107 +#define PG4 108 +#define PG5 109 +#define PG7 110 +#define PG8 111 +#define PG9 112 +#define PG10 113 +#define PG11 114 // RMII TX Enable - SB27 ON (default) +#define PG13 115 // RXII TXD0 - SB30 ON (default) +#define PG15 116 +#define PH0 117 +#define PH1 118 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB8_ALT2 (PB8 | ALT2) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC0_ALT2 (PC0 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC1_ALT2 (PC1 | ALT2) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC6_ALT2 (PC6 | ALT2) +#define PC7_ALT1 (PC7 | ALT1) +#define PC7_ALT2 (PC7 | ALT2) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) + +#define NUM_DIGITAL_PINS 119 +#define NUM_DUALPAD_PINS 2 +#define NUM_ANALOG_INPUTS 28 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PB0 // LD1 +#endif +#define LED_GREEN LED_BUILTIN +#define LED_BLUE PB7 // LD2 +#define LED_RED PB14 // LD3 + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 3 //Connected to ST-Link +#endif + +// Serial pin used for console (ex: ST-Link) +// Required by Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PD9 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PD8 +#endif + +// HSE default value is 25MHz in HAL +// HSE_BYPASS is 8MHz +#ifndef HSE_BYPASS_NOT_USED + #define HSE_VALUE 8000000 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_QSPI_MODULE_DISABLED) + #define HAL_QSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #define SERIAL_PORT_MONITOR Serial + #define SERIAL_PORT_HARDWARE Serial +#endif From 200e6e64910a6bebbece6b5b9ed43717e475846d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 20 Sep 2023 23:55:19 +0200 Subject: [PATCH 02/83] Revert "chore(pio): disable build" This reverts commit 01e4f0c9a8d20fc20125fd5be539a1ef3bf9d546. --- .github/workflows/PIO-build.yml | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/.github/workflows/PIO-build.yml b/.github/workflows/PIO-build.yml index 3c397671b9..23316d9a3c 100644 --- a/.github/workflows/PIO-build.yml +++ b/.github/workflows/PIO-build.yml @@ -39,11 +39,6 @@ jobs: - name: Checkout uses: actions/checkout@main - # - name: PlatformIO - # id: Compile - # uses: ./.github/actions/pio-build - # Use the output from the `Astyle` step - - name: Warning - run: | - echo "PlatformIO build disabled while not support CMSIS update." - exit 0 + - name: PlatformIO + id: Compile + uses: ./.github/actions/pio-build From 40b4a1a1b9a50f37c531f8fc2017fc5070d36815 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 21 Sep 2023 00:00:02 +0200 Subject: [PATCH 03/83] fix(ci): wrong path for pio build Signed-off-by: Frederic Pillon --- .github/workflows/PIO-build.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/PIO-build.yml b/.github/workflows/PIO-build.yml index 23316d9a3c..cb331e557b 100644 --- a/.github/workflows/PIO-build.yml +++ b/.github/workflows/PIO-build.yml @@ -14,7 +14,7 @@ on: - '!CI/build/platformio-builder.py' - cmake/** - tools/** - - '!tools/platformio-build.py' + - '!tools/platformio/platformio-build.py' pull_request: paths-ignore: - .github/** @@ -27,7 +27,7 @@ on: - '!CI/build/platformio-builder.py' - cmake/** - tools/** - - '!tools/platformio-build.py' + - '!tools/platformio/platformio-build.py' # Allows you to run this workflow manually from the Actions tab workflow_dispatch: jobs: From b89a4c0e215192cedfafea61e39dda39e004f024 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 21 Sep 2023 10:17:44 +0200 Subject: [PATCH 04/83] fix(ci): skip cmsis_dsp for pio build Signed-off-by: Frederic Pillon --- CI/build/platformio-builder.py | 1 + 1 file changed, 1 insertion(+) diff --git a/CI/build/platformio-builder.py b/CI/build/platformio-builder.py index a1cbb22042..082851deed 100644 --- a/CI/build/platformio-builder.py +++ b/CI/build/platformio-builder.py @@ -5,6 +5,7 @@ # Libraries that are not meant to be checked in CI by default DEFAULT_IGNORED_LIBRARIES = ( + "cmsis_dsp", "keyboard", "mouse", "subghz" From 1ee0a03609d0a5a8dc89f792263765df1f3d1404 Mon Sep 17 00:00:00 2001 From: Valerii Koval Date: Wed, 20 Sep 2023 16:48:00 +0300 Subject: [PATCH 05/83] Update platformio-build.py Signed-off-by: Valerii Koval --- tools/platformio/platformio-build.py | 40 +++++++++++++++++++--------- 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/tools/platformio/platformio-build.py b/tools/platformio/platformio-build.py index 08e53ab66c..19a16715c8 100644 --- a/tools/platformio/platformio-build.py +++ b/tools/platformio/platformio-build.py @@ -136,13 +136,19 @@ def configure_application_offset(mcu, upload_protocol): offset = 0x2000 env.Append(CPPDEFINES=["BL_LEGACY_LEAF"]) - if offset != 0: - env.Append( - CPPDEFINES=[("VECT_TAB_OFFSET", "%s" % hex(offset))], - ) + env.Append( + CPPDEFINES=[ + ("VECT_TAB_OFFSET", board_config.get("build.flash_offset", hex(offset))) + ], + ) # LD_FLASH_OFFSET is mandatory even if there is no offset - env.Append(LINKFLAGS=["-Wl,--defsym=LD_FLASH_OFFSET=%s" % hex(offset)]) + env.Append( + LINKFLAGS=[ + "-Wl,--defsym=LD_FLASH_OFFSET=%s" + % board_config.get("build.flash_offset", hex(offset)) + ] + ) def load_boards_remap(): @@ -190,6 +196,7 @@ def get_arduino_board_id(board_config, mcu): return board_id.upper() + board_id = get_arduino_board_id(board_config, mcu) machine_flags = [ "-mcpu=%s" % board_config.get("build.cpu"), @@ -197,7 +204,10 @@ def get_arduino_board_id(board_config, mcu): ] if ( - any(cpu in board_config.get("build.cpu") for cpu in ("cortex-m33", "cortex-m4", "cortex-m7")) + any( + cpu in board_config.get("build.cpu") + for cpu in ("cortex-m33", "cortex-m4", "cortex-m7") + ) and "stm32wl" not in mcu ): machine_flags.extend(["-mfpu=fpv4-sp-d16", "-mfloat-abi=hard"]) @@ -205,27 +215,31 @@ def get_arduino_board_id(board_config, mcu): env.Append( ASFLAGS=machine_flags, ASPPFLAGS=[ - "-x", "assembler-with-cpp", + "-x", + "assembler-with-cpp", ], - CFLAGS=["-std=gnu11"], + CFLAGS=["-std=gnu17"], CXXFLAGS=[ - "-std=gnu++14", + "-std=gnu++17", "-fno-threadsafe-statics", "-fno-rtti", "-fno-exceptions", "-fno-use-cxa-atexit", ], - CCFLAGS=machine_flags + [ + CCFLAGS=machine_flags + + [ "-Os", # optimize for size "-ffunction-sections", # place each function in its own section "-fdata-sections", "-nostdlib", - "--param", "max-inline-insns-single=500", + "--param", + "max-inline-insns-single=500", ], CPPDEFINES=[ series, ("ARDUINO", 10808), "ARDUINO_ARCH_STM32", + "NDEBUG", "ARDUINO_%s" % board_id, ("BOARD_NAME", '\\"%s\\"' % board_id), "HAL_UART_MODULE_ENABLED", @@ -316,7 +330,8 @@ def get_arduino_board_id(board_config, mcu): join(CMSIS_DIR, "DSP", "PrivateInclude"), join(FRAMEWORK_DIR, "cores", "arduino"), ], - LINKFLAGS=machine_flags + [ + LINKFLAGS=machine_flags + + [ "-Os", "--specs=nano.specs", "-Wl,--gc-sections,--relax", @@ -327,6 +342,7 @@ def get_arduino_board_id(board_config, mcu): "-Wl,--defsym=LD_MAX_SIZE=%d" % board_config.get("upload.maximum_size"), "-Wl,--defsym=LD_MAX_DATA_SIZE=%d" % board_config.get("upload.maximum_ram_size"), + '-Wl,-Map="%s"' % join("${BUILD_DIR}", "${PROGNAME}.map"), ], LIBS=[ "c", From 61a1680ef96871a38672b5d9ea57d7a9df9b3141 Mon Sep 17 00:00:00 2001 From: Daniel Berlin Date: Wed, 27 Sep 2023 10:25:35 -0400 Subject: [PATCH 06/83] Add support for setting the channel input filter (#2136) * Add support for setting the channel input filter * Format with astyle * Start enum from 0 so we can directly convert enum to filter value --- cores/arduino/HardwareTimer.h | 23 ++++++++++++++++++++-- libraries/SrcWrapper/src/HardwareTimer.cpp | 8 ++++---- 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/cores/arduino/HardwareTimer.h b/cores/arduino/HardwareTimer.h index d975ffb1b2..2215743df1 100644 --- a/cores/arduino/HardwareTimer.h +++ b/cores/arduino/HardwareTimer.h @@ -90,6 +90,25 @@ typedef enum { PERCENT_COMPARE_FORMAT, // used for Dutycycle } TimerCompareFormat_t; +typedef enum { + FILTER_NONE = 0, // No filter + FILTER_CKINT_N2, // Sampling rate is same as clock interrupt, n=2 events + FILTER_CKINT_N4, // Sampling rate is same as clock interrupt, n=4 events + FILTER_CKINT_N8, // Sampling rate is same as clock interrupt, n=8 events + FILTER_DTS2_N6, // Sampling rate is DTS/2, n=6 events + FILTER_DTS2_N8, // Sampling rate is DTS/2, n=8 events + FILTER_DTS4_N6, // Sampling rate is DTS/4, n=6 events + FILTER_DTS4_N8, // Sampling rate is DTS/4, n=8 events + FILTER_DTS8_N6, // Sampling rate is DTS/8, n=6 events + FILTER_DTS8_N8, // Sampling rate is DTS/8, n=8 events + FILTER_DTS16_N5, // Sampling rate is DTS/16, n=5 events + FILTER_DTS16_N6, // Sampling rate is DTS/16, n=6 events + FILTER_DTS16_N8, // Sampling rate is DTS/16, n=8 events + FILTER_DTS32_N5, // Sampling rate is DTS/32, n=5 events + FILTER_DTS32_N6, // Sampling rate is DTS/32, n=6 events + FILTER_DTS32_N8, // Sampling rate is DTS/32, n=8 events +} ChannelInputFilter_t; + #ifdef __cplusplus #include @@ -121,8 +140,8 @@ class HardwareTimer { void setCount(uint32_t val, TimerFormat_t format = TICK_FORMAT); // set timer counter to value 'val' depending on format provided uint32_t getCount(TimerFormat_t format = TICK_FORMAT); // return current counter value of timer depending on format provided - void setMode(uint32_t channel, TimerModes_t mode, PinName pin = NC); // Configure timer channel with specified mode on specified pin if available - void setMode(uint32_t channel, TimerModes_t mode, uint32_t pin); + void setMode(uint32_t channel, TimerModes_t mode, PinName pin = NC, ChannelInputFilter_t filter = FILTER_NONE); // Configure timer channel with specified mode on specified pin if available + void setMode(uint32_t channel, TimerModes_t mode, uint32_t pin, ChannelInputFilter_t filter = FILTER_NONE); TimerModes_t getMode(uint32_t channel); // Retrieve configured mode diff --git a/libraries/SrcWrapper/src/HardwareTimer.cpp b/libraries/SrcWrapper/src/HardwareTimer.cpp index 231f53f41d..f65a4f4f13 100644 --- a/libraries/SrcWrapper/src/HardwareTimer.cpp +++ b/libraries/SrcWrapper/src/HardwareTimer.cpp @@ -619,9 +619,9 @@ void HardwareTimer::setCount(uint32_t counter, TimerFormat_t format) * @param pin: Arduino pin number, ex: D1, 1 or PA1 * @retval None */ -void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, uint32_t pin) +void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, uint32_t pin, ChannelInputFilter_t filter) { - setMode(channel, mode, digitalPinToPinName(pin)); + setMode(channel, mode, digitalPinToPinName(pin), filter); } /** @@ -631,7 +631,7 @@ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, uint32_t pin) * @param pin: pin name, ex: PB_0 * @retval None */ -void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, PinName pin) +void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, PinName pin, ChannelInputFilter_t filter) { int timChannel = getChannel(channel); int timAssociatedInputChannel; @@ -659,7 +659,7 @@ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, PinName pin) channelIC.ICPolarity = TIM_ICPOLARITY_RISING; channelIC.ICSelection = TIM_ICSELECTION_DIRECTTI; channelIC.ICPrescaler = TIM_ICPSC_DIV1; - channelIC.ICFilter = 0; + channelIC.ICFilter = filter; switch (mode) { case TIMER_DISABLED: From 937590b25792594b1e79e52f3457bc59800ffe14 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Oct 2023 17:35:19 +0200 Subject: [PATCH 07/83] fix: typo raised by codespell Signed-off-by: Frederic Pillon --- cores/arduino/stm32/OpenAMP/openamp.c | 2 +- cores/arduino/stm32/backup.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cores/arduino/stm32/OpenAMP/openamp.c b/cores/arduino/stm32/OpenAMP/openamp.c index 351026d7ad..8055a552d6 100644 --- a/cores/arduino/stm32/OpenAMP/openamp.c +++ b/cores/arduino/stm32/OpenAMP/openamp.c @@ -119,7 +119,7 @@ int OPENAMP_Init() MAILBOX_Init(); - /* Libmetal Initilalization */ + /* Libmetal Initialization */ status = OPENAMP_shmem_init(RPMSG_REMOTE); if (status) { return status; diff --git a/cores/arduino/stm32/backup.h b/cores/arduino/stm32/backup.h index 6f422e19b7..63cf7bb22d 100644 --- a/cores/arduino/stm32/backup.h +++ b/cores/arduino/stm32/backup.h @@ -95,7 +95,7 @@ static inline void disableBackupDomain(void) HAL_PWR_DisableBkUpAccess(); #endif #ifdef __HAL_RCC_BKPSRAM_CLK_DISABLE - /* Disnable BKPSRAM CLK for backup SRAM */ + /* Disable BKPSRAM CLK for backup SRAM */ __HAL_RCC_BKPSRAM_CLK_DISABLE(); #endif #ifdef __HAL_RCC_BKP_CLK_DISABLE From 471a0ea4b9e686d24898a4cbfa126385911c4cf2 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 18 Oct 2023 09:35:04 +0200 Subject: [PATCH 08/83] fix: remove broken midatronics links Signed-off-by: Frederic Pillon --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 7e348625c9..e9ceb0d2d0 100644 --- a/README.md +++ b/README.md @@ -781,11 +781,11 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32L151CB | [RAK811 LoRa Tracker](https://www.rakwireless.com/en/) | *1.4.0* | [Wiki](https://github.com/stm32duino/Arduino_Core_STM32/wiki/Connectivities#lora) | | :green_heart: | STM32L051C8 | [RHF76-052](https://lora-alliance.org/lora_products/rhf76-052/) | *1.7.0* | Basic support | -### [Midatronics](https://midatronics.com/) boards +### Midatronics boards | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | -| :green_heart: | STM32WB55CE | [SharkyMKR](https://midatronics.com/shop/development-boards/mkr-sharky-i/) | *1.7.0* | | +| :green_heart: | STM32WB55CE | SharkyMKR | *1.7.0* | | ### [SparkFun](https://www.sparkfun.com/) boards From 843b4d9a078c822f97fc4b7365d33c19e8c5d1ae Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Oct 2023 15:42:50 +0200 Subject: [PATCH 09/83] variants(U5): add generic generic U575C(G-I)x and U585CIx support Signed-off-by: Frederic Pillon --- README.md | 8 +- boards.txt | 48 ++++- .../generic_clock.c | 59 ++++++- .../U575C(G-I)(T-U)_U585CI(T-U)/ldscript.ld | 166 ++++++++++++++++++ 4 files changed, 269 insertions(+), 12 deletions(-) create mode 100644 variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/ldscript.ld diff --git a/README.md b/README.md index e9ceb0d2d0..5574a02bf6 100644 --- a/README.md +++ b/README.md @@ -693,8 +693,12 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | -| :green_heart: | STM32U575AGIxQ
STM32U575AIIxQ
STM32U585AIIxQ | Generic Board | *2.1.0* | | -| :green_heart: | STM32U575ZGTxQ
STM32U575ZITxQ
STM32U585ZITxQ | Generic Board | *2.1.0* | | +| :green_heart: | STM32U575AGIxQ
STM32U575AIIxQ | Generic Board | *2.1.0* | | +| :yellow_heart: | STM32U575CGx
STM32U575CIx | Generic Board | **2.7.0** | | +| :green_heart: | STM32U575ZGTxQ
STM32U575ZITxQ | Generic Board | *2.1.0* | | +| :green_heart: | STM32U585AIIxQ | Generic Board | *2.1.0* | | +| :yellow_heart: | STM32U585CIx | Generic Board | **2.7.0** | | +| :green_heart: | STM32U585ZITxQ | Generic Board | *2.1.0* | | ### Generic STM32WB boards diff --git a/boards.txt b/boards.txt index eb421f6be6..c1ae04a83e 100644 --- a/boards.txt +++ b/boards.txt @@ -9932,6 +9932,22 @@ GenU5.menu.pnum.GENERIC_U575AIIXQ.build.board=GENERIC_U575AIIXQ GenU5.menu.pnum.GENERIC_U575AIIXQ.build.product_line=STM32U575xx GenU5.menu.pnum.GENERIC_U575AIIXQ.build.variant=STM32U5xx/U575A(G-I)IxQ_U585AIIxQ +# Generic U575CITx +GenU5.menu.pnum.GENERIC_U575CITX=Generic U575CITx +GenU5.menu.pnum.GENERIC_U575CITX.upload.maximum_size=2097152 +GenU5.menu.pnum.GENERIC_U575CITX.upload.maximum_data_size=786432 +GenU5.menu.pnum.GENERIC_U575CITX.build.board=GENERIC_U575CITX +GenU5.menu.pnum.GENERIC_U575CITX.build.product_line=STM32U575xx +GenU5.menu.pnum.GENERIC_U575CITX.build.variant=STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U) + +# Generic U575CIUx +GenU5.menu.pnum.GENERIC_U575CIUX=Generic U575CIUx +GenU5.menu.pnum.GENERIC_U575CIUX.upload.maximum_size=2097152 +GenU5.menu.pnum.GENERIC_U575CIUX.upload.maximum_data_size=786432 +GenU5.menu.pnum.GENERIC_U575CIUX.build.board=GENERIC_U575CIUX +GenU5.menu.pnum.GENERIC_U575CIUX.build.product_line=STM32U575xx +GenU5.menu.pnum.GENERIC_U575CIUX.build.variant=STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U) + # Generic U575ZGTxQ GenU5.menu.pnum.GENERIC_U575ZGTXQ=Generic U575ZGTxQ GenU5.menu.pnum.GENERIC_U575ZGTXQ.upload.maximum_size=1048576 @@ -9948,14 +9964,6 @@ GenU5.menu.pnum.GENERIC_U575ZITXQ.build.board=GENERIC_U575ZITXQ GenU5.menu.pnum.GENERIC_U575ZITXQ.build.product_line=STM32U575xx GenU5.menu.pnum.GENERIC_U575ZITXQ.build.variant=STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ -# Generic U585ZITxQ -GenU5.menu.pnum.GENERIC_U585ZITXQ=Generic U585ZITxQ -GenU5.menu.pnum.GENERIC_U585ZITXQ.upload.maximum_size=2097152 -GenU5.menu.pnum.GENERIC_U585ZITXQ.upload.maximum_data_size=786432 -GenU5.menu.pnum.GENERIC_U585ZITXQ.build.board=GENERIC_U585ZITXQ -GenU5.menu.pnum.GENERIC_U585ZITXQ.build.product_line=STM32U585xx -GenU5.menu.pnum.GENERIC_U585ZITXQ.build.variant=STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ - # Generic U585AIIxQ GenU5.menu.pnum.GENERIC_U585AIIXQ=Generic U585AIIxQ GenU5.menu.pnum.GENERIC_U585AIIXQ.upload.maximum_size=2097152 @@ -9964,6 +9972,30 @@ GenU5.menu.pnum.GENERIC_U585AIIXQ.build.board=GENERIC_U585AIIXQ GenU5.menu.pnum.GENERIC_U585AIIXQ.build.product_line=STM32U585xx GenU5.menu.pnum.GENERIC_U585AIIXQ.build.variant=STM32U5xx/U575A(G-I)IxQ_U585AIIxQ +# Generic U585CITx +GenU5.menu.pnum.GENERIC_U585CITX=Generic U585CITx +GenU5.menu.pnum.GENERIC_U585CITX.upload.maximum_size=2097152 +GenU5.menu.pnum.GENERIC_U585CITX.upload.maximum_data_size=786432 +GenU5.menu.pnum.GENERIC_U585CITX.build.board=GENERIC_U585CITX +GenU5.menu.pnum.GENERIC_U585CITX.build.product_line=STM32U585xx +GenU5.menu.pnum.GENERIC_U585CITX.build.variant=STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U) + +# Generic U585CIUx +GenU5.menu.pnum.GENERIC_U585CIUX=Generic U585CIUx +GenU5.menu.pnum.GENERIC_U585CIUX.upload.maximum_size=2097152 +GenU5.menu.pnum.GENERIC_U585CIUX.upload.maximum_data_size=786432 +GenU5.menu.pnum.GENERIC_U585CIUX.build.board=GENERIC_U585CIUX +GenU5.menu.pnum.GENERIC_U585CIUX.build.product_line=STM32U585xx +GenU5.menu.pnum.GENERIC_U585CIUX.build.variant=STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U) + +# Generic U585ZITxQ +GenU5.menu.pnum.GENERIC_U585ZITXQ=Generic U585ZITxQ +GenU5.menu.pnum.GENERIC_U585ZITXQ.upload.maximum_size=2097152 +GenU5.menu.pnum.GENERIC_U585ZITXQ.upload.maximum_data_size=786432 +GenU5.menu.pnum.GENERIC_U585ZITXQ.build.board=GENERIC_U585ZITXQ +GenU5.menu.pnum.GENERIC_U585ZITXQ.build.product_line=STM32U585xx +GenU5.menu.pnum.GENERIC_U585ZITXQ.build.variant=STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ + # Upload menu GenU5.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenU5.menu.upload_method.swdMethod.upload.protocol=0 diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/generic_clock.c b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/generic_clock.c index 284135ee70..1d67c73267 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/generic_clock.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/generic_clock.c @@ -22,8 +22,63 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI + | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_0; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV4; + RCC_OscInitStruct.PLL.PLLM = 3; + RCC_OscInitStruct.PLL.PLLN = 10; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 1; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_LPUART1; + PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/ldscript.ld b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/ldscript.ld new file mode 100644 index 0000000000..a5f0ee1452 --- /dev/null +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/ldscript.ld @@ -0,0 +1,166 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32U575xI Device from STM32U5 series +** +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From ff1731f7012791d837ea24925324176746526ae0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 19 Oct 2023 09:24:28 +0200 Subject: [PATCH 10/83] fix(Wire): avoid memory leaks add destructor to call end(). Fixes #2142 Signed-off-by: Frederic Pillon --- libraries/Wire/src/Wire.cpp | 21 +++++++++++++++++---- libraries/Wire/src/Wire.h | 1 + 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp index 1d8d3ee556..c0b1a25d7a 100644 --- a/libraries/Wire/src/Wire.cpp +++ b/libraries/Wire/src/Wire.cpp @@ -45,6 +45,15 @@ TwoWire::TwoWire(uint32_t sda, uint32_t scl) _i2c.scl = digitalPinToPinName(scl); } +/** + * @brief TwoWire destructor + * @retval None + */ +TwoWire::~TwoWire() +{ + end(); +} + // Public Methods ////////////////////////////////////////////////////////////// void TwoWire::begin(uint32_t sda, uint32_t scl) @@ -106,11 +115,15 @@ void TwoWire::begin(int address, bool generalCall, bool NoStretchMode) void TwoWire::end(void) { i2c_deinit(&_i2c); - free(txBuffer); - txBuffer = nullptr; + if (txBuffer != nullptr) { + free(txBuffer); + txBuffer = nullptr; + } txBufferAllocated = 0; - free(rxBuffer); - rxBuffer = nullptr; + if (rxBuffer != nullptr) { + free(rxBuffer); + rxBuffer = nullptr; + } rxBufferAllocated = 0; } diff --git a/libraries/Wire/src/Wire.h b/libraries/Wire/src/Wire.h index e5a5d8d4e3..fafea29dd9 100644 --- a/libraries/Wire/src/Wire.h +++ b/libraries/Wire/src/Wire.h @@ -78,6 +78,7 @@ class TwoWire : public Stream { public: TwoWire(); TwoWire(uint32_t sda, uint32_t scl); + ~TwoWire(); // setSCL/SDA have to be called before begin() void setSCL(uint32_t scl) { From b3400a462daa7292075c9a3be3978f64dee56323 Mon Sep 17 00:00:00 2001 From: bendiabdallah Date: Mon, 16 Oct 2023 20:34:59 +0200 Subject: [PATCH 11/83] variants(U5): add Iot continuum devkit board Signed-off-by: bendiabdallah --- README.md | 7 + boards.txt | 87 ++++- .../PeripheralPins_DEVKIT_IOT_CONTINUUM.c | 299 ++++++++++++++++++ .../README_IOTCONTINUUM_DEVKIT.md | 47 +++ .../variant_DEVKIT_IOT_CONTINUUM.cpp | 126 ++++++++ .../variant_DEVKIT_IOT_CONTINUUM.h | 256 +++++++++++++++ 6 files changed, 821 insertions(+), 1 deletion(-) create mode 100644 variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins_DEVKIT_IOT_CONTINUUM.c create mode 100644 variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/README_IOTCONTINUUM_DEVKIT.md create mode 100644 variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/variant_DEVKIT_IOT_CONTINUUM.cpp create mode 100644 variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/variant_DEVKIT_IOT_CONTINUUM.h diff --git a/README.md b/README.md index 5574a02bf6..f108692c8a 100644 --- a/README.md +++ b/README.md @@ -79,6 +79,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d - [Electronic Speed Controller boards](#electronic-speed-controller-boards) - [Garatronic/McHobby boards](#garatronicmchobby-boards) - [Generic flight controllers](#generic-flight-controllers) + - [IoT continuum boards](#iot-continuum-boards) - [LoRa boards](#lora-boards) - [Midatronics boards](#midatronics-boards) - [SparkFun boards](#sparkfun-boards) @@ -774,6 +775,12 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F103CB | Afro Flight Rev5 (8/12MHz) | *1.7.0* | | | :green_heart: | STM32F303CC | [Sparky V1](https://github.com/TauLabs/TauLabs/wiki/Sparky) | *1.6.0* | | +### [IoT continuum](https://iotjourney.orange.com/fr-FR) boards + +| Status | Device(s) | Name | Release | Notes | +| :----: | :-------: | ---- | :-----: | :---- | +| :yellow_heart: | STM32U585CIU6 | [IoT continuum DevKit Board - STM32U585CIU6](https://iotjourney.orange.com/en/iotcontinuum/kits) | **2.7.0** | | + ### LoRa boards | Status | Device(s) | Name | Release | Notes | diff --git a/boards.txt b/boards.txt index c1ae04a83e..a6772f8989 100644 --- a/boards.txt +++ b/boards.txt @@ -10757,6 +10757,48 @@ GenFlight.menu.upload_method.dfuoMethod.upload.altID=1 GenFlight.menu.upload_method.dfuoMethod.build.flash_offset=0x5000 GenFlight.menu.upload_method.dfuoMethod.build.bootloader_flags=-DBL_LEGACY_LEAF +################################################################################ +# IoT continuum Boards + +IotContinuum.name=IoT continuum boards + +IotContinuum.build.core=arduino +IotContinuum.build.board=IOT_CONTINUUM +IotContinuum.build.variant_h=variant_{build.board}.h +IotContinuum.build.st_extra_flags=-D{build.product_line} {build.xSerial} +IotContinuum.build.flash_offset=0x0 +IotContinuum.upload.maximum_size=0 +IotContinuum.upload.maximum_data_size=0 + +# IoT continuum Dev Kit Board +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM=IoT continuum Dev Kit +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.upload.maximum_size=2097152 +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.upload.maximum_data_size=786432 +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.mcu=cortex-m33 +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.fpu=-mfpu=fpv4-sp-d16 +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.float-abi=-mfloat-abi=hard +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.board=DEVKIT_IOT_CONTINUUM +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.series=STM32U5xx +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.product_line=STM32U585xx +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.variant=STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U) +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS + +# Upload menu +IotContinuum.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) +IotContinuum.menu.upload_method.swdMethod.upload.protocol=0 +IotContinuum.menu.upload_method.swdMethod.upload.options= +IotContinuum.menu.upload_method.swdMethod.upload.tool=stm32CubeProg + +IotContinuum.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) +IotContinuum.menu.upload_method.serialMethod.upload.protocol=1 +IotContinuum.menu.upload_method.serialMethod.upload.options={serial.port.file} +IotContinuum.menu.upload_method.serialMethod.upload.tool=stm32CubeProg + +IotContinuum.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) +IotContinuum.menu.upload_method.dfuMethod.upload.protocol=2 +IotContinuum.menu.upload_method.dfuMethod.upload.options= +IotContinuum.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg + ################################################################################ # LoRa boards @@ -10998,7 +11040,6 @@ SparkFun.menu.upload_method.dfuMethod.upload.protocol=2 SparkFun.menu.upload_method.dfuMethod.upload.options= SparkFun.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg - ################################################################################ # Serialx activation Nucleo_144.menu.xserial.generic=Enabled (generic 'Serial') @@ -11189,6 +11230,12 @@ GenFlight.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_N GenFlight.menu.xserial.disabled=Disabled (no Serial support) GenFlight.menu.xserial.disabled.build.xSerial= +IotContinuum.menu.xserial.generic=Enabled (generic 'Serial') +IotContinuum.menu.xserial.none=Enabled (no generic 'Serial') +IotContinuum.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE +IotContinuum.menu.xserial.disabled=Disabled (no Serial support) +IotContinuum.menu.xserial.disabled.build.xSerial= + LoRa.menu.xserial.generic=Enabled (generic 'Serial') LoRa.menu.xserial.none=Enabled (no generic 'Serial') LoRa.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE @@ -12157,6 +12204,26 @@ GenFlight.menu.opt.ogstd.build.flags.optimize=-Og GenFlight.menu.opt.o0std=No Optimization (-O0) GenFlight.menu.opt.o0std.build.flags.optimize=-O0 +IotContinuum.menu.opt.osstd=Smallest (-Os default) +IotContinuum.menu.opt.oslto=Smallest (-Os) with LTO +IotContinuum.menu.opt.oslto.build.flags.optimize=-Os -flto +IotContinuum.menu.opt.o1std=Fast (-O1) +IotContinuum.menu.opt.o1std.build.flags.optimize=-O1 +IotContinuum.menu.opt.o1lto=Fast (-O1) with LTO +IotContinuum.menu.opt.o1lto.build.flags.optimize=-O1 -flto +IotContinuum.menu.opt.o2std=Faster (-O2) +IotContinuum.menu.opt.o2std.build.flags.optimize=-O2 +IotContinuum.menu.opt.o2lto=Faster (-O2) with LTO +IotContinuum.menu.opt.o2lto.build.flags.optimize=-O2 -flto +IotContinuum.menu.opt.o3std=Fastest (-O3) +IotContinuum.menu.opt.o3std.build.flags.optimize=-O3 +IotContinuum.menu.opt.o3lto=Fastest (-O3) with LTO +IotContinuum.menu.opt.o3lto.build.flags.optimize=-O3 -flto +IotContinuum.menu.opt.ogstd=Debug (-Og) +IotContinuum.menu.opt.ogstd.build.flags.optimize=-Og +IotContinuum.menu.opt.o0std=No Optimization (-O0) +IotContinuum.menu.opt.o0std.build.flags.optimize=-O0 + LoRa.menu.opt.osstd=Smallest (-Os default) LoRa.menu.opt.oslto=Smallest (-Os) with LTO LoRa.menu.opt.oslto.build.flags.optimize=-Os -flto @@ -12446,6 +12513,14 @@ GenFlight.menu.dbg.enable_log.build.flags.debug= GenFlight.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) GenFlight.menu.dbg.enable_all.build.flags.debug=-g +IotContinuum.menu.dbg.none=None +IotContinuum.menu.dbg.enable_sym=Symbols Enabled (-g) +IotContinuum.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG +IotContinuum.menu.dbg.enable_log=Core logs Enabled +IotContinuum.menu.dbg.enable_log.build.flags.debug= +IotContinuum.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) +IotContinuum.menu.dbg.enable_all.build.flags.debug=-g + LoRa.menu.dbg.none=None LoRa.menu.dbg.enable_sym=Symbols Enabled (-g) LoRa.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG @@ -12771,6 +12846,16 @@ GenFlight.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_f GenFlight.menu.rtlib.full=Newlib Standard GenFlight.menu.rtlib.full.build.flags.ldspecs= +IotContinuum.menu.rtlib.nano=Newlib Nano (default) +IotContinuum.menu.rtlib.nanofp=Newlib Nano + Float Printf +IotContinuum.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +IotContinuum.menu.rtlib.nanofs=Newlib Nano + Float Scanf +IotContinuum.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +IotContinuum.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +IotContinuum.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +IotContinuum.menu.rtlib.full=Newlib Standard +IotContinuum.menu.rtlib.full.build.flags.ldspecs= + LoRa.menu.rtlib.nano=Newlib Nano (default) LoRa.menu.rtlib.nanofp=Newlib Nano + Float Printf LoRa.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins_DEVKIT_IOT_CONTINUUM.c b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins_DEVKIT_IOT_CONTINUUM.c new file mode 100644 index 0000000000..18d049bfec --- /dev/null +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins_DEVKIT_IOT_CONTINUUM.c @@ -0,0 +1,299 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U575CGTx.xml, STM32U575CGUx.xml + * STM32U575CITx.xml, STM32U575CIUx.xml + * STM32U585CITx.xml, STM32U585CIUx.xml + * CubeMX DB release 6.0.90 + */ +#if defined(ARDUINO_DEVKIT_IOT_CONTINUUM) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC4_IN18 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC4_IN19 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PB_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCS + {PA_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_FS[] = { + {PA_8, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_OTG_FS_SOF + {PA_9, USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS + {PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_OTG_FS_ID + {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_OTG_FS_DM + {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_OTG_FS_DP + {PA_13, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_OTG_FS_NOE + {PA_14, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_OTG_FS_SOF + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* ARDUINO_DEVKIT_IOT_CONTINUUM */ diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/README_IOTCONTINUUM_DEVKIT.md b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/README_IOTCONTINUUM_DEVKIT.md new file mode 100644 index 0000000000..8025fcb3dc --- /dev/null +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/README_IOTCONTINUUM_DEVKIT.md @@ -0,0 +1,47 @@ +## Pinout + + +### Outer PINs + +| I/O Pins | Arduino | STM32U585 | +| --- | --- | --- | +| 13 | IO13 | GPIO6 Expander | +| 12 | D12 | PB13 | +| 11 | D11 | PA11 | +| 10 | D10 | PA8 | +| 9 | D9 | PB15 | +| 6 | D6 | PB14 | +| 5 | D5 | PB10 | +| 4 | IO4 | GPIO1 Expander | +| SCL | D17 | PB6 | +| SDA | D18 | PB7 | +| RX/D1 | D1 | PA3 | +| TX/D0 | D0 | PA2 | +| A0 | A0/D2 | PA0 | +| A1 | A1/D3 | PA1 | +| A2 | A2/D4 | PA6 | +| A3 | A3/D7 | PB0 | +| A4 | A4/D8 | PB1 | +| A5 | A5/D13 | PB2 | +| SCK | D14 | PB3 | +| MISO | D15 | PB4 | +| MOSI | D16 | PB5 | + +### Inner PINs + +| I/O Pins | Arduino | STM32U585 | Comment | +| --- | --- | --- | --- | +| BAT_LEVEL | BAT_LEVEL | PA4 | Battery level | +| USB_UART_RX | PIN_SERIAL_RX | PA5 | RX to USB | +| USB_UART_TX | PIN_SERIAL_TX | PA7 | TX to USB | +| MODULE_TX | PIN_SERIAL3_TX | PA9 | TX to HL7812 | +| MODULE_RX | PIN_SERIAL3_RX | PA10 | RX to HL7812 | +| BUTTON | USER_BTN | PA12 | Push button status | +| SWDIO | NC | PA13 | J-TAG Programming | +| SWCLK | NC | PA14 | J-TAG Programming | +| WAKE_UP | WAKE_UP_HL7812 | PA15 | Module wake up on sleep | +| VGPIO | VGPIO | PC13 | Module state (active/on sleep) | +| SEL_MODE_UART | SWITCH_TO_HL7812 | PB8 | UART mode activation (STM32 or HL7812) | +| RESET MODULE | RESET_HL7812 | PB12 | Module Reset | +| INT2_ACCEL | INT_ACCEL | PB9 | LSM6DSOX interrupt state | +| LED RGB | RED_LED, GREEN_LED, BLUE_LED | NC | Led R=GPIO3, G=GPIO4, B=GPIO5 Expander | diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/variant_DEVKIT_IOT_CONTINUUM.cpp b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/variant_DEVKIT_IOT_CONTINUUM.cpp new file mode 100644 index 0000000000..252e5db632 --- /dev/null +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/variant_DEVKIT_IOT_CONTINUUM.cpp @@ -0,0 +1,126 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_DEVKIT_IOT_CONTINUUM) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_2, // D0/TX + PA_3, // D1/RX + PA_0, // D2/A0 + PA_1, // D3/A1 + PA_6, // D4/A2 + PB_10, // D5 + PB_14, // D6 + PB_0, // D7/A3 + PB_1, // D8/A4 + PB_15, // D9 + PA_8, // D10 + PA_11, // D11 + PB_13, // D12 + PB_2, // D13/A5 + PB_3, // D14/SCK + PB_4, // D15/MISO + PB_5, // D16/MOSI + PB_6, // D17/SCL + PB_7, // D18/SDA + PA_4, // D19/A6 + PA_5, // D20 + PA_7, // D21 + PA_9, // D22 + PA_10, // D23 + PA_12, // D24 + PA_13, // D25 + PA_14, // D26 + PA_15, // D27 + PB_8, // D28 + PB_9, // D29 + PB_12, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PH_0, // D34 + PH_1, // D35 + PH_3 // D36 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 2, // A0, PA0 + 3, // A1, PA1 + 4, // A2, PA6 + 7, // A3, PB0 + 8, // A4, PB1 + 13, // A5, PB2 + 19 // A6, PA4 +}; + +/** System Clock Configuration +*/ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { + Error_Handler(); + } + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 10; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 1; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } + + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } +} + +#endif /* ARDUINO_DEVKIT_IOT_CONTINUUM */ diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/variant_DEVKIT_IOT_CONTINUUM.h b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/variant_DEVKIT_IOT_CONTINUUM.h new file mode 100644 index 0000000000..b6782b2dd0 --- /dev/null +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/variant_DEVKIT_IOT_CONTINUUM.h @@ -0,0 +1,256 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA2 0 +#define PA3 1 +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA6 PIN_A2 +#define PB10 5 +#define PB14 6 +#define PB0 PIN_A3 +#define PB1 PIN_A4 +#define PB15 9 +#define PA8 10 +#define PA11 11 +#define PB13 12 +#define PB2 PIN_A5 +#define PB3 14 +#define PB4 15 +#define PB5 16 +#define PB6 17 +#define PB7 18 +#define PA4 PIN_A6 +#define PA5 20 +#define PA7 21 +#define PA9 22 +#define PA10 23 +#define PA12 24 +#define PA13 25 +#define PA14 26 +#define PA15 27 +#define PB8 28 +#define PB9 29 +#define PB12 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PH0 34 +#define PH1 35 +#define PH3 36 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 37 +#define NUM_ANALOG_INPUTS 7 + +// User button +#ifndef USER_BTN + #define USER_BTN PA12 +#endif + +// Switch to HL7812 +#ifndef SWITCH_TO_HL7812 + #define SWITCH_TO_HL7812 PB8 +#endif + +// WAKE UP HL721 +#ifndef WAKE_UP_HL7812 + #define WAKE_UP_HL7812 PA15 +#endif + +// Battery level +#ifndef BAT_LEVEL + #define BAT_LEVEL PA4 +#endif + +// Accelerator interrupt +#ifndef INT_ACCEL + #define INT_ACCEL PB9 +#endif + +// reset HL7812 +#ifndef RESET_HL7812 + #define RESET_HL7812 PB12 +#endif + +// VGPIO_SHIFT +#ifndef VGPIO + #define VGPIO PC13 +#endif + +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PB5 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB4 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB3 +#endif + +// GPIO Expander (warning: not a pin number) +#ifndef RED_LED + #define RED_LED 3 +#endif + +#ifndef GREEN_LED + #define GREEN_LED 4 +#endif + +#ifndef BLUE_LED + #define BLUE_LED 5 +#endif + +#ifndef IO4 + #define IO4 1 +#endif + +#ifndef IO13 + #define IO13 6 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB7 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 3 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA5 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA7 +#endif + +#ifndef PIN_SERIALLP1_RX + #define PIN_SERIALLP1_RX PA3 +#endif +#ifndef PIN_SERIALLP1_TX + #define PIN_SERIALLP1_TX PA2 +#endif + +#ifndef PIN_SERIAL3_RX + #define PIN_SERIAL3_RX PA10 +#endif +#ifndef PIN_SERIAL3_TX + #define PIN_SERIAL3_TX PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// Extra HAL modules +// #if !defined(HAL_DAC_MODULE_DISABLED) +// #define HAL_DAC_MODULE_ENABLED +// #endif +// #if !defined(HAL_OSPI_MODULE_DISABLED) +// #define HAL_OSPI_MODULE_ENABLED +// #endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 81583c57056b8aba47c56e4bb3eb588dae669f88 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 23 Oct 2023 10:08:24 +0200 Subject: [PATCH 12/83] feat: implement weaked _gettimeofday Fixes #2129. Signed-off-by: Frederic Pillon --- cores/arduino/wiring_time.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/cores/arduino/wiring_time.h b/cores/arduino/wiring_time.h index 74b1978c92..4b32537629 100644 --- a/cores/arduino/wiring_time.h +++ b/cores/arduino/wiring_time.h @@ -22,6 +22,7 @@ #include "clock.h" #include "dwt.h" +#include // for struct timeval #ifdef __cplusplus extern "C" { @@ -86,6 +87,27 @@ static inline void delayMicroseconds(uint32_t us) #endif } +/** + * \brief gives the number of seconds and microseconds since the Epoch + * + * based on millisecond since last power on. + * + * \note The function is declared as weak to be overwritten in case of other + * implementations in user file (using RTC values for example). + * + * \param tv argument is a struct timeval + * \param tz argument is a struct timezone (unused) + * + * \return 0 + */ +int __attribute__((weak)) _gettimeofday(struct timeval *tv, void *tz) +{ + (void)tz; + tv->tv_sec = getCurrentMillis() / 1000; + tv->tv_usec = getCurrentMicros() - (tv->tv_sec * 1000000); // get remaining microseconds + return 0; +} + #ifdef __cplusplus } #endif From ff982297443c944f7921dd9acab2a650469596b7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 26 Oct 2023 11:29:26 +0200 Subject: [PATCH 13/83] fix(backup): enable RTC clock for TAMP backup registers Fixes #2152. Signed-off-by: Frederic Pillon --- cores/arduino/stm32/backup.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/cores/arduino/stm32/backup.h b/cores/arduino/stm32/backup.h index 63cf7bb22d..9965f68c79 100644 --- a/cores/arduino/stm32/backup.h +++ b/cores/arduino/stm32/backup.h @@ -86,6 +86,10 @@ static inline void enableBackupDomain(void) /* Enable BKPSRAM CLK for backup SRAM */ __HAL_RCC_BKPSRAM_CLK_ENABLE(); #endif +#if defined(TAMP_BKP0R) && defined(__HAL_RCC_RTCAPB_CLK_ENABLE) + /* Enable RTC CLK for TAMP backup registers */ + __HAL_RCC_RTCAPB_CLK_ENABLE(); +#endif } static inline void disableBackupDomain(void) @@ -102,6 +106,10 @@ static inline void disableBackupDomain(void) /* Disable BKP CLK for backup registers */ __HAL_RCC_BKP_CLK_DISABLE(); #endif +#if defined(TAMP_BKP0R) && defined(__HAL_RCC_RTCAPB_CLK_DISABLE) + /* Disable RTC CLK for TAMP backup registers */ + __HAL_RCC_RTCAPB_CLK_DISABLE(); +#endif } static inline void setBackupRegister(uint32_t index, uint32_t value) From 7c3c9f0d5b85c6f8e489247de38ecfa9671c018d Mon Sep 17 00:00:00 2001 From: Trent Houliston Date: Sun, 29 Oct 2023 14:38:11 +1100 Subject: [PATCH 14/83] Wrap cmake policies in an if statement --- cmake/FindArduinoCtags.cmake | 4 +++- cmake/ensure_core_deps.cmake | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/cmake/FindArduinoCtags.cmake b/cmake/FindArduinoCtags.cmake index 95a16749a0..6e497cc0ad 100644 --- a/cmake/FindArduinoCtags.cmake +++ b/cmake/FindArduinoCtags.cmake @@ -6,7 +6,9 @@ function(get_ctags) # Prevent warnings in CMake>=3.24 regarding ExternalProject_Add() # cf. https://cmake.org/cmake/help/latest/policy/CMP0135.html - cmake_policy(SET CMP0135 OLD) + if (POLICY CMP0135) + cmake_policy(SET CMP0135 OLD) + endif() cmake_host_system_information( RESULT HOSTINFO diff --git a/cmake/ensure_core_deps.cmake b/cmake/ensure_core_deps.cmake index 9aaf552bba..82319cd29c 100644 --- a/cmake/ensure_core_deps.cmake +++ b/cmake/ensure_core_deps.cmake @@ -61,7 +61,9 @@ function(declare_deps CORE_VERSION) # Prevent warnings in CMake>=3.24 regarding ExternalProject_Add() # cf. https://cmake.org/cmake/help/latest/policy/CMP0135.html - cmake_policy(SET CMP0135 OLD) + if (POLICY CMP0135) + cmake_policy(SET CMP0135 OLD) + endif() file(REAL_PATH "${DL_DIR}/package_stmicroelectronics_index.json" JSONFILE) if (NOT EXISTS ${JSONFILE}) From d3465d5651cdac37fec556440667cc1570533d5f Mon Sep 17 00:00:00 2001 From: Mathieu CHOPLAIN Date: Tue, 17 Oct 2023 15:25:33 +0200 Subject: [PATCH 15/83] variant(H7): add generic H747X(G-I)xx support This commit adds generic support for H747XIH and compatible MCUs: * H742X(G-I)H * H743X(G-I)H * H745X(G-I)H * H747X(G-I)H * H750XBH * H753XIH * H755XIH * H757XIH The clock is configured to have core running at 480MHz. Tested successfully (working LED/Joystick via GPIO) on STM32H747I-DISCO. Signed-off-by: Mathieu Choplain --- README.md | 8 + boards.txt | 96 ++++++++ .../generic_clock.c | 111 +++++++++- .../ldscript.ld | 205 ++++++++++++++++++ 4 files changed, 418 insertions(+), 2 deletions(-) create mode 100644 variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/ldscript.ld diff --git a/README.md b/README.md index f108692c8a..5b3ba3470e 100644 --- a/README.md +++ b/README.md @@ -541,14 +541,18 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H733ZGT | Generic Board | *2.4.0* | | | :green_heart: | STM32H742IG
STM32H742II | Generic Board | *2.1.0* | | | :green_heart: | STM32H742VG
STM32H742VI | Generic Board | *2.0.0* | | +| :yellow_heart: | STM32H742XG
STM32H742XI | Generic Board | **2.7.0** | | | :green_heart: | STM32H742ZG
STM32H742ZI | Generic Board | *2.0.0* | | | :green_heart: | STM32H743IG
STM32H743II | Generic Board | *2.0.0* | | | :green_heart: | STM32H743VG
STM32H743VI | Generic Board | *2.0.0* | | | :green_heart: | STM32H743VI | [DevEBox H743VIT6](https://github.com/mcauser/MCUDEV_DEVEBOX_H7XX_M) | *2.2.0* | | | :green_heart: | STM32H743VI | [WeAct MiniSTM32H743VIT6](https://github.com/WeActStudio/MiniSTM32H7xx) | *2.2.0* | [More info](https://github.com/stm32duino/Arduino_Core_STM32/pull/1552) | +| :yellow_heart: | STM32H743XG
STM32H743XI | Generic Board | **2.7.0** | | | :green_heart: | STM32H743ZG
STM32H743ZI | Generic Board | *2.0.0* | | +| :yellow_heart: | STM32H745XG
STM32H745XI | Generic Board | **2.7.0** | | | :green_heart: | STM32H747AG
STM32H747AI | Generic Board | *2.0.0* | | | :green_heart: | STM32H747IG
STM32H747II | Generic Board | *2.0.0* | | +| :yellow_heart: | STM32H747XG
STM32H747XI | Generic Board | **2.7.0** | | | :green_heart: | STM32H750ZB | Generic Board | *2.0.0* | | | :green_heart: | STM32H750IB
STM32H750II | Generic Board | *2.0.0* | | | :green_heart: | STM32H750IB | [Daisy](https://www.electro-smith.com/daisy/daisy) | *1.9.0* | | @@ -557,10 +561,14 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H750VB | Generic Board | *2.0.0* | | | :green_heart: | STM32H750VB | [DevEBox H750VBT6](https://github.com/mcauser/MCUDEV_DEVEBOX_H7XX_M) | *2.2.0* | | | :green_heart: | STM32H750VB | [WeAct MiniSTM32H750VBT6](https://github.com/WeActStudio/MiniSTM32H7xx) | *2.2.0* | [More info](https://github.com/stm32duino/Arduino_Core_STM32/pull/1552) | +| :yellow_heart: | STM32H750XB | Generic Board | **2.7.0** | | | :green_heart: | STM32H753VI | Generic Board | *2.0.0* | | +| :yellow_heart: | STM32H753XI | Generic Board | **2.7.0** | | | :green_heart: | STM32H753ZI | Generic Board | *2.0.0* | | +| :yellow_heart: | STM32H755XI | Generic Board | **2.7.0** | | | :green_heart: | STM32H757AI | Generic Board | *2.0.0* | | | :green_heart: | STM32H757II | Generic Board | *2.0.0* | | +| :yellow_heart: | STM32H757XI | Generic Board | **2.7.0** | | ### Generic STM32L0 boards diff --git a/boards.txt b/boards.txt index a6772f8989..4fbe9e34c3 100644 --- a/boards.txt +++ b/boards.txt @@ -7540,6 +7540,22 @@ GenH7.menu.pnum.GENERIC_H742VITX.build.board=GENERIC_H742VITX GenH7.menu.pnum.GENERIC_H742VITX.build.product_line=STM32H742xx GenH7.menu.pnum.GENERIC_H742VITX.build.variant=STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T) +# Generic H742XGHx +GenH7.menu.pnum.GENERIC_H742XGHX=Generic H742XGHx +GenH7.menu.pnum.GENERIC_H742XGHX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H742XGHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H742XGHX.build.board=GENERIC_H742XGHX +GenH7.menu.pnum.GENERIC_H742XGHX.build.product_line=STM32H742xx +GenH7.menu.pnum.GENERIC_H742XGHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + +# Generic H742XIHx +GenH7.menu.pnum.GENERIC_H742XIHX=Generic H742XIHx +GenH7.menu.pnum.GENERIC_H742XIHX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H742XIHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H742XIHX.build.board=GENERIC_H742XIHX +GenH7.menu.pnum.GENERIC_H742XIHX.build.product_line=STM32H742xx +GenH7.menu.pnum.GENERIC_H742XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + # Generic H742ZGTx GenH7.menu.pnum.GENERIC_H742ZGTX=Generic H742ZGTx GenH7.menu.pnum.GENERIC_H742ZGTX.upload.maximum_size=1048576 @@ -7620,6 +7636,22 @@ GenH7.menu.pnum.GENERIC_H743VITX.build.board=GENERIC_H743VITX GenH7.menu.pnum.GENERIC_H743VITX.build.product_line=STM32H743xx GenH7.menu.pnum.GENERIC_H743VITX.build.variant=STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T) +# Generic H743XGHx +GenH7.menu.pnum.GENERIC_H743XGHX=Generic H743XGHx +GenH7.menu.pnum.GENERIC_H743XGHX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H743XGHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H743XGHX.build.board=GENERIC_H743XGHX +GenH7.menu.pnum.GENERIC_H743XGHX.build.product_line=STM32H743xx +GenH7.menu.pnum.GENERIC_H743XGHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + +# Generic H743XIHx +GenH7.menu.pnum.GENERIC_H743XIHX=Generic H743XIHx +GenH7.menu.pnum.GENERIC_H743XIHX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H743XIHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H743XIHX.build.board=GENERIC_H743XIHX +GenH7.menu.pnum.GENERIC_H743XIHX.build.product_line=STM32H743xx +GenH7.menu.pnum.GENERIC_H743XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + # Generic H743ZGTx GenH7.menu.pnum.GENERIC_H743ZGTX=Generic H743ZGTx GenH7.menu.pnum.GENERIC_H743ZGTX.upload.maximum_size=1048576 @@ -7636,6 +7668,22 @@ GenH7.menu.pnum.GENERIC_H743ZITX.build.board=GENERIC_H743ZITX GenH7.menu.pnum.GENERIC_H743ZITX.build.product_line=STM32H743xx GenH7.menu.pnum.GENERIC_H743ZITX.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT +# Generic H745XGHx +GenH7.menu.pnum.GENERIC_H745XGHX=Generic H745XGHx +GenH7.menu.pnum.GENERIC_H745XGHX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H745XGHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H745XGHX.build.board=GENERIC_H745XGHX +GenH7.menu.pnum.GENERIC_H745XGHX.build.product_line=STM32H745xG +GenH7.menu.pnum.GENERIC_H745XGHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + +# Generic H745XIHx +GenH7.menu.pnum.GENERIC_H745XIHX=Generic H745XIHx +GenH7.menu.pnum.GENERIC_H745XIHX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H745XIHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H745XIHX.build.board=GENERIC_H745XIHX +GenH7.menu.pnum.GENERIC_H745XIHX.build.product_line=STM32H745xx +GenH7.menu.pnum.GENERIC_H745XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + # Generic H747AGIx GenH7.menu.pnum.GENERIC_H747AGIX=Generic H747AGIx GenH7.menu.pnum.GENERIC_H747AGIX.upload.maximum_size=1048576 @@ -7668,6 +7716,22 @@ GenH7.menu.pnum.GENERIC_H747IITX.build.board=GENERIC_H747IITX GenH7.menu.pnum.GENERIC_H747IITX.build.product_line=STM32H747xx GenH7.menu.pnum.GENERIC_H747IITX.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT +# Generic H747XGHx +GenH7.menu.pnum.GENERIC_H747XGHX=Generic H747XGHx +GenH7.menu.pnum.GENERIC_H747XGHX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H747XGHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H747XGHX.build.board=GENERIC_H747XGHX +GenH7.menu.pnum.GENERIC_H747XGHX.build.product_line=STM32H747xG +GenH7.menu.pnum.GENERIC_H747XGHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + +# Generic H747XIHx +GenH7.menu.pnum.GENERIC_H747XIHX=Generic H747XIHx +GenH7.menu.pnum.GENERIC_H747XIHX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H747XIHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H747XIHX.build.board=GENERIC_H747XIHX +GenH7.menu.pnum.GENERIC_H747XIHX.build.product_line=STM32H747xx +GenH7.menu.pnum.GENERIC_H747XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + # Generic H750IBKx GenH7.menu.pnum.GENERIC_H750IBKX=Generic H750IBKx GenH7.menu.pnum.GENERIC_H750IBKX.upload.maximum_size=131072 @@ -7692,6 +7756,14 @@ GenH7.menu.pnum.GENERIC_H750VBTX.build.board=GENERIC_H750VBTX GenH7.menu.pnum.GENERIC_H750VBTX.build.product_line=STM32H750xx GenH7.menu.pnum.GENERIC_H750VBTX.build.variant=STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T) +# Generic H750XBHx +GenH7.menu.pnum.GENERIC_H750XBHX=Generic H750XBHx +GenH7.menu.pnum.GENERIC_H750XBHX.upload.maximum_size=131072 +GenH7.menu.pnum.GENERIC_H750XBHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H750XBHX.build.board=GENERIC_H750XBHX +GenH7.menu.pnum.GENERIC_H750XBHX.build.product_line=STM32H750xx +GenH7.menu.pnum.GENERIC_H750XBHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + # Generic H750ZBTx GenH7.menu.pnum.GENERIC_H750ZBTX=Generic H750ZBTx GenH7.menu.pnum.GENERIC_H750ZBTX.upload.maximum_size=131072 @@ -7732,6 +7804,14 @@ GenH7.menu.pnum.GENERIC_H753VITX.build.board=GENERIC_H753VITX GenH7.menu.pnum.GENERIC_H753VITX.build.product_line=STM32H753xx GenH7.menu.pnum.GENERIC_H753VITX.build.variant=STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T) +# Generic H753XIHx +GenH7.menu.pnum.GENERIC_H753XIHX=Generic H753XIHx +GenH7.menu.pnum.GENERIC_H753XIHX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H753XIHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H753XIHX.build.board=GENERIC_H753XIHX +GenH7.menu.pnum.GENERIC_H753XIHX.build.product_line=STM32H753xx +GenH7.menu.pnum.GENERIC_H753XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + # Generic H753ZITx GenH7.menu.pnum.GENERIC_H753ZITX=Generic H753ZITx GenH7.menu.pnum.GENERIC_H753ZITX.upload.maximum_size=2097152 @@ -7740,6 +7820,14 @@ GenH7.menu.pnum.GENERIC_H753ZITX.build.board=GENERIC_H753ZITX GenH7.menu.pnum.GENERIC_H753ZITX.build.product_line=STM32H753xx GenH7.menu.pnum.GENERIC_H753ZITX.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT +# Generic H755XIHx +GenH7.menu.pnum.GENERIC_H755XIHX=Generic H755XIHx +GenH7.menu.pnum.GENERIC_H755XIHX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H755XIHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H755XIHX.build.board=GENERIC_H755XIHX +GenH7.menu.pnum.GENERIC_H755XIHX.build.product_line=STM32H755xx +GenH7.menu.pnum.GENERIC_H755XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + # Generic H757AIIx GenH7.menu.pnum.GENERIC_H757AIIX=Generic H757AIIx GenH7.menu.pnum.GENERIC_H757AIIX.upload.maximum_size=2097152 @@ -7756,6 +7844,14 @@ GenH7.menu.pnum.GENERIC_H757IITX.build.board=GENERIC_H757IITX GenH7.menu.pnum.GENERIC_H757IITX.build.product_line=STM32H757xx GenH7.menu.pnum.GENERIC_H757IITX.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT +# Generic H757XIHx +GenH7.menu.pnum.GENERIC_H757XIHX=Generic H757XIHx +GenH7.menu.pnum.GENERIC_H757XIHX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H757XIHX.upload.maximum_data_size=524288 +GenH7.menu.pnum.GENERIC_H757XIHX.build.board=GENERIC_H757XIHX +GenH7.menu.pnum.GENERIC_H757XIHX.build.product_line=STM32H757xx +GenH7.menu.pnum.GENERIC_H757XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH + # Upload menu GenH7.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenH7.menu.upload_method.swdMethod.upload.protocol=0 diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/generic_clock.c b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/generic_clock.c index fb9444e7c9..26228f0a6a 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/generic_clock.c +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/generic_clock.c @@ -25,8 +25,115 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + + /** Supply configuration update enable + */ +#if defined(SMPS) + /** If SMPS is available on this MCU, assume that the MCU's board is + * built to power the MCU using the SMPS since it's more efficient. + * In this case, we must configure the MCU to use DIRECT_SMPS_SUPPLY. + * + * N.B.: if the hardware configuration does not match the argument to + * HAL_PWREx_ConfigSupply(), the board will deadlock at this function call. + * This can manifest immediately or after a RESET/power cycle. + * + * Trying to flash the board at this point will result in errors such as + * "No STM32 target found". To overcome this problem, erase the MCU's flash. + * + * The following settings in STM32CubeProgrammer appear to work for this purpose: + * - Mode: Power down + * - Reset mode: Hardware reset + */ + HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); +#else + /** No SMPS available: use the internal voltage regulator (LDO). + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); +#endif + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_CSI + | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 60; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 5; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_CKPER + | RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_I2C123 | RCC_PERIPHCLK_I2C4 + | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM3 + | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_USB + | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 + | RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP; + PeriphClkInitStruct.CecClockSelection = RCC_CECCLKSOURCE_CSI; + PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; + PeriphClkInitStruct.Hrtim1ClockSelection = RCC_HRTIM1CLK_CPUCLK; + PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.Lptim2ClockSelection = RCC_LPTIM2CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.Lptim345ClockSelection = RCC_LPTIM345CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/ldscript.ld b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/ldscript.ld new file mode 100644 index 0000000000..f5102fa972 --- /dev/null +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/ldscript.ld @@ -0,0 +1,205 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE & Mathieu CHOPLAIN +** +** Abstract : Linker script for STM32H7XIHx series +** 2048Kbytes FLASH +** 512Kbytes RAM_D1 +** 288Kbytes RAM_D2 (stack) +** 64Kbytes RAM_D3 (unused) +** 128Kbytes ITCMRAM (unused) +** 64Kbytes DTCMRAM (unused) +** +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software component is licensed by ST under BSD 3-Clause license, +** the "License"; You may not use this file except in compliance with the +** License. You may obtain a copy of the License at: +** opensource.org/licenses/BSD-3-Clause +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM_D2) + LENGTH(RAM_D2); /* Use the otherwise wasted RAM_D2 region for stack */ + +/* Special value for CRT to prevent heap overflow into address space hole: + _sbrk assumes the RAM between _end and _estack is contiguous and prevents + heap overflowing into the stack by checking that the heap end pointer is + never going past (_estack - _Min_Stack_Size). + + By setting _Min_Stack_Size to this value, we ensure that _sbrk considers the + end of RAM_D1 as the heap's upper limit, preventing reserved memory space from + being used as heap memory improperly. +*/ +_Min_Stack_Size = _estack - (ORIGIN(RAM_D1) + LENGTH(RAM_D1)); +_Min_Heap_Size = 0x200; /* required amount of heap */ + + +/* Memories definition */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = LD_MAX_DATA_SIZE + RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K + RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K + +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM_D1 AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM_D1 + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; +/* . = . + _Min_Stack_Size; - stack is in a separate SRAM region, no need to check its size */ + . = ALIGN(8); + } >RAM_D1 + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From 332cdf04512c086718f4f04c4fe20808f33895ae Mon Sep 17 00:00:00 2001 From: Mathieu CHOPLAIN Date: Tue, 17 Oct 2023 18:13:35 +0200 Subject: [PATCH 16/83] variant(H7): add STM32H747I-DISCO support Signed-off-by: Mathieu Choplain --- README.md | 1 + boards.txt | 15 + .../CMakeLists.txt | 1 + .../PeripheralPins_DISCO_H747I.c | 781 ++++++++++++++++++ .../variant_STM32H747I_DISCO.cpp | 313 +++++++ .../variant_STM32H747I_DISCO.h | 357 ++++++++ 6 files changed, 1468 insertions(+) create mode 100644 variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins_DISCO_H747I.c create mode 100644 variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.cpp create mode 100644 variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h diff --git a/README.md b/README.md index 5b3ba3470e..d1534a8efa 100644 --- a/README.md +++ b/README.md @@ -172,6 +172,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32G031J6 | [STM32G0316-DISCO](https://www.st.com/en/evaluation-tools/stm32g0316-disco.html) | *1.9.0* | | | :green_heart: | STM32G431CB | [B-G431B-ESC1](https://www.st.com/en/evaluation-tools/b-g431b-esc1.html) | *2.0.0* | | | :green_heart: | STM32H573IIKxQ | [STM32H573I-DK](https://www.st.com/en/evaluation-tools/stm32h573i-dk.html) | *2.6.0* | | +| :yellow_heart: | STM32H747XIHx | [STM32H747I-DISCO](https://www.st.com/en/evaluation-tools/stm32h747i-disco.html) | **2.7.0** | | | :green_heart: | STM32L4S5VI | [B-L4S5I-IOT01A](https://www.st.com/en/evaluation-tools/b-l4s5i-iot01a.html) | *2.0.0* | | | :green_heart: | STM32U585AIIxQ | [B-U585I-IOT02A](https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html) | *2.1.0* | | | :green_heart: | STM32WB5MMG | [STM32WB5MM-DK](https://www.st.com/en/evaluation-tools/stm32wb5mm-dk.html) | *2.1.0* | | diff --git a/boards.txt b/boards.txt index 4fbe9e34c3..a4a192a0e3 100644 --- a/boards.txt +++ b/boards.txt @@ -1047,6 +1047,21 @@ Disco.menu.pnum.STM32H573I_DK.build.product_line=STM32H573xx Disco.menu.pnum.STM32H573I_DK.build.variant=STM32H5xx/H573IIKxQ Disco.menu.pnum.STM32H573I_DK.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS +# STM32H747I-DISCO +Disco.menu.pnum.STM32H747I_DISCO=STM32H747I-DISCO +Disco.menu.pnum.STM32H747I_DISCO.node=DIS_H747XI +Disco.menu.pnum.STM32H747I_DISCO.upload.maximum_size=2097152 +Disco.menu.pnum.STM32H747I_DISCO.upload.maximum_data_size=524288 +Disco.menu.pnum.STM32H747I_DISCO.build.mcu=cortex-m7 +Disco.menu.pnum.STM32H747I_DISCO.build.fpu=-mfpu=fpv4-sp-d16 +Disco.menu.pnum.STM32H747I_DISCO.build.float-abi=-mfloat-abi=hard +Disco.menu.pnum.STM32H747I_DISCO.build.board=STM32H747I_DISCO +Disco.menu.pnum.STM32H747I_DISCO.build.series=STM32H7xx +Disco.menu.pnum.STM32H747I_DISCO.build.product_line=STM32H747xx +Disco.menu.pnum.STM32H747I_DISCO.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH +Disco.menu.pnum.STM32H747I_DISCO.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -DCORE_CM7 +Disco.menu.pnum.STM32H747I_DISCO.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS + # STM32WB5MM-DK board Disco.menu.pnum.STM32WB5MM_DK=STM32WB5MM-DK Disco.menu.pnum.STM32WB5MM_DK.node="DIS_WB5MMG" diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt index 2a4d55b6b1..b9cca5b0a1 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_DISCO_H747I.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins_DISCO_H747I.c b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins_DISCO_H747I.c new file mode 100644 index 0000000000..b364cd946c --- /dev/null +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins_DISCO_H747I.c @@ -0,0 +1,781 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H742X(G-I)Hx.xml, STM32H743XGHx.xml + * STM32H743XIHx.xml, STM32H745XGHx.xml + * STM32H745XIHx.xml, STM32H747XGHx.xml + * STM32H747XIHx.xml, STM32H750XBHx.xml + * STM32H753XIHx.xml, STM32H755XIHx.xml + * STM32H757XIHx.xml + * CubeMX DB release 6.0.90 + */ +#if defined(ARDUINO_STM32H747I_DISCO) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 + {PA_0_C, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_C_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + // {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 + {PA_1_C, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_C_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + // {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + // {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + // {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + // {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + // {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + // {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + // {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + // {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + // {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + // {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + // {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + // {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + // {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + // {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + // {PC_0_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 + // {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + // {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + // {PC_1_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_2_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12 + {PC_2_C, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_3_C, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 + // {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + // {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + // {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + // {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + // {PF_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 + // {PF_4, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 + // {PF_5, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 + // {PF_6, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 + // {PF_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 + {PF_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 + // {PF_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 + {PF_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 + // {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + // {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + // {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + // {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + // {PH_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 + // {PH_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 + // {PH_4, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 + // {PH_5, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + // {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + // {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + // {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + // {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + // {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + // {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + // {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + // {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + // {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + // {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + // {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + // {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + // {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + // {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + // {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + // {PF_14, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + // {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + // {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + // {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_0_C, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_C_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + // {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + // {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + // {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_C, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_C_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_C_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + // {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + // {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + // {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + // {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + // {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + // {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + // {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + // {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + // {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + // {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + // {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + // {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + // {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + // {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + // {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + // {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + // {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + // {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + // {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + // {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + // {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + // {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + // {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + // {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + // {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + // {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + // {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + // {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + // {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + // {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + // {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + // {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + // {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + // {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + // {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + // {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + // {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + // {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + // {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + // {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + // {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + // {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + // {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + // {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + // {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + // {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + // {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + // {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + // {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + // {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + // {PH_6, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + // {PH_9, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + // {PH_10, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + // {PH_11, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + // {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + // {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + // {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + // {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + // {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + // {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + // {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + // {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + // {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PJ_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PJ_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PJ_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PJ_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PJ_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PJ_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PJ_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PJ_11_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PK_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PK_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PK_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PK_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_0_C, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + // {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + // {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + // {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + // {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + // {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + // {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + // {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + // {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + // {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + // {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + // {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_8, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + // {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_1_C, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + // {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + // {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + // {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + // {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + // {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + // {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + // {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + // {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + // {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PI_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_9, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + // {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_1_C, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + // {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + // {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + // {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + // {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_0_C, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + // {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + // {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + // {PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + // {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + // {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + // {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + // {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3_C, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + // {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + // {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + // {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + // {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PJ_10, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + // {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2_C, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + // {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + // {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + // {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PJ_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + // {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + // {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + // {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + // {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PK_0, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + // {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + // {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + // {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + // {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + // {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PK_1, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + // {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + // {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + // {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + // {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + // {PI_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + // {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + // {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + // {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + // {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED) +WEAK const PinMap PinMap_Ethernet[] = { + // {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + // {PA_0_C, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + // {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + // {PA_1_C, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + // {PA_1_C_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + // {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + // {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + // {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + // {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + // {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + // {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + // {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + // {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + // {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + // {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + // {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + // {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + // {PC_2_C, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + // {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + // {PC_3_C, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + // {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + // {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + // {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + // {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + // {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + // {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + // {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + // {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {NC, NP, 0} +}; +#endif + +//*** QUADSPI *** + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA0[] = { + // {PC_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PD_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + // {PE_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 + // {PF_8, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {PH_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA1[] = { + // {PC_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + // {PD_12, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + // {PE_8, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 + {PF_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {PH_3, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA2[] = { + // {PE_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + // {PE_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 + {PF_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {PG_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA3[] = { + // {PA_1, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + // {PA_1_C, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + // {PD_13, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + // {PE_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 + {PF_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PG_14, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_SCLK[] = { + {PB_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + // {PF_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_SSEL[] = { + // {PB_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + // {PB_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS + // {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS + {PG_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_FS[] = { + // {PA_8, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF + // {PA_9, USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS + // {PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID + // {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM + // {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP + {NC, NP, 0} +}; + +#ifndef USE_USB_HS + #error USB speed cannot be "Low/Full Speed" on this board +#endif + +#endif + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_HS[] = { +#ifdef USE_USB_HS_IN_FS +#error USB speed cannot be "High Speed in Full Speed mode" on this board + // {PA_4, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF + // {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID + // {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + // {PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM + // {PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP +#else + {PA_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP + // {PC_2, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR + // {PC_2_C, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR + // {PC_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT + // {PC_3_C, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT + {PH_4, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT + {PI_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR +#endif /* USE_USB_HS_IN_FS */ + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO1)}, // SDMMC1_CMD + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDIO2)}, // SDMMC2_CMD + {PA_0_C, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDIO2)}, // SDMMC2_CMD + // {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDIO2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + // {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDIO2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDIO2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D0 + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + // {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + // {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D2 + // {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + // {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + // {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D4 + // {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + // {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D5 + // {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + // {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D6 + // {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + // {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D7 + // {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + // {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDIO1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + // {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDIO1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + // {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDIO1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + // {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDIO1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* ARDUINO_STM32H747I_DISCO */ diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.cpp b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.cpp new file mode 100644 index 0000000000..8bcaf7fcc5 --- /dev/null +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.cpp @@ -0,0 +1,313 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_STM32H747I_DISCO) +#include "pins_arduino.h" + +//Digital pin number mapping array +const PinName digitalPin[] = { + PJ_9, + PJ_8, + PJ_3, + PF_8, + PJ_4, + PA_6, + PJ_7, + PJ_0, + PJ_5, + PJ_6, + PK_1, + PJ_10, + PJ_11, + PK_0, + PD_13, + PD_12, + PA_4, + PF_10, + PA_0_C, + PA_1_C, + PC_2_C, + PC_3_C, + PI_12, + PI_13, + PI_14, + PI_15, + PA_10, + PA_9, + PA_11, + PA_12, + PC_2, + PC_3, + PK_2, + PK_3, + PK_4, + PK_5, + PK_6, + PC_13, + PB_2, + PG_6, + PD_11, + PF_9, + PF_7, + PF_6, + PH_2, + PH_3, + PG_9, + PG_14, + PC_8, + PC_9, + PC_10, + PC_11, + PC_12, + PD_2, + PI_8, + PG_10, + PB_7, + PJ_14, + PA_5, + PA_3, + PB_0, + PB_1, + PB_10, + PB_11, + PB_12, + PB_13, + PB_5, + PC_0, + PH_4, + PI_11, + PJ_1, + PD_7, + PE_3, + PE_4, + PE_5, + PE_6, + PG_7, + PC_1, + PE_2, + PJ_15, + PA_0, + PD_5, + PD_6, + PD_4, + PB_15, + PB_14, + PC_6, + PJ_13, + PC_7, + PD_3, + PB_9, + PB_8, + PH_0, + PH_1, + PC_14, + PC_15, + PA_8, + PJ_12, + PG_3, + PJ_2, + PB_6, + PK_7, + PE_0, + PE_1, + PI_4, + PI_5, + PG_8, + PH_5, + PH_6, + PH_7, + PF_11, + PG_15, + PD_14, + PD_15, + PD_0, + PD_1, + PE_7, + PE_8, + PE_9, + PE_10, + PE_11, + PE_12, + PE_13, + PE_14, + PE_15, + PD_8, + PD_9, + PD_10, + PH_8, + PH_9, + PH_10, + PH_11, + PH_12, + PH_13, + PH_14, + PH_15, + PI_0, + PI_1, + PI_2, + PI_3, + PI_6, + PI_7, + PI_9, + PI_10, + PF_0, + PF_1, + PF_2, + PF_3, + PF_4, + PF_5, + PF_12, + PF_13, + PF_14, + PF_15, + PG_0, + PG_1, + PG_2, + PG_4, + PG_5, + PA_13, + PA_14, + PA_15, + PB_3, + PB_4, + PA_1, + PA_2, + PA_7, + PC_4, + PC_5, + PG_11, + PG_12, + PG_13 +}; + +// Analog (Ax) pin number mapping array +const uint32_t analogInputPin[] = { + 16, //A0 + 17, //A1 + 18, //A2 + 19, //A3 + 20, //A4 + 21 //A5 +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_CSI + | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE + | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; + RCC_OscInitStruct.PLL.PLLN = 192; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 6; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /** Initializes the peripherals clock + */ + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_CKPER + | RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_I2C123 | RCC_PERIPHCLK_I2C4 + | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM3 + | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_USB + | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 + | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_FMC; + PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP; + PeriphClkInitStruct.CecClockSelection = RCC_CECCLKSOURCE_CSI; + PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; + PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK; + PeriphClkInitStruct.Hrtim1ClockSelection = RCC_HRTIM1CLK_CPUCLK; + PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.Lptim2ClockSelection = RCC_LPTIM2CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.Lptim345ClockSelection = RCC_LPTIM345CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_D3PCLK1; + PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* ARDUINO_STM32H747I_DISCO */ diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h new file mode 100644 index 0000000000..43c21a3f4e --- /dev/null +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h @@ -0,0 +1,357 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PJ9 0 // UART8_RX +#define PJ8 1 // UART8_TX +#define PJ3 2 +#define PF8 3 // S_TIM13_CH1 / PMOD #14 +#define PJ4 4 +#define PA6 5 // DCMI_PIXCK +#define PJ7 6 // TIM8_CH2N +#define PJ0 7 +#define PJ5 8 +#define PJ6 9 // S_TIM8_CH2 +#define PK1 10 // SPI5_NSS +#define PJ10 11 // SPI5_MOSI +#define PJ11 12 // SPI5_MISO +#define PK0 13 // SPI5_SCK +#define PD13 14 // I2C4_SDA / PMOD #10 +#define PD12 15 // I2C4_SCL / PMOD #7 +#define PA4 PIN_A0 // Pin 16 - ADC12_INP18 / DCMI_HSYNC / PMOD #13 +#define PF10 PIN_A1 // Pin 17 - ADC3_INP6 +#define PA0_C PIN_A2 // Pin 18 - ADC12_INP0 +#define PA1_C PIN_A3 // Pin 19 - ADC12_INP1 +#define PC2_C PIN_A4 // Pin 20 - ADC3_INP0 +#define PC3_C PIN_A5 // Pin 21 - ADC3_INP1 + +// User LEDs +#define PI12 22 // LED1 +#define PI13 23 // LED2 +#define PI14 24 // LED3 +#define PI15 25 // LED4 + +// ST-Link UART +#define PA10 26 // USART1_RX / ST-Link Tx +#define PA9 27 // USART1_TX / ST-Link Rx + +// SPI +#define PA11 28 // SPI2_NSS / PMOD #1 NSS +#define PA12 29 // SPI2_SCK / PMOD #4 SCK +#define PC2 30 // SPI2_MISO / PMOD #3 MISOp +#define PC3 31 // SPI2_MOSI / PMOD #2 MOSIp + +// GPIO Buttons +#define PK2 32 // JOY_SEL +#define PK3 33 // JOY_DOWN +#define PK4 34 // JOY_LEFT +#define PK5 35 // JOY_RIGHT +#define PK6 36 // JOY_UP +#define PC13 37 // Wakeup Button / RTC_TAMP1 + +// QuadSPI +#define PB2 38 // QUADSPI_CLK +#define PG6 39 // QUADSPI_BK1_NCS +#define PD11 40 // QUADSPI_BK1_IO0 +#define PF9 41 // QUADSPI_BK1_IO1 +#define PF7 42 // QUADSPI_BK1_IO2 +#define PF6 43 // QUADSPI_BK1_IO3 +#define PH2 44 // QUADSPI_BK2_IO0 +#define PH3 45 // QUADSPI_BK2_IO1 +#define PG9 46 // QUADSPI_BK2_IO2 +#define PG14 47 // QUADSPI_BK2_IO3 + +// SDIO/SDMMC +#define PC8 48 // SDMMC1_D0 / SDIO1_D0 +#define PC9 49 // SDMMC1_D1 / SDIO1_D1 / DCMI_D3 +#define PC10 50 // SDMMC1_D2 / SDIO1_D2 +#define PC11 51 // SDMMC1_D3 / SDIO1_D3 / DCMI_D4 +#define PC12 52 // SDMMC1_CK / SDIO1_CK +#define PD2 53 // SDMMC1_CMD / SDIO1_CMD +#define PI8 54 // uSD_Detect + +// Digital Camera Interface +#define PG10 55 // DCMI_D2 +#define PB7 56 // DCMI_VSYNC +#define PJ14 57 // DCMI_PWR_EN + +// USB +#define PA5 58 // USB_OTG_HS_ULPI_CK +#define PA3 59 // USB_OTG_HS_ULPI_D0 +#define PB0 60 // USB_OTG_HS_ULPI_D1 +#define PB1 61 // USB_OTG_HS_ULPI_D2 +#define PB10 62 // USB_OTG_HS_ULPI_D3 +#define PB11 63 // USB_OTG_HS_ULPI_D4 +#define PB12 64 // USB_OTG_HS_ULPI_D5 +#define PB13 65 // USB_OTG_HS_ULPI_D6 +#define PB5 66 // USB_OTG_HS_ULPI_D7 +#define PC0 67 // USB_OTG_HS_ULPI_STP +#define PH4 68 // USB_OTG_HS_ULPI_NXT +#define PI11 69 // USB_OTG_HS_ULPI_DIR +#define PJ1 70 // OTG_HS_OverCurrent + +// Audio +#define PD7 71 // SPDIF_RX0 +#define PE3 72 // SAI1_SD_B +#define PE4 73 // SAI1_FS_A +#define PE5 74 // SAI1_SCK_A +#define PE6 75 // SAI1_SD_A +#define PG7 76 // SAI1_MCLK_A +#define PC1 77 // SAI4_D1 / ETH_MDC +#define PE2 78 // SAI4_CK1 / ETH_nINT +#define PJ15 79 // Audio_INT (Audio Codec IRQ) + +// Pmod™ +#define PA0 80 // PMOD #1 CTS +#define PD5 81 // PMOD #2 TX +#define PD6 82 // PMOD #3 RX +#define PD4 83 // PMOD #4 RTS +#define PB15 84 // PMOD #8 +#define PB14 85 // PMOD #9 +#define PC6 86 // PMOD #11 / DCMI_D0 +#define PJ13 87 // PMOD #12 +#define PC7 88 // PMOD #17 / DCMI_D1 +#define PD3 89 // PMOD #18 / DCMI_D5 +#define PB9 90 // PMOD #19 +#define PB8 91 // PMOD #20 + +// Clock outputs +#define PH0 92 // RCC_OSC_IN +#define PH1 93 // RCC_OSC_OUT +#define PC14 94 // RCC_OSC32_IN +#define PC15 95 // RCC_OSC32_OUT +#define PA8 96 // CEC_CK / RCC_MCO_1 + +// LCD/DSI +#define PJ12 97 // LCD_BL_CTRL +#define PG3 98 // DSI_Reset +#define PJ2 99 // DSI_TE +#define PB6 100 // HDMI_CEC + +// Touch Screen Controller +#define PK7 101 // TOUCH_INT + +// Flash Memory Controller +#define PE0 102 // FMC_NBL0 +#define PE1 103 // FMC_NBL1 +#define PI4 104 // FMC_NBL2 +#define PI5 105 // FMC_NBL3 +#define PG8 106 // FMC_SDCLK +#define PH5 107 // FMC_SDNWE +#define PH6 108 // FMC_SDNE1 +#define PH7 109 // FMC_SDCKE1 +#define PF11 110 // FMC_SDNRAS +#define PG15 111 // FMC_SDNCAS +#define PD14 112 // FMC_D0 +#define PD15 113 // FMC_D1 +#define PD0 114 // FMC_D2 +#define PD1 115 // FMC_D3 +#define PE7 116 // FMC_D4 +#define PE8 117 // FMC_D5 +#define PE9 118 // FMC_D6 +#define PE10 119 // FMC_D7 +#define PE11 120 // FMC_D8 +#define PE12 121 // FMC_D9 +#define PE13 122 // FMC_D10 +#define PE14 123 // FMC_D11 +#define PE15 124 // FMC_D12 +#define PD8 125 // FMC_D13 +#define PD9 126 // FMC_D14 +#define PD10 127 // FMC_D15 +#define PH8 128 // FMC_D16 +#define PH9 129 // FMC_D17 +#define PH10 130 // FMC_D18 +#define PH11 131 // FMC_D19 +#define PH12 132 // FMC_D20 +#define PH13 133 // FMC_D21 +#define PH14 134 // FMC_D22 +#define PH15 135 // FMC_D23 +#define PI0 136 // FMC_D24 +#define PI1 137 // FMC_D25 +#define PI2 138 // FMC_D26 +#define PI3 139 // FMC_D27 +#define PI6 140 // FMC_D28 +#define PI7 141 // FMC_D29 +#define PI9 142 // FMC_D30 +#define PI10 143 // FMC_D31 +#define PF0 144 // FMC_A0 +#define PF1 145 // FMC_A1 +#define PF2 146 // FMC_A2 +#define PF3 147 // FMC_A3 +#define PF4 148 // FMC_A4 +#define PF5 149 // FMC_A5 +#define PF12 150 // FMC_A6 +#define PF13 151 // FMC_A7 +#define PF14 152 // FMC_A8 +#define PF15 153 // FMC_A9 +#define PG0 154 // FMC_A10 +#define PG1 155 // FMC_A11 +#define PG2 156 // FMC_A12 +// FMC_A13 does not exist +#define PG4 157 // FMC_A14 +#define PG5 158 // FMC A15 + +// JTAG/SWD +#define PA13 159 // TMS / SWDIO +#define PA14 160 // TCK / SWCLK +#define PA15 161 // TDI +#define PB3 162 // TDO / SWO +#define PB4 163 // TRST + +/* WARNING: Ethernet is unusable by default on the board */ +// Ethernet port +#define PA1 164 // ETH_REF_CLK +#define PA2 165 // ETH_MDIO +#define PA7 166 // ETH_CRS_DV +#define PC4 167 // ETH_RXD0 +#define PC5 168 // ETH_RXD1 +#define PG11 169 // ETH_TX_EN +#define PG12 170 // ETH_TXD1 +#define PG13 171 // ETH_TXD0 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_C_ALT1 (PA0_C | ALT1) +#define PA1_C_ALT1 (PA1_C | ALT1) +#define PA1_C_ALT2 (PA1_C | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA9_ALT (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC2_ALT1 (PC2 | ALT1) +#define PC2_ALT2 (PC2 | ALT2) +#define PC3_ALT1 (PC3 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PJ8_ALT1 (PJ8 | ALT1) +#define PJ9_ALT1 (PJ9 | ALT1) +#define PJ10_ALT1 (PJ10 | ALT1) +#define PJ11_ALT1 (PJ11 | ALT1) +#define PK0_ALT1 (PK0 | ALT1) +#define PK1_ALT1 (PK1 | ALT1) + +#define NUM_DIGITAL_PINS 172 +#define NUM_DUALPAD_PINS 4 +#define NUM_ANALOG_INPUTS 6 + +// On-board LED pin number +#define LED_GREEN PI12 //LED1 +#define LED_ORANGE PI13 //LED2 +#define LED_RED PI14 //LED3 +#define LED_BLUE PI15 //LED4 + +#ifndef LED_BUILTIN + #define LED_BUILTIN LED_GREEN +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 //Wakeup button +#endif + +// SPI Definitions are provided by "pins_arduino.h" +// I2C definitions are provided by "pins_arduino.h" + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 //LPUART1 is connected to ST-Link +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// Default pin used for generic 'Serial' instance (wired to ST-Link) +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA10 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA9 +#endif + +// SDMMC signals - only define not available, +// the rest is automatically provided by PeripheralPins +#define SDMMC_CKIN_NA +#define SDMMC_CDIR_NA +#define SDMMC_D0DIR_NA +#define SDMMC_D123DIR_NA + +// SD detect signal +#ifndef SD_DETECT_PIN + #define SD_DETECT_PIN PI8 +#endif + +// HAL configuration +#define HSE_VALUE 25000000U + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_QSPI_MODULE_DISABLED) + #define HAL_QSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 384ee0039f6c818ee9e37cc19ce5a8911b46ef13 Mon Sep 17 00:00:00 2001 From: Mathieu Choplain Date: Mon, 30 Oct 2023 15:20:20 +0100 Subject: [PATCH 17/83] chore(cmake): update files Signed-off-by: Mathieu Choplain --- cmake/boards_db.cmake | 1530 +++++++++++++++++ .../CMakeLists.txt | 3 +- .../CMakeLists.txt | 2 + 3 files changed, 1534 insertions(+), 1 deletion(-) diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index bfa15ec206..efb6d9af9b 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -4786,6 +4786,60 @@ target_compile_options(DevEBoxH750VBTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# DEVKIT_IOT_CONTINUUM +# ----------------------------------------------------------------------------- + +set(DEVKIT_IOT_CONTINUUM_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)") +set(DEVKIT_IOT_CONTINUUM_MAXSIZE 2097152) +set(DEVKIT_IOT_CONTINUUM_MAXDATASIZE 786432) +set(DEVKIT_IOT_CONTINUUM_MCU cortex-m33) +set(DEVKIT_IOT_CONTINUUM_FPCONF "fpv4-sp-d16-hard") +add_library(DEVKIT_IOT_CONTINUUM INTERFACE) +target_compile_options(DEVKIT_IOT_CONTINUUM INTERFACE + "SHELL:-DSTM32U585xx " + "SHELL:-DCUSTOM_PERIPHERAL_PINS" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${DEVKIT_IOT_CONTINUUM_MCU} +) +target_compile_definitions(DEVKIT_IOT_CONTINUUM INTERFACE + "STM32U5xx" + "ARDUINO_DEVKIT_IOT_CONTINUUM" + "BOARD_NAME=\"DEVKIT_IOT_CONTINUUM\"" + "BOARD_ID=DEVKIT_IOT_CONTINUUM" + "VARIANT_H=\"variant_DEVKIT_IOT_CONTINUUM.h\"" +) +target_include_directories(DEVKIT_IOT_CONTINUUM INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ + ${DEVKIT_IOT_CONTINUUM_VARIANT_PATH} +) + +target_link_options(DEVKIT_IOT_CONTINUUM INTERFACE + "LINKER:--default-script=${DEVKIT_IOT_CONTINUUM_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=786432" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${DEVKIT_IOT_CONTINUUM_MCU} +) + +add_library(DEVKIT_IOT_CONTINUUM_serial_disabled INTERFACE) +target_compile_options(DEVKIT_IOT_CONTINUUM_serial_disabled INTERFACE + "SHELL:" +) +add_library(DEVKIT_IOT_CONTINUUM_serial_generic INTERFACE) +target_compile_options(DEVKIT_IOT_CONTINUUM_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(DEVKIT_IOT_CONTINUUM_serial_none INTERFACE) +target_compile_options(DEVKIT_IOT_CONTINUUM_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + # DISCO_F030R8 # ----------------------------------------------------------------------------- @@ -73450,6 +73504,170 @@ target_compile_options(GENERIC_H742VITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H742XGHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H742XGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H742XGHX_MAXSIZE 1048576) +set(GENERIC_H742XGHX_MAXDATASIZE 524288) +set(GENERIC_H742XGHX_MCU cortex-m7) +set(GENERIC_H742XGHX_FPCONF "-") +add_library(GENERIC_H742XGHX INTERFACE) +target_compile_options(GENERIC_H742XGHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H742xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H742XGHX_MCU} +) +target_compile_definitions(GENERIC_H742XGHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H742XGHX" + "BOARD_NAME=\"GENERIC_H742XGHX\"" + "BOARD_ID=GENERIC_H742XGHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H742XGHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H742XGHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H742XGHX INTERFACE + "LINKER:--default-script=${GENERIC_H742XGHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H742XGHX_MCU} +) + +add_library(GENERIC_H742XGHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H742XGHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H742XGHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H742XGHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H742XGHX_serial_none INTERFACE) +target_compile_options(GENERIC_H742XGHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H742XGHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H742XGHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H742XGHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H742XGHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H742XGHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H742XGHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H742XGHX_usb_none INTERFACE) +target_compile_options(GENERIC_H742XGHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H742XGHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H742XGHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H742XGHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H742XGHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H742XGHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H742XGHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H742XIHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H742XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H742XIHX_MAXSIZE 2097152) +set(GENERIC_H742XIHX_MAXDATASIZE 524288) +set(GENERIC_H742XIHX_MCU cortex-m7) +set(GENERIC_H742XIHX_FPCONF "-") +add_library(GENERIC_H742XIHX INTERFACE) +target_compile_options(GENERIC_H742XIHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H742xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H742XIHX_MCU} +) +target_compile_definitions(GENERIC_H742XIHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H742XIHX" + "BOARD_NAME=\"GENERIC_H742XIHX\"" + "BOARD_ID=GENERIC_H742XIHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H742XIHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H742XIHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H742XIHX INTERFACE + "LINKER:--default-script=${GENERIC_H742XIHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H742XIHX_MCU} +) + +add_library(GENERIC_H742XIHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H742XIHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H742XIHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H742XIHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H742XIHX_serial_none INTERFACE) +target_compile_options(GENERIC_H742XIHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H742XIHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H742XIHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H742XIHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H742XIHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H742XIHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H742XIHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H742XIHX_usb_none INTERFACE) +target_compile_options(GENERIC_H742XIHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H742XIHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H742XIHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H742XIHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H742XIHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H742XIHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H742XIHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H742ZGTX # ----------------------------------------------------------------------------- @@ -74270,6 +74488,170 @@ target_compile_options(GENERIC_H743VITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H743XGHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H743XGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H743XGHX_MAXSIZE 1048576) +set(GENERIC_H743XGHX_MAXDATASIZE 524288) +set(GENERIC_H743XGHX_MCU cortex-m7) +set(GENERIC_H743XGHX_FPCONF "-") +add_library(GENERIC_H743XGHX INTERFACE) +target_compile_options(GENERIC_H743XGHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H743xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H743XGHX_MCU} +) +target_compile_definitions(GENERIC_H743XGHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H743XGHX" + "BOARD_NAME=\"GENERIC_H743XGHX\"" + "BOARD_ID=GENERIC_H743XGHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H743XGHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H743XGHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H743XGHX INTERFACE + "LINKER:--default-script=${GENERIC_H743XGHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H743XGHX_MCU} +) + +add_library(GENERIC_H743XGHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H743XGHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H743XGHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H743XGHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H743XGHX_serial_none INTERFACE) +target_compile_options(GENERIC_H743XGHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H743XGHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H743XGHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H743XGHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H743XGHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H743XGHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H743XGHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H743XGHX_usb_none INTERFACE) +target_compile_options(GENERIC_H743XGHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H743XGHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H743XGHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H743XGHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H743XGHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H743XGHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H743XGHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H743XIHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H743XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H743XIHX_MAXSIZE 2097152) +set(GENERIC_H743XIHX_MAXDATASIZE 524288) +set(GENERIC_H743XIHX_MCU cortex-m7) +set(GENERIC_H743XIHX_FPCONF "-") +add_library(GENERIC_H743XIHX INTERFACE) +target_compile_options(GENERIC_H743XIHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H743xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H743XIHX_MCU} +) +target_compile_definitions(GENERIC_H743XIHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H743XIHX" + "BOARD_NAME=\"GENERIC_H743XIHX\"" + "BOARD_ID=GENERIC_H743XIHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H743XIHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H743XIHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H743XIHX INTERFACE + "LINKER:--default-script=${GENERIC_H743XIHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H743XIHX_MCU} +) + +add_library(GENERIC_H743XIHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H743XIHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H743XIHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H743XIHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H743XIHX_serial_none INTERFACE) +target_compile_options(GENERIC_H743XIHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H743XIHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H743XIHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H743XIHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H743XIHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H743XIHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H743XIHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H743XIHX_usb_none INTERFACE) +target_compile_options(GENERIC_H743XIHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H743XIHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H743XIHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H743XIHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H743XIHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H743XIHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H743XIHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H743ZGTX # ----------------------------------------------------------------------------- @@ -74434,6 +74816,170 @@ target_compile_options(GENERIC_H743ZITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H745XGHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H745XGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H745XGHX_MAXSIZE 1048576) +set(GENERIC_H745XGHX_MAXDATASIZE 524288) +set(GENERIC_H745XGHX_MCU cortex-m7) +set(GENERIC_H745XGHX_FPCONF "-") +add_library(GENERIC_H745XGHX INTERFACE) +target_compile_options(GENERIC_H745XGHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H745xG " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H745XGHX_MCU} +) +target_compile_definitions(GENERIC_H745XGHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H745XGHX" + "BOARD_NAME=\"GENERIC_H745XGHX\"" + "BOARD_ID=GENERIC_H745XGHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H745XGHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H745XGHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H745XGHX INTERFACE + "LINKER:--default-script=${GENERIC_H745XGHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H745XGHX_MCU} +) + +add_library(GENERIC_H745XGHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H745XGHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H745XGHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H745XGHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H745XGHX_serial_none INTERFACE) +target_compile_options(GENERIC_H745XGHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H745XGHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H745XGHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H745XGHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H745XGHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H745XGHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H745XGHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H745XGHX_usb_none INTERFACE) +target_compile_options(GENERIC_H745XGHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H745XGHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H745XGHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H745XGHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H745XGHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H745XGHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H745XGHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H745XIHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H745XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H745XIHX_MAXSIZE 2097152) +set(GENERIC_H745XIHX_MAXDATASIZE 524288) +set(GENERIC_H745XIHX_MCU cortex-m7) +set(GENERIC_H745XIHX_FPCONF "-") +add_library(GENERIC_H745XIHX INTERFACE) +target_compile_options(GENERIC_H745XIHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H745xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H745XIHX_MCU} +) +target_compile_definitions(GENERIC_H745XIHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H745XIHX" + "BOARD_NAME=\"GENERIC_H745XIHX\"" + "BOARD_ID=GENERIC_H745XIHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H745XIHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H745XIHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H745XIHX INTERFACE + "LINKER:--default-script=${GENERIC_H745XIHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H745XIHX_MCU} +) + +add_library(GENERIC_H745XIHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H745XIHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H745XIHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H745XIHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H745XIHX_serial_none INTERFACE) +target_compile_options(GENERIC_H745XIHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H745XIHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H745XIHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H745XIHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H745XIHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H745XIHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H745XIHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H745XIHX_usb_none INTERFACE) +target_compile_options(GENERIC_H745XIHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H745XIHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H745XIHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H745XIHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H745XIHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H745XIHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H745XIHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H747AGIX # ----------------------------------------------------------------------------- @@ -74762,6 +75308,170 @@ target_compile_options(GENERIC_H747IITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H747XGHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H747XGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H747XGHX_MAXSIZE 1048576) +set(GENERIC_H747XGHX_MAXDATASIZE 524288) +set(GENERIC_H747XGHX_MCU cortex-m7) +set(GENERIC_H747XGHX_FPCONF "-") +add_library(GENERIC_H747XGHX INTERFACE) +target_compile_options(GENERIC_H747XGHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H747xG " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H747XGHX_MCU} +) +target_compile_definitions(GENERIC_H747XGHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H747XGHX" + "BOARD_NAME=\"GENERIC_H747XGHX\"" + "BOARD_ID=GENERIC_H747XGHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H747XGHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H747XGHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H747XGHX INTERFACE + "LINKER:--default-script=${GENERIC_H747XGHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H747XGHX_MCU} +) + +add_library(GENERIC_H747XGHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H747XGHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H747XGHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H747XGHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H747XGHX_serial_none INTERFACE) +target_compile_options(GENERIC_H747XGHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H747XGHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H747XGHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H747XGHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H747XGHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H747XGHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H747XGHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H747XGHX_usb_none INTERFACE) +target_compile_options(GENERIC_H747XGHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H747XGHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H747XGHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H747XGHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H747XGHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H747XGHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H747XGHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H747XIHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H747XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H747XIHX_MAXSIZE 2097152) +set(GENERIC_H747XIHX_MAXDATASIZE 524288) +set(GENERIC_H747XIHX_MCU cortex-m7) +set(GENERIC_H747XIHX_FPCONF "-") +add_library(GENERIC_H747XIHX INTERFACE) +target_compile_options(GENERIC_H747XIHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H747xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H747XIHX_MCU} +) +target_compile_definitions(GENERIC_H747XIHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H747XIHX" + "BOARD_NAME=\"GENERIC_H747XIHX\"" + "BOARD_ID=GENERIC_H747XIHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H747XIHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H747XIHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H747XIHX INTERFACE + "LINKER:--default-script=${GENERIC_H747XIHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H747XIHX_MCU} +) + +add_library(GENERIC_H747XIHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H747XIHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H747XIHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H747XIHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H747XIHX_serial_none INTERFACE) +target_compile_options(GENERIC_H747XIHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H747XIHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H747XIHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H747XIHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H747XIHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H747XIHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H747XIHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H747XIHX_usb_none INTERFACE) +target_compile_options(GENERIC_H747XIHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H747XIHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H747XIHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H747XIHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H747XIHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H747XIHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H747XIHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H750IBKX # ----------------------------------------------------------------------------- @@ -75008,6 +75718,88 @@ target_compile_options(GENERIC_H750VBTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H750XBHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H750XBHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H750XBHX_MAXSIZE 131072) +set(GENERIC_H750XBHX_MAXDATASIZE 524288) +set(GENERIC_H750XBHX_MCU cortex-m7) +set(GENERIC_H750XBHX_FPCONF "-") +add_library(GENERIC_H750XBHX INTERFACE) +target_compile_options(GENERIC_H750XBHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H750xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H750XBHX_MCU} +) +target_compile_definitions(GENERIC_H750XBHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H750XBHX" + "BOARD_NAME=\"GENERIC_H750XBHX\"" + "BOARD_ID=GENERIC_H750XBHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H750XBHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H750XBHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H750XBHX INTERFACE + "LINKER:--default-script=${GENERIC_H750XBHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H750XBHX_MCU} +) + +add_library(GENERIC_H750XBHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H750XBHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H750XBHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H750XBHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H750XBHX_serial_none INTERFACE) +target_compile_options(GENERIC_H750XBHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H750XBHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H750XBHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H750XBHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H750XBHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H750XBHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H750XBHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H750XBHX_usb_none INTERFACE) +target_compile_options(GENERIC_H750XBHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H750XBHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H750XBHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H750XBHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H750XBHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H750XBHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H750XBHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H750ZBTX # ----------------------------------------------------------------------------- @@ -75418,6 +76210,88 @@ target_compile_options(GENERIC_H753VITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H753XIHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H753XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H753XIHX_MAXSIZE 2097152) +set(GENERIC_H753XIHX_MAXDATASIZE 524288) +set(GENERIC_H753XIHX_MCU cortex-m7) +set(GENERIC_H753XIHX_FPCONF "-") +add_library(GENERIC_H753XIHX INTERFACE) +target_compile_options(GENERIC_H753XIHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H753xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H753XIHX_MCU} +) +target_compile_definitions(GENERIC_H753XIHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H753XIHX" + "BOARD_NAME=\"GENERIC_H753XIHX\"" + "BOARD_ID=GENERIC_H753XIHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H753XIHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H753XIHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H753XIHX INTERFACE + "LINKER:--default-script=${GENERIC_H753XIHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H753XIHX_MCU} +) + +add_library(GENERIC_H753XIHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H753XIHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H753XIHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H753XIHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H753XIHX_serial_none INTERFACE) +target_compile_options(GENERIC_H753XIHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H753XIHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H753XIHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H753XIHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H753XIHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H753XIHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H753XIHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H753XIHX_usb_none INTERFACE) +target_compile_options(GENERIC_H753XIHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H753XIHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H753XIHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H753XIHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H753XIHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H753XIHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H753XIHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H753ZITX # ----------------------------------------------------------------------------- @@ -75500,6 +76374,88 @@ target_compile_options(GENERIC_H753ZITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H755XIHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H755XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H755XIHX_MAXSIZE 2097152) +set(GENERIC_H755XIHX_MAXDATASIZE 524288) +set(GENERIC_H755XIHX_MCU cortex-m7) +set(GENERIC_H755XIHX_FPCONF "-") +add_library(GENERIC_H755XIHX INTERFACE) +target_compile_options(GENERIC_H755XIHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H755xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H755XIHX_MCU} +) +target_compile_definitions(GENERIC_H755XIHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H755XIHX" + "BOARD_NAME=\"GENERIC_H755XIHX\"" + "BOARD_ID=GENERIC_H755XIHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H755XIHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H755XIHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H755XIHX INTERFACE + "LINKER:--default-script=${GENERIC_H755XIHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H755XIHX_MCU} +) + +add_library(GENERIC_H755XIHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H755XIHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H755XIHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H755XIHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H755XIHX_serial_none INTERFACE) +target_compile_options(GENERIC_H755XIHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H755XIHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H755XIHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H755XIHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H755XIHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H755XIHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H755XIHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H755XIHX_usb_none INTERFACE) +target_compile_options(GENERIC_H755XIHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H755XIHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H755XIHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H755XIHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H755XIHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H755XIHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H755XIHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H757AIIX # ----------------------------------------------------------------------------- @@ -75664,6 +76620,88 @@ target_compile_options(GENERIC_H757IITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H757XIHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H757XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(GENERIC_H757XIHX_MAXSIZE 2097152) +set(GENERIC_H757XIHX_MAXDATASIZE 524288) +set(GENERIC_H757XIHX_MCU cortex-m7) +set(GENERIC_H757XIHX_FPCONF "-") +add_library(GENERIC_H757XIHX INTERFACE) +target_compile_options(GENERIC_H757XIHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H757xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H757XIHX_MCU} +) +target_compile_definitions(GENERIC_H757XIHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H757XIHX" + "BOARD_NAME=\"GENERIC_H757XIHX\"" + "BOARD_ID=GENERIC_H757XIHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H757XIHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H757XIHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H757XIHX INTERFACE + "LINKER:--default-script=${GENERIC_H757XIHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H757XIHX_MCU} +) + +add_library(GENERIC_H757XIHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H757XIHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H757XIHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H757XIHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H757XIHX_serial_none INTERFACE) +target_compile_options(GENERIC_H757XIHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H757XIHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H757XIHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H757XIHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H757XIHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H757XIHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H757XIHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H757XIHX_usb_none INTERFACE) +target_compile_options(GENERIC_H757XIHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H757XIHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H757XIHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H757XIHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H757XIHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H757XIHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H757XIHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_L010C6TX # ----------------------------------------------------------------------------- @@ -94168,6 +95206,170 @@ target_compile_options(GENERIC_U575AIIXQ_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_U575CITX +# ----------------------------------------------------------------------------- + +set(GENERIC_U575CITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)") +set(GENERIC_U575CITX_MAXSIZE 2097152) +set(GENERIC_U575CITX_MAXDATASIZE 786432) +set(GENERIC_U575CITX_MCU cortex-m33) +set(GENERIC_U575CITX_FPCONF "-") +add_library(GENERIC_U575CITX INTERFACE) +target_compile_options(GENERIC_U575CITX INTERFACE + "SHELL:-DSTM32U575xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_U575CITX_MCU} +) +target_compile_definitions(GENERIC_U575CITX INTERFACE + "STM32U5xx" + "ARDUINO_GENERIC_U575CITX" + "BOARD_NAME=\"GENERIC_U575CITX\"" + "BOARD_ID=GENERIC_U575CITX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U575CITX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ + ${GENERIC_U575CITX_VARIANT_PATH} +) + +target_link_options(GENERIC_U575CITX INTERFACE + "LINKER:--default-script=${GENERIC_U575CITX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=786432" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_U575CITX_MCU} +) + +add_library(GENERIC_U575CITX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U575CITX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U575CITX_serial_generic INTERFACE) +target_compile_options(GENERIC_U575CITX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U575CITX_serial_none INTERFACE) +target_compile_options(GENERIC_U575CITX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U575CITX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U575CITX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U575CITX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U575CITX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U575CITX_usb_HID INTERFACE) +target_compile_options(GENERIC_U575CITX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U575CITX_usb_none INTERFACE) +target_compile_options(GENERIC_U575CITX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_U575CITX_xusb_FS INTERFACE) +target_compile_options(GENERIC_U575CITX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_U575CITX_xusb_HS INTERFACE) +target_compile_options(GENERIC_U575CITX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_U575CITX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_U575CITX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_U575CIUX +# ----------------------------------------------------------------------------- + +set(GENERIC_U575CIUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)") +set(GENERIC_U575CIUX_MAXSIZE 2097152) +set(GENERIC_U575CIUX_MAXDATASIZE 786432) +set(GENERIC_U575CIUX_MCU cortex-m33) +set(GENERIC_U575CIUX_FPCONF "-") +add_library(GENERIC_U575CIUX INTERFACE) +target_compile_options(GENERIC_U575CIUX INTERFACE + "SHELL:-DSTM32U575xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_U575CIUX_MCU} +) +target_compile_definitions(GENERIC_U575CIUX INTERFACE + "STM32U5xx" + "ARDUINO_GENERIC_U575CIUX" + "BOARD_NAME=\"GENERIC_U575CIUX\"" + "BOARD_ID=GENERIC_U575CIUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U575CIUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ + ${GENERIC_U575CIUX_VARIANT_PATH} +) + +target_link_options(GENERIC_U575CIUX INTERFACE + "LINKER:--default-script=${GENERIC_U575CIUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=786432" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_U575CIUX_MCU} +) + +add_library(GENERIC_U575CIUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U575CIUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U575CIUX_serial_generic INTERFACE) +target_compile_options(GENERIC_U575CIUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U575CIUX_serial_none INTERFACE) +target_compile_options(GENERIC_U575CIUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U575CIUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U575CIUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U575CIUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U575CIUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U575CIUX_usb_HID INTERFACE) +target_compile_options(GENERIC_U575CIUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U575CIUX_usb_none INTERFACE) +target_compile_options(GENERIC_U575CIUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_U575CIUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_U575CIUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_U575CIUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_U575CIUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_U575CIUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_U575CIUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_U575ZGTXQ # ----------------------------------------------------------------------------- @@ -94414,6 +95616,170 @@ target_compile_options(GENERIC_U585AIIXQ_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_U585CITX +# ----------------------------------------------------------------------------- + +set(GENERIC_U585CITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)") +set(GENERIC_U585CITX_MAXSIZE 2097152) +set(GENERIC_U585CITX_MAXDATASIZE 786432) +set(GENERIC_U585CITX_MCU cortex-m33) +set(GENERIC_U585CITX_FPCONF "-") +add_library(GENERIC_U585CITX INTERFACE) +target_compile_options(GENERIC_U585CITX INTERFACE + "SHELL:-DSTM32U585xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_U585CITX_MCU} +) +target_compile_definitions(GENERIC_U585CITX INTERFACE + "STM32U5xx" + "ARDUINO_GENERIC_U585CITX" + "BOARD_NAME=\"GENERIC_U585CITX\"" + "BOARD_ID=GENERIC_U585CITX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U585CITX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ + ${GENERIC_U585CITX_VARIANT_PATH} +) + +target_link_options(GENERIC_U585CITX INTERFACE + "LINKER:--default-script=${GENERIC_U585CITX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=786432" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_U585CITX_MCU} +) + +add_library(GENERIC_U585CITX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U585CITX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U585CITX_serial_generic INTERFACE) +target_compile_options(GENERIC_U585CITX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U585CITX_serial_none INTERFACE) +target_compile_options(GENERIC_U585CITX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U585CITX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U585CITX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U585CITX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U585CITX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U585CITX_usb_HID INTERFACE) +target_compile_options(GENERIC_U585CITX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U585CITX_usb_none INTERFACE) +target_compile_options(GENERIC_U585CITX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_U585CITX_xusb_FS INTERFACE) +target_compile_options(GENERIC_U585CITX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_U585CITX_xusb_HS INTERFACE) +target_compile_options(GENERIC_U585CITX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_U585CITX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_U585CITX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_U585CIUX +# ----------------------------------------------------------------------------- + +set(GENERIC_U585CIUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)") +set(GENERIC_U585CIUX_MAXSIZE 2097152) +set(GENERIC_U585CIUX_MAXDATASIZE 786432) +set(GENERIC_U585CIUX_MCU cortex-m33) +set(GENERIC_U585CIUX_FPCONF "-") +add_library(GENERIC_U585CIUX INTERFACE) +target_compile_options(GENERIC_U585CIUX INTERFACE + "SHELL:-DSTM32U585xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_U585CIUX_MCU} +) +target_compile_definitions(GENERIC_U585CIUX INTERFACE + "STM32U5xx" + "ARDUINO_GENERIC_U585CIUX" + "BOARD_NAME=\"GENERIC_U585CIUX\"" + "BOARD_ID=GENERIC_U585CIUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U585CIUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ + ${GENERIC_U585CIUX_VARIANT_PATH} +) + +target_link_options(GENERIC_U585CIUX INTERFACE + "LINKER:--default-script=${GENERIC_U585CIUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=786432" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_U585CIUX_MCU} +) + +add_library(GENERIC_U585CIUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U585CIUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U585CIUX_serial_generic INTERFACE) +target_compile_options(GENERIC_U585CIUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U585CIUX_serial_none INTERFACE) +target_compile_options(GENERIC_U585CIUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U585CIUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U585CIUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U585CIUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U585CIUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U585CIUX_usb_HID INTERFACE) +target_compile_options(GENERIC_U585CIUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U585CIUX_usb_none INTERFACE) +target_compile_options(GENERIC_U585CIUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_U585CIUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_U585CIUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_U585CIUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_U585CIUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_U585CIUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_U585CIUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_U585ZITXQ # ----------------------------------------------------------------------------- @@ -99836,6 +101202,88 @@ target_compile_options(NUCLEO_H743ZI2_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_H753ZI +# ----------------------------------------------------------------------------- + +set(NUCLEO_H753ZI_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT") +set(NUCLEO_H753ZI_MAXSIZE 2097152) +set(NUCLEO_H753ZI_MAXDATASIZE 524288) +set(NUCLEO_H753ZI_MCU cortex-m7) +set(NUCLEO_H753ZI_FPCONF "fpv4-sp-d16-hard") +add_library(NUCLEO_H753ZI INTERFACE) +target_compile_options(NUCLEO_H753ZI INTERFACE + "SHELL:-DSTM32H753xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_H753ZI_MCU} +) +target_compile_definitions(NUCLEO_H753ZI INTERFACE + "STM32H7xx" + "ARDUINO_NUCLEO_H753ZI" + "BOARD_NAME=\"NUCLEO_H753ZI\"" + "BOARD_ID=NUCLEO_H753ZI" + "VARIANT_H=\"variant_NUCLEO_H753ZI.h\"" +) +target_include_directories(NUCLEO_H753ZI INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${NUCLEO_H753ZI_VARIANT_PATH} +) + +target_link_options(NUCLEO_H753ZI INTERFACE + "LINKER:--default-script=${NUCLEO_H753ZI_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_H753ZI_MCU} +) + +add_library(NUCLEO_H753ZI_serial_disabled INTERFACE) +target_compile_options(NUCLEO_H753ZI_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_H753ZI_serial_generic INTERFACE) +target_compile_options(NUCLEO_H753ZI_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_H753ZI_serial_none INTERFACE) +target_compile_options(NUCLEO_H753ZI_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_H753ZI_usb_CDC INTERFACE) +target_compile_options(NUCLEO_H753ZI_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_H753ZI_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_H753ZI_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_H753ZI_usb_HID INTERFACE) +target_compile_options(NUCLEO_H753ZI_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_H753ZI_usb_none INTERFACE) +target_compile_options(NUCLEO_H753ZI_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_H753ZI_xusb_FS INTERFACE) +target_compile_options(NUCLEO_H753ZI_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_H753ZI_xusb_HS INTERFACE) +target_compile_options(NUCLEO_H753ZI_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_H753ZI_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_H753ZI_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_L010RB # ----------------------------------------------------------------------------- @@ -103296,6 +104744,88 @@ target_compile_options(STM32H573I_DK_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# STM32H747I_DISCO +# ----------------------------------------------------------------------------- + +set(STM32H747I_DISCO_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH") +set(STM32H747I_DISCO_MAXSIZE 2097152) +set(STM32H747I_DISCO_MAXDATASIZE 524288) +set(STM32H747I_DISCO_MCU cortex-m7) +set(STM32H747I_DISCO_FPCONF "fpv4-sp-d16-hard") +add_library(STM32H747I_DISCO INTERFACE) +target_compile_options(STM32H747I_DISCO INTERFACE + "SHELL:-DSTM32H747xx -DCORE_CM7" + "SHELL:-DCUSTOM_PERIPHERAL_PINS" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${STM32H747I_DISCO_MCU} +) +target_compile_definitions(STM32H747I_DISCO INTERFACE + "STM32H7xx" + "ARDUINO_STM32H747I_DISCO" + "BOARD_NAME=\"STM32H747I_DISCO\"" + "BOARD_ID=STM32H747I_DISCO" + "VARIANT_H=\"variant_STM32H747I_DISCO.h\"" +) +target_include_directories(STM32H747I_DISCO INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${STM32H747I_DISCO_VARIANT_PATH} +) + +target_link_options(STM32H747I_DISCO INTERFACE + "LINKER:--default-script=${STM32H747I_DISCO_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=524288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${STM32H747I_DISCO_MCU} +) + +add_library(STM32H747I_DISCO_serial_disabled INTERFACE) +target_compile_options(STM32H747I_DISCO_serial_disabled INTERFACE + "SHELL:" +) +add_library(STM32H747I_DISCO_serial_generic INTERFACE) +target_compile_options(STM32H747I_DISCO_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(STM32H747I_DISCO_serial_none INTERFACE) +target_compile_options(STM32H747I_DISCO_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(STM32H747I_DISCO_usb_CDC INTERFACE) +target_compile_options(STM32H747I_DISCO_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(STM32H747I_DISCO_usb_CDCgen INTERFACE) +target_compile_options(STM32H747I_DISCO_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(STM32H747I_DISCO_usb_HID INTERFACE) +target_compile_options(STM32H747I_DISCO_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(STM32H747I_DISCO_usb_none INTERFACE) +target_compile_options(STM32H747I_DISCO_usb_none INTERFACE + "SHELL:" +) +add_library(STM32H747I_DISCO_xusb_FS INTERFACE) +target_compile_options(STM32H747I_DISCO_xusb_FS INTERFACE + "SHELL:" +) +add_library(STM32H747I_DISCO_xusb_HS INTERFACE) +target_compile_options(STM32H747I_DISCO_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(STM32H747I_DISCO_xusb_HSFS INTERFACE) +target_compile_options(STM32H747I_DISCO_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # STM32MP157A_DK1 # ----------------------------------------------------------------------------- diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt index b9cca5b0a1..4dbf924ae4 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt @@ -21,8 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage) add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c + PeripheralPins_DISCO_H747I.c variant_generic.cpp - variant_DISCO_H747I.cpp + variant_STM32H747I_DISCO.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/CMakeLists.txt b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/CMakeLists.txt index 2a4d55b6b1..4b0ade045e 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/CMakeLists.txt +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/CMakeLists.txt @@ -21,6 +21,8 @@ target_link_libraries(variant INTERFACE variant_usage) add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c + PeripheralPins_DEVKIT_IOT_CONTINUUM.c + variant_DEVKIT_IOT_CONTINUUM.cpp variant_generic.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) From 1cffd988ad813728189c14bfd6ba02d77e5bca7f Mon Sep 17 00:00:00 2001 From: Mathieu Choplain Date: Mon, 30 Oct 2023 15:25:23 +0100 Subject: [PATCH 18/83] chore(CI): update skip list Signed-off-by: Mathieu Choplain --- CI/build/conf/cores_config.json | 16 ++++++++++++++++ CI/build/conf/cores_config_ci.json | 16 ++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index ac16c89faf..91d4d3af5a 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -546,6 +546,8 @@ "GENERIC_H742VGTX", "GENERIC_H742VIHX", "GENERIC_H742VITX", + "GENERIC_H742XGHX", + "GENERIC_H742XIHX", "GENERIC_H742ZGTX", "GENERIC_H742ZITX", "GENERIC_H743IGKX", @@ -556,19 +558,28 @@ "GENERIC_H743VGTX", "GENERIC_H743VIHX", "GENERIC_H743VITX", + "GENERIC_H743XGHX", + "GENERIC_H743XIHX", "GENERIC_H743ZGTX", "GENERIC_H743ZITX", + "GENERIC_H745XGHX", + "GENERIC_H745XIHX", "GENERIC_H747AGIX", "GENERIC_H747AIIX", "GENERIC_H747IGTX", "GENERIC_H747IITX", + "GENERIC_H747XGHX", + "GENERIC_H747XIHX", "GENERIC_H750IBKX", "GENERIC_H750IBTX", "GENERIC_H750VBTX", + "GENERIC_H750XBHX", "GENERIC_H750ZBTX", "GENERIC_H753IIKX", "GENERIC_H753VIHX", + "GENERIC_H753XIHX", "GENERIC_H753ZITX", + "GENERIC_H755XIHX", "GENERIC_H757AIIX", "GENERIC_L010F4PX", "GENERIC_L010K4TX", @@ -778,8 +789,13 @@ "GENERIC_MP157DACX", "GENERIC_U575AGIXQ", "GENERIC_U575AIIXQ", + "GENERIC_U575CGTX", + "GENERIC_U575CGUX", + "GENERIC_U575CITX", + "GENERIC_U575CIUX", "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", + "GENERIC_U585CITX", "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", "GENERIC_WB55CCUX", diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json index faa9c15f63..61d024436f 100644 --- a/CI/build/conf/cores_config_ci.json +++ b/CI/build/conf/cores_config_ci.json @@ -546,6 +546,8 @@ "GENERIC_H742VGTX", "GENERIC_H742VIHX", "GENERIC_H742VITX", + "GENERIC_H742XGHX", + "GENERIC_H742XIHX", "GENERIC_H742ZGTX", "GENERIC_H742ZITX", "GENERIC_H743IGKX", @@ -556,19 +558,28 @@ "GENERIC_H743VGTX", "GENERIC_H743VIHX", "GENERIC_H743VITX", + "GENERIC_H743XGHX", + "GENERIC_H743XIHX", "GENERIC_H743ZGTX", "GENERIC_H743ZITX", + "GENERIC_H745XGHX", + "GENERIC_H745XIHX", "GENERIC_H747AGIX", "GENERIC_H747AIIX", "GENERIC_H747IGTX", "GENERIC_H747IITX", + "GENERIC_H747XGHX", + "GENERIC_H747XIHX", "GENERIC_H750IBKX", "GENERIC_H750IBTX", "GENERIC_H750VBTX", + "GENERIC_H750XBHX", "GENERIC_H750ZBTX", "GENERIC_H753IIKX", "GENERIC_H753VIHX", + "GENERIC_H753XIHX", "GENERIC_H753ZITX", + "GENERIC_H755XIHX", "GENERIC_H757AIIX", "GENERIC_L010F4PX", "GENERIC_L010K4TX", @@ -778,8 +789,13 @@ "GENERIC_MP157DACX", "GENERIC_U575AGIXQ", "GENERIC_U575AIIXQ", + "GENERIC_U575CGTX", + "GENERIC_U575CGUX", + "GENERIC_U575CITX", + "GENERIC_U575CIUX", "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", + "GENERIC_U585CITX", "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", "GENERIC_WB55CCUX", From 42b2ab21373f6769cfc6a9b6ca03bf303fe9b4fa Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 31 Oct 2023 15:55:21 +0100 Subject: [PATCH 19/83] fix: add missing USB libraries html ressources Required for html release note. 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0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# 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font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 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xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: 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z78`u%m5S@^_F;_foidufzP z&ueh-zU1yM&8~0lmOfkio-gBex`)?hCJcI8Jv*R0c|WUqSq z?RU?Rmm=3t_2C%%UW9c*D%T{T{EjryCKnsz9-*Bs0}M*xS&-odhCK5eS_Eqi&c6J4o|f&;uUT=p7Fedw#EUl4%Jv{w zq-cCF^otBvw~~$yj6O>>;VqU)3Ml&Atm$B(Ht8=+&x2VS5aWD&t*+04{@k^Gn~yHY zWYC%@ld;g_qz=k*;Iv&xs5M85cEZCU&n2Baf>R6*bN>V|!)eF&l#C93eAMLD=ZF7= zOISFfB5P;F!ngWD3jfMJE_53F&dFc{h2TwSbT*(h6!c}_5_UFeB_*DiyCrtQ7Byr@ z-aCWVt?J}YP7-lfelbrCgZ5mdv(^W&Yf^OvpI}#NbS1Lc`r4&t#3kM!utm&#a;?GR z-1FusfX7&?a9h`%8wf-ub7UXp44xm4w04)S$}}_hPqn-#IabO^bo6$K07>?%G5Xs( zA$*lz_K>lAJ_o<;fsP-*-%~O(716KRqVq+X@=5J~Z~bba(yWL`;EN`@Mr2it&Lkgb z&I|R5!`ZSk%)xFX*FYDaAh=5qWSY@rx1Du9J$$=lh#!~NcFJM&aOv)eqg_@`i^zJCR9a%_{k_i%msw5q z*3!~#Xx3r|VaAwiG}~9M#c`=$Uk6~xe)47ymW+;0DD_lV67L#ouJBa7mF{)X^?eIvPdOMu4ksr`jUP$~{x@?ev2 zdX#ite2RMim01PEg`;qfwg^;v8nx9F!CtNCvz)V{PVgCs*;_@_Rk*oLx@f7hJ7^^1 zu66b)mb!ZMXLZ%8dj-+JCMoWS-Wji-Q-~U7Pt~UiXMej8JcNjk<6?Wk9eLBIhu&Vo^0;AH> z;Q5^a!NZhP(vDfBv&?jdnQavv#8N0E{ZEgs>|1)qYo^t5 zIV$g~`C2%g$*(z4)8hJlK2mF-MJW#3%Cs6`uAvsgRtTo8n!Et)1pZx@_9I18 zw7ER9v~DyrC*R$do9aEw5r@B)YzHOLB^-c9Eu9D!sFmI8^VljVKE89{zY_8PTSF+J b^}%0^qYmp2WD(pA|JtZ4>nPPKybJpu3@X?! literal 0 HcmV?d00001 From 586319c6c2cee268747c8826d93e84b26d1549fd Mon Sep 17 00:00:00 2001 From: Paolo Patruno Date: Mon, 6 Nov 2023 09:30:25 +0100 Subject: [PATCH 20/83] chrore(usb): external redefinition of CDC_*_QUEUE_BUFFER_PACKET_NUMBER (#2165) * admit external definition of CDC_TRANSMIT_QUEUE_BUFFER_PACKET_NUMBER CDC_RECEIVE_QUEUE_BUFFER_PACKET_NUMBER --- cores/arduino/stm32/usb/cdc/cdc_queue.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/cores/arduino/stm32/usb/cdc/cdc_queue.h b/cores/arduino/stm32/usb/cdc/cdc_queue.h index cd10ac2bc5..1ec58d02f0 100644 --- a/cores/arduino/stm32/usb/cdc/cdc_queue.h +++ b/cores/arduino/stm32/usb/cdc/cdc_queue.h @@ -53,8 +53,14 @@ extern "C" { #else #define CDC_QUEUE_MAX_PACKET_SIZE USB_FS_MAX_PACKET_SIZE #endif -#define CDC_TRANSMIT_QUEUE_BUFFER_SIZE ((uint16_t)(CDC_QUEUE_MAX_PACKET_SIZE * 2)) -#define CDC_RECEIVE_QUEUE_BUFFER_SIZE ((uint16_t)(CDC_QUEUE_MAX_PACKET_SIZE * 3)) +#ifndef CDC_TRANSMIT_QUEUE_BUFFER_PACKET_NUMBER +#define CDC_TRANSMIT_QUEUE_BUFFER_PACKET_NUMBER 2 +#endif +#ifndef CDC_RECEIVE_QUEUE_BUFFER_PACKET_NUMBER +#define CDC_RECEIVE_QUEUE_BUFFER_PACKET_NUMBER 3 +#endif +#define CDC_TRANSMIT_QUEUE_BUFFER_SIZE ((uint16_t)(CDC_QUEUE_MAX_PACKET_SIZE * CDC_TRANSMIT_QUEUE_BUFFER_PACKET_NUMBER)) +#define CDC_RECEIVE_QUEUE_BUFFER_SIZE ((uint16_t)(CDC_QUEUE_MAX_PACKET_SIZE * CDC_RECEIVE_QUEUE_BUFFER_PACKET_NUMBER)) typedef struct { uint8_t buffer[CDC_TRANSMIT_QUEUE_BUFFER_SIZE]; @@ -91,4 +97,4 @@ void CDC_ReceiveQueue_CommitBlock(CDC_ReceiveQueue_TypeDef *queue, uint16_t size } #endif -#endif // __CDC_QUEUE_H \ No newline at end of file +#endif // __CDC_QUEUE_H From 462c518c9b08ee018d4dddab50db31381ab93219 Mon Sep 17 00:00:00 2001 From: Jidong Chen <123861172+jchen-dawnscene@users.noreply.github.com> Date: Mon, 13 Nov 2023 09:07:17 +0100 Subject: [PATCH 21/83] fix(SPI): avoid 0 delay when SPI clock > 1MHz Fixes #2181. Signed-off-by: Jidong Chen <123861172+jchen-dawnscene@users.noreply.github.com> Co-Authored-By: Frederic Pillon --- libraries/SPI/src/utility/spi_com.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index a67813e6b7..2cc6c28907 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -214,7 +214,7 @@ static uint32_t compute_disable_delay(spi_t *obj) SPI_HandleTypeDef *handle = &(obj->handle); prescaler = 1 << ((handle->Init.BaudRatePrescaler >> SPI_CFG1_MBR_Pos) + 1); - disable_delay = ((prescaler * 1000000) / spi_freq) / 2; + disable_delay = (((prescaler * 1000000) / spi_freq) / 2) + 1; return disable_delay; } #endif From 97bebdc811f997f0d826453f7c90d91f56e7bbd7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 31 Oct 2023 15:52:21 +0100 Subject: [PATCH 22/83] chore(SPI): remove deprecated WiFi library workaround Signed-off-by: Frederic Pillon --- libraries/SPI/src/SPI.cpp | 7 ------- 1 file changed, 7 deletions(-) diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index eab0792182..7717e0f220 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -74,13 +74,6 @@ void SPIClass::begin(uint8_t _pin) spiSettings[idx].dMode, spiSettings[idx].bOrder); _CSPinConfig = _pin; -#if __has_include("WiFi.h") - // Wait wifi shield initialization. - // Should be better to do in SpiDrv::begin() of WiFi library but it seems - // there is no more update on this library as shield is retired. - delay(2000); -#endif - } /** From 43ec3cb54120d2545aefd8d6c554750b5891e0eb Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 31 Oct 2023 19:44:55 +0100 Subject: [PATCH 23/83] chore(SPI): clean up internal CS pin managements To be aligned with Arduino API. Only Hardware CS pin support kept. Allows to save memory space and increase execution speed. Fixes #257. Signed-off-by: Frederic Pillon --- libraries/SPI/README.md | 93 +++++------ libraries/SPI/src/SPI.cpp | 320 ++++++++------------------------------ libraries/SPI/src/SPI.h | 170 +++----------------- 3 files changed, 126 insertions(+), 457 deletions(-) diff --git a/libraries/SPI/README.md b/libraries/SPI/README.md index 18fa5c632d..5bf0889c59 100644 --- a/libraries/SPI/README.md +++ b/libraries/SPI/README.md @@ -1,70 +1,63 @@ ## SPI -STM32 SPI library has been modified with the possibility to manage several CS pins without to stop the SPI interface. +STM32 SPI library has been modified with the possibility to manage hardware CS pin linked to the SPI peripheral. _We do not describe here the [SPI Arduino API](https://www.arduino.cc/en/Reference/SPI) but the functionalities added._ -We give to the user 3 possibilities about the management of the CS pin: -1. the CS pin is managed directly by the user code before to transfer the data (like the Arduino SPI library) -2. the user gives the CS pin number to the library API and the library manages itself the CS pin (see example below) -3. the user uses a hardware CS pin linked to the SPI peripheral +User have 2 possibilities about the management of the CS pin: +* the CS pin is managed directly by the user code before to transfer the data (like the Arduino SPI library) +* the user uses a hardware CS pin linked to the SPI peripheral -### New API functions +### New SPISetting parameter -* **`SPIClass::SPIClass(uint8_t mosi, uint8_t miso, uint8_t sclk, uint8_t ssel)`**: alternative class constructor -_Params_ SPI mosi pin -_Params_ SPI miso pin -_Params_ SPI sclk pin -_Params_ (optional) SPI ssel pin. This pin must be an hardware CS pin. If you configure this pin, the chip select will be managed by the SPI peripheral. Do not use API functions with CS pin in parameter. +* `noReceive`: value can be `SPI_TRANSMITRECEIVE` or `SPI_TRANSMITONLY`. It allows to skip receive data after transmitting. Default `SPI_TRANSMITRECEIVE`. -* **`void SPIClass::begin(uint8_t _pin)`**: initialize the SPI interface and add a CS pin -_Params_ spi CS pin to be managed by the SPI library +### New API functions -* **`void beginTransaction(uint8_t pin, SPISettings settings)`**: allows to configure the SPI with other parameter. These new parameter are saved this an associated CS pin. -_Params_ SPI CS pin to be managed by the SPI library -_Params_ SPI settings +* `SPIClass::SPIClass(uint8_t mosi, uint8_t miso, uint8_t sclk, uint8_t ssel)`: alternative class constructor +_Params_ SPI `mosi` pin +_Params_ SPI `miso` pin +_Params_ SPI `sclk` pin +_Params_ (optional) SPI `ssel` pin. This pin must be an hardware CS pin. If you configure this pin, the chip select will be managed by the SPI peripheral. -* **`void endTransaction(uint8_t pin)`**: removes a CS pin and the SPI settings associated -_Params_ SPI CS pin managed by the SPI library + * `SPI_HandleTypeDef *getHandle(void)`: Could be used to mix Arduino API and STM32Cube HAL API (ex: DMA). **Use at your own risk.** -**_Note 1_** The following functions must be called after initialization of the SPI instance with `begin()` or `beginTransaction()`. -If you have several device to manage, you can call `beginTransaction()` several time with different CS pin in parameter. -Then you can call the following functions with different CS pin without call again `beginTransaction()` (until you call `end()` or `endTransaction()`). -**_Note 2_** If the mode is set to `SPI_CONTINUE`, the CS pin is kept enabled. Be careful in case you use several CS pin. +##### Example -* **`byte transfer(uint8_t pin, uint8_t _data, SPITransferMode _mode = SPI_LAST)`**: write/read one byte -_Params_ SPI CS pin managed by the SPI library -_Params_ data to write -_Params_ (optional) if `SPI_LAST` CS pin is reset, `SPI_CONTINUE` the CS pin is kept enabled. -_Return_ byte received +This is an example of the use of the hardware CS pin linked to the SPI peripheral: -* **`uint16_t transfer16(uint8_t pin, uint16_t _data, SPITransferMode _mode = SPI_LAST)`**: write/read half-word -_Params_ SPI CS pin managed by the SPI library -_Params_ 16bits data to write -_Params_ (optional) if `SPI_LAST` CS pin is reset, `SPI_CONTINUE` the CS pin is kept enabled. -_Return_ 16bits data received +```C++ +#include +// MOSI MISO SCLK SSEL +SPIClass SPI_3(PC12, PC11, PC10, PC9); + +void setup() { + SPI_3.begin(); // Enable the SPI_3 instance with default SPISsettings + SPI_3.beginTransaction(settings); // Configure the SPI_3 instance with other settings + SPI_3.transfer(0x52); // Transfers data to the first device + SPI_3.end() //SPI_3 instance is disabled +} +``` -* **`void transfer(uint8_t pin, void *_buf, size_t _count, SPITransferMode _mode = SPI_LAST)`**: write/read several bytes. Only one buffer used to write and read the data -_Params_ SPI CS pin managed by the SPI library -_Params_ pointer to data to write. The data will be replaced by the data read. -_Params_ number of data to write/read. -_Params_ (optional) if `SPI_LAST` CS pin is reset, `SPI_CONTINUE` the CS pin is kept enabled. +#### Change default `SPI` instance pins +It is also possible to change the default pins used by the `SPI` instance using above API: -* **`void transfer(byte _pin, void *_bufout, void *_bufin, size_t _count, SPITransferMode _mode = SPI_LAST)`**: write/read several bytes. One buffer for the output data and one for the input data -_Params_ SPI CS pin managed by the SPI library -_Params_ pointer to data to write. -_Params_ pointer where to store the data read. -_Params_ number of data to write/read. -_Params_ (optional) if `SPI_LAST` CS pin is reset, `SPI_CONTINUE` the CS pin is kept enabled. +[[/img/Warning-icon.png|alt="Warning"]] **Have to be called before `begin()`.** -### Example +* `void setMISO(uint32_t miso)` +* `void setMOSI(uint32_t mosi)` +* `void setSCLK(uint32_t sclk)` +* `void setSSEL(uint32_t ssel)` +* `void setMISO(PinName miso)` +* `void setMOSI(PinName mosi)` +* `void setSCLK(PinName sclk)` +* `void setSSEL(PinName ssel)` -This is an example of the use of the CS pin management: +**_Note 1_** Using `setSSEL()` allows to enable hardware CS pin management linked to the SPI peripheral. +##### Example: ```C++ -SPI.begin(2); //Enables the SPI instance with default settings and attaches the CS pin -SPI.beginTransaction(1, settings); //Attaches another CS pin and configure the SPI instance with other settings -SPI.transfer(1, 0x52); //Transfers data to the first device -SPI.transfer(2, 0xA4); //Transfers data to the second device. The SPI instance is configured with the right settings -SPI.end() //SPI instance is disabled + SPI.setMISO(PC_4); // using pin name PY_n + SPI.setMOSI(PC2); // using pin number PYn + SPI.begin(2); ``` diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index 7717e0f220..ae68e59252 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -16,7 +16,7 @@ SPIClass SPI; /** * @brief Default constructor. Uses pin configuration of variant.h. */ -SPIClass::SPIClass() : _CSPinConfig(NO_CONFIG) +SPIClass::SPIClass() { _spi.pin_miso = digitalPinToPinName(MISO); _spi.pin_mosi = digitalPinToPinName(MOSI); @@ -43,7 +43,7 @@ SPIClass::SPIClass() : _CSPinConfig(NO_CONFIG) * another CS pin and don't pass a CS pin as parameter to any functions * of the class. */ -SPIClass::SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) : _CSPinConfig(NO_CONFIG) +SPIClass::SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) { _spi.pin_miso = digitalPinToPinName(miso); _spi.pin_mosi = digitalPinToPinName(mosi); @@ -53,70 +53,38 @@ SPIClass::SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) : /** * @brief Initialize the SPI instance. - * @param _pin: chip select pin (optional). If this parameter is filled, - * it gives the management of the CS pin to the SPI class. In this case - * do not manage the CS pin outside of the SPI class. */ -void SPIClass::begin(uint8_t _pin) +void SPIClass::begin(void) { - uint8_t idx = pinIdx(_pin, ADD_NEW_PIN); - if (idx >= NB_SPI_SETTINGS) { - return; - } - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_spi.pin_ssel == NC)) { - pinMode(_pin, OUTPUT); - digitalWrite(_pin, HIGH); - } - _spi.handle.State = HAL_SPI_STATE_RESET; - spi_init(&_spi, spiSettings[idx].clk, - spiSettings[idx].dMode, - spiSettings[idx].bOrder); - _CSPinConfig = _pin; + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** * @brief This function should be used to configure the SPI instance in case you * don't use the default parameters set by the begin() function. - * @param _pin: CS pin (optional). This pin will be attached with the settings. * @param settings: SPI settings(clock speed, bit order, data mode). - * @Note For each SPI instance you are able to manage until NB_SPI_SETTINGS - * devices attached to the same SPI peripheral. You need to indicate the - * CS pin used to the transfer() function and the SPI instance will be - * configured with the right settings. */ -void SPIClass::beginTransaction(uint8_t _pin, SPISettings settings) +void SPIClass::beginTransaction(SPISettings settings) { - uint8_t idx = pinIdx(_pin, ADD_NEW_PIN); - if (idx >= NB_SPI_SETTINGS) { - return; - } - - spiSettings[idx].clk = settings.clk; - spiSettings[idx].dMode = settings.dMode; - spiSettings[idx].bOrder = settings.bOrder; - spiSettings[idx].noReceive = settings.noReceive; - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_spi.pin_ssel == NC)) { - pinMode(_pin, OUTPUT); - digitalWrite(_pin, HIGH); - } - - spi_init(&_spi, spiSettings[idx].clk, - spiSettings[idx].dMode, - spiSettings[idx].bOrder); - _CSPinConfig = _pin; + _spiSettings.clk = settings.clk; + _spiSettings.dMode = settings.dMode; + _spiSettings.bOrder = settings.bOrder; + _spiSettings.noReceive = settings.noReceive; + + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** - * @brief Remove the CS pin and the settings associated to the SPI instance. - * @param _pin: CS pin (optional) + * @brief End the transaction after beginTransaction usage */ -void SPIClass::endTransaction(uint8_t _pin) +void SPIClass::endTransaction(void) { - RemovePin(_pin); - _CSPinConfig = NO_CONFIG; + } /** @@ -125,34 +93,25 @@ void SPIClass::endTransaction(uint8_t _pin) void SPIClass::end() { spi_deinit(&_spi); - RemoveAllPin(); - _CSPinConfig = NO_CONFIG; } /** * @brief Deprecated function. * Configure the bit order: MSB first or LSB first. - * @param _pin: CS pin associated to a configuration (optional). * @param _bitOrder: MSBFIRST or LSBFIRST */ -void SPIClass::setBitOrder(uint8_t _pin, BitOrder _bitOrder) +void SPIClass::setBitOrder(BitOrder bitOrder) { - uint8_t idx = pinIdx(_pin, GET_IDX); - if (idx >= NB_SPI_SETTINGS) { - return; - } - - spiSettings[idx].bOrder = _bitOrder; + _spiSettings.bOrder = bitOrder; - spi_init(&_spi, spiSettings[idx].clk, - spiSettings[idx].dMode, - spiSettings[idx].bOrder); + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** * @brief Deprecated function. * Configure the data mode (clock polarity and clock phase) - * @param _pin: CS pin associated to a configuration (optional). * @param _mode: SPI_MODE0, SPI_MODE1, SPI_MODE2 or SPI_MODE3 * @note * Mode Clock Polarity (CPOL) Clock Phase (CPHA) @@ -161,142 +120,75 @@ void SPIClass::setBitOrder(uint8_t _pin, BitOrder _bitOrder) * SPI_MODE2 1 0 * SPI_MODE3 1 1 */ -void SPIClass::setDataMode(uint8_t _pin, uint8_t _mode) +void SPIClass::setDataMode(uint8_t _mode) { - uint8_t idx = pinIdx(_pin, GET_IDX); - if (idx >= NB_SPI_SETTINGS) { - return; - } - if (SPI_MODE0 == _mode) { - spiSettings[idx].dMode = SPI_MODE_0; + _spiSettings.dMode = SPI_MODE_0; } else if (SPI_MODE1 == _mode) { - spiSettings[idx].dMode = SPI_MODE_1; + _spiSettings.dMode = SPI_MODE_1; } else if (SPI_MODE2 == _mode) { - spiSettings[idx].dMode = SPI_MODE_2; + _spiSettings.dMode = SPI_MODE_2; } else if (SPI_MODE3 == _mode) { - spiSettings[idx].dMode = SPI_MODE_3; + _spiSettings.dMode = SPI_MODE_3; } - spi_init(&_spi, spiSettings[idx].clk, - spiSettings[idx].dMode, - spiSettings[idx].bOrder); + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** * @brief Deprecated function. * Configure the clock speed - * @param _pin: CS pin associated to a configuration (optional). * @param _divider: the SPI clock can be divided by values from 1 to 255. * If 0, default SPI speed is used. */ -void SPIClass::setClockDivider(uint8_t _pin, uint8_t _divider) +void SPIClass::setClockDivider(uint8_t _divider) { - uint8_t idx = pinIdx(_pin, GET_IDX); - if (idx >= NB_SPI_SETTINGS) { - return; - } if (_divider == 0) { - spiSettings[idx].clk = SPI_SPEED_CLOCK_DEFAULT; + _spiSettings.clk = SPI_SPEED_CLOCK_DEFAULT; } else { /* Get clk freq of the SPI instance and compute it */ - spiSettings[idx].clk = spi_getClkFreq(&_spi) / _divider; + _spiSettings.clk = spi_getClkFreq(&_spi) / _divider; } - spi_init(&_spi, spiSettings[idx].clk, - spiSettings[idx].dMode, - spiSettings[idx].bOrder); + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** * @brief Transfer one byte on the SPI bus. * begin() or beginTransaction() must be called at least once before. - * @param _pin: CS pin to select a device (optional). If the previous transfer - * used another CS pin then the SPI instance will be reconfigured. * @param data: byte to send. - * @param _mode: (optional) can be SPI_CONTINUE in case of multiple successive - * send or SPI_LAST to indicate the end of send. - * If the _mode is set to SPI_CONTINUE, keep the SPI instance alive. - * That means the CS pin is not reset. Be careful in case you use - * several CS pin. * @return byte received from the slave. */ -byte SPIClass::transfer(uint8_t _pin, uint8_t data, SPITransferMode _mode) +byte SPIClass::transfer(uint8_t data) { uint8_t rx_buffer = 0; - - uint8_t idx = pinIdx(_pin, GET_IDX); - if (idx >= NB_SPI_SETTINGS) { - return rx_buffer; - } - - if (_pin != _CSPinConfig) { - spi_init(&_spi, spiSettings[idx].clk, - spiSettings[idx].dMode, - spiSettings[idx].bOrder); - _CSPinConfig = _pin; - } - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_spi.pin_ssel == NC)) { - digitalWrite(_pin, LOW); - } - - spi_transfer(&_spi, &data, &rx_buffer, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, spiSettings[idx].noReceive); - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_mode == SPI_LAST) && (_spi.pin_ssel == NC)) { - digitalWrite(_pin, HIGH); - } - + spi_transfer(&_spi, &data, &rx_buffer, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); return rx_buffer; } /** * @brief Transfer two bytes on the SPI bus in 16 bits format. * begin() or beginTransaction() must be called at least once before. - * @param _pin: CS pin to select a device (optional). If the previous transfer - * used another CS pin then the SPI instance will be reconfigured. * @param data: bytes to send. - * @param _mode: (optional) can be SPI_CONTINUE in case of multiple successive - * send or SPI_LAST to indicate the end of send. - * If the _mode is set to SPI_CONTINUE, keep the SPI instance alive. - * That means the CS pin is not reset. Be careful in case you use - * several CS pin. * @return bytes received from the slave in 16 bits format. */ -uint16_t SPIClass::transfer16(uint8_t _pin, uint16_t data, SPITransferMode _mode) +uint16_t SPIClass::transfer16(uint16_t data) { uint16_t rx_buffer = 0; uint16_t tmp; - uint8_t idx = pinIdx(_pin, GET_IDX); - if (idx >= NB_SPI_SETTINGS) { - return rx_buffer; - } - - if (_pin != _CSPinConfig) { - spi_init(&_spi, spiSettings[idx].clk, - spiSettings[idx].dMode, - spiSettings[idx].bOrder); - _CSPinConfig = _pin; - } - - if (spiSettings[idx].bOrder) { + if (_spiSettings.bOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_spi.pin_ssel == NC)) { - digitalWrite(_pin, LOW); - } - spi_transfer(&_spi, (uint8_t *)&data, (uint8_t *)&rx_buffer, sizeof(uint16_t), - SPI_TRANSFER_TIMEOUT, spiSettings[idx].noReceive); - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_mode == SPI_LAST) && (_spi.pin_ssel == NC)) { - digitalWrite(_pin, HIGH); - } + SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); - if (spiSettings[idx].bOrder) { + if (_spiSettings.bOrder) { tmp = ((rx_buffer & 0xff00) >> 8) | ((rx_buffer & 0xff) << 8); rx_buffer = tmp; } @@ -307,43 +199,15 @@ uint16_t SPIClass::transfer16(uint8_t _pin, uint16_t data, SPITransferMode _mode /** * @brief Transfer several bytes. Only one buffer used to send and receive data. * begin() or beginTransaction() must be called at least once before. - * @param _pin: CS pin to select a device (optional). If the previous transfer - * used another CS pin then the SPI instance will be reconfigured. * @param _buf: pointer to the bytes to send. The bytes received are copy in * this buffer. * @param _count: number of bytes to send/receive. - * @param _mode: (optional) can be SPI_CONTINUE in case of multiple successive - * send or SPI_LAST to indicate the end of send. - * If the _mode is set to SPI_CONTINUE, keep the SPI instance alive. - * That means the CS pin is not reset. Be careful in case you use - * several CS pin. */ -void SPIClass::transfer(uint8_t _pin, void *_buf, size_t _count, SPITransferMode _mode) +void SPIClass::transfer(void *_buf, size_t _count) { - if ((_count == 0) || (_buf == NULL)) { - return; - } - uint8_t idx = pinIdx(_pin, GET_IDX); - if (idx >= NB_SPI_SETTINGS) { - return; - } - if (_pin != _CSPinConfig) { - - spi_init(&_spi, spiSettings[idx].clk, - spiSettings[idx].dMode, - spiSettings[idx].bOrder); - _CSPinConfig = _pin; - } - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_spi.pin_ssel == NC)) { - digitalWrite(_pin, LOW); - } - - spi_transfer(&_spi, ((uint8_t *)_buf), ((uint8_t *)_buf), _count, - SPI_TRANSFER_TIMEOUT, spiSettings[idx].noReceive); - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_mode == SPI_LAST) && (_spi.pin_ssel == NC)) { - digitalWrite(_pin, HIGH); + if ((_count != 0) && (_buf != NULL)) { + spi_transfer(&_spi, ((uint8_t *)_buf), ((uint8_t *)_buf), _count, + SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); } } @@ -351,43 +215,15 @@ void SPIClass::transfer(uint8_t _pin, void *_buf, size_t _count, SPITransferMode * @brief Transfer several bytes. One buffer contains the data to send and * another one will contains the data received. begin() or * beginTransaction() must be called at least once before. - * @param _pin: CS pin to select a device (optional). If the previous transfer - * used another CS pin then the SPI instance will be reconfigured. * @param _bufout: pointer to the bytes to send. * @param _bufin: pointer to the bytes received. * @param _count: number of bytes to send/receive. - * @param _mode: (optional) can be SPI_CONTINUE in case of multiple successive - * send or SPI_LAST to indicate the end of send. - * If the _mode is set to SPI_CONTINUE, keep the SPI instance alive. - * That means the CS pin is not reset. Be careful in case you use - * several CS pin. */ -void SPIClass::transfer(byte _pin, void *_bufout, void *_bufin, size_t _count, SPITransferMode _mode) +void SPIClass::transfer(void *_bufout, void *_bufin, size_t _count) { - if ((_count == 0) || (_bufout == NULL) || (_bufin == NULL)) { - return; - } - uint8_t idx = pinIdx(_pin, GET_IDX); - if (idx >= NB_SPI_SETTINGS) { - return; - } - - if (_pin != _CSPinConfig) { - spi_init(&_spi, spiSettings[idx].clk, - spiSettings[idx].dMode, - spiSettings[idx].bOrder); - _CSPinConfig = _pin; - } - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_spi.pin_ssel == NC)) { - digitalWrite(_pin, LOW); - } - - spi_transfer(&_spi, ((uint8_t *)_bufout), ((uint8_t *)_bufin), _count, - SPI_TRANSFER_TIMEOUT, spiSettings[idx].noReceive); - - if ((_pin != CS_PIN_CONTROLLED_BY_USER) && (_mode == SPI_LAST) && (_spi.pin_ssel == NC)) { - digitalWrite(_pin, HIGH); + if ((_count != 0) && (_bufout != NULL) && (_bufin != NULL)) { + spi_transfer(&_spi, ((uint8_t *)_bufout), ((uint8_t *)_bufin), _count, + SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); } } @@ -416,68 +252,38 @@ void SPIClass::detachInterrupt(void) } #if defined(SUBGHZSPI_BASE) -void SUBGHZSPIClass::begin(uint8_t _pin) +void SUBGHZSPIClass::begin() { - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_UnselectSUBGHZSPI_NSS(); - } - SPIClass::begin(CS_PIN_CONTROLLED_BY_USER); + SPIClass::begin(); } -void SUBGHZSPIClass::beginTransaction(uint8_t _pin, SPISettings settings) +void SUBGHZSPIClass::beginTransaction(SPISettings settings) { - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_UnselectSUBGHZSPI_NSS(); - } - SPIClass::beginTransaction(CS_PIN_CONTROLLED_BY_USER, settings); + SPIClass::beginTransaction(settings); } -byte SUBGHZSPIClass::transfer(uint8_t _pin, uint8_t _data, SPITransferMode _mode) +byte SUBGHZSPIClass::transfer(uint8_t _data) { byte res; - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_SelectSUBGHZSPI_NSS(); - } - res = SPIClass::transfer(CS_PIN_CONTROLLED_BY_USER, _data, _mode); - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_UnselectSUBGHZSPI_NSS(); - } + res = SPIClass::transfer(_data); return res; } -uint16_t SUBGHZSPIClass::transfer16(uint8_t _pin, uint16_t _data, SPITransferMode _mode) +uint16_t SUBGHZSPIClass::transfer16(uint16_t _data) { uint16_t rx_buffer = 0; - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_SelectSUBGHZSPI_NSS(); - } - SPIClass::transfer16(CS_PIN_CONTROLLED_BY_USER, _data, _mode); - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_UnselectSUBGHZSPI_NSS(); - } + rx_buffer = SPIClass::transfer16(_data); return rx_buffer; } -void SUBGHZSPIClass::transfer(uint8_t _pin, void *_buf, size_t _count, SPITransferMode _mode) +void SUBGHZSPIClass::transfer(void *_buf, size_t _count) { - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_SelectSUBGHZSPI_NSS(); - } - SPIClass::transfer(CS_PIN_CONTROLLED_BY_USER, _buf, _count, _mode); - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_UnselectSUBGHZSPI_NSS(); - } + SPIClass::transfer(_buf, _count); } -void SUBGHZSPIClass::transfer(byte _pin, void *_bufout, void *_bufin, size_t _count, SPITransferMode _mode) +void SUBGHZSPIClass::transfer(void *_bufout, void *_bufin, size_t _count) { - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_SelectSUBGHZSPI_NSS(); - } - SPIClass::transfer(CS_PIN_CONTROLLED_BY_USER, _bufout, _bufin, _count, _mode); - if (_pin != CS_PIN_CONTROLLED_BY_USER) { - LL_PWR_UnselectSUBGHZSPI_NSS(); - } + SPIClass::transfer(_bufout, _bufin, _count); } void SUBGHZSPIClass::enableDebugPins(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index 7bde790337..8d5aaacce9 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -47,36 +47,15 @@ extern "C" { #define SPI_TRANSMITRECEIVE 0x0 #define SPI_TRANSMITONLY 0x1 -// Transfer mode -enum SPITransferMode { - SPI_CONTINUE, /* Transfer not finished: CS pin kept active */ - SPI_LAST /* Transfer ended: CS pin released */ -}; - -// Indicates the user controls himself the CS pin outside of the spi class -#define CS_PIN_CONTROLLED_BY_USER NUM_DIGITAL_PINS - -// Indicates there is no configuration selected -#define NO_CONFIG ((int16_t)(-1)) - // Defines a default timeout delay in milliseconds for the SPI transfer #ifndef SPI_TRANSFER_TIMEOUT #define SPI_TRANSFER_TIMEOUT 1000 #endif -/* - * Defines the number of settings saved per SPI instance. Must be in range 1 to 254. - * Can be redefined in variant.h - */ -#ifndef NB_SPI_SETTINGS - #define NB_SPI_SETTINGS 4 -#endif - class SPISettings { public: constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, bool noRecv = SPI_TRANSMITRECEIVE) - : pinCS(-1), - clk(clock), + : clk(clock), bOrder(bitOrder), dMode((spi_mode_e)( (SPI_MODE0 == dataMode) ? SPI_MODE_0 : @@ -88,14 +67,12 @@ class SPISettings { noReceive(noRecv) { } constexpr SPISettings() - : pinCS(-1), - clk(SPI_SPEED_CLOCK_DEFAULT), + : clk(SPI_SPEED_CLOCK_DEFAULT), bOrder(MSBFIRST), dMode(SPI_MODE_0), noReceive(SPI_TRANSMITRECEIVE) { } private: - int16_t pinCS; //CS pin associated to the configuration uint32_t clk; //specifies the spi bus maximum clock speed BitOrder bOrder; //bit order (MSBFirst or LSBFirst) spi_mode_e dMode; //one of the data mode @@ -148,76 +125,29 @@ class SPIClass { _spi.pin_ssel = (ssel); }; - virtual void begin(uint8_t _pin = CS_PIN_CONTROLLED_BY_USER); + virtual void begin(); void end(void); /* This function should be used to configure the SPI instance in case you * don't use default parameters. - * You can attach another CS pin to the SPI instance and each CS pin can be - * attach with specific SPI settings. */ - virtual void beginTransaction(uint8_t pin, SPISettings settings); - void beginTransaction(SPISettings settings) - { - beginTransaction(CS_PIN_CONTROLLED_BY_USER, settings); - } - - void endTransaction(uint8_t pin); - void endTransaction(void) - { - endTransaction(CS_PIN_CONTROLLED_BY_USER); - } + void beginTransaction(SPISettings settings); + virtual void endTransaction(void); /* Transfer functions: must be called after initialization of the SPI * instance with begin() or beginTransaction(). - * You can specify the CS pin to use. */ - virtual byte transfer(uint8_t pin, uint8_t _data, SPITransferMode _mode = SPI_LAST); - virtual uint16_t transfer16(uint8_t pin, uint16_t _data, SPITransferMode _mode = SPI_LAST); - virtual void transfer(uint8_t pin, void *_buf, size_t _count, SPITransferMode _mode = SPI_LAST); - virtual void transfer(byte _pin, void *_bufout, void *_bufin, size_t _count, SPITransferMode _mode = SPI_LAST); - - // Transfer functions when user controls himself the CS pin. - byte transfer(uint8_t _data, SPITransferMode _mode = SPI_LAST) - { - return transfer(CS_PIN_CONTROLLED_BY_USER, _data, _mode); - } - - uint16_t transfer16(uint16_t _data, SPITransferMode _mode = SPI_LAST) - { - return transfer16(CS_PIN_CONTROLLED_BY_USER, _data, _mode); - } - - void transfer(void *_buf, size_t _count, SPITransferMode _mode = SPI_LAST) - { - transfer(CS_PIN_CONTROLLED_BY_USER, _buf, _count, _mode); - } - - void transfer(void *_bufout, void *_bufin, size_t _count, SPITransferMode _mode = SPI_LAST) - { - transfer(CS_PIN_CONTROLLED_BY_USER, _bufout, _bufin, _count, _mode); - } + virtual byte transfer(uint8_t _data); + virtual uint16_t transfer16(uint16_t _data); + virtual void transfer(void *_buf, size_t _count); + virtual void transfer(void *_bufout, void *_bufin, size_t _count); /* These methods are deprecated and kept for compatibility. * Use SPISettings with SPI.beginTransaction() to configure SPI parameters. */ - void setBitOrder(uint8_t _pin, BitOrder); - void setBitOrder(BitOrder _order) - { - setBitOrder(CS_PIN_CONTROLLED_BY_USER, _order); - } - - void setDataMode(uint8_t _pin, uint8_t); - void setDataMode(uint8_t _mode) - { - setDataMode(CS_PIN_CONTROLLED_BY_USER, _mode); - } - - void setClockDivider(uint8_t _pin, uint8_t); - void setClockDivider(uint8_t _div) - { - setClockDivider(CS_PIN_CONTROLLED_BY_USER, _div); - } + void setBitOrder(BitOrder); + void setDataMode(uint8_t); + void setClockDivider(uint8_t); // Not implemented functions. Kept for backward compatibility. void usingInterrupt(uint8_t interruptNumber); @@ -235,68 +165,8 @@ class SPIClass { spi_t _spi; private: - /* Contains various spiSettings for the same spi instance. Each spi spiSettings - is associated to a CS pin. */ - SPISettings spiSettings[NB_SPI_SETTINGS]; - - // Use to know which configuration is selected. - int16_t _CSPinConfig; - - typedef enum { - GET_IDX = 0, - ADD_NEW_PIN = 1 - } pin_option_t; - - uint8_t pinIdx(uint8_t _pin, pin_option_t option) - { - uint8_t i; - - if ((_pin > NUM_DIGITAL_PINS) && (!digitalPinIsValid(_pin))) { - return NB_SPI_SETTINGS; - } - - for (i = 0; i < NB_SPI_SETTINGS; i++) { - if (_pin == spiSettings[i].pinCS) { - return i; - } - } - - if (option == ADD_NEW_PIN) { - for (i = 0; i < NB_SPI_SETTINGS; i++) { - if (spiSettings[i].pinCS == -1) { - spiSettings[i].pinCS = _pin; - return i; - } - } - } - return i; - } - - void RemovePin(uint8_t _pin) - { - if ((_pin > NUM_DIGITAL_PINS) && (!digitalPinIsValid(_pin))) { - return; - } - - for (uint8_t i = 0; i < NB_SPI_SETTINGS; i++) { - if (spiSettings[i].pinCS == _pin) { - spiSettings[i].pinCS = -1; - spiSettings[i].clk = SPI_SPEED_CLOCK_DEFAULT; - spiSettings[i].bOrder = MSBFIRST; - spiSettings[i].dMode = SPI_MODE_0; - } - } - } - - void RemoveAllPin(void) - { - for (uint8_t i = 0; i < NB_SPI_SETTINGS; i++) { - spiSettings[i].pinCS = -1; - spiSettings[i].clk = SPI_SPEED_CLOCK_DEFAULT; - spiSettings[i].bOrder = MSBFIRST; - spiSettings[i].dMode = SPI_MODE_0; - } - } + /* Current SPISettings */ + SPISettings _spiSettings = SPISettings(); }; extern SPIClass SPI; @@ -309,12 +179,12 @@ class SUBGHZSPIClass : public SPIClass { _spi.spi = SUBGHZSPI; } - void begin(uint8_t _pin = CS_PIN_CONTROLLED_BY_USER); - void beginTransaction(uint8_t pin, SPISettings settings); - byte transfer(uint8_t pin, uint8_t _data, SPITransferMode _mode = SPI_LAST); - uint16_t transfer16(uint8_t pin, uint16_t _data, SPITransferMode _mode = SPI_LAST); - void transfer(uint8_t pin, void *_buf, size_t _count, SPITransferMode _mode = SPI_LAST); - void transfer(byte _pin, void *_bufout, void *_bufin, size_t _count, SPITransferMode _mode = SPI_LAST); + void begin(); + void beginTransaction(SPISettings settings); + byte transfer(uint8_t _data); + uint16_t transfer16(uint16_t _data); + void transfer(void *_buf, size_t _count); + void transfer(void *_bufout, void *_bufin, size_t _count); void enableDebugPins(uint32_t mosi = DEBUG_SUBGHZSPI_MOSI, uint32_t miso = DEBUG_SUBGHZSPI_MISO, uint32_t sclk = DEBUG_SUBGHZSPI_SCLK, uint32_t ssel = DEBUG_SUBGHZSPI_SS); using SPIClass::beginTransaction; From 0ada13f60819d7be5cf5979284c8edf15da21df7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 3 Nov 2023 11:23:47 +0100 Subject: [PATCH 24/83] chore(SPI): remove non arduino transfer api with 2 buffer Signed-off-by: Frederic Pillon --- libraries/SPI/src/SPI.cpp | 39 ++++++----------------------- libraries/SPI/src/SPI.h | 2 -- libraries/SPI/src/utility/spi_com.c | 25 +++++------------- libraries/SPI/src/utility/spi_com.h | 5 ++-- 4 files changed, 16 insertions(+), 55 deletions(-) diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index ae68e59252..b8f282ffe5 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -165,9 +165,8 @@ void SPIClass::setClockDivider(uint8_t _divider) */ byte SPIClass::transfer(uint8_t data) { - uint8_t rx_buffer = 0; - spi_transfer(&_spi, &data, &rx_buffer, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); - return rx_buffer; + spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); + return data; } /** @@ -178,22 +177,21 @@ byte SPIClass::transfer(uint8_t data) */ uint16_t SPIClass::transfer16(uint16_t data) { - uint16_t rx_buffer = 0; uint16_t tmp; if (_spiSettings.bOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } - spi_transfer(&_spi, (uint8_t *)&data, (uint8_t *)&rx_buffer, sizeof(uint16_t), + spi_transfer(&_spi, (uint8_t *)&data, sizeof(uint16_t), SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); if (_spiSettings.bOrder) { - tmp = ((rx_buffer & 0xff00) >> 8) | ((rx_buffer & 0xff) << 8); - rx_buffer = tmp; + tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); + data = tmp; } - return rx_buffer; + return data; } /** @@ -205,24 +203,8 @@ uint16_t SPIClass::transfer16(uint16_t data) */ void SPIClass::transfer(void *_buf, size_t _count) { - if ((_count != 0) && (_buf != NULL)) { - spi_transfer(&_spi, ((uint8_t *)_buf), ((uint8_t *)_buf), _count, - SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); - } -} - -/** - * @brief Transfer several bytes. One buffer contains the data to send and - * another one will contains the data received. begin() or - * beginTransaction() must be called at least once before. - * @param _bufout: pointer to the bytes to send. - * @param _bufin: pointer to the bytes received. - * @param _count: number of bytes to send/receive. - */ -void SPIClass::transfer(void *_bufout, void *_bufin, size_t _count) -{ - if ((_count != 0) && (_bufout != NULL) && (_bufin != NULL)) { - spi_transfer(&_spi, ((uint8_t *)_bufout), ((uint8_t *)_bufin), _count, + if ((count != 0) && (buf != NULL)) { + spi_transfer(&_spi, ((uint8_t *)buf), count, SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); } } @@ -281,11 +263,6 @@ void SUBGHZSPIClass::transfer(void *_buf, size_t _count) SPIClass::transfer(_buf, _count); } -void SUBGHZSPIClass::transfer(void *_bufout, void *_bufin, size_t _count) -{ - SPIClass::transfer(_bufout, _bufin, _count); -} - void SUBGHZSPIClass::enableDebugPins(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) { /* Configure SPI GPIO pins */ diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index 8d5aaacce9..f8e41bea5c 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -140,7 +140,6 @@ class SPIClass { virtual byte transfer(uint8_t _data); virtual uint16_t transfer16(uint16_t _data); virtual void transfer(void *_buf, size_t _count); - virtual void transfer(void *_bufout, void *_bufin, size_t _count); /* These methods are deprecated and kept for compatibility. * Use SPISettings with SPI.beginTransaction() to configure SPI parameters. @@ -184,7 +183,6 @@ class SUBGHZSPIClass : public SPIClass { byte transfer(uint8_t _data); uint16_t transfer16(uint16_t _data); void transfer(void *_buf, size_t _count); - void transfer(void *_bufout, void *_bufin, size_t _count); void enableDebugPins(uint32_t mosi = DEBUG_SUBGHZSPI_MOSI, uint32_t miso = DEBUG_SUBGHZSPI_MISO, uint32_t sclk = DEBUG_SUBGHZSPI_SCLK, uint32_t ssel = DEBUG_SUBGHZSPI_SS); using SPIClass::beginTransaction; diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index 2cc6c28907..cfc2c2cc45 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -496,38 +496,25 @@ void spi_deinit(spi_t *obj) #endif } -/** - * @brief This function is implemented by user to send data over SPI interface - * @param obj : pointer to spi_t structure - * @param Data : data to be sent - * @param len : length in bytes of the data to be sent - * @param Timeout: Timeout duration in tick - * @retval status of the send operation (0) in case of error - */ -spi_status_e spi_send(spi_t *obj, uint8_t *Data, uint16_t len, uint32_t Timeout) -{ - return spi_transfer(obj, Data, Data, len, Timeout, 1 /* SPI_TRANSMITONLY */); -} - /** * @brief This function is implemented by user to send/receive data over * SPI interface * @param obj : pointer to spi_t structure - * @param tx_buffer : tx data to send before reception - * @param rx_buffer : data to receive + * @param buffer : tx data to send before reception * @param len : length in byte of the data to send and receive * @param Timeout: Timeout duration in tick * @param skipReceive: skip receiving data after transmit or not * @retval status of the send operation (0) in case of error */ -spi_status_e spi_transfer(spi_t *obj, uint8_t *tx_buffer, uint8_t *rx_buffer, - uint16_t len, uint32_t Timeout, bool skipReceive) +spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, + uint32_t Timeout, bool skipReceive) { spi_status_e ret = SPI_OK; uint32_t tickstart, size = len; SPI_TypeDef *_SPI = obj->handle.Instance; + uint8_t *tx_buffer = buffer; - if ((obj == NULL) || (len == 0) || (Timeout == 0U)) { + if ((len == 0) || (Timeout == 0U)) { return Timeout > 0U ? SPI_ERROR : SPI_TIMEOUT; } tickstart = HAL_GetTick(); @@ -553,7 +540,7 @@ spi_status_e spi_transfer(spi_t *obj, uint8_t *tx_buffer, uint8_t *rx_buffer, #else while (!LL_SPI_IsActiveFlag_RXNE(_SPI)); #endif - *rx_buffer++ = LL_SPI_ReceiveData8(_SPI); + *buffer++ = LL_SPI_ReceiveData8(_SPI); } if ((Timeout != HAL_MAX_DELAY) && (HAL_GetTick() - tickstart >= Timeout)) { ret = SPI_TIMEOUT; diff --git a/libraries/SPI/src/utility/spi_com.h b/libraries/SPI/src/utility/spi_com.h index daba244b4c..ee322e6982 100644 --- a/libraries/SPI/src/utility/spi_com.h +++ b/libraries/SPI/src/utility/spi_com.h @@ -102,9 +102,8 @@ typedef enum { /* Exported functions ------------------------------------------------------- */ void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb); void spi_deinit(spi_t *obj); -spi_status_e spi_send(spi_t *obj, uint8_t *Data, uint16_t len, uint32_t Timeout); -spi_status_e spi_transfer(spi_t *obj, uint8_t *tx_buffer, - uint8_t *rx_buffer, uint16_t len, uint32_t Timeout, bool skipReceive); +spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, + uint32_t Timeout, bool skipReceive); uint32_t spi_getClkFreq(spi_t *obj); #ifdef __cplusplus From 392469a1dc66448dea543119b7258128b5596a03 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 3 Nov 2023 11:39:15 +0100 Subject: [PATCH 25/83] chore(SPI): align with ArduinoCoreAPI Signed-off-by: Frederic Pillon --- libraries/SPI/src/SPI.cpp | 95 +++++++++--------- libraries/SPI/src/SPI.h | 144 ++++++++++++++++++++-------- libraries/SPI/src/utility/spi_com.c | 6 +- libraries/SPI/src/utility/spi_com.h | 13 +-- 4 files changed, 164 insertions(+), 94 deletions(-) diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index b8f282ffe5..b3266d348a 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -57,9 +57,10 @@ SPIClass::SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) void SPIClass::begin(void) { _spi.handle.State = HAL_SPI_STATE_RESET; - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); + _spiSettings = DEFAULT_SPI_SETTINGS; + spi_init(&_spi, _spiSettings.getClockFreq(), + _spiSettings.getDataMode(), + _spiSettings.getBitOrder()); } /** @@ -69,14 +70,12 @@ void SPIClass::begin(void) */ void SPIClass::beginTransaction(SPISettings settings) { - _spiSettings.clk = settings.clk; - _spiSettings.dMode = settings.dMode; - _spiSettings.bOrder = settings.bOrder; - _spiSettings.noReceive = settings.noReceive; - - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); + if (_spiSettings != settings) { + _spiSettings = settings; + spi_init(&_spi, _spiSettings.getClockFreq(), + _spiSettings.getDataMode(), + _spiSettings.getBitOrder()); + } } /** @@ -102,17 +101,17 @@ void SPIClass::end() */ void SPIClass::setBitOrder(BitOrder bitOrder) { - _spiSettings.bOrder = bitOrder; + _spiSettings.setBitOrder(bitOrder); - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); + spi_init(&_spi, _spiSettings.getClockFreq(), + _spiSettings.getDataMode(), + _spiSettings.getBitOrder()); } /** * @brief Deprecated function. * Configure the data mode (clock polarity and clock phase) - * @param _mode: SPI_MODE0, SPI_MODE1, SPI_MODE2 or SPI_MODE3 + * @param mode: SPI_MODE0, SPI_MODE1, SPI_MODE2 or SPI_MODE3 * @note * Mode Clock Polarity (CPOL) Clock Phase (CPHA) * SPI_MODE0 0 0 @@ -120,21 +119,19 @@ void SPIClass::setBitOrder(BitOrder bitOrder) * SPI_MODE2 1 0 * SPI_MODE3 1 1 */ -void SPIClass::setDataMode(uint8_t _mode) + +void SPIClass::setDataMode(uint8_t mode) { - if (SPI_MODE0 == _mode) { - _spiSettings.dMode = SPI_MODE_0; - } else if (SPI_MODE1 == _mode) { - _spiSettings.dMode = SPI_MODE_1; - } else if (SPI_MODE2 == _mode) { - _spiSettings.dMode = SPI_MODE_2; - } else if (SPI_MODE3 == _mode) { - _spiSettings.dMode = SPI_MODE_3; - } + setDataMode((SPIMode)mode); +} - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); +void SPIClass::setDataMode(SPIMode mode) +{ + _spiSettings.setDataMode(mode); + + spi_init(&_spi, _spiSettings.getClockFreq(), + _spiSettings.getDataMode(), + _spiSettings.getBitOrder()); } /** @@ -146,15 +143,15 @@ void SPIClass::setDataMode(uint8_t _mode) void SPIClass::setClockDivider(uint8_t _divider) { if (_divider == 0) { - _spiSettings.clk = SPI_SPEED_CLOCK_DEFAULT; + _spiSettings.setClockFreq(SPI_SPEED_CLOCK_DEFAULT); } else { - /* Get clk freq of the SPI instance and compute it */ - _spiSettings.clk = spi_getClkFreq(&_spi) / _divider; + /* Get clock freq of the SPI instance and compute it */ + _spiSettings.setClockFreq(spi_getClkFreq(&_spi) / _divider); } - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); + spi_init(&_spi, _spiSettings.getClockFreq(), + _spiSettings.getDataMode(), + _spiSettings.getBitOrder()); } /** @@ -163,9 +160,9 @@ void SPIClass::setClockDivider(uint8_t _divider) * @param data: byte to send. * @return byte received from the slave. */ -byte SPIClass::transfer(uint8_t data) +uint8_t SPIClass::transfer(uint8_t data) { - spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); + spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, _spiSettings.getSkipRecv()); return data; } @@ -179,14 +176,14 @@ uint16_t SPIClass::transfer16(uint16_t data) { uint16_t tmp; - if (_spiSettings.bOrder) { + if (_spiSettings.getBitOrder()) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } spi_transfer(&_spi, (uint8_t *)&data, sizeof(uint16_t), - SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); + SPI_TRANSFER_TIMEOUT, _spiSettings.getSkipRecv()); - if (_spiSettings.bOrder) { + if (_spiSettings.getBitOrder()) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } @@ -197,22 +194,30 @@ uint16_t SPIClass::transfer16(uint16_t data) /** * @brief Transfer several bytes. Only one buffer used to send and receive data. * begin() or beginTransaction() must be called at least once before. - * @param _buf: pointer to the bytes to send. The bytes received are copy in + * @param buf: pointer to the bytes to send. The bytes received are copy in * this buffer. - * @param _count: number of bytes to send/receive. + * @param count: number of bytes to send/receive. */ -void SPIClass::transfer(void *_buf, size_t _count) +void SPIClass::transfer(void *buf, size_t count) { if ((count != 0) && (buf != NULL)) { spi_transfer(&_spi, ((uint8_t *)buf), count, - SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); + SPI_TRANSFER_TIMEOUT, _spiSettings.getSkipRecv()); } } /** * @brief Not implemented. */ -void SPIClass::usingInterrupt(uint8_t interruptNumber) +void SPIClass::usingInterrupt(int interruptNumber) +{ + UNUSED(interruptNumber); +} + +/** + * @brief Not implemented. + */ +void SPIClass::notUsingInterrupt(int interruptNumber) { UNUSED(interruptNumber); } diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index f8e41bea5c..9509c871eb 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -38,12 +38,6 @@ extern "C" { #define SPI_CLOCK_DIV64 64 #define SPI_CLOCK_DIV128 128 -// SPI mode parameters for SPISettings -#define SPI_MODE0 0x00 -#define SPI_MODE1 0x01 -#define SPI_MODE2 0x02 -#define SPI_MODE3 0x03 - #define SPI_TRANSMITRECEIVE 0x0 #define SPI_TRANSMITONLY 0x1 @@ -54,37 +48,105 @@ extern "C" { class SPISettings { public: - constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, bool noRecv = SPI_TRANSMITRECEIVE) - : clk(clock), - bOrder(bitOrder), - dMode((spi_mode_e)( - (SPI_MODE0 == dataMode) ? SPI_MODE_0 : - (SPI_MODE1 == dataMode) ? SPI_MODE_1 : - (SPI_MODE2 == dataMode) ? SPI_MODE_2 : - (SPI_MODE3 == dataMode) ? SPI_MODE_3 : - SPI_MODE0 - )), - noReceive(noRecv) - { } - constexpr SPISettings() - : clk(SPI_SPEED_CLOCK_DEFAULT), - bOrder(MSBFIRST), - dMode(SPI_MODE_0), - noReceive(SPI_TRANSMITRECEIVE) - { } + SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, bool skipRecv = SPI_TRANSMITRECEIVE) + { + if (__builtin_constant_p(clock)) { + init_AlwaysInline(clock, bitOrder, dataMode, skipRecv); + } else { + init_MightInline(clock, bitOrder, dataMode, skipRecv); + } + } + + SPISettings(uint32_t clock, BitOrder bitOrder, int dataMode, bool skipRecv = SPI_TRANSMITRECEIVE) + { + if (__builtin_constant_p(clock)) { + init_AlwaysInline(clock, bitOrder, (SPIMode)dataMode, skipRecv); + } else { + init_MightInline(clock, bitOrder, (SPIMode)dataMode, skipRecv); + } + } + + // Default speed set to 4MHz, SPI mode set to MODE 0 and Bit order set to MSB first. + SPISettings() + { + init_AlwaysInline(SPI_SPEED_CLOCK_DEFAULT, MSBFIRST, SPI_MODE0, SPI_TRANSMITRECEIVE); + } + + bool operator==(const SPISettings &rhs) const + { + if ((this->clockFreq == rhs.clockFreq) && + (this->bitOrder == rhs.bitOrder) && + (this->dataMode == rhs.dataMode) && + (this->skipRecv == rhs.skipRecv)) { + return true; + } + return false; + } + + bool operator!=(const SPISettings &rhs) const + { + return !(*this == rhs); + } + + uint32_t getClockFreq() const + { + return clockFreq; + } + SPIMode getDataMode() const + { + return dataMode; + } + BitOrder getBitOrder() const + { + return (bitOrder); + } + bool getSkipRecv() const + { + return skipRecv; + } + + void setClockFreq(uint32_t clkFreq) + { + clockFreq = clkFreq; + } + void setDataMode(SPIMode mode) + { + dataMode = mode; + } + void setBitOrder(BitOrder order) + { + bitOrder = order; + } + void setSkipRecv(bool skip) + { + skipRecv = skip; + } + private: - uint32_t clk; //specifies the spi bus maximum clock speed - BitOrder bOrder; //bit order (MSBFirst or LSBFirst) - spi_mode_e dMode; //one of the data mode - //Mode Clock Polarity (CPOL) Clock Phase (CPHA) - //SPI_MODE0 0 0 - //SPI_MODE1 0 1 - //SPI_MODE2 1 0 - //SPI_MODE3 1 1 - friend class SPIClass; - bool noReceive; + void init_MightInline(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, bool skipRecv) + { + init_AlwaysInline(clock, bitOrder, dataMode, skipRecv); + } + + // Core developer MUST use an helper function in beginTransaction() to use this data + void init_AlwaysInline(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, bool skipRecv) __attribute__((__always_inline__)) + { + this->clockFreq = clock; + this->dataMode = dataMode; + this->bitOrder = bitOrder; + this->skipRecv = skipRecv; + } + + uint32_t clockFreq; + SPIMode dataMode; + BitOrder bitOrder; + bool skipRecv; + + friend class HardwareSPI; }; +const SPISettings DEFAULT_SPI_SETTINGS = SPISettings(); + class SPIClass { public: SPIClass(); @@ -125,7 +187,7 @@ class SPIClass { _spi.pin_ssel = (ssel); }; - virtual void begin(); + virtual void begin(void); void end(void); /* This function should be used to configure the SPI instance in case you @@ -137,19 +199,21 @@ class SPIClass { /* Transfer functions: must be called after initialization of the SPI * instance with begin() or beginTransaction(). */ - virtual byte transfer(uint8_t _data); + virtual uint8_t transfer(uint8_t _data); virtual uint16_t transfer16(uint16_t _data); - virtual void transfer(void *_buf, size_t _count); + virtual void transfer(void *buf, size_t count); /* These methods are deprecated and kept for compatibility. * Use SPISettings with SPI.beginTransaction() to configure SPI parameters. */ void setBitOrder(BitOrder); void setDataMode(uint8_t); + void setDataMode(SPIMode); void setClockDivider(uint8_t); - // Not implemented functions. Kept for backward compatibility. - void usingInterrupt(uint8_t interruptNumber); + // Not implemented functions. Kept for compatibility. + void usingInterrupt(int interruptNumber); + void notUsingInterrupt(int interruptNumber); void attachInterrupt(void); void detachInterrupt(void); @@ -165,7 +229,7 @@ class SPIClass { private: /* Current SPISettings */ - SPISettings _spiSettings = SPISettings(); + SPISettings _spiSettings = DEFAULT_SPI_SETTINGS; }; extern SPIClass SPI; diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index cfc2c2cc45..bd582681bd 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -227,7 +227,7 @@ static uint32_t compute_disable_delay(spi_t *obj) * @param msb : set to 1 in msb first * @retval None */ -void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb) +void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb) { if (obj == NULL) { return; @@ -313,13 +313,13 @@ void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb) handle->Init.Direction = SPI_DIRECTION_2LINES; - if ((mode == SPI_MODE_0) || (mode == SPI_MODE_2)) { + if ((mode == SPI_MODE0) || (mode == SPI_MODE2)) { handle->Init.CLKPhase = SPI_PHASE_1EDGE; } else { handle->Init.CLKPhase = SPI_PHASE_2EDGE; } - if ((mode == SPI_MODE_0) || (mode == SPI_MODE_1)) { + if ((mode == SPI_MODE0) || (mode == SPI_MODE1)) { handle->Init.CLKPolarity = SPI_POLARITY_LOW; } else { handle->Init.CLKPolarity = SPI_POLARITY_HIGH; diff --git a/libraries/SPI/src/utility/spi_com.h b/libraries/SPI/src/utility/spi_com.h index ee322e6982..7562c08118 100644 --- a/libraries/SPI/src/utility/spi_com.h +++ b/libraries/SPI/src/utility/spi_com.h @@ -85,12 +85,13 @@ typedef struct spi_s spi_t; //SPI_MODE2 1 0 //SPI_MODE3 1 1 //enum definitions coming from SPI.h of SAM +// SPI mode parameters for SPISettings typedef enum { - SPI_MODE_0 = 0x00, - SPI_MODE_1 = 0x01, - SPI_MODE_2 = 0x02, - SPI_MODE_3 = 0x03 -} spi_mode_e; + SPI_MODE0 = 0, + SPI_MODE1 = 1, + SPI_MODE2 = 2, + SPI_MODE3 = 3, +} SPIMode; ///@brief SPI errors typedef enum { @@ -100,7 +101,7 @@ typedef enum { } spi_status_e; /* Exported functions ------------------------------------------------------- */ -void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb); +void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb); void spi_deinit(spi_t *obj); spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, uint32_t Timeout, bool skipReceive); From 0a926cfdb998a112e9a8c042d44402af0ddf1f25 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 9 Nov 2023 17:26:00 +0100 Subject: [PATCH 26/83] ci(example): update BareMinimun.ino Signed-off-by: Frederic Pillon --- CI/build/examples/BareMinimum/BareMinimum.ino | 36 +++++++++---------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/CI/build/examples/BareMinimum/BareMinimum.ino b/CI/build/examples/BareMinimum/BareMinimum.ino index ac299b56f9..404d98c22c 100644 --- a/CI/build/examples/BareMinimum/BareMinimum.ino +++ b/CI/build/examples/BareMinimum/BareMinimum.ino @@ -19,26 +19,25 @@ /* ---------------------------------------------------------------------- Defines each of the tests performed ------------------------------------------------------------------- */ -#define MAX_BLOCKSIZE 2 -#define DELTA (0.0001f) +#define MAX_BLOCKSIZE 2 +#define DELTA (0.0001f) /* ---------------------------------------------------------------------- Test input data for Floating point sin_cos example for 32-blockSize Generated by the MATLAB randn() function ------------------------------------------------------------------- */ -const float32_t testInput_f32[MAX_BLOCKSIZE] = -{ - -1.244916875853235400, -4.793533929171324800 +const float32_t testInput_f32[MAX_BLOCKSIZE] = { + -1.244916875853235400, -4.793533929171324800 }; const float32_t testRefOutput_f32 = 1.000000000; /* ---------------------------------------------------------------------- Declare Global variables ------------------------------------------------------------------- */ uint32_t blockSize = 2; -float32_t testOutput; -float32_t cosOutput; -float32_t sinOutput; -float32_t cosSquareOutput; -float32_t sinSquareOutput; +float32_t testOutput; +float32_t cosOutput; +float32_t sinOutput; +float32_t cosSquareOutput; +float32_t sinSquareOutput; /* ---------------------------------------------------------------------- Max magnitude FFT Bin test ------------------------------------------------------------------- */ @@ -46,11 +45,11 @@ arm_status status; /* CMSIS_DSP */ #ifndef USER_BTN -#define USER_BTN 2 +#define USER_BTN 2 #endif #ifndef LED_BUILTIN -#define LED_BUILTIN 13 +#define LED_BUILTIN 13 #endif #ifndef PIN_SERIAL_RX @@ -72,8 +71,7 @@ SoftwareSerial swSerial(10, 11); void setup() { // Serial HW & SW -#if (!defined(USBD_USE_CDC) && !defined(DISABLE_GENERIC_SERIALUSB)) &&\ - (!defined(VIRTIOCON) && !defined(DISABLE_GENERIC_SERIALVIRTIO)) +#if (!defined(USBD_USE_CDC) && !defined(DISABLE_GENERIC_SERIALUSB)) && (!defined(VIRTIOCON) && !defined(DISABLE_GENERIC_SERIALVIRTIO)) Serial.setRx(PIN_SERIAL_RX); Serial.setTx(digitalPinToPinName(PIN_SERIAL_TX)); #endif @@ -92,7 +90,7 @@ void setup() { // EEPROM byte value = EEPROM.read(0x01); - EEPROM.write(EEPROM.length()-1, value); + EEPROM.write(EEPROM.length() - 1, value); #ifndef STM32MP1xx // IWDG @@ -111,13 +109,13 @@ void setup() { #endif // SPI - SPISettings settings(SPI_SPEED_CLOCK_DEFAULT, MSBFIRST, SPI_MODE_0); + SPISettings settings(SPI_SPEED_CLOCK_DEFAULT, MSBFIRST, SPI_MODE0); SPI.setMISO(PIN_SPI_MISO); SPI.setMOSI(PIN_SPI_MOSI); SPI.setSCLK(PIN_SPI_SCK); SPI.setSSEL(digitalPinToPinName(PIN_SPI_SS)); - SPI.begin(PIN_SPI_SS); - SPI.beginTransaction(1, settings); + SPI.begin(); + SPI.beginTransaction(settings); SPI.endTransaction(); SPI.transfer(1); SPI.end(); @@ -146,7 +144,7 @@ void setup() { diff = fabsf(testRefOutput_f32 - testOutput); /* Comparison of sin_cos value with reference */ status = (diff > DELTA) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; - if ( status == ARM_MATH_TEST_FAILURE) { + if (status == ARM_MATH_TEST_FAILURE) { break; } } From d21f82957416c1e95ffeb95072b32b2aeef6b7a4 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 15 Nov 2023 16:07:26 +0100 Subject: [PATCH 27/83] feat: support compiler.optimization_flags for Arduino IDE 2.X Fixes #2159 Signed-off-by: Frederic Pillon --- platform.txt | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/platform.txt b/platform.txt index 6c6f00e27c..18b5b246f5 100644 --- a/platform.txt +++ b/platform.txt @@ -17,6 +17,12 @@ compiler.warning_flags.default= compiler.warning_flags.more=-Wall compiler.warning_flags.all=-Wall -Wextra +# EXPERIMENTAL feature: optimization flags +# - this is alpha and may be subject to change without notice +compiler.optimization_flags={compiler.optimization_flags} +compiler.optimization_flags.release={build.flags.optimize} {build.flags.debug} +compiler.optimization_flags.debug=-Og -g + compiler.path={runtime.tools.xpack-arm-none-eabi-gcc-12.2.1-1.2.path}/bin/ compiler.S.cmd=arm-none-eabi-gcc @@ -32,13 +38,13 @@ compiler.extra_flags=-mcpu={build.mcu} {build.fpu} {build.float-abi} -DVECT_TAB_ compiler.S.flags={compiler.extra_flags} -c -x assembler-with-cpp {compiler.stm.extra_include} -compiler.c.flags={compiler.extra_flags} -c {build.flags.optimize} {build.flags.debug} {compiler.warning_flags} -std={compiler.c.std} -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -MMD {compiler.stm.extra_include} +compiler.c.flags={compiler.extra_flags} -c {compiler.optimization_flags} {compiler.warning_flags} -std={compiler.c.std} -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -MMD {compiler.stm.extra_include} -compiler.cpp.flags={compiler.extra_flags} -c {build.flags.optimize} {build.flags.debug} {compiler.warning_flags} -std={compiler.cpp.std} -ffunction-sections -fdata-sections -fno-threadsafe-statics --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -fno-use-cxa-atexit -MMD {compiler.stm.extra_include} +compiler.cpp.flags={compiler.extra_flags} -c {compiler.optimization_flags} {compiler.warning_flags} -std={compiler.cpp.std} -ffunction-sections -fdata-sections -fno-threadsafe-statics --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -fno-use-cxa-atexit -MMD {compiler.stm.extra_include} compiler.ar.flags=rcs -compiler.c.elf.flags=-mcpu={build.mcu} {build.fpu} {build.float-abi} -mthumb {build.flags.optimize} {build.flags.debug} {build.flags.ldspecs} -Wl,--defsym=LD_FLASH_OFFSET={build.flash_offset} -Wl,--defsym=LD_MAX_SIZE={upload.maximum_size} -Wl,--defsym=LD_MAX_DATA_SIZE={upload.maximum_data_size} -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common +compiler.c.elf.flags=-mcpu={build.mcu} {build.fpu} {build.float-abi} -mthumb {compiler.optimization_flags} {build.flags.ldspecs} -Wl,--defsym=LD_FLASH_OFFSET={build.flash_offset} -Wl,--defsym=LD_MAX_SIZE={upload.maximum_size} -Wl,--defsym=LD_MAX_DATA_SIZE={upload.maximum_data_size} -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0 From 90be73c6c78d0cd77061dcfcfc0590490711863b Mon Sep 17 00:00:00 2001 From: Shreyas Kulkarni Date: Fri, 10 Nov 2023 23:29:51 +0530 Subject: [PATCH 28/83] variants(F7): add generic F723I(C-E)(K-T)_F730I8K_F733IE(K-T) Signed-off-by: Shreyas Kulkarni Co-authored-by: Frederic Pillon --- README.md | 6 +- boards.txt | 56 ++++++ .../generic_clock.c | 61 +++++- .../ldscript.ld | 183 ++++++++++++++++++ 4 files changed, 300 insertions(+), 6 deletions(-) create mode 100644 variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/ldscript.ld diff --git a/README.md b/README.md index d1534a8efa..664b4d0090 100644 --- a/README.md +++ b/README.md @@ -383,8 +383,12 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :----: | :-------: | ---- | :-----: | :---- | | :green_heart: | STM32F722RC
STM32F722RE | Generic Board | *2.3.0* | | | :green_heart: | STM32F722ZC
STM32F722ZE | Generic Board | *2.4.0* | | -| :green_heart: | STM32F730R8
STM32F732RE | Generic Board | *2.3.0* | | +| :yellow_heart: | STM32F723IC
STM32F723IE | Generic Board | **2.7.0** | | +| :yellow_heart: | STM32F730I8K | Generic Board | **2.7.0** | | +| :green_heart: | STM32F730R8 | Generic Board | *2.3.0* | | +| :green_heart: | STM32F732RE | Generic Board | *2.3.0* | | | :green_heart: | STM32F732ZE | Generic Board | *2.4.0* | | +| :yellow_heart: | STM32F733IE
| Generic Board | **2.7.0** | | | :green_heart: | STM32F745ZE
STM32F745ZG | Generic Board | *2.0.0* | | | :green_heart: | STM32F746BE
STM32F746BG
STM32F746NE
STM32F746NG | Generic Board | *2.0.0* | | | :green_heart: | STM32F746ZE
STM32F746ZG | Generic Board | *2.0.0* | | diff --git a/boards.txt b/boards.txt index a4a192a0e3..23e9d17871 100644 --- a/boards.txt +++ b/boards.txt @@ -4628,6 +4628,46 @@ GenF7.menu.pnum.GENERIC_F722ZETX.build.board=GENERIC_F722ZETX GenF7.menu.pnum.GENERIC_F722ZETX.build.product_line=STM32F722xx GenF7.menu.pnum.GENERIC_F722ZETX.build.variant=STM32F7xx/F722Z(C-E)T_F732ZET +# Generic F723ICKx +GenF7.menu.pnum.GENERIC_F723ICKX=Generic F723ICKx +GenF7.menu.pnum.GENERIC_F723ICKX.upload.maximum_size=262144 +GenF7.menu.pnum.GENERIC_F723ICKX.upload.maximum_data_size=196608 +GenF7.menu.pnum.GENERIC_F723ICKX.build.board=GENERIC_F723ICKX +GenF7.menu.pnum.GENERIC_F723ICKX.build.product_line=STM32F723xx +GenF7.menu.pnum.GENERIC_F723ICKX.build.variant=STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T) + +# Generic F723ICTx +GenF7.menu.pnum.GENERIC_F723ICTX=Generic F723ICTx +GenF7.menu.pnum.GENERIC_F723ICTX.upload.maximum_size=262144 +GenF7.menu.pnum.GENERIC_F723ICTX.upload.maximum_data_size=196608 +GenF7.menu.pnum.GENERIC_F723ICTX.build.board=GENERIC_F723ICTX +GenF7.menu.pnum.GENERIC_F723ICTX.build.product_line=STM32F723xx +GenF7.menu.pnum.GENERIC_F723ICTX.build.variant=STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T) + +# Generic F723IEKx +GenF7.menu.pnum.GENERIC_F723IEKX=Generic F723IEKx +GenF7.menu.pnum.GENERIC_F723IEKX.upload.maximum_size=524288 +GenF7.menu.pnum.GENERIC_F723IEKX.upload.maximum_data_size=196608 +GenF7.menu.pnum.GENERIC_F723IEKX.build.board=GENERIC_F723IEKX +GenF7.menu.pnum.GENERIC_F723IEKX.build.product_line=STM32F723xx +GenF7.menu.pnum.GENERIC_F723IEKX.build.variant=STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T) + +# Generic F723IETx +GenF7.menu.pnum.GENERIC_F723IETX=Generic F723IETx +GenF7.menu.pnum.GENERIC_F723IETX.upload.maximum_size=524288 +GenF7.menu.pnum.GENERIC_F723IETX.upload.maximum_data_size=196608 +GenF7.menu.pnum.GENERIC_F723IETX.build.board=GENERIC_F723IETX +GenF7.menu.pnum.GENERIC_F723IETX.build.product_line=STM32F723xx +GenF7.menu.pnum.GENERIC_F723IETX.build.variant=STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T) + +# Generic F730I8Kx +GenF7.menu.pnum.GENERIC_F730I8KX=Generic F730I8Kx +GenF7.menu.pnum.GENERIC_F730I8KX.upload.maximum_size=65536 +GenF7.menu.pnum.GENERIC_F730I8KX.upload.maximum_data_size=196608 +GenF7.menu.pnum.GENERIC_F730I8KX.build.board=GENERIC_F730I8KX +GenF7.menu.pnum.GENERIC_F730I8KX.build.product_line=STM32F730xx +GenF7.menu.pnum.GENERIC_F730I8KX.build.variant=STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T) + # Generic F730R8Tx GenF7.menu.pnum.GENERIC_F730R8TX=Generic F730R8Tx GenF7.menu.pnum.GENERIC_F730R8TX.upload.maximum_size=65536 @@ -4652,6 +4692,22 @@ GenF7.menu.pnum.GENERIC_F732ZETX.build.board=GENERIC_F732ZETX GenF7.menu.pnum.GENERIC_F732ZETX.build.product_line=STM32F732xx GenF7.menu.pnum.GENERIC_F732ZETX.build.variant=STM32F7xx/F722Z(C-E)T_F732ZET +# Generic F733IEKx +GenF7.menu.pnum.GENERIC_F733IEKX=Generic F733IEKx +GenF7.menu.pnum.GENERIC_F733IEKX.upload.maximum_size=524288 +GenF7.menu.pnum.GENERIC_F733IEKX.upload.maximum_data_size=196608 +GenF7.menu.pnum.GENERIC_F733IEKX.build.board=GENERIC_F733IEKX +GenF7.menu.pnum.GENERIC_F733IEKX.build.product_line=STM32F733xx +GenF7.menu.pnum.GENERIC_F733IEKX.build.variant=STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T) + +# Generic F733IETx +GenF7.menu.pnum.GENERIC_F733IETX=Generic F733IETx +GenF7.menu.pnum.GENERIC_F733IETX.upload.maximum_size=524288 +GenF7.menu.pnum.GENERIC_F733IETX.upload.maximum_data_size=196608 +GenF7.menu.pnum.GENERIC_F733IETX.build.board=GENERIC_F733IETX +GenF7.menu.pnum.GENERIC_F733IETX.build.product_line=STM32F733xx +GenF7.menu.pnum.GENERIC_F733IETX.build.variant=STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T) + # Generic F745ZETx GenF7.menu.pnum.GENERIC_F745ZETX=Generic F745ZETx GenF7.menu.pnum.GENERIC_F745ZETX.upload.maximum_size=524288 diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/generic_clock.c b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/generic_clock.c index 133409760d..ac1f2886a6 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/generic_clock.c +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/generic_clock.c @@ -17,14 +17,65 @@ #include "pins_arduino.h" /** - * @brief System Clock Configuration - * @param None - * @retval None - */ + * @brief System Clock Configuration + * @param None + * @retval None + */ WEAK void SystemClock_Config(void) { /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/ldscript.ld b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/ldscript.ld new file mode 100644 index 0000000000..b1bb71f37f --- /dev/null +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/ldscript.ld @@ -0,0 +1,183 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for F723I(C-E)(K-T)_F730I8K_F733IE(K-T) Devices from STM32F7 series +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From a58d6ebdf3a0efbe84aae82db9ba6c6851956fef Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 16 Nov 2023 09:07:29 +0100 Subject: [PATCH 29/83] ci(build): update generic variants list to skip Signed-off-by: Frederic Pillon --- CI/build/conf/cores_config.json | 6 ++++++ CI/build/conf/cores_config_ci.json | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index 91d4d3af5a..bd679e0924 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -277,7 +277,13 @@ "GENERIC_F722RETX", "GENERIC_F722ZCTX", "GENERIC_F722ZETX", + "GENERIC_F723ICKX", + "GENERIC_F723ICTX", + "GENERIC_F723IEKX", + "GENERIC_F723IETX", + "GENERIC_F730I8KX", "GENERIC_F730R8TX", + "GENERIC_F733IEKX", "GENERIC_F745ZETX", "GENERIC_F745ZGTX", "GENERIC_F746BETX", diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json index 61d024436f..d6510018ba 100644 --- a/CI/build/conf/cores_config_ci.json +++ b/CI/build/conf/cores_config_ci.json @@ -277,7 +277,13 @@ "GENERIC_F722RETX", "GENERIC_F722ZCTX", "GENERIC_F722ZETX", + "GENERIC_F723ICKX", + "GENERIC_F723ICTX", + "GENERIC_F723IEKX", + "GENERIC_F723IETX", + "GENERIC_F730I8KX", "GENERIC_F730R8TX", + "GENERIC_F733IEKX", "GENERIC_F745ZETX", "GENERIC_F745ZGTX", "GENERIC_F746BETX", From ed8ba842c775bcb4e4072a41763dac626178e006 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 16 Nov 2023 09:08:02 +0100 Subject: [PATCH 30/83] chore(cmake): update files Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 574 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 574 insertions(+) diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index efb6d9af9b..ef9956129f 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -47600,6 +47600,416 @@ target_compile_options(GENERIC_F722ZETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_F723ICKX +# ----------------------------------------------------------------------------- + +set(GENERIC_F723ICKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)") +set(GENERIC_F723ICKX_MAXSIZE 262144) +set(GENERIC_F723ICKX_MAXDATASIZE 196608) +set(GENERIC_F723ICKX_MCU cortex-m7) +set(GENERIC_F723ICKX_FPCONF "-") +add_library(GENERIC_F723ICKX INTERFACE) +target_compile_options(GENERIC_F723ICKX INTERFACE + "SHELL:-DSTM32F723xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F723ICKX_MCU} +) +target_compile_definitions(GENERIC_F723ICKX INTERFACE + "STM32F7xx" + "ARDUINO_GENERIC_F723ICKX" + "BOARD_NAME=\"GENERIC_F723ICKX\"" + "BOARD_ID=GENERIC_F723ICKX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F723ICKX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ + ${GENERIC_F723ICKX_VARIANT_PATH} +) + +target_link_options(GENERIC_F723ICKX INTERFACE + "LINKER:--default-script=${GENERIC_F723ICKX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F723ICKX_MCU} +) + +add_library(GENERIC_F723ICKX_serial_disabled INTERFACE) +target_compile_options(GENERIC_F723ICKX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_F723ICKX_serial_generic INTERFACE) +target_compile_options(GENERIC_F723ICKX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_F723ICKX_serial_none INTERFACE) +target_compile_options(GENERIC_F723ICKX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_F723ICKX_usb_CDC INTERFACE) +target_compile_options(GENERIC_F723ICKX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_F723ICKX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_F723ICKX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_F723ICKX_usb_HID INTERFACE) +target_compile_options(GENERIC_F723ICKX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_F723ICKX_usb_none INTERFACE) +target_compile_options(GENERIC_F723ICKX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_F723ICKX_xusb_FS INTERFACE) +target_compile_options(GENERIC_F723ICKX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_F723ICKX_xusb_HS INTERFACE) +target_compile_options(GENERIC_F723ICKX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_F723ICKX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_F723ICKX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_F723ICTX +# ----------------------------------------------------------------------------- + +set(GENERIC_F723ICTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)") +set(GENERIC_F723ICTX_MAXSIZE 262144) +set(GENERIC_F723ICTX_MAXDATASIZE 196608) +set(GENERIC_F723ICTX_MCU cortex-m7) +set(GENERIC_F723ICTX_FPCONF "-") +add_library(GENERIC_F723ICTX INTERFACE) +target_compile_options(GENERIC_F723ICTX INTERFACE + "SHELL:-DSTM32F723xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F723ICTX_MCU} +) +target_compile_definitions(GENERIC_F723ICTX INTERFACE + "STM32F7xx" + "ARDUINO_GENERIC_F723ICTX" + "BOARD_NAME=\"GENERIC_F723ICTX\"" + "BOARD_ID=GENERIC_F723ICTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F723ICTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ + ${GENERIC_F723ICTX_VARIANT_PATH} +) + +target_link_options(GENERIC_F723ICTX INTERFACE + "LINKER:--default-script=${GENERIC_F723ICTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F723ICTX_MCU} +) + +add_library(GENERIC_F723ICTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_F723ICTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_F723ICTX_serial_generic INTERFACE) +target_compile_options(GENERIC_F723ICTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_F723ICTX_serial_none INTERFACE) +target_compile_options(GENERIC_F723ICTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_F723ICTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_F723ICTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_F723ICTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_F723ICTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_F723ICTX_usb_HID INTERFACE) +target_compile_options(GENERIC_F723ICTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_F723ICTX_usb_none INTERFACE) +target_compile_options(GENERIC_F723ICTX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_F723ICTX_xusb_FS INTERFACE) +target_compile_options(GENERIC_F723ICTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_F723ICTX_xusb_HS INTERFACE) +target_compile_options(GENERIC_F723ICTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_F723ICTX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_F723ICTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_F723IEKX +# ----------------------------------------------------------------------------- + +set(GENERIC_F723IEKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)") +set(GENERIC_F723IEKX_MAXSIZE 524288) +set(GENERIC_F723IEKX_MAXDATASIZE 196608) +set(GENERIC_F723IEKX_MCU cortex-m7) +set(GENERIC_F723IEKX_FPCONF "-") +add_library(GENERIC_F723IEKX INTERFACE) +target_compile_options(GENERIC_F723IEKX INTERFACE + "SHELL:-DSTM32F723xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F723IEKX_MCU} +) +target_compile_definitions(GENERIC_F723IEKX INTERFACE + "STM32F7xx" + "ARDUINO_GENERIC_F723IEKX" + "BOARD_NAME=\"GENERIC_F723IEKX\"" + "BOARD_ID=GENERIC_F723IEKX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F723IEKX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ + ${GENERIC_F723IEKX_VARIANT_PATH} +) + +target_link_options(GENERIC_F723IEKX INTERFACE + "LINKER:--default-script=${GENERIC_F723IEKX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F723IEKX_MCU} +) + +add_library(GENERIC_F723IEKX_serial_disabled INTERFACE) +target_compile_options(GENERIC_F723IEKX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_F723IEKX_serial_generic INTERFACE) +target_compile_options(GENERIC_F723IEKX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_F723IEKX_serial_none INTERFACE) +target_compile_options(GENERIC_F723IEKX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_F723IEKX_usb_CDC INTERFACE) +target_compile_options(GENERIC_F723IEKX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_F723IEKX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_F723IEKX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_F723IEKX_usb_HID INTERFACE) +target_compile_options(GENERIC_F723IEKX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_F723IEKX_usb_none INTERFACE) +target_compile_options(GENERIC_F723IEKX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_F723IEKX_xusb_FS INTERFACE) +target_compile_options(GENERIC_F723IEKX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_F723IEKX_xusb_HS INTERFACE) +target_compile_options(GENERIC_F723IEKX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_F723IEKX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_F723IEKX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_F723IETX +# ----------------------------------------------------------------------------- + +set(GENERIC_F723IETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)") +set(GENERIC_F723IETX_MAXSIZE 524288) +set(GENERIC_F723IETX_MAXDATASIZE 196608) +set(GENERIC_F723IETX_MCU cortex-m7) +set(GENERIC_F723IETX_FPCONF "-") +add_library(GENERIC_F723IETX INTERFACE) +target_compile_options(GENERIC_F723IETX INTERFACE + "SHELL:-DSTM32F723xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F723IETX_MCU} +) +target_compile_definitions(GENERIC_F723IETX INTERFACE + "STM32F7xx" + "ARDUINO_GENERIC_F723IETX" + "BOARD_NAME=\"GENERIC_F723IETX\"" + "BOARD_ID=GENERIC_F723IETX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F723IETX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ + ${GENERIC_F723IETX_VARIANT_PATH} +) + +target_link_options(GENERIC_F723IETX INTERFACE + "LINKER:--default-script=${GENERIC_F723IETX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F723IETX_MCU} +) + +add_library(GENERIC_F723IETX_serial_disabled INTERFACE) +target_compile_options(GENERIC_F723IETX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_F723IETX_serial_generic INTERFACE) +target_compile_options(GENERIC_F723IETX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_F723IETX_serial_none INTERFACE) +target_compile_options(GENERIC_F723IETX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_F723IETX_usb_CDC INTERFACE) +target_compile_options(GENERIC_F723IETX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_F723IETX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_F723IETX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_F723IETX_usb_HID INTERFACE) +target_compile_options(GENERIC_F723IETX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_F723IETX_usb_none INTERFACE) +target_compile_options(GENERIC_F723IETX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_F723IETX_xusb_FS INTERFACE) +target_compile_options(GENERIC_F723IETX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_F723IETX_xusb_HS INTERFACE) +target_compile_options(GENERIC_F723IETX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_F723IETX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_F723IETX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_F730I8KX +# ----------------------------------------------------------------------------- + +set(GENERIC_F730I8KX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)") +set(GENERIC_F730I8KX_MAXSIZE 65536) +set(GENERIC_F730I8KX_MAXDATASIZE 196608) +set(GENERIC_F730I8KX_MCU cortex-m7) +set(GENERIC_F730I8KX_FPCONF "-") +add_library(GENERIC_F730I8KX INTERFACE) +target_compile_options(GENERIC_F730I8KX INTERFACE + "SHELL:-DSTM32F730xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F730I8KX_MCU} +) +target_compile_definitions(GENERIC_F730I8KX INTERFACE + "STM32F7xx" + "ARDUINO_GENERIC_F730I8KX" + "BOARD_NAME=\"GENERIC_F730I8KX\"" + "BOARD_ID=GENERIC_F730I8KX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F730I8KX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ + ${GENERIC_F730I8KX_VARIANT_PATH} +) + +target_link_options(GENERIC_F730I8KX INTERFACE + "LINKER:--default-script=${GENERIC_F730I8KX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F730I8KX_MCU} +) + +add_library(GENERIC_F730I8KX_serial_disabled INTERFACE) +target_compile_options(GENERIC_F730I8KX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_F730I8KX_serial_generic INTERFACE) +target_compile_options(GENERIC_F730I8KX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_F730I8KX_serial_none INTERFACE) +target_compile_options(GENERIC_F730I8KX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_F730I8KX_usb_CDC INTERFACE) +target_compile_options(GENERIC_F730I8KX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_F730I8KX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_F730I8KX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_F730I8KX_usb_HID INTERFACE) +target_compile_options(GENERIC_F730I8KX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_F730I8KX_usb_none INTERFACE) +target_compile_options(GENERIC_F730I8KX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_F730I8KX_xusb_FS INTERFACE) +target_compile_options(GENERIC_F730I8KX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_F730I8KX_xusb_HS INTERFACE) +target_compile_options(GENERIC_F730I8KX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_F730I8KX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_F730I8KX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_F730R8TX # ----------------------------------------------------------------------------- @@ -47846,6 +48256,170 @@ target_compile_options(GENERIC_F732ZETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_F733IEKX +# ----------------------------------------------------------------------------- + +set(GENERIC_F733IEKX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)") +set(GENERIC_F733IEKX_MAXSIZE 524288) +set(GENERIC_F733IEKX_MAXDATASIZE 196608) +set(GENERIC_F733IEKX_MCU cortex-m7) +set(GENERIC_F733IEKX_FPCONF "-") +add_library(GENERIC_F733IEKX INTERFACE) +target_compile_options(GENERIC_F733IEKX INTERFACE + "SHELL:-DSTM32F733xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F733IEKX_MCU} +) +target_compile_definitions(GENERIC_F733IEKX INTERFACE + "STM32F7xx" + "ARDUINO_GENERIC_F733IEKX" + "BOARD_NAME=\"GENERIC_F733IEKX\"" + "BOARD_ID=GENERIC_F733IEKX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F733IEKX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ + ${GENERIC_F733IEKX_VARIANT_PATH} +) + +target_link_options(GENERIC_F733IEKX INTERFACE + "LINKER:--default-script=${GENERIC_F733IEKX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F733IEKX_MCU} +) + +add_library(GENERIC_F733IEKX_serial_disabled INTERFACE) +target_compile_options(GENERIC_F733IEKX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_F733IEKX_serial_generic INTERFACE) +target_compile_options(GENERIC_F733IEKX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_F733IEKX_serial_none INTERFACE) +target_compile_options(GENERIC_F733IEKX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_F733IEKX_usb_CDC INTERFACE) +target_compile_options(GENERIC_F733IEKX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_F733IEKX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_F733IEKX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_F733IEKX_usb_HID INTERFACE) +target_compile_options(GENERIC_F733IEKX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_F733IEKX_usb_none INTERFACE) +target_compile_options(GENERIC_F733IEKX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_F733IEKX_xusb_FS INTERFACE) +target_compile_options(GENERIC_F733IEKX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_F733IEKX_xusb_HS INTERFACE) +target_compile_options(GENERIC_F733IEKX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_F733IEKX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_F733IEKX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_F733IETX +# ----------------------------------------------------------------------------- + +set(GENERIC_F733IETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)") +set(GENERIC_F733IETX_MAXSIZE 524288) +set(GENERIC_F733IETX_MAXDATASIZE 196608) +set(GENERIC_F733IETX_MCU cortex-m7) +set(GENERIC_F733IETX_FPCONF "-") +add_library(GENERIC_F733IETX INTERFACE) +target_compile_options(GENERIC_F733IETX INTERFACE + "SHELL:-DSTM32F733xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F733IETX_MCU} +) +target_compile_definitions(GENERIC_F733IETX INTERFACE + "STM32F7xx" + "ARDUINO_GENERIC_F733IETX" + "BOARD_NAME=\"GENERIC_F733IETX\"" + "BOARD_ID=GENERIC_F733IETX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F733IETX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ + ${GENERIC_F733IETX_VARIANT_PATH} +) + +target_link_options(GENERIC_F733IETX INTERFACE + "LINKER:--default-script=${GENERIC_F733IETX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F733IETX_MCU} +) + +add_library(GENERIC_F733IETX_serial_disabled INTERFACE) +target_compile_options(GENERIC_F733IETX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_F733IETX_serial_generic INTERFACE) +target_compile_options(GENERIC_F733IETX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_F733IETX_serial_none INTERFACE) +target_compile_options(GENERIC_F733IETX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_F733IETX_usb_CDC INTERFACE) +target_compile_options(GENERIC_F733IETX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_F733IETX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_F733IETX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_F733IETX_usb_HID INTERFACE) +target_compile_options(GENERIC_F733IETX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_F733IETX_usb_none INTERFACE) +target_compile_options(GENERIC_F733IETX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_F733IETX_xusb_FS INTERFACE) +target_compile_options(GENERIC_F733IETX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_F733IETX_xusb_HS INTERFACE) +target_compile_options(GENERIC_F733IETX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_F733IETX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_F733IETX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_F745ZETX # ----------------------------------------------------------------------------- From e283b8ce0e23bd9cafb416599f526935514b8553 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 16 Nov 2023 10:45:39 +0100 Subject: [PATCH 31/83] fix(nucleo_G474RE): wrong SystemClock_Config configuration Signed-off-by: Frederic Pillon --- .../variant_NUCLEO_G474RE.cpp | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET/variant_NUCLEO_G474RE.cpp b/variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET/variant_NUCLEO_G474RE.cpp index cceaf69562..8d80757b57 100644 --- a/variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET/variant_NUCLEO_G474RE.cpp +++ b/variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET/variant_NUCLEO_G474RE.cpp @@ -106,22 +106,23 @@ WEAK void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; -#ifdef USBCON RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; -#endif /* Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); /* Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; - RCC_OscInitStruct.PLL.PLLN = 28; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6; + RCC_OscInitStruct.PLL.PLLN = 85; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV6; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -134,18 +135,17 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); } -#ifdef USBCON /* Initializes the peripherals clocks */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); } -#endif } #ifdef __cplusplus From 4e90a1a78d7f69439fa2e280c604f4dca79bf843 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 16 Nov 2023 11:16:44 +0100 Subject: [PATCH 32/83] fix(nucleo_G431KB): add missing analog pin Signed-off-by: Frederic Pillon --- .../G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.cpp | 3 ++- .../G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.h | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.cpp b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.cpp index fa6fad23c4..b65c00253d 100644 --- a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.cpp +++ b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.cpp @@ -49,7 +49,8 @@ const uint32_t analogInputPin[] = { 18, // A4 19, // A5 20, // A6 - 21 // A7 + 21, // A7 + 3 // A8 }; // ---------------------------------------------------------------------------- diff --git a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.h b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.h index 0aa0bbe752..2de47e4ba0 100644 --- a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.h +++ b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/variant_NUCLEO_G431KB.h @@ -19,7 +19,7 @@ #define PA10 0 #define PA9 1 #define PA12 2 -#define PB0 3 +#define PB0 PIN_A8 #define PB7 4 #define PA15 5 #define PB6 6 @@ -78,7 +78,7 @@ // This must be a literal #define NUM_DIGITAL_PINS 25 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS -#define NUM_ANALOG_INPUTS 8 +#define NUM_ANALOG_INPUTS 9 // On-board LED pin number #ifndef LED_BUILTIN From 01b599b13cd76436297d70ad3490ff15c389fe79 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 16 Nov 2023 15:09:49 +0100 Subject: [PATCH 33/83] chore: bump release version to 2.7.0 Signed-off-by: Frederic Pillon --- README.md | 48 ++++++++++++++++++--------------- cores/arduino/stm32/stm32_def.h | 2 +- platform.txt | 2 +- 3 files changed, 28 insertions(+), 24 deletions(-) diff --git a/README.md b/README.md index 664b4d0090..e0da18c1b0 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,7 @@ [![GitHub release](https://img.shields.io/github/release/stm32duino/Arduino_Core_STM32.svg)](https://github.com/stm32duino/Arduino_Core_STM32/releases/latest) ![GitHub All Releases](https://img.shields.io/github/downloads/stm32duino/Arduino_Core_STM32/total.svg?label=downloads%20since%201.4.0) -[![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/2.6.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/2.6.0...main) +[![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/2.7.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/2.7.0...main) * [Introduction](https://github.com/stm32duino/Arduino_Core_STM32#Introduction)
@@ -84,6 +84,10 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d - [Midatronics boards](#midatronics-boards) - [SparkFun boards](#sparkfun-boards) +**Note about Status**: + - :green_heart: board support is available since the specified release version. + - :yellow_heart: board support is available in the main branch and will be available in the specified release version. + ### [Nucleo 144](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-nucleo-boards.html) boards | Status | Device(s) | Name | Release | Notes | @@ -92,7 +96,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F412ZG | [Nucleo F412ZG](http://www.st.com/en/evaluation-tools/nucleo-f412zg.html) | *2.6.0* | | | :green_heart: | STM32F413ZH | [Nucleo F413ZH](http://www.st.com/en/evaluation-tools/nucleo-f413zh.html) | *2.4.0* | | | :green_heart: | STM32F429ZI | [Nucleo F429ZI](http://www.st.com/en/evaluation-tools/nucleo-f429zi.html) | *0.1.0* | | -| :yellow_heart: | STM32F446ZE | [Nucleo F446ZE](http://www.st.com/en/evaluation-tools/nucleo-f446ze.html) | **2.7.0** | | +| :green_heart: | STM32F446ZE | [Nucleo F446ZE](http://www.st.com/en/evaluation-tools/nucleo-f446ze.html) | *2.7.0* | | | :green_heart: | STM32F722ZE | [Nucleo F722ZE](http://www.st.com/en/evaluation-tools/nucleo-f722ze.html) | *2.4.0* | | | :green_heart: | STM32F767ZI | [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) | *1.4.0* | | | :green_heart: | STM32F746ZG | [Nucleo F746ZG](https://www.st.com/en/evaluation-tools/nucleo-f746zg.html) | *1.9.0* | | @@ -100,7 +104,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H563ZI | [Nucleo H563ZI](https://www.st.com/en/evaluation-tools/nucleo-h563zi.html) | *2.6.0* | | | :green_heart: | STM32H723ZG | [Nucleo H723ZG](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html) | *2.4.0* | | | :green_heart: | STM32H743ZI | [Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) | *1.5.0* | Nucleo H743ZI2 since 1.6.0 | -| :yellow_heart: | STM32H753ZI | [Nucleo H753ZI](https://www.st.com/en/evaluation-tools/nucleo-h753zi.html) | **2.7.0** | | +| :green_heart: | STM32H753ZI | [Nucleo H753ZI](https://www.st.com/en/evaluation-tools/nucleo-h753zi.html) | *2.7.0* | | | :green_heart: | STM32L496ZG | [Nucleo L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) | *1.3.0* | | | :green_heart: | STM32L496ZG-P | [Nucleo L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) | *1.3.0* | | | :green_heart: | STM32L4R5ZI | [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) | *1.4.0* | | @@ -128,7 +132,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32G0B1RE | [Nucleo G0B1RE](https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html) | *2.1.0* | | | :green_heart: | STM32G431RB | [Nucleo G431RB](https://www.st.com/en/evaluation-tools/nucleo-g431rb.html) | *1.7.0* | | | :green_heart: | STM32G474RE | [Nucleo G474RE](https://www.st.com/en/evaluation-tools/nucleo-g474re.html) | *1.7.0* | | -| :yellow_heart: | STM32H503RB | [Nucleo H503RB](https://www.st.com/en/evaluation-tools/nucleo-h503rb.html) | **2.7.0** | | +| :green_heart: | STM32H503RB | [Nucleo H503RB](https://www.st.com/en/evaluation-tools/nucleo-h503rb.html) | *2.7.0* | | | :green_heart: | STM32L010RB | [Nucleo L010RB](https://www.st.com/en/evaluation-tools/nucleo-l010rb.html) | *2.1.0* | | | :green_heart: | STM32L053R8 | [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) | *0.1.0* | | | :green_heart: | STM32L073RZ | [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) | *1.4.0* | | @@ -171,8 +175,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F746NG | [STM32F746G-DISCOVERY](http://www.st.com/en/evaluation-tools/32f746gdiscovery.html) | *0.1.0* | | | :green_heart: | STM32G031J6 | [STM32G0316-DISCO](https://www.st.com/en/evaluation-tools/stm32g0316-disco.html) | *1.9.0* | | | :green_heart: | STM32G431CB | [B-G431B-ESC1](https://www.st.com/en/evaluation-tools/b-g431b-esc1.html) | *2.0.0* | | -| :green_heart: | STM32H573IIKxQ | [STM32H573I-DK](https://www.st.com/en/evaluation-tools/stm32h573i-dk.html) | *2.6.0* | | -| :yellow_heart: | STM32H747XIHx | [STM32H747I-DISCO](https://www.st.com/en/evaluation-tools/stm32h747i-disco.html) | **2.7.0** | | +| :green_heart: | STM32H573IIKxQ | [STM32H573I-DK](https://www.st.com/en/evaluation-tools/stm32h573i-dk.html) | *2.6.0* | | +| :green_heart: | STM32H747XIHx | [STM32H747I-DISCO](https://www.st.com/en/evaluation-tools/stm32h747i-disco.html) | *2.7.0* | | | :green_heart: | STM32L4S5VI | [B-L4S5I-IOT01A](https://www.st.com/en/evaluation-tools/b-l4s5i-iot01a.html) | *2.0.0* | | | :green_heart: | STM32U585AIIxQ | [B-U585I-IOT02A](https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html) | *2.1.0* | | | :green_heart: | STM32WB5MMG | [STM32WB5MM-DK](https://www.st.com/en/evaluation-tools/stm32wb5mm-dk.html) | *2.1.0* | | @@ -373,7 +377,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F437ZG
STM32F437ZI | Generic Board | **2.0.0** | | :green_heart: | STM32F439ZG
STM32F439ZI | Generic Board | **2.0.0** | | :green_heart: | STM32F446RC
STM32F446RE | Generic Board | *1.9.0* | | -| :yellow_heart: | STM32F446ZC
STM32F446ZE | Generic Board | **2.7.0** | | +| :green_heart: | STM32F446ZC
STM32F446ZE | Generic Board | *2.7.0* | | | :green_heart: | STM32F446VC
STM32F446VE | Generic Board | **2.0.0** | | :green_heart: | STM32F411CE | [ThunderPack v1.1+](https://github.com/jgillick/ThunderPack) | *1.9.0* | | @@ -383,12 +387,12 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :----: | :-------: | ---- | :-----: | :---- | | :green_heart: | STM32F722RC
STM32F722RE | Generic Board | *2.3.0* | | | :green_heart: | STM32F722ZC
STM32F722ZE | Generic Board | *2.4.0* | | -| :yellow_heart: | STM32F723IC
STM32F723IE | Generic Board | **2.7.0** | | -| :yellow_heart: | STM32F730I8K | Generic Board | **2.7.0** | | +| :green_heart: | STM32F723IC
STM32F723IE | Generic Board | *2.7.0* | | +| :green_heart: | STM32F730I8K | Generic Board | *2.7.0* | | | :green_heart: | STM32F730R8 | Generic Board | *2.3.0* | | | :green_heart: | STM32F732RE | Generic Board | *2.3.0* | | | :green_heart: | STM32F732ZE | Generic Board | *2.4.0* | | -| :yellow_heart: | STM32F733IE
| Generic Board | **2.7.0** | | +| :green_heart: | STM32F733IE
| Generic Board | *2.7.0* | | | :green_heart: | STM32F745ZE
STM32F745ZG | Generic Board | *2.0.0* | | | :green_heart: | STM32F746BE
STM32F746BG
STM32F746NE
STM32F746NG | Generic Board | *2.0.0* | | | :green_heart: | STM32F746ZE
STM32F746ZG | Generic Board | *2.0.0* | | @@ -531,7 +535,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | -| :yellow_heart: | STM32H503RB | Generic Board | **2.7.0** | | +| :green_heart: | STM32H503RB | Generic Board | *2.7.0* | | | :green_heart: | STM32H563IIKxQ | Generic Board | *2.6.0* | | | :green_heart: | STM32H563ZG
STM32H563ZI | Generic Board | *2.6.0* | | | :green_heart: | STM32H573IIKxQ | Generic Board | *2.6.0* | | @@ -546,18 +550,18 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H733ZGT | Generic Board | *2.4.0* | | | :green_heart: | STM32H742IG
STM32H742II | Generic Board | *2.1.0* | | | :green_heart: | STM32H742VG
STM32H742VI | Generic Board | *2.0.0* | | -| :yellow_heart: | STM32H742XG
STM32H742XI | Generic Board | **2.7.0** | | +| :green_heart: | STM32H742XG
STM32H742XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H742ZG
STM32H742ZI | Generic Board | *2.0.0* | | | :green_heart: | STM32H743IG
STM32H743II | Generic Board | *2.0.0* | | | :green_heart: | STM32H743VG
STM32H743VI | Generic Board | *2.0.0* | | | :green_heart: | STM32H743VI | [DevEBox H743VIT6](https://github.com/mcauser/MCUDEV_DEVEBOX_H7XX_M) | *2.2.0* | | | :green_heart: | STM32H743VI | [WeAct MiniSTM32H743VIT6](https://github.com/WeActStudio/MiniSTM32H7xx) | *2.2.0* | [More info](https://github.com/stm32duino/Arduino_Core_STM32/pull/1552) | -| :yellow_heart: | STM32H743XG
STM32H743XI | Generic Board | **2.7.0** | | +| :green_heart: | STM32H743XG
STM32H743XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H743ZG
STM32H743ZI | Generic Board | *2.0.0* | | -| :yellow_heart: | STM32H745XG
STM32H745XI | Generic Board | **2.7.0** | | +| :green_heart: | STM32H745XG
STM32H745XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H747AG
STM32H747AI | Generic Board | *2.0.0* | | | :green_heart: | STM32H747IG
STM32H747II | Generic Board | *2.0.0* | | -| :yellow_heart: | STM32H747XG
STM32H747XI | Generic Board | **2.7.0** | | +| :green_heart: | STM32H747XG
STM32H747XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H750ZB | Generic Board | *2.0.0* | | | :green_heart: | STM32H750IB
STM32H750II | Generic Board | *2.0.0* | | | :green_heart: | STM32H750IB | [Daisy](https://www.electro-smith.com/daisy/daisy) | *1.9.0* | | @@ -566,14 +570,14 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H750VB | Generic Board | *2.0.0* | | | :green_heart: | STM32H750VB | [DevEBox H750VBT6](https://github.com/mcauser/MCUDEV_DEVEBOX_H7XX_M) | *2.2.0* | | | :green_heart: | STM32H750VB | [WeAct MiniSTM32H750VBT6](https://github.com/WeActStudio/MiniSTM32H7xx) | *2.2.0* | [More info](https://github.com/stm32duino/Arduino_Core_STM32/pull/1552) | -| :yellow_heart: | STM32H750XB | Generic Board | **2.7.0** | | +| :green_heart: | STM32H750XB | Generic Board | *2.7.0* | | | :green_heart: | STM32H753VI | Generic Board | *2.0.0* | | -| :yellow_heart: | STM32H753XI | Generic Board | **2.7.0** | | +| :green_heart: | STM32H753XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H753ZI | Generic Board | *2.0.0* | | -| :yellow_heart: | STM32H755XI | Generic Board | **2.7.0** | | +| :green_heart: | STM32H755XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H757AI | Generic Board | *2.0.0* | | | :green_heart: | STM32H757II | Generic Board | *2.0.0* | | -| :yellow_heart: | STM32H757XI | Generic Board | **2.7.0** | | +| :green_heart: | STM32H757XI | Generic Board | *2.7.0* | | ### Generic STM32L0 boards @@ -708,10 +712,10 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | | :green_heart: | STM32U575AGIxQ
STM32U575AIIxQ | Generic Board | *2.1.0* | | -| :yellow_heart: | STM32U575CGx
STM32U575CIx | Generic Board | **2.7.0** | | +| :green_heart: | STM32U575CGx
STM32U575CIx | Generic Board | *2.7.0* | | | :green_heart: | STM32U575ZGTxQ
STM32U575ZITxQ | Generic Board | *2.1.0* | | | :green_heart: | STM32U585AIIxQ | Generic Board | *2.1.0* | | -| :yellow_heart: | STM32U585CIx | Generic Board | **2.7.0** | | +| :green_heart: | STM32U585CIx | Generic Board | *2.7.0* | | | :green_heart: | STM32U585ZITxQ | Generic Board | *2.1.0* | | ### Generic STM32WB boards @@ -792,7 +796,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | -| :yellow_heart: | STM32U585CIU6 | [IoT continuum DevKit Board - STM32U585CIU6](https://iotjourney.orange.com/en/iotcontinuum/kits) | **2.7.0** | | +| :green_heart: | STM32U585CIU6 | [IoT continuum DevKit Board - STM32U585CIU6](https://iotjourney.orange.com/en/iotcontinuum/kits) | *2.7.0* | | ### LoRa boards diff --git a/cores/arduino/stm32/stm32_def.h b/cores/arduino/stm32/stm32_def.h index 46cea8fc10..126cc4c76d 100644 --- a/cores/arduino/stm32/stm32_def.h +++ b/cores/arduino/stm32/stm32_def.h @@ -14,7 +14,7 @@ * [1-9]: release candidate * F[0-9]: development */ -#define STM32_CORE_VERSION_EXTRA (0xF0U) /*!< [7:0] extra version */ +#define STM32_CORE_VERSION_EXTRA (0x00U) /*!< [7:0] extra version */ #define STM32_CORE_VERSION ((STM32_CORE_VERSION_MAJOR << 24U)\ |(STM32_CORE_VERSION_MINOR << 16U)\ |(STM32_CORE_VERSION_PATCH << 8U )\ diff --git a/platform.txt b/platform.txt index 18b5b246f5..ebc1fd98ff 100644 --- a/platform.txt +++ b/platform.txt @@ -5,7 +5,7 @@ # https://arduino.github.io/arduino-cli/latest/platform-specification/ name=STM32 boards groups (Board to be selected from Tools submenu 'Board part number') -version=2.7.0-dev +version=2.7.0 # STM compile variables # ---------------------- From 753366b501a77a0a1855386559430287bb0f061a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 16 Nov 2023 16:15:56 +0100 Subject: [PATCH 34/83] chore: update core version to 2.8.0-dev (0x020800F0) Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32_def.h | 4 ++-- platform.txt | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cores/arduino/stm32/stm32_def.h b/cores/arduino/stm32/stm32_def.h index 126cc4c76d..52a27ff051 100644 --- a/cores/arduino/stm32/stm32_def.h +++ b/cores/arduino/stm32/stm32_def.h @@ -6,7 +6,7 @@ * @brief STM32 core version number */ #define STM32_CORE_VERSION_MAJOR (0x02U) /*!< [31:24] major version */ -#define STM32_CORE_VERSION_MINOR (0x07U) /*!< [23:16] minor version */ +#define STM32_CORE_VERSION_MINOR (0x08U) /*!< [23:16] minor version */ #define STM32_CORE_VERSION_PATCH (0x00U) /*!< [15:8] patch version */ /* * Extra label for development: @@ -14,7 +14,7 @@ * [1-9]: release candidate * F[0-9]: development */ -#define STM32_CORE_VERSION_EXTRA (0x00U) /*!< [7:0] extra version */ +#define STM32_CORE_VERSION_EXTRA (0xF0U) /*!< [7:0] extra version */ #define STM32_CORE_VERSION ((STM32_CORE_VERSION_MAJOR << 24U)\ |(STM32_CORE_VERSION_MINOR << 16U)\ |(STM32_CORE_VERSION_PATCH << 8U )\ diff --git a/platform.txt b/platform.txt index ebc1fd98ff..70da3b5774 100644 --- a/platform.txt +++ b/platform.txt @@ -5,7 +5,7 @@ # https://arduino.github.io/arduino-cli/latest/platform-specification/ name=STM32 boards groups (Board to be selected from Tools submenu 'Board part number') -version=2.7.0 +version=2.8.0-dev # STM compile variables # ---------------------- From 4d69ea75479842f5a7241b3f8a5e6433aaca224d Mon Sep 17 00:00:00 2001 From: jgromes Date: Sat, 18 Nov 2023 17:08:36 +0100 Subject: [PATCH 35/83] Fixed SPI mode --- libraries/SubGhz/src/SubGhz.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/SubGhz/src/SubGhz.h b/libraries/SubGhz/src/SubGhz.h index 178998ad9f..60bb621fad 100644 --- a/libraries/SubGhz/src/SubGhz.h +++ b/libraries/SubGhz/src/SubGhz.h @@ -101,7 +101,7 @@ class SubGhzClass { // supported by the radio, which should always work (no chance of // bad wiring that requires reducing the speed). // This value should be passed to `SubGhz.SPI.beginTransaction()`. - static constexpr SPISettings spi_settings = {16000000, MSBFIRST, SPI_MODE_0}; + static constexpr SPISettings spi_settings = {16000000, MSBFIRST, SPI_MODE0}; protected: // To access handleIrq() From d61ad831a72241657fcd2dfd1d3e6d704dd601e6 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 20 Nov 2023 11:01:08 +0100 Subject: [PATCH 36/83] fix(SubGhz): SPISettings not properly defined after SPI rework Signed-off-by: Frederic Pillon --- libraries/SubGhz/src/SubGhz.cpp | 2 -- libraries/SubGhz/src/SubGhz.h | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/libraries/SubGhz/src/SubGhz.cpp b/libraries/SubGhz/src/SubGhz.cpp index b5394fd55f..a175c0c551 100644 --- a/libraries/SubGhz/src/SubGhz.cpp +++ b/libraries/SubGhz/src/SubGhz.cpp @@ -21,8 +21,6 @@ extern "C" void SUBGHZ_Radio_IRQHandler(void) SubGhz.handleIrq(); } -constexpr SPISettings SubGhzClass::spi_settings; - void SubGhzClass::handleIrq() { if (callback) { diff --git a/libraries/SubGhz/src/SubGhz.h b/libraries/SubGhz/src/SubGhz.h index 60bb621fad..dd8683f279 100644 --- a/libraries/SubGhz/src/SubGhz.h +++ b/libraries/SubGhz/src/SubGhz.h @@ -101,7 +101,7 @@ class SubGhzClass { // supported by the radio, which should always work (no chance of // bad wiring that requires reducing the speed). // This value should be passed to `SubGhz.SPI.beginTransaction()`. - static constexpr SPISettings spi_settings = {16000000, MSBFIRST, SPI_MODE0}; + const SPISettings spi_settings = {16000000, MSBFIRST, SPI_MODE0}; protected: // To access handleIrq() From 61a41ecc1eb8e3006c40e046987b350f6fb82321 Mon Sep 17 00:00:00 2001 From: Giovanni Bruno Date: Tue, 21 Nov 2023 14:58:57 +0100 Subject: [PATCH 37/83] Fixed memory on Wire instance The constructor doesn't cleanup memory for a wire instance. Issues could happen, such as wrong initialization during boot Signed-off-by: Giovanni Bruno --- libraries/Wire/src/Wire.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp index c0b1a25d7a..055bdec262 100644 --- a/libraries/Wire/src/Wire.cpp +++ b/libraries/Wire/src/Wire.cpp @@ -35,12 +35,14 @@ static const uint8_t MASTER_ADDRESS = 0x01; TwoWire::TwoWire() { + memset((void *)&_i2c, 0, sizeof(_i2c)); _i2c.sda = digitalPinToPinName(SDA); _i2c.scl = digitalPinToPinName(SCL); } TwoWire::TwoWire(uint32_t sda, uint32_t scl) { + memset((void *)&_i2c, 0, sizeof(_i2c)); _i2c.sda = digitalPinToPinName(sda); _i2c.scl = digitalPinToPinName(scl); } From b2b9c8c32ee575aa9d39bc74ef8fd4ad31a1d31f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 23 Nov 2023 14:55:26 +0100 Subject: [PATCH 38/83] fix(doc): update broken links raised by CI. Signed-off-by: Frederic Pillon --- .../README.md | 2 +- .../variant_STM32MP157_DK.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/README.md b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/README.md index c1547b9963..164eca6e2b 100644 --- a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/README.md +++ b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/README.md @@ -298,7 +298,7 @@ And then the Device Tree should enable TIM1 for the coprocessor, although this d [STM32MP157A-DK1]: https://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html [STM32MP157C-DK2]: https://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html -[Cortex-M4 Engineering mode]: https://wiki.st.com/stm32mpu/wiki/STM32CubeMP1_development_guidelines +[Cortex-M4 Engineering mode]: https://wiki.st.com/stm32mpu/wiki/How_to_use_engineering_and_production_modes [STM32MP15 Starter Package]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_Discovery_kits_-_Starter_Package [STM32 MPU OpenSTLinux Distribution]: https://wiki.st.com/stm32mpu/wiki/STM32MP1_Distribution_Package [Balena OS]: https://github.com/kbumsik/balena-st-stm32mp diff --git a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/variant_STM32MP157_DK.cpp b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/variant_STM32MP157_DK.cpp index c16649885f..55f38064d0 100644 --- a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/variant_STM32MP157_DK.cpp +++ b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/variant_STM32MP157_DK.cpp @@ -126,7 +126,7 @@ void SystemClock_Config(void) * * Production mode: Both CA7 and CM4 core running, BOOT0 and BOOT2 are ON. * * Engineering mode: Only CM4 running, BOOT0 = OFF, BOOT2 = ON. * See: - * https://wiki.st.com/stm32mpu/wiki/STM32CubeMP1_development_guidelines + * https://wiki.st.com/stm32mpu/wiki/How_to_use_engineering_and_production_modes */ if (!IS_ENGINEERING_BOOT_MODE()) { return; From e2b913a298710dcca51260247cb1f7d50f702410 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 23 Nov 2023 14:31:12 +0100 Subject: [PATCH 39/83] system(U5) update STM32U5xx HAL Drivers to v1.4.0 Included in STM32CubeU5 FW v1.4.0 Signed-off-by: Frederic Pillon --- .../Inc/stm32u5xx_hal_adc.h | 30 +- .../Inc/stm32u5xx_ll_adc.h | 628 ++++++++++-------- system/Drivers/STM32U5xx_HAL_Driver/README.md | 25 +- .../STM32U5xx_HAL_Driver/Release_Notes.html | 89 ++- .../STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c | 4 +- .../Src/stm32u5xx_hal_adc_ex.c | 5 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 7 files changed, 447 insertions(+), 336 deletions(-) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h index 60cc15ca4a..d52c9a44c4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h @@ -2127,10 +2127,36 @@ __LL_ADC_CONVERT_DATA_RESOLUTION((__ADCx__), (__DATA__),\ #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__ADCx__, __VREFANALOG_VOLTAGE__, \ __ADC_DATA__, \ __ADC_RESOLUTION__) \ -__LL_ADC_CALC_DATA_TO_VOLTAGE((__ADCx__), (__VREFANALOG_VOLTAGE__), \ - (__ADC_DATA__), \ +__LL_ADC_CALC_DATA_TO_VOLTAGE((__ADCx__), (__VREFANALOG_VOLTAGE__), \ + (__ADC_DATA__), \ (__ADC_RESOLUTION__)) +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) + * in differential ended mode. + * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __ADCx__ ADC instance + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_14B + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__ADCx__, __VREFANALOG_VOLTAGE__, \ + __ADC_DATA__, \ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__ADCx__), (__VREFANALOG_VOLTAGE__), \ + (__ADC_DATA__), \ + (__ADC_RESOLUTION__)) + /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h index 8d97c40f7a..a6970bfd12 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h @@ -2684,10 +2684,37 @@ single-ended and differential modes. */ #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\ __ADC_DATA__, \ __ADC_RESOLUTION__) \ -((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \ +((__ADC_DATA__) * (int32_t)(__VREFANALOG_VOLTAGE__) \ + / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) \ ) +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) in + * differential ended mode. + * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2. + * @note ADC data from ADC data register is unsigned and centered around + * middle code in. Converted voltage can be positive or negative + * depending on differential input voltages. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (unit: digital value). + * @param __ADC_INSTANCE__ ADC instance + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_14B + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__, \ + __ADC_DATA__, \ + __ADC_RESOLUTION__) \ +((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__) \ + / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) - (int32_t)(__VREFANALOG_VOLTAGE__)) + /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage @@ -2895,8 +2922,8 @@ single-ended and differential modes. */ * use a different data register outside of ADC instance scope * (common data register). This macro manages this register difference, * only ADC instance has to be set as parameter. - * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr - * CDR RDATA_MST LL_ADC_DMA_GetRegAddr + * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr * @param ADCx ADC instance * @param RegisterValue This parameter can be one of the following values: @@ -2980,7 +3007,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR CKMODE LL_ADC_SetCommonClock + * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n * CCR PRESC LL_ADC_SetCommonClock * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3006,7 +3033,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin /** * @brief Get parameter common to several ADC: Clock source and prescaler. - * @rmtoll CCR CKMODE LL_ADC_GetCommonClock + * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n * CCR PRESC LL_ADC_GetCommonClock * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3053,8 +3080,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_C * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd - * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3083,8 +3110,8 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem - * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n * CCR VBATEN LL_ADC_SetCommonPathInternalChRem * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3123,8 +3150,8 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh - * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n * CCR VBATEN LL_ADC_SetCommonPathInternalCh * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3146,8 +3173,8 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh - * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh + * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n + * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n * CCR VBATEN LL_ADC_GetCommonPathInternalCh * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3272,7 +3299,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. - * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor + * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor\n * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2) * @param LinearityWord This parameter can be one of the following values: @@ -3302,7 +3329,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32 * @note Calibration factors are set by hardware after performing * a calibration run using function @ref LL_ADC_StartCalibration(). * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2. - * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor + * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor\n * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2) * @param LinearityWord This parameter can be one of the following values: @@ -3564,17 +3591,17 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) * on either groups regular or injected. * @note On STM32U5, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN0..5). - * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset - * OFR1 OFFSET1 LL_ADC_SetOffset - * OFR1 OFFSET1_EN LL_ADC_SetOffset - * OFR2 OFFSET2_CH LL_ADC_SetOffset - * OFR2 OFFSET2 LL_ADC_SetOffset - * OFR2 OFFSET2_EN LL_ADC_SetOffset - * OFR3 OFFSET3_CH LL_ADC_SetOffset - * OFR3 OFFSET3 LL_ADC_SetOffset - * OFR3 OFFSET3_EN LL_ADC_SetOffset - * OFR4 OFFSET4_CH LL_ADC_SetOffset - * OFR4 OFFSET4 LL_ADC_SetOffset + * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n + * OFR1 OFFSET1 LL_ADC_SetOffset\n + * OFR1 OFFSET1_EN LL_ADC_SetOffset\n + * OFR2 OFFSET2_CH LL_ADC_SetOffset\n + * OFR2 OFFSET2 LL_ADC_SetOffset\n + * OFR2 OFFSET2_EN LL_ADC_SetOffset\n + * OFR3 OFFSET3_CH LL_ADC_SetOffset\n + * OFR3 OFFSET3 LL_ADC_SetOffset\n + * OFR3 OFFSET3_EN LL_ADC_SetOffset\n + * OFR4 OFFSET4_CH LL_ADC_SetOffset\n + * OFR4 OFFSET4 LL_ADC_SetOffset\n * OFR4 OFFSET4_EN LL_ADC_SetOffset * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3645,9 +3672,9 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * @note On STM32U5, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN0..5). - * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel - * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel - * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel + * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n + * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n + * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3706,9 +3733,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32 * @note Caution: Offset format is dependent to ADC resolution: * offset has to be left-aligned on bit 11, the LSB (right bits) * are set to 0. - * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel - * OFR2 OFFSET2 LL_ADC_GetOffsetLevel - * OFR3 OFFSET3 LL_ADC_GetOffsetLevel + * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n + * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n + * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n * OFR4 OFFSET4 LL_ADC_GetOffsetLevel * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3732,9 +3759,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign - * OFR2 OFFSETPOS LL_ADC_SetOffsetSign - * OFR3 OFFSETPOS LL_ADC_SetOffsetSign + * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n + * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n + * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n * OFR4 OFFSETPOS LL_ADC_SetOffsetSign * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3757,9 +3784,9 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u /** * @brief Get for the ADC selected offset number 1, 2, 3 or 4: * offset sign if positive or negative. - * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign - * OFR2 OFFSETPOS LL_ADC_GetOffsetSign - * OFR3 OFFSETPOS LL_ADC_GetOffsetSign + * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n + * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n + * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n * OFR4 OFFSETPOS LL_ADC_GetOffsetSign * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3781,9 +3808,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t /** * @brief Set Signed saturation for the ADC selected offset number 1, 2, 3 or 4: * signed offset saturation if enabled or disabled. - * @rmtoll OFR1 SSAT LL_ADC_SetOffsetSignedSaturation - * OFR2 SSAT LL_ADC_SetOffsetSignedSaturation - * OFR3 SSAT LL_ADC_SetOffsetSignedSaturation + * @rmtoll OFR1 SSAT LL_ADC_SetOffsetSignedSaturation\n + * OFR2 SSAT LL_ADC_SetOffsetSignedSaturation\n + * OFR3 SSAT LL_ADC_SetOffsetSignedSaturation\n * OFR4 SSAT LL_ADC_SetOffsetSignedSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3806,9 +3833,9 @@ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_ /** * @brief Get Signed saturation for the ADC selected offset number 1, 2, 3 or 4: * signed offset saturation if enabled or disabled. - * @rmtoll OFR1 SSAT LL_ADC_GetOffsetSignedSaturation - * OFR2 SSAT LL_ADC_GetOffsetSignedSaturation - * OFR3 SSAT LL_ADC_GetOffsetSignedSaturation + * @rmtoll OFR1 SSAT LL_ADC_GetOffsetSignedSaturation\n + * OFR2 SSAT LL_ADC_GetOffsetSignedSaturation\n + * OFR3 SSAT LL_ADC_GetOffsetSignedSaturation\n * OFR4 SSAT LL_ADC_GetOffsetSignedSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3829,9 +3856,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADC /** * @brief Set Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4: * signed offset saturation if enabled or disabled. - * @rmtoll OFR1 USAT LL_ADC_SetOffsetUnsignedSaturation - * OFR2 USAT LL_ADC_SetOffsetUnsignedSaturation - * OFR3 USAT LL_ADC_SetOffsetUnsignedSaturation + * @rmtoll OFR1 USAT LL_ADC_SetOffsetUnsignedSaturation\n + * OFR2 USAT LL_ADC_SetOffsetUnsignedSaturation\n + * OFR3 USAT LL_ADC_SetOffsetUnsignedSaturation\n * OFR4 USAT LL_ADC_SetOffsetUnsignedSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3854,9 +3881,9 @@ __STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint3 /** * @brief Get Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4: * signed offset saturation if enabled or disabled. - * @rmtoll OFR1 USAT LL_ADC_GetOffsetUnsignedSaturation - * OFR2 USAT LL_ADC_GetOffsetUnsignedSaturation - * OFR3 USAT LL_ADC_GetOffsetUnsignedSaturation + * @rmtoll OFR1 USAT LL_ADC_GetOffsetUnsignedSaturation\n + * OFR2 USAT LL_ADC_GetOffsetUnsignedSaturation\n + * OFR3 USAT LL_ADC_GetOffsetUnsignedSaturation\n * OFR4 USAT LL_ADC_GetOffsetUnsignedSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3886,7 +3913,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef *A * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation + * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n * CFGR2 GCOMP LL_ADC_SetGainCompensation * @param ADCx ADC instance * @param GainCompensation This parameter can be: @@ -3902,7 +3929,7 @@ __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t Gain /** * @brief Get the ADC gain compensation value - * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation + * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n * CFGR2 GCOMP LL_ADC_GetGainCompensation * @param ADCx ADC instance * @retval Returned value can be: @@ -3947,8 +3974,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx) * ADC must be disabled or enabled without conversion on going * on group regular. * @note Applicable only on ADC4 instance - * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels - * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels + * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n + * SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels * @param ADCx ADC instance * @param SamplingTimeY This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 @@ -3981,8 +4008,8 @@ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uin * @note Conversion time is the addition of sampling time and processing time. * Refer to reference manual for ADC processing time of * this STM32 series. - * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels - * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels + * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n + * SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels * @param ADCx ADC instance (ADC4 for this device) * @param SamplingTimeY This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 @@ -4023,7 +4050,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource + * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n * CFGR EXTEN LL_ADC_REG_SetTriggerSource * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: @@ -4073,7 +4100,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource + * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n * CFGR EXTEN LL_ADC_REG_GetTriggerSource * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -4250,7 +4277,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode + * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode * @param ADCx ADC instance * @param SamplingMode This parameter can be one of the following values: @@ -4266,7 +4293,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t Samp /** * @brief Get the ADC sampling mode - * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode + * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -4540,7 +4567,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont + * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont * @param ADCx ADC instance * @param SeqDiscont This parameter can be one of the following values: @@ -4564,7 +4591,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @brief Get ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. - * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont + * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -4603,21 +4630,21 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks - * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks - * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks - * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks - * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks + * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n + * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -4717,21 +4744,21 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks - * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks - * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks - * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks - * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks + * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n + * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -4880,24 +4907,24 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef * on group regular. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: @@ -4964,24 +4991,24 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t * on group regular. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: @@ -5048,24 +5075,24 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Ch * on group regular. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: @@ -5130,24 +5157,24 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch * on group regular. * @note One or several values can be retrieved. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels * @param ADCx ADC instance * @retval Returned value can be a combination of the following values: @@ -5215,6 +5242,26 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx * @note This function set the the value for the channel preselection register * corresponding to ADC channel to be selected. * @note Caution: This is not valid for ADC4. + * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0\n + * PCSEL PCSEL1 LL_ADC_CHANNEL_1\n + * PCSEL PCSEL2 LL_ADC_CHANNEL_2\n + * PCSEL PCSEL3 LL_ADC_CHANNEL_3\n + * PCSEL PCSEL4 LL_ADC_CHANNEL_4\n + * PCSEL PCSEL5 LL_ADC_CHANNEL_5\n + * PCSEL PCSEL6 LL_ADC_CHANNEL_6\n + * PCSEL PCSEL7 LL_ADC_CHANNEL_7\n + * PCSEL PCSEL8 LL_ADC_CHANNEL_8\n + * PCSEL PCSEL9 LL_ADC_CHANNEL_9\n + * PCSEL PCSEL10 LL_ADC_CHANNEL_10\n + * PCSEL PCSEL11 LL_ADC_CHANNEL_11\n + * PCSEL PCSEL12 LL_ADC_CHANNEL_12\n + * PCSEL PCSEL13 LL_ADC_CHANNEL_13\n + * PCSEL PCSEL14 LL_ADC_CHANNEL_14\n + * PCSEL PCSEL15 LL_ADC_CHANNEL_15\n + * PCSEL PCSEL16 LL_ADC_CHANNEL_16\n + * PCSEL PCSEL17 LL_ADC_CHANNEL_17\n + * PCSEL PCSEL18 LL_ADC_CHANNEL_18\n + * PCSEL PCSEL19 LL_ADC_CHANNEL_19 * @param ADCx ADC instance. * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 @@ -5255,29 +5302,28 @@ __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t C * @note This function set the the value for the channel preselection register * corresponding to ADC channel to be selected. * @note Caution: This is not valid for ADC4. + * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0\n + * PCSEL PCSEL1 LL_ADC_CHANNEL_1\n + * PCSEL PCSEL2 LL_ADC_CHANNEL_2\n + * PCSEL PCSEL3 LL_ADC_CHANNEL_3\n + * PCSEL PCSEL4 LL_ADC_CHANNEL_4\n + * PCSEL PCSEL5 LL_ADC_CHANNEL_5\n + * PCSEL PCSEL6 LL_ADC_CHANNEL_6\n + * PCSEL PCSEL7 LL_ADC_CHANNEL_7\n + * PCSEL PCSEL8 LL_ADC_CHANNEL_8\n + * PCSEL PCSEL9 LL_ADC_CHANNEL_9\n + * PCSEL PCSEL10 LL_ADC_CHANNEL_10\n + * PCSEL PCSEL11 LL_ADC_CHANNEL_11\n + * PCSEL PCSEL12 LL_ADC_CHANNEL_12\n + * PCSEL PCSEL13 LL_ADC_CHANNEL_13\n + * PCSEL PCSEL14 LL_ADC_CHANNEL_14\n + * PCSEL PCSEL15 LL_ADC_CHANNEL_15\n + * PCSEL PCSEL16 LL_ADC_CHANNEL_16\n + * PCSEL PCSEL17 LL_ADC_CHANNEL_17\n + * PCSEL PCSEL18 LL_ADC_CHANNEL_18\n + * PCSEL PCSEL19 LL_ADC_CHANNEL_19 * @param ADCx ADC instance. - * * @retval Returned decimal value that can correspend to one or multiple channels: - * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0 - * PCSEL PCSEL1 LL_ADC_CHANNEL_1 - * PCSEL PCSEL2 LL_ADC_CHANNEL_2 - * PCSEL PCSEL3 LL_ADC_CHANNEL_3 - * PCSEL PCSEL4 LL_ADC_CHANNEL_4 - * PCSEL PCSEL5 LL_ADC_CHANNEL_5 - * PCSEL PCSEL6 LL_ADC_CHANNEL_6 - * PCSEL PCSEL7 LL_ADC_CHANNEL_7 - * PCSEL PCSEL8 LL_ADC_CHANNEL_8 - * PCSEL PCSEL9 LL_ADC_CHANNEL_9 - * PCSEL PCSEL10 LL_ADC_CHANNEL_10 - * PCSEL PCSEL11 LL_ADC_CHANNEL_11 - * PCSEL PCSEL12 LL_ADC_CHANNEL_12 - * PCSEL PCSEL13 LL_ADC_CHANNEL_13 - * PCSEL PCSEL14 LL_ADC_CHANNEL_14 - * PCSEL PCSEL15 LL_ADC_CHANNEL_15 - * PCSEL PCSEL16 LL_ADC_CHANNEL_16 - * PCSEL PCSEL17 LL_ADC_CHANNEL_17 - * PCSEL PCSEL18 LL_ADC_CHANNEL_18 - * PCSEL PCSEL19 LL_ADC_CHANNEL_19 * * @note User helper macro @ref __LL_ADC_DECIMAL_NB_TO_CHANNEL(). */ @@ -5364,7 +5410,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef *ADCx) * ADC4 is put on hold during one or two ADC4 clock cycles to avoid noise on Vref+. * ADC state: * ADC must be disabled. - * @rmtoll PWRR VREFPROT LL_ADC_SetVrefProtection + * @rmtoll PWRR VREFPROT LL_ADC_SetVrefProtection\n * PWRR VREFSECSMP LL_ADC_SetVrefProtection * @param ADCx ADC instance * @param VrefProtection This parameter can be one of the following values: @@ -5380,7 +5426,7 @@ __STATIC_INLINE void LL_ADC_SetVrefProtection(ADC_TypeDef *ADCx, uint32_t VrefPr /** * @brief ADC VREF protection when multiple ADCs are working simultaneously - * @rmtoll PWRR VREFPROT LL_ADC_GetVrefProtection + * @rmtoll PWRR VREFPROT LL_ADC_GetVrefProtection\n * PWRR VREFSECSMP LL_ADC_GetVrefProtection * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -5499,7 +5545,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer + * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer * @param ADCx ADC instance * @param DMATransfer This parameter can be one of the following values: @@ -5533,7 +5579,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATr * (overrun flag and interruption if enabled). * @note To configure DMA source address (peripheral address), * use function @ref LL_ADC_DMA_GetRegAddr(). - * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer + * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -5609,7 +5655,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. - * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource + * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: @@ -5652,7 +5698,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource + * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -5839,9 +5885,9 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. - * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks - * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks - * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -5912,9 +5958,9 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks - * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks - * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks + * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -6043,12 +6089,12 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. - * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext - * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext - * JSQR JL LL_ADC_INJ_ConfigQueueContext - * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext - * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext - * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext + * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n + * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n + * JSQR JL LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: @@ -6290,24 +6336,24 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime + * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: @@ -6400,24 +6446,24 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits * - 6.5 ADC clock cycles at ADC resolution 6 bits - * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime + * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: @@ -6650,11 +6696,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, ui * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels - * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels - * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels - * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels - * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels + * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n + * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -6818,11 +6864,11 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels - * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels - * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels - * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels - * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels + * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n + * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -7016,11 +7062,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx * ADC state: * ADC must be disabled or enabled without conversion on going * on either ADC groups regular or injected. - * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds - * TR2 HT2 LL_ADC_SetAnalogWDThresholds - * TR3 HT3 LL_ADC_SetAnalogWDThresholds - * TR1 LT1 LL_ADC_SetAnalogWDThresholds - * TR2 LT2 LL_ADC_SetAnalogWDThresholds + * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n + * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n + * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n + * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n + * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n * TR3 LT3 LL_ADC_SetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -7084,11 +7130,11 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). - * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds - * TR2 HT2 LL_ADC_GetAnalogWDThresholds - * TR3 HT3 LL_ADC_GetAnalogWDThresholds - * TR1 LT1 LL_ADC_GetAnalogWDThresholds - * TR2 LT2 LL_ADC_GetAnalogWDThresholds + * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n + * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n + * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n + * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n + * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n * TR3 LT3 LL_ADC_GetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -7186,11 +7232,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, u * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds - * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds - * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds - * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds - * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds + * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n + * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n + * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n + * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n + * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -7325,8 +7371,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef * * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope - * CFGR2 JOVSE LL_ADC_SetOverSamplingScope + * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n + * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n * CFGR2 ROVSM LL_ADC_SetOverSamplingScope * @param ADCx ADC instance * @param OvsScope This parameter can be one of the following values: @@ -7358,8 +7404,8 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). - * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope - * CFGR2 JOVSE LL_ADC_GetOverSamplingScope + * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n + * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n * CFGR2 ROVSM LL_ADC_GetOverSamplingScope * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -7437,7 +7483,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift + * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift * @param ADCx ADC instance * @param Ratio For ADC instance ADC1, ADC2: This parameter can be in the range from 1 to 1024. @@ -7956,8 +8002,8 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. - * @rmtoll CR ADCAL LL_ADC_StartCalibration - * CR ADCALDIF LL_ADC_StartCalibration + * @rmtoll CR ADCAL LL_ADC_StartCalibration\n + * CR ADCALDIF LL_ADC_StartCalibration\n * CR ADCALLIN LL_ADC_StartCalibration * @param ADCx ADC instance * @param CalibrationMode This parameter can be one of the following values: @@ -8170,7 +8216,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) * transfer by DMA, because this function can do the same * by getting multimode conversion data of ADC master or ADC slave * separately). - * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32 + * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -8265,9 +8311,9 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *A * all ADC configurations: all ADC resolutions and * all oversampling increased data width (for devices * with feature oversampling). - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData32 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData32 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8291,9 +8337,9 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData16 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData16 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData16\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData16\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData16 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8317,9 +8363,9 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData14 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData14 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData14\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData14\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData14 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8343,9 +8389,9 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData12 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData12 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8369,9 +8415,9 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData10 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData10 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8395,9 +8441,9 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData8 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData8 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: diff --git a/system/Drivers/STM32U5xx_HAL_Driver/README.md b/system/Drivers/STM32U5xx_HAL_Driver/README.md index 717e8e7478..9d77735a7a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/README.md +++ b/system/Drivers/STM32U5xx_HAL_Driver/README.md @@ -1,21 +1,22 @@ # STM32CubeU5 HAL Driver MCU Component +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32u5xx_hal_driver.svg?color=brightgreen) + ## Overview -**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. +**STM32Cube** is a STMicroelectronics original initiative aimed at making life easier for developers by reducing effort, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product - * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio - * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series - * A consistent set of middlewares components such as ThreadX, FileX, USBX, NetDuoX, OpenBootloader, USBPD, trustedfirmware, mbed-crypto, Network Library... - * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, demonstration, or nucleo board provided for this STM32 series. + * A consistent set of middleware libraries such as ThreadX, FileX, USBX, NetDuoX, OpenBootloader, USBPD, trustedfirmware, mbed-crypto, Network Library... + * A full set of software projects (basic examples, applications, and demonstrations) for each board, each project developed in three flavors using three toolchains (EWARM, MDK-ARM, and STM32CubeIDE). * A new LPBAM utility which is a software helper that assists STM32U5 users in the elaboration of LPBAM scenarios. - * A development with three Toolchains and Compilers (IAR Embedded Workbench for ARM (EWARM), RealView Microcontroller Development Kit (MDK-ARM), and STM32CubeIDE). Two models of publication are proposed for the STM32Cube embedded software: - * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) - * The **MCU component** : progressively from June 2021, each STM32Cube software module being part of the STM32Cube MCU Package, are delivered as an individual repo, allowing the user to select and get only the required software functions. + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. ## Description @@ -34,6 +35,4 @@ The full **STM32CubeU5** MCU package is available [here](https://github.com/STMi ## Troubleshooting -If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32u5xx_hal_driver/issues/new/choose). - -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html index dd2ec3808e..d335e141ee 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html @@ -40,16 +40,53 @@

Purpose

Update History

- +

Main Changes

    +
  • HAL and LL drivers Maintenance Release for STM32U5XX devices
    • +
  • Update ADC HAL and LL drivers to fix known defects and add implementation enhancements
    • +
  • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and CodeSonar compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
    • +
+

HAL Drivers updates

+
    +
  • HAL ADC driver +
      +
    • Add new Helper macro for differential mode raw data to voltage conversion
      • +
    • +
  • HAL ADC_EX driver +
      +
    • Enhance calibration procedure implementation
      • +
    • +
+

LL Drivers updates

+
    +
  • LL ADC driver +
      +
    • Add new Helper macro for differential mode raw data to voltage conversion
      • +
    • +
+

Known Limitations

+
    +
  • N/A
    • +
+

Backward compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+
  • HAL and LL drivers official Release for STM32U5F7xx/STM32U5G7xx, STM32U5F9xx/STM32U5G9xx, STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U595xx/STM32U5A5xx and STM32U599xx/STM32U5A9xx devices
  • Add 2 new HAL drivers : GFXTIM and JPEG highlighting the graphics aspect of STM32U5F7/STM32U5G7/STM32U5F9/STM32U5G9 devices
  • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and CodeSonar compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
  • General updates to fix known defects and implementation enhancements
-

HAL Drivers updates

+

HAL Drivers updates

  • HAL CRYP driver
      @@ -87,7 +124,7 @@

      HAL Drivers updates

    • Add IS_TIM_CCX_CHANNEL define
-

LL Drivers updates

+

LL Drivers updates

  • LL PWR driver
      @@ -132,11 +169,11 @@

      LL Drivers updates

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -145,12 +182,12 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Official Release for STM32U535xx / STM32U545xx, STM32U575xx / STM32U585xx, STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices.
  • Update STM32U545xx_User_Manual, STM32U585xx_User_Manual and STM32U5A9xx_User_Manual CHM User Manuals
-

HAL Drivers updates

+

HAL Drivers updates

  • HAL ADC driver
      @@ -303,7 +340,7 @@

      HAL Drivers updates

    • Add HAL_HCD_HC_SetHubInfo and HAL_HCD_HC_ClearHubInfo macros
-

LL Drivers updates

+

LL Drivers updates

  • LL ADC driver
      @@ -345,11 +382,11 @@

      LL Drivers updates

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -358,7 +395,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Maintenance Release for STM32U575xx / STM32U585xx devices and new support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices
  • Add New LTDC, GFXMMU, DSI, GPU2D HAL drivers highlighting the graphics aspect of STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
    • @@ -367,7 +404,7 @@

    Main Changes

  • General updates to fix known defects and implementation enhancements
  • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and CodeSonar compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
-

HAL Drivers updates

+

HAL Drivers updates

  • All the HAL drivers are updated to support both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
  • HAL ADC driver @@ -505,7 +542,7 @@

    HAL Drivers updates

  • Rework HAL_USART_DMAResume() function in order to use DMA instead of USART to resume data transfer
-

LL Drivers updates

+

LL Drivers updates

  • All the LL drivers are updated to support both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
  • LL ADC driver @@ -576,11 +613,11 @@

    LL Drivers updates

Backward compatibility ensured by legacy defines

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -589,11 +626,11 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Patch release V1.0.2 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
-

LL Drivers updates

+

LL Drivers updates

  • LL DAC driver
      @@ -605,11 +642,11 @@

      LL Drivers updates

  • Backward compatibility ensured by legacy defines
-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -618,11 +655,11 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Patch release V1.0.1 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
-

HAL Drivers updates

+

HAL Drivers updates

  • HAL ADC driver
      @@ -660,18 +697,18 @@

      HAL Drivers updates

    • Fix setting Flash latency from MSIRange in Oscillator Configuration
-

LL Drivers updates

+

LL Drivers updates

  • LL I2C driver
    • Add LL_I2C_EnableFastModePlus, LL_I2C_DisableFastModePlus and LL_I2C_IsEnabledFastModePlus APIs
-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -680,11 +717,11 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First official release of HAL and LL drivers for STM32U575xx / STM32U585xx devices
-

Known Limitations

+

Known Limitations

  • N/A
diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c index cabce48acb..9c640570c5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c @@ -52,10 +52,10 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.3.0 + * @brief STM32U5xx HAL Driver version number 1.4.0 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U5xx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32U5xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c index 471e5d9cf9..c9a1397da0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c @@ -210,8 +210,11 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t if (tmp_hal_status == HAL_OK) { + /* Use a Data Memory Barrier instruction to avoid synchronization issues when accessing ADC registers */ MODIFY_REG(hadc->Instance->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos); - MODIFY_REG(hadc->Instance->CALFACT2, 0x00FF0000UL, 0x00020000UL); + __DMB(); + MODIFY_REG(hadc->Instance->CALFACT2, 0xFFFFFF00UL, 0x03021100UL); + __DMB(); SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF); tmp_hal_status = ADC_Disable(hadc); diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 0b3ddb1b68..5abbc1daf2 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.13.4 * STM32L5: 1.0.5 * STM32MP1: 1.6.0 - * STM32U5: 1.3.0 + * STM32U5: 1.4.0 * STM32WB: 1.14.0 * STM32WL: 1.3.0 From 4165032fb425ee74d2376a58264b112bac624e28 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 23 Nov 2023 14:31:13 +0100 Subject: [PATCH 40/83] system(U5): update STM32U5xx CMSIS Drivers to v1.3.1 Included in STM32CubeU5 FW v1.4.0 Signed-off-by: Frederic Pillon --- .../Include/Templates/partition_stm32u595xx.h | 2 +- .../Include/Templates/partition_stm32u5f7xx.h | 4 +-- .../Device/ST/STM32U5xx/Include/stm32u5f7xx.h | 6 ++-- .../Device/ST/STM32U5xx/Include/stm32u5g7xx.h | 6 ++-- .../Device/ST/STM32U5xx/Include/stm32u5xx.h | 14 +++++----- .../Device/ST/STM32U5xx/Release_Notes.html | 28 ++++++++++++++----- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 7 files changed, 38 insertions(+), 24 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h index 2a187b4a12..f9da0df15d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file partition_stm32u595xx.h * @author MCD Application Team - * @brief CMSIS STM32U599xx Device Initial Setup for Secure / Non-Secure Zones + * @brief CMSIS STM32U595xx Device Initial Setup for Secure / Non-Secure Zones * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. * * This file contains: diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h index 627156cc38..36e09bbb10 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * @file partition_stm32u5f9xx.h + * @file partition_stm32u5f7xx.h * @author MCD Application Team - * @brief CMSIS STM32U5F9xx Device Initial Setup for Secure / Non-Secure Zones + * @brief CMSIS STM32U5F7xx Device Initial Setup for Secure / Non-Secure Zones * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. * * This file contains: diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h index 723478ad75..515f70e902 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h @@ -26361,11 +26361,11 @@ typedef struct */ /******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ - ((INSTANCE) == ADC1_S) || \ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ ((INSTANCE) == ADC2_NS) || \ ((INSTANCE) == ADC2_S) || \ - ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_NS) || \ ((INSTANCE) == ADC4_S)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h index f460e275c0..7e18d0f3b7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h @@ -27335,11 +27335,11 @@ typedef struct */ /******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ - ((INSTANCE) == ADC1_S) || \ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ ((INSTANCE) == ADC2_NS) || \ ((INSTANCE) == ADC2_S) || \ - ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_NS) || \ ((INSTANCE) == ADC4_S)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h index 5519775501..52dd767b45 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h @@ -66,14 +66,14 @@ /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */ /* #define STM32U595xx */ /*!< STM32U595AJH6 STM32U595ZJT6 STM32U595QJI6 STM32U595VJT6 STM32U595RJT6 STM32U595AJH6Q STM32U595ZJY6QTR STM32U595ZJT6Q STM32U595QJI6Q STM32U595VJT6Q STM32U595RJT6Q STM32U595AIH6 STM32U595ZIT6 STM32U595QII6 STM32U595VIT6 STM32U595RIT6 STM32U595AIH6Q STM32U595ZIY6QTR STM32U595ZIT6Q STM32U595QII6Q STM32U595VIT6Q STM32U595RIT6Q Devices */ /* #define STM32U599xx */ /*!< STM32U599VJT6 STM32U599NJH6Q STM32U599BJY6QTR STM32U599ZJY6QTR STM32U599ZJT6Q STM32U599VJT6Q STM32U599NIH6Q STM32U599ZIY6QTR STM32U599ZIT6Q STM32U599VIT6Q Devices */ - /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q Devices */ + /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q STM32U5A5QII3Q Devices */ /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6QTR STM32U5A9ZJY6QTR STM32U5A9ZJT6Q STM32U5A9VJT6Q Devices */ - /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 Devices STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ + /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ /* #define STM32U5G7xx */ /*!< STM32U5G7VJT6Q STM32U5G7VJT6 Devices */ - /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q Devices */ + /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q STM32U5F9ZIJ6QTR STM32U5F9ZIT6Q STM32U5F9VIT6Q Devices */ /* #define STM32U5G9xx */ /*!< STM32U5G9NJH6Q STM32U5G9BJY6QTR STM32U5G9ZJJ6QTR STM32U5G9ZJT6Q STM32U5G9VJT6Q Devices */ - /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Device */ - /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Device */ + /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Devices */ + /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Devices */ #endif /* Tip: To avoid modifying this file each time you need to switch between these @@ -89,11 +89,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.3.0 + * @brief CMSIS Device version number 1.3.1 */ #define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32U5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ -#define __STM32U5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32U5_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html index 1083f827a1..afffc85ad5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html @@ -30,11 +30,25 @@

Release Notes for  STM32U5xx C

Update History

- +

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

    +
  • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h” file
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

+
  • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices:
    • Add “stm32u5f9xx.h”, “stm32u5g9xx.h”, “stm32u5f7xx.h” and “stm32u5g7xx.h” files
      • @@ -42,7 +56,7 @@

      Main Changes

    • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -51,7 +65,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of stm32u535xx and stm32u545xx devices: @@ -104,7 +118,7 @@

    Main Changes

  • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -113,7 +127,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
      @@ -143,7 +157,7 @@

      Main Changes

      -

      Main Changes

      +

      Main Changes

      • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
      • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
        • @@ -155,7 +169,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
        diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 5d25504345..80132be290 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.7.3 * STM32L5: 1.0.5 * STM32MP1: 1.6.0 - * STM32U5: 1.3.0 + * STM32U5: 1.3.1 * STM32WB: 1.12.0 * STM32WL: 1.2.0 From 08f58852217f9ef6202614f8873559fdab5257a2 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 23 Nov 2023 15:19:09 +0100 Subject: [PATCH 41/83] fix(nucleo_f722ze): remove duplicate PE2 definition Fixes #2199 Signed-off-by: Frederic Pillon --- variants/STM32F7xx/F722Z(C-E)T_F732ZET/variant_NUCLEO_F722ZE.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/variant_NUCLEO_F722ZE.h b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/variant_NUCLEO_F722ZE.h index d2217da335..7c83434ddd 100644 --- a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/variant_NUCLEO_F722ZE.h +++ b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/variant_NUCLEO_F722ZE.h @@ -71,7 +71,7 @@ #define PD5 53 #define PD4 54 #define PD3 55 -#define PE2 56 +// 56 is PE2 (31) #define PE4 57 #define PE5 58 #define PE6 59 From 8e8feb0c58c1ac17008c5dd082226d746232a4ea Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 23 Nov 2023 15:28:26 +0100 Subject: [PATCH 42/83] Revert "chore(SPI): align with ArduinoCoreAPI" This reverts commit 392469a1dc66448dea543119b7258128b5596a03. --- libraries/SPI/src/SPI.cpp | 95 +++++++++--------- libraries/SPI/src/SPI.h | 144 ++++++++-------------------- libraries/SPI/src/utility/spi_com.c | 6 +- libraries/SPI/src/utility/spi_com.h | 13 ++- 4 files changed, 94 insertions(+), 164 deletions(-) diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index b3266d348a..b8f282ffe5 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -57,10 +57,9 @@ SPIClass::SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) void SPIClass::begin(void) { _spi.handle.State = HAL_SPI_STATE_RESET; - _spiSettings = DEFAULT_SPI_SETTINGS; - spi_init(&_spi, _spiSettings.getClockFreq(), - _spiSettings.getDataMode(), - _spiSettings.getBitOrder()); + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** @@ -70,12 +69,14 @@ void SPIClass::begin(void) */ void SPIClass::beginTransaction(SPISettings settings) { - if (_spiSettings != settings) { - _spiSettings = settings; - spi_init(&_spi, _spiSettings.getClockFreq(), - _spiSettings.getDataMode(), - _spiSettings.getBitOrder()); - } + _spiSettings.clk = settings.clk; + _spiSettings.dMode = settings.dMode; + _spiSettings.bOrder = settings.bOrder; + _spiSettings.noReceive = settings.noReceive; + + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** @@ -101,17 +102,17 @@ void SPIClass::end() */ void SPIClass::setBitOrder(BitOrder bitOrder) { - _spiSettings.setBitOrder(bitOrder); + _spiSettings.bOrder = bitOrder; - spi_init(&_spi, _spiSettings.getClockFreq(), - _spiSettings.getDataMode(), - _spiSettings.getBitOrder()); + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** * @brief Deprecated function. * Configure the data mode (clock polarity and clock phase) - * @param mode: SPI_MODE0, SPI_MODE1, SPI_MODE2 or SPI_MODE3 + * @param _mode: SPI_MODE0, SPI_MODE1, SPI_MODE2 or SPI_MODE3 * @note * Mode Clock Polarity (CPOL) Clock Phase (CPHA) * SPI_MODE0 0 0 @@ -119,19 +120,21 @@ void SPIClass::setBitOrder(BitOrder bitOrder) * SPI_MODE2 1 0 * SPI_MODE3 1 1 */ - -void SPIClass::setDataMode(uint8_t mode) +void SPIClass::setDataMode(uint8_t _mode) { - setDataMode((SPIMode)mode); -} - -void SPIClass::setDataMode(SPIMode mode) -{ - _spiSettings.setDataMode(mode); + if (SPI_MODE0 == _mode) { + _spiSettings.dMode = SPI_MODE_0; + } else if (SPI_MODE1 == _mode) { + _spiSettings.dMode = SPI_MODE_1; + } else if (SPI_MODE2 == _mode) { + _spiSettings.dMode = SPI_MODE_2; + } else if (SPI_MODE3 == _mode) { + _spiSettings.dMode = SPI_MODE_3; + } - spi_init(&_spi, _spiSettings.getClockFreq(), - _spiSettings.getDataMode(), - _spiSettings.getBitOrder()); + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** @@ -143,15 +146,15 @@ void SPIClass::setDataMode(SPIMode mode) void SPIClass::setClockDivider(uint8_t _divider) { if (_divider == 0) { - _spiSettings.setClockFreq(SPI_SPEED_CLOCK_DEFAULT); + _spiSettings.clk = SPI_SPEED_CLOCK_DEFAULT; } else { - /* Get clock freq of the SPI instance and compute it */ - _spiSettings.setClockFreq(spi_getClkFreq(&_spi) / _divider); + /* Get clk freq of the SPI instance and compute it */ + _spiSettings.clk = spi_getClkFreq(&_spi) / _divider; } - spi_init(&_spi, _spiSettings.getClockFreq(), - _spiSettings.getDataMode(), - _spiSettings.getBitOrder()); + spi_init(&_spi, _spiSettings.clk, + _spiSettings.dMode, + _spiSettings.bOrder); } /** @@ -160,9 +163,9 @@ void SPIClass::setClockDivider(uint8_t _divider) * @param data: byte to send. * @return byte received from the slave. */ -uint8_t SPIClass::transfer(uint8_t data) +byte SPIClass::transfer(uint8_t data) { - spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, _spiSettings.getSkipRecv()); + spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); return data; } @@ -176,14 +179,14 @@ uint16_t SPIClass::transfer16(uint16_t data) { uint16_t tmp; - if (_spiSettings.getBitOrder()) { + if (_spiSettings.bOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } spi_transfer(&_spi, (uint8_t *)&data, sizeof(uint16_t), - SPI_TRANSFER_TIMEOUT, _spiSettings.getSkipRecv()); + SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); - if (_spiSettings.getBitOrder()) { + if (_spiSettings.bOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } @@ -194,30 +197,22 @@ uint16_t SPIClass::transfer16(uint16_t data) /** * @brief Transfer several bytes. Only one buffer used to send and receive data. * begin() or beginTransaction() must be called at least once before. - * @param buf: pointer to the bytes to send. The bytes received are copy in + * @param _buf: pointer to the bytes to send. The bytes received are copy in * this buffer. - * @param count: number of bytes to send/receive. + * @param _count: number of bytes to send/receive. */ -void SPIClass::transfer(void *buf, size_t count) +void SPIClass::transfer(void *_buf, size_t _count) { if ((count != 0) && (buf != NULL)) { spi_transfer(&_spi, ((uint8_t *)buf), count, - SPI_TRANSFER_TIMEOUT, _spiSettings.getSkipRecv()); + SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); } } /** * @brief Not implemented. */ -void SPIClass::usingInterrupt(int interruptNumber) -{ - UNUSED(interruptNumber); -} - -/** - * @brief Not implemented. - */ -void SPIClass::notUsingInterrupt(int interruptNumber) +void SPIClass::usingInterrupt(uint8_t interruptNumber) { UNUSED(interruptNumber); } diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index 9509c871eb..f8e41bea5c 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -38,6 +38,12 @@ extern "C" { #define SPI_CLOCK_DIV64 64 #define SPI_CLOCK_DIV128 128 +// SPI mode parameters for SPISettings +#define SPI_MODE0 0x00 +#define SPI_MODE1 0x01 +#define SPI_MODE2 0x02 +#define SPI_MODE3 0x03 + #define SPI_TRANSMITRECEIVE 0x0 #define SPI_TRANSMITONLY 0x1 @@ -48,105 +54,37 @@ extern "C" { class SPISettings { public: - SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, bool skipRecv = SPI_TRANSMITRECEIVE) - { - if (__builtin_constant_p(clock)) { - init_AlwaysInline(clock, bitOrder, dataMode, skipRecv); - } else { - init_MightInline(clock, bitOrder, dataMode, skipRecv); - } - } - - SPISettings(uint32_t clock, BitOrder bitOrder, int dataMode, bool skipRecv = SPI_TRANSMITRECEIVE) - { - if (__builtin_constant_p(clock)) { - init_AlwaysInline(clock, bitOrder, (SPIMode)dataMode, skipRecv); - } else { - init_MightInline(clock, bitOrder, (SPIMode)dataMode, skipRecv); - } - } - - // Default speed set to 4MHz, SPI mode set to MODE 0 and Bit order set to MSB first. - SPISettings() - { - init_AlwaysInline(SPI_SPEED_CLOCK_DEFAULT, MSBFIRST, SPI_MODE0, SPI_TRANSMITRECEIVE); - } - - bool operator==(const SPISettings &rhs) const - { - if ((this->clockFreq == rhs.clockFreq) && - (this->bitOrder == rhs.bitOrder) && - (this->dataMode == rhs.dataMode) && - (this->skipRecv == rhs.skipRecv)) { - return true; - } - return false; - } - - bool operator!=(const SPISettings &rhs) const - { - return !(*this == rhs); - } - - uint32_t getClockFreq() const - { - return clockFreq; - } - SPIMode getDataMode() const - { - return dataMode; - } - BitOrder getBitOrder() const - { - return (bitOrder); - } - bool getSkipRecv() const - { - return skipRecv; - } - - void setClockFreq(uint32_t clkFreq) - { - clockFreq = clkFreq; - } - void setDataMode(SPIMode mode) - { - dataMode = mode; - } - void setBitOrder(BitOrder order) - { - bitOrder = order; - } - void setSkipRecv(bool skip) - { - skipRecv = skip; - } - + constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, bool noRecv = SPI_TRANSMITRECEIVE) + : clk(clock), + bOrder(bitOrder), + dMode((spi_mode_e)( + (SPI_MODE0 == dataMode) ? SPI_MODE_0 : + (SPI_MODE1 == dataMode) ? SPI_MODE_1 : + (SPI_MODE2 == dataMode) ? SPI_MODE_2 : + (SPI_MODE3 == dataMode) ? SPI_MODE_3 : + SPI_MODE0 + )), + noReceive(noRecv) + { } + constexpr SPISettings() + : clk(SPI_SPEED_CLOCK_DEFAULT), + bOrder(MSBFIRST), + dMode(SPI_MODE_0), + noReceive(SPI_TRANSMITRECEIVE) + { } private: - void init_MightInline(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, bool skipRecv) - { - init_AlwaysInline(clock, bitOrder, dataMode, skipRecv); - } - - // Core developer MUST use an helper function in beginTransaction() to use this data - void init_AlwaysInline(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, bool skipRecv) __attribute__((__always_inline__)) - { - this->clockFreq = clock; - this->dataMode = dataMode; - this->bitOrder = bitOrder; - this->skipRecv = skipRecv; - } - - uint32_t clockFreq; - SPIMode dataMode; - BitOrder bitOrder; - bool skipRecv; - - friend class HardwareSPI; + uint32_t clk; //specifies the spi bus maximum clock speed + BitOrder bOrder; //bit order (MSBFirst or LSBFirst) + spi_mode_e dMode; //one of the data mode + //Mode Clock Polarity (CPOL) Clock Phase (CPHA) + //SPI_MODE0 0 0 + //SPI_MODE1 0 1 + //SPI_MODE2 1 0 + //SPI_MODE3 1 1 + friend class SPIClass; + bool noReceive; }; -const SPISettings DEFAULT_SPI_SETTINGS = SPISettings(); - class SPIClass { public: SPIClass(); @@ -187,7 +125,7 @@ class SPIClass { _spi.pin_ssel = (ssel); }; - virtual void begin(void); + virtual void begin(); void end(void); /* This function should be used to configure the SPI instance in case you @@ -199,21 +137,19 @@ class SPIClass { /* Transfer functions: must be called after initialization of the SPI * instance with begin() or beginTransaction(). */ - virtual uint8_t transfer(uint8_t _data); + virtual byte transfer(uint8_t _data); virtual uint16_t transfer16(uint16_t _data); - virtual void transfer(void *buf, size_t count); + virtual void transfer(void *_buf, size_t _count); /* These methods are deprecated and kept for compatibility. * Use SPISettings with SPI.beginTransaction() to configure SPI parameters. */ void setBitOrder(BitOrder); void setDataMode(uint8_t); - void setDataMode(SPIMode); void setClockDivider(uint8_t); - // Not implemented functions. Kept for compatibility. - void usingInterrupt(int interruptNumber); - void notUsingInterrupt(int interruptNumber); + // Not implemented functions. Kept for backward compatibility. + void usingInterrupt(uint8_t interruptNumber); void attachInterrupt(void); void detachInterrupt(void); @@ -229,7 +165,7 @@ class SPIClass { private: /* Current SPISettings */ - SPISettings _spiSettings = DEFAULT_SPI_SETTINGS; + SPISettings _spiSettings = SPISettings(); }; extern SPIClass SPI; diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index bd582681bd..cfc2c2cc45 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -227,7 +227,7 @@ static uint32_t compute_disable_delay(spi_t *obj) * @param msb : set to 1 in msb first * @retval None */ -void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb) +void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb) { if (obj == NULL) { return; @@ -313,13 +313,13 @@ void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb) handle->Init.Direction = SPI_DIRECTION_2LINES; - if ((mode == SPI_MODE0) || (mode == SPI_MODE2)) { + if ((mode == SPI_MODE_0) || (mode == SPI_MODE_2)) { handle->Init.CLKPhase = SPI_PHASE_1EDGE; } else { handle->Init.CLKPhase = SPI_PHASE_2EDGE; } - if ((mode == SPI_MODE0) || (mode == SPI_MODE1)) { + if ((mode == SPI_MODE_0) || (mode == SPI_MODE_1)) { handle->Init.CLKPolarity = SPI_POLARITY_LOW; } else { handle->Init.CLKPolarity = SPI_POLARITY_HIGH; diff --git a/libraries/SPI/src/utility/spi_com.h b/libraries/SPI/src/utility/spi_com.h index 7562c08118..ee322e6982 100644 --- a/libraries/SPI/src/utility/spi_com.h +++ b/libraries/SPI/src/utility/spi_com.h @@ -85,13 +85,12 @@ typedef struct spi_s spi_t; //SPI_MODE2 1 0 //SPI_MODE3 1 1 //enum definitions coming from SPI.h of SAM -// SPI mode parameters for SPISettings typedef enum { - SPI_MODE0 = 0, - SPI_MODE1 = 1, - SPI_MODE2 = 2, - SPI_MODE3 = 3, -} SPIMode; + SPI_MODE_0 = 0x00, + SPI_MODE_1 = 0x01, + SPI_MODE_2 = 0x02, + SPI_MODE_3 = 0x03 +} spi_mode_e; ///@brief SPI errors typedef enum { @@ -101,7 +100,7 @@ typedef enum { } spi_status_e; /* Exported functions ------------------------------------------------------- */ -void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb); +void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb); void spi_deinit(spi_t *obj); spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, uint32_t Timeout, bool skipReceive); From c9a89f1b611df1c1bdb5694c2069071201860991 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 23 Nov 2023 16:14:31 +0100 Subject: [PATCH 43/83] Revert "fix(SubGhz): SPISettings not properly defined" This reverts commit d61ad831a72241657fcd2dfd1d3e6d704dd601e6. --- libraries/SubGhz/src/SubGhz.cpp | 2 ++ libraries/SubGhz/src/SubGhz.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/libraries/SubGhz/src/SubGhz.cpp b/libraries/SubGhz/src/SubGhz.cpp index a175c0c551..b5394fd55f 100644 --- a/libraries/SubGhz/src/SubGhz.cpp +++ b/libraries/SubGhz/src/SubGhz.cpp @@ -21,6 +21,8 @@ extern "C" void SUBGHZ_Radio_IRQHandler(void) SubGhz.handleIrq(); } +constexpr SPISettings SubGhzClass::spi_settings; + void SubGhzClass::handleIrq() { if (callback) { diff --git a/libraries/SubGhz/src/SubGhz.h b/libraries/SubGhz/src/SubGhz.h index dd8683f279..60bb621fad 100644 --- a/libraries/SubGhz/src/SubGhz.h +++ b/libraries/SubGhz/src/SubGhz.h @@ -101,7 +101,7 @@ class SubGhzClass { // supported by the radio, which should always work (no chance of // bad wiring that requires reducing the speed). // This value should be passed to `SubGhz.SPI.beginTransaction()`. - const SPISettings spi_settings = {16000000, MSBFIRST, SPI_MODE0}; + static constexpr SPISettings spi_settings = {16000000, MSBFIRST, SPI_MODE0}; protected: // To access handleIrq() From ea70e88cfa393c2f2683a75de6c2d9d06b0d4ed0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 23 Nov 2023 16:13:57 +0100 Subject: [PATCH 44/83] chore(spi): partially align with ArduinoCoreAPI Keep constexpr constructor to ensures that constructing an SPISettings object can be done at compiletime. Fixes #2201. Signed-off-by: Frederic Pillon --- libraries/SPI/src/SPI.cpp | 95 +++++++++++++++-------------- libraries/SPI/src/SPI.h | 71 ++++++++++----------- libraries/SPI/src/utility/spi_com.c | 6 +- libraries/SPI/src/utility/spi_com.h | 13 ++-- 4 files changed, 96 insertions(+), 89 deletions(-) diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index b8f282ffe5..15dbb79f18 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -57,9 +57,10 @@ SPIClass::SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) void SPIClass::begin(void) { _spi.handle.State = HAL_SPI_STATE_RESET; - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); + _spiSettings = SPISettings(); + spi_init(&_spi, _spiSettings.clockFreq, + _spiSettings.dataMode, + _spiSettings.bitOrder); } /** @@ -69,14 +70,12 @@ void SPIClass::begin(void) */ void SPIClass::beginTransaction(SPISettings settings) { - _spiSettings.clk = settings.clk; - _spiSettings.dMode = settings.dMode; - _spiSettings.bOrder = settings.bOrder; - _spiSettings.noReceive = settings.noReceive; - - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); + if (_spiSettings != settings) { + _spiSettings = settings; + spi_init(&_spi, _spiSettings.clockFreq, + _spiSettings.dataMode, + _spiSettings.bitOrder); + } } /** @@ -90,7 +89,7 @@ void SPIClass::endTransaction(void) /** * @brief Deinitialize the SPI instance and stop it. */ -void SPIClass::end() +void SPIClass::end(void) { spi_deinit(&_spi); } @@ -98,21 +97,21 @@ void SPIClass::end() /** * @brief Deprecated function. * Configure the bit order: MSB first or LSB first. - * @param _bitOrder: MSBFIRST or LSBFIRST + * @param bitOrder: MSBFIRST or LSBFIRST */ void SPIClass::setBitOrder(BitOrder bitOrder) { - _spiSettings.bOrder = bitOrder; + _spiSettings.bitOrder = bitOrder; - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); + spi_init(&_spi, _spiSettings.clockFreq, + _spiSettings.dataMode, + _spiSettings.bitOrder); } /** * @brief Deprecated function. * Configure the data mode (clock polarity and clock phase) - * @param _mode: SPI_MODE0, SPI_MODE1, SPI_MODE2 or SPI_MODE3 + * @param mode: SPI_MODE0, SPI_MODE1, SPI_MODE2 or SPI_MODE3 * @note * Mode Clock Polarity (CPOL) Clock Phase (CPHA) * SPI_MODE0 0 0 @@ -120,41 +119,37 @@ void SPIClass::setBitOrder(BitOrder bitOrder) * SPI_MODE2 1 0 * SPI_MODE3 1 1 */ -void SPIClass::setDataMode(uint8_t _mode) +void SPIClass::setDataMode(uint8_t mode) { - if (SPI_MODE0 == _mode) { - _spiSettings.dMode = SPI_MODE_0; - } else if (SPI_MODE1 == _mode) { - _spiSettings.dMode = SPI_MODE_1; - } else if (SPI_MODE2 == _mode) { - _spiSettings.dMode = SPI_MODE_2; - } else if (SPI_MODE3 == _mode) { - _spiSettings.dMode = SPI_MODE_3; - } + setDataMode((SPIMode)mode); +} - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); +void SPIClass::setDataMode(SPIMode mode) +{ + _spiSettings.dataMode = mode; + spi_init(&_spi, _spiSettings.clockFreq, + _spiSettings.dataMode, + _spiSettings.bitOrder); } /** * @brief Deprecated function. * Configure the clock speed - * @param _divider: the SPI clock can be divided by values from 1 to 255. + * @param divider: the SPI clock can be divided by values from 1 to 255. * If 0, default SPI speed is used. */ -void SPIClass::setClockDivider(uint8_t _divider) +void SPIClass::setClockDivider(uint8_t divider) { - if (_divider == 0) { - _spiSettings.clk = SPI_SPEED_CLOCK_DEFAULT; + if (divider == 0) { + _spiSettings.clockFreq = SPI_SPEED_CLOCK_DEFAULT; } else { /* Get clk freq of the SPI instance and compute it */ - _spiSettings.clk = spi_getClkFreq(&_spi) / _divider; + _spiSettings.clockFreq = spi_getClkFreq(&_spi) / divider; } - spi_init(&_spi, _spiSettings.clk, - _spiSettings.dMode, - _spiSettings.bOrder); + spi_init(&_spi, _spiSettings.clockFreq, + _spiSettings.dataMode, + _spiSettings.bitOrder); } /** @@ -163,7 +158,7 @@ void SPIClass::setClockDivider(uint8_t _divider) * @param data: byte to send. * @return byte received from the slave. */ -byte SPIClass::transfer(uint8_t data) +uint8_t SPIClass::transfer(uint8_t data) { spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); return data; @@ -179,14 +174,14 @@ uint16_t SPIClass::transfer16(uint16_t data) { uint16_t tmp; - if (_spiSettings.bOrder) { + if (_spiSettings.bitOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } spi_transfer(&_spi, (uint8_t *)&data, sizeof(uint16_t), SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); - if (_spiSettings.bOrder) { + if (_spiSettings.bitOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } @@ -197,11 +192,11 @@ uint16_t SPIClass::transfer16(uint16_t data) /** * @brief Transfer several bytes. Only one buffer used to send and receive data. * begin() or beginTransaction() must be called at least once before. - * @param _buf: pointer to the bytes to send. The bytes received are copy in + * @param buf: pointer to the bytes to send. The bytes received are copy in * this buffer. - * @param _count: number of bytes to send/receive. + * @param count: number of bytes to send/receive. */ -void SPIClass::transfer(void *_buf, size_t _count) +void SPIClass::transfer(void *buf, size_t count) { if ((count != 0) && (buf != NULL)) { spi_transfer(&_spi, ((uint8_t *)buf), count, @@ -212,7 +207,15 @@ void SPIClass::transfer(void *_buf, size_t _count) /** * @brief Not implemented. */ -void SPIClass::usingInterrupt(uint8_t interruptNumber) +void SPIClass::usingInterrupt(int interruptNumber) +{ + UNUSED(interruptNumber); +} + +/** + * @brief Not implemented. + */ +void SPIClass::notUsingInterrupt(int interruptNumber) { UNUSED(interruptNumber); } diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index f8e41bea5c..af19d4e38e 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -38,12 +38,6 @@ extern "C" { #define SPI_CLOCK_DIV64 64 #define SPI_CLOCK_DIV128 128 -// SPI mode parameters for SPISettings -#define SPI_MODE0 0x00 -#define SPI_MODE1 0x01 -#define SPI_MODE2 0x02 -#define SPI_MODE3 0x03 - #define SPI_TRANSMITRECEIVE 0x0 #define SPI_TRANSMITONLY 0x1 @@ -54,35 +48,42 @@ extern "C" { class SPISettings { public: - constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, bool noRecv = SPI_TRANSMITRECEIVE) - : clk(clock), - bOrder(bitOrder), - dMode((spi_mode_e)( - (SPI_MODE0 == dataMode) ? SPI_MODE_0 : - (SPI_MODE1 == dataMode) ? SPI_MODE_1 : - (SPI_MODE2 == dataMode) ? SPI_MODE_2 : - (SPI_MODE3 == dataMode) ? SPI_MODE_3 : - SPI_MODE0 - )), + constexpr SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, bool noRecv = SPI_TRANSMITRECEIVE) + : clockFreq(clock), + bitOrder(bitOrder), + dataMode(dataMode), noReceive(noRecv) { } constexpr SPISettings() - : clk(SPI_SPEED_CLOCK_DEFAULT), - bOrder(MSBFIRST), - dMode(SPI_MODE_0), + : clockFreq(SPI_SPEED_CLOCK_DEFAULT), + bitOrder(MSBFIRST), + dataMode(SPI_MODE0), noReceive(SPI_TRANSMITRECEIVE) { } + + bool operator==(const SPISettings &rhs) const + { + if ((this->clockFreq == rhs.clockFreq) && + (this->bitOrder == rhs.bitOrder) && + (this->dataMode == rhs.dataMode) && + (this->noReceive == rhs.noReceive)) { + return true; + } + return false; + } + + bool operator!=(const SPISettings &rhs) const + { + return !(*this == rhs); + } + private: - uint32_t clk; //specifies the spi bus maximum clock speed - BitOrder bOrder; //bit order (MSBFirst or LSBFirst) - spi_mode_e dMode; //one of the data mode - //Mode Clock Polarity (CPOL) Clock Phase (CPHA) - //SPI_MODE0 0 0 - //SPI_MODE1 0 1 - //SPI_MODE2 1 0 - //SPI_MODE3 1 1 - friend class SPIClass; + uint32_t clockFreq; //specifies the spi bus maximum clock speed + BitOrder bitOrder; //bit order (MSBFirst or LSBFirst) + SPIMode dataMode; //one of the data mode bool noReceive; + + friend class SPIClass; }; class SPIClass { @@ -125,7 +126,7 @@ class SPIClass { _spi.pin_ssel = (ssel); }; - virtual void begin(); + virtual void begin(void); void end(void); /* This function should be used to configure the SPI instance in case you @@ -137,19 +138,21 @@ class SPIClass { /* Transfer functions: must be called after initialization of the SPI * instance with begin() or beginTransaction(). */ - virtual byte transfer(uint8_t _data); - virtual uint16_t transfer16(uint16_t _data); - virtual void transfer(void *_buf, size_t _count); + virtual uint8_t transfer(uint8_t data); + virtual uint16_t transfer16(uint16_t data); + virtual void transfer(void *buf, size_t count); /* These methods are deprecated and kept for compatibility. * Use SPISettings with SPI.beginTransaction() to configure SPI parameters. */ void setBitOrder(BitOrder); void setDataMode(uint8_t); + void setDataMode(SPIMode); void setClockDivider(uint8_t); - // Not implemented functions. Kept for backward compatibility. - void usingInterrupt(uint8_t interruptNumber); + // Not implemented functions. Kept for compatibility. + void usingInterrupt(int interruptNumber); + void notUsingInterrupt(int interruptNumber); void attachInterrupt(void); void detachInterrupt(void); diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index cfc2c2cc45..bd582681bd 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -227,7 +227,7 @@ static uint32_t compute_disable_delay(spi_t *obj) * @param msb : set to 1 in msb first * @retval None */ -void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb) +void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb) { if (obj == NULL) { return; @@ -313,13 +313,13 @@ void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb) handle->Init.Direction = SPI_DIRECTION_2LINES; - if ((mode == SPI_MODE_0) || (mode == SPI_MODE_2)) { + if ((mode == SPI_MODE0) || (mode == SPI_MODE2)) { handle->Init.CLKPhase = SPI_PHASE_1EDGE; } else { handle->Init.CLKPhase = SPI_PHASE_2EDGE; } - if ((mode == SPI_MODE_0) || (mode == SPI_MODE_1)) { + if ((mode == SPI_MODE0) || (mode == SPI_MODE1)) { handle->Init.CLKPolarity = SPI_POLARITY_LOW; } else { handle->Init.CLKPolarity = SPI_POLARITY_HIGH; diff --git a/libraries/SPI/src/utility/spi_com.h b/libraries/SPI/src/utility/spi_com.h index ee322e6982..7562c08118 100644 --- a/libraries/SPI/src/utility/spi_com.h +++ b/libraries/SPI/src/utility/spi_com.h @@ -85,12 +85,13 @@ typedef struct spi_s spi_t; //SPI_MODE2 1 0 //SPI_MODE3 1 1 //enum definitions coming from SPI.h of SAM +// SPI mode parameters for SPISettings typedef enum { - SPI_MODE_0 = 0x00, - SPI_MODE_1 = 0x01, - SPI_MODE_2 = 0x02, - SPI_MODE_3 = 0x03 -} spi_mode_e; + SPI_MODE0 = 0, + SPI_MODE1 = 1, + SPI_MODE2 = 2, + SPI_MODE3 = 3, +} SPIMode; ///@brief SPI errors typedef enum { @@ -100,7 +101,7 @@ typedef enum { } spi_status_e; /* Exported functions ------------------------------------------------------- */ -void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb); +void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb); void spi_deinit(spi_t *obj); spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, uint32_t Timeout, bool skipReceive); From c1b1d61ac158f3c571ad4044f8a97fd59c3bbaf8 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 20 Nov 2023 17:02:50 +0100 Subject: [PATCH 45/83] feat(spi): remove skip receive from SPISettings This parameter should not be part of SPISettings. Signed-off-by: Frederic Pillon --- libraries/SPI/README.md | 4 ---- libraries/SPI/src/SPI.cpp | 6 +++--- libraries/SPI/src/SPI.h | 15 ++++----------- 3 files changed, 7 insertions(+), 18 deletions(-) diff --git a/libraries/SPI/README.md b/libraries/SPI/README.md index 5bf0889c59..2849c787ac 100644 --- a/libraries/SPI/README.md +++ b/libraries/SPI/README.md @@ -7,10 +7,6 @@ User have 2 possibilities about the management of the CS pin: * the CS pin is managed directly by the user code before to transfer the data (like the Arduino SPI library) * the user uses a hardware CS pin linked to the SPI peripheral -### New SPISetting parameter - -* `noReceive`: value can be `SPI_TRANSMITRECEIVE` or `SPI_TRANSMITONLY`. It allows to skip receive data after transmitting. Default `SPI_TRANSMITRECEIVE`. - ### New API functions * `SPIClass::SPIClass(uint8_t mosi, uint8_t miso, uint8_t sclk, uint8_t ssel)`: alternative class constructor diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index 15dbb79f18..01d74b2852 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -160,7 +160,7 @@ void SPIClass::setClockDivider(uint8_t divider) */ uint8_t SPIClass::transfer(uint8_t data) { - spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); + spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, false); return data; } @@ -179,7 +179,7 @@ uint16_t SPIClass::transfer16(uint16_t data) data = tmp; } spi_transfer(&_spi, (uint8_t *)&data, sizeof(uint16_t), - SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); + SPI_TRANSFER_TIMEOUT, false); if (_spiSettings.bitOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); @@ -200,7 +200,7 @@ void SPIClass::transfer(void *buf, size_t count) { if ((count != 0) && (buf != NULL)) { spi_transfer(&_spi, ((uint8_t *)buf), count, - SPI_TRANSFER_TIMEOUT, _spiSettings.noReceive); + SPI_TRANSFER_TIMEOUT, false); } } diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index af19d4e38e..fc673ca882 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -38,9 +38,6 @@ extern "C" { #define SPI_CLOCK_DIV64 64 #define SPI_CLOCK_DIV128 128 -#define SPI_TRANSMITRECEIVE 0x0 -#define SPI_TRANSMITONLY 0x1 - // Defines a default timeout delay in milliseconds for the SPI transfer #ifndef SPI_TRANSFER_TIMEOUT #define SPI_TRANSFER_TIMEOUT 1000 @@ -48,25 +45,22 @@ extern "C" { class SPISettings { public: - constexpr SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, bool noRecv = SPI_TRANSMITRECEIVE) + constexpr SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode) : clockFreq(clock), bitOrder(bitOrder), - dataMode(dataMode), - noReceive(noRecv) + dataMode(dataMode) { } constexpr SPISettings() : clockFreq(SPI_SPEED_CLOCK_DEFAULT), bitOrder(MSBFIRST), - dataMode(SPI_MODE0), - noReceive(SPI_TRANSMITRECEIVE) + dataMode(SPI_MODE0) { } bool operator==(const SPISettings &rhs) const { if ((this->clockFreq == rhs.clockFreq) && (this->bitOrder == rhs.bitOrder) && - (this->dataMode == rhs.dataMode) && - (this->noReceive == rhs.noReceive)) { + (this->dataMode == rhs.dataMode)) { return true; } return false; @@ -81,7 +75,6 @@ class SPISettings { uint32_t clockFreq; //specifies the spi bus maximum clock speed BitOrder bitOrder; //bit order (MSBFirst or LSBFirst) SPIMode dataMode; //one of the data mode - bool noReceive; friend class SPIClass; }; From 98fca7dc081def1ac072196cf91ffbf82833af89 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 22 Nov 2023 14:30:24 +0100 Subject: [PATCH 46/83] chore(subghzspi): clean up useless declaration Since internal CS pin removed. Signed-off-by: Frederic Pillon --- libraries/SPI/src/SPI.cpp | 29 ----------------------------- libraries/SPI/src/SPI.h | 9 --------- 2 files changed, 38 deletions(-) diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index 01d74b2852..4bd483a5da 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -237,35 +237,6 @@ void SPIClass::detachInterrupt(void) } #if defined(SUBGHZSPI_BASE) -void SUBGHZSPIClass::begin() -{ - SPIClass::begin(); -} - -void SUBGHZSPIClass::beginTransaction(SPISettings settings) -{ - SPIClass::beginTransaction(settings); -} - -byte SUBGHZSPIClass::transfer(uint8_t _data) -{ - byte res; - res = SPIClass::transfer(_data); - return res; -} - -uint16_t SUBGHZSPIClass::transfer16(uint16_t _data) -{ - uint16_t rx_buffer = 0; - rx_buffer = SPIClass::transfer16(_data); - return rx_buffer; -} - -void SUBGHZSPIClass::transfer(void *_buf, size_t _count) -{ - SPIClass::transfer(_buf, _count); -} - void SUBGHZSPIClass::enableDebugPins(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) { /* Configure SPI GPIO pins */ diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index fc673ca882..49dcdbcd6e 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -174,16 +174,7 @@ class SUBGHZSPIClass : public SPIClass { _spi.spi = SUBGHZSPI; } - void begin(); - void beginTransaction(SPISettings settings); - byte transfer(uint8_t _data); - uint16_t transfer16(uint16_t _data); - void transfer(void *_buf, size_t _count); void enableDebugPins(uint32_t mosi = DEBUG_SUBGHZSPI_MOSI, uint32_t miso = DEBUG_SUBGHZSPI_MISO, uint32_t sclk = DEBUG_SUBGHZSPI_SCLK, uint32_t ssel = DEBUG_SUBGHZSPI_SS); - - using SPIClass::beginTransaction; - using SPIClass::transfer; - using SPIClass::transfer16; }; #endif From aa5abaad419792c61dbab5101d78fe8496da0539 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 21 Nov 2023 10:04:26 +0100 Subject: [PATCH 47/83] feat(spi): allow to skip receive during transfer Linked to #912. Signed-off-by: Frederic Pillon --- libraries/SPI/README.md | 4 ++++ libraries/SPI/src/SPI.cpp | 21 +++++++++++++++------ libraries/SPI/src/SPI.h | 9 ++++++--- 3 files changed, 25 insertions(+), 9 deletions(-) diff --git a/libraries/SPI/README.md b/libraries/SPI/README.md index 2849c787ac..a74b2fc272 100644 --- a/libraries/SPI/README.md +++ b/libraries/SPI/README.md @@ -35,6 +35,10 @@ void setup() { } ``` +### Extended API + +* All `transfer()` API's have a new bool argument `skipReceive`. It allows to skip receive data after transmitting. Value can be `SPI_TRANSMITRECEIVE` or `SPI_TRANSMITONLY`. Default `SPI_TRANSMITRECEIVE`. + #### Change default `SPI` instance pins It is also possible to change the default pins used by the `SPI` instance using above API: diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index 4bd483a5da..f42f2e88d7 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -156,11 +156,14 @@ void SPIClass::setClockDivider(uint8_t divider) * @brief Transfer one byte on the SPI bus. * begin() or beginTransaction() must be called at least once before. * @param data: byte to send. + * @param skipReceive: skip receiving data after transmit or not. + * SPI_TRANSMITRECEIVE or SPI_TRANSMITONLY. + * Optional, default: SPI_TRANSMITRECEIVE. * @return byte received from the slave. */ -uint8_t SPIClass::transfer(uint8_t data) +uint8_t SPIClass::transfer(uint8_t data, bool skipReceive) { - spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, false); + spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, skipReceive); return data; } @@ -168,9 +171,12 @@ uint8_t SPIClass::transfer(uint8_t data) * @brief Transfer two bytes on the SPI bus in 16 bits format. * begin() or beginTransaction() must be called at least once before. * @param data: bytes to send. + * @param skipReceive: skip receiving data after transmit or not. + * SPI_TRANSMITRECEIVE or SPI_TRANSMITONLY. + * Optional, default: SPI_TRANSMITRECEIVE. * @return bytes received from the slave in 16 bits format. */ -uint16_t SPIClass::transfer16(uint16_t data) +uint16_t SPIClass::transfer16(uint16_t data, bool skipReceive) { uint16_t tmp; @@ -179,7 +185,7 @@ uint16_t SPIClass::transfer16(uint16_t data) data = tmp; } spi_transfer(&_spi, (uint8_t *)&data, sizeof(uint16_t), - SPI_TRANSFER_TIMEOUT, false); + SPI_TRANSFER_TIMEOUT, skipReceive); if (_spiSettings.bitOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); @@ -195,12 +201,15 @@ uint16_t SPIClass::transfer16(uint16_t data) * @param buf: pointer to the bytes to send. The bytes received are copy in * this buffer. * @param count: number of bytes to send/receive. + * @param skipReceive: skip receiving data after transmit or not. + * SPI_TRANSMITRECEIVE or SPI_TRANSMITONLY. + * Optional, default: SPI_TRANSMITRECEIVE. */ -void SPIClass::transfer(void *buf, size_t count) +void SPIClass::transfer(void *buf, size_t count, bool skipReceive) { if ((count != 0) && (buf != NULL)) { spi_transfer(&_spi, ((uint8_t *)buf), count, - SPI_TRANSFER_TIMEOUT, false); + SPI_TRANSFER_TIMEOUT, skipReceive); } } diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index 49dcdbcd6e..d293d3ac46 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -38,6 +38,9 @@ extern "C" { #define SPI_CLOCK_DIV64 64 #define SPI_CLOCK_DIV128 128 +#define SPI_TRANSMITRECEIVE false +#define SPI_TRANSMITONLY true + // Defines a default timeout delay in milliseconds for the SPI transfer #ifndef SPI_TRANSFER_TIMEOUT #define SPI_TRANSFER_TIMEOUT 1000 @@ -131,9 +134,9 @@ class SPIClass { /* Transfer functions: must be called after initialization of the SPI * instance with begin() or beginTransaction(). */ - virtual uint8_t transfer(uint8_t data); - virtual uint16_t transfer16(uint16_t data); - virtual void transfer(void *buf, size_t count); + virtual uint8_t transfer(uint8_t data, bool skipReceive = SPI_TRANSMITRECEIVE); + virtual uint16_t transfer16(uint16_t data, bool skipReceive = SPI_TRANSMITRECEIVE); + virtual void transfer(void *buf, size_t count, bool skipReceive = SPI_TRANSMITRECEIVE); /* These methods are deprecated and kept for compatibility. * Use SPISettings with SPI.beginTransaction() to configure SPI parameters. From 8a01b92bb15db6ec5a056d8cdad034a8134051a0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 21 Nov 2023 09:48:56 +0100 Subject: [PATCH 48/83] doc(spi): update README.md Signed-off-by: Frederic Pillon --- libraries/SPI/README.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/libraries/SPI/README.md b/libraries/SPI/README.md index a74b2fc272..59564fd7e5 100644 --- a/libraries/SPI/README.md +++ b/libraries/SPI/README.md @@ -42,7 +42,8 @@ void setup() { #### Change default `SPI` instance pins It is also possible to change the default pins used by the `SPI` instance using above API: -[[/img/Warning-icon.png|alt="Warning"]] **Have to be called before `begin()`.** +> [!WARNING] +> **Have to be called before `begin()`.** * `void setMISO(uint32_t miso)` * `void setMOSI(uint32_t mosi)` @@ -53,7 +54,8 @@ It is also possible to change the default pins used by the `SPI` instance using * `void setSCLK(PinName sclk)` * `void setSSEL(PinName ssel)` -**_Note 1_** Using `setSSEL()` allows to enable hardware CS pin management linked to the SPI peripheral. +> [!NOTE] +> Using `setSSEL()` allows to enable hardware CS pin management linked to the SPI peripheral. ##### Example: ```C++ From e781dc78a81b3f3fe92d4c49a86e9d59c375a850 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 23 Nov 2023 17:14:04 +0100 Subject: [PATCH 49/83] feat(spi): add SPISettings constructor with uint8_t for backward compatibility. Example with Adafruit GFX Library library. Signed-off-by: Frederic Pillon --- libraries/SPI/src/SPI.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index d293d3ac46..1c8bbc11cd 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -48,6 +48,11 @@ extern "C" { class SPISettings { public: + constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) + : clockFreq(clock), + bitOrder(bitOrder), + dataMode((SPIMode)dataMode) + { } constexpr SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode) : clockFreq(clock), bitOrder(bitOrder), From b7c9e55274711c70f7add43adc6e409b3c02e115 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 31 Oct 2023 09:46:24 +0100 Subject: [PATCH 50/83] chore(ci): add support for submodule STM32Cube repos have submodules. Signed-off-by: Frederic Pillon --- CI/update/stm32cube.py | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/CI/update/stm32cube.py b/CI/update/stm32cube.py index 6cd0b30915..754849766d 100644 --- a/CI/update/stm32cube.py +++ b/CI/update/stm32cube.py @@ -316,9 +316,24 @@ def updateSTRepo(): f"{rname}/{bname}", ], ] + gitmodule_path = repo_path / ".gitmodules" + if gitmodule_path.exists(): + git_cmds += ( + [ + "git", + "-C", + repo_path, + "submodule", + "update", + "--init", + "--recursive", + ], + ) else: # Clone it as it does not exists yet - git_cmds = [["git", "-C", repo_local_path, "clone", gh_STM32Cube]] + git_cmds = [ + ["git", "-C", repo_local_path, "clone", "--recursive", gh_STM32Cube] + ] for cmd in git_cmds: execute_cmd(cmd, None) latestTag(serie, repo_name, repo_path) @@ -336,7 +351,10 @@ def latestTag(serie, repo_name, repo_path): version_tag = execute_cmd( ["git", "-C", repo_path, "describe", "--tags", sha1_id], None ) - execute_cmd(["git", "-C", repo_path, "checkout", version_tag], subprocess.DEVNULL) + execute_cmd( + ["git", "-C", repo_path, "checkout", "-f", "--recurse-submodules", version_tag], + subprocess.DEVNULL, + ) cube_versions[serie] = version_tag # print(f"Latest tagged version available for {repo_name} is {version_tag}") From a46472a08c6c0cf862f845bf1ca081586cf87b76 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 23 Nov 2023 14:42:10 +0100 Subject: [PATCH 51/83] chore(ci): update skip pattern to ignore files added due to submodule usage for HAL drivers and CMSIS device headers. Signed-off-by: Frederic Pillon --- CI/update/stm32cube.py | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/CI/update/stm32cube.py b/CI/update/stm32cube.py index 754849766d..ae7023efb9 100644 --- a/CI/update/stm32cube.py +++ b/CI/update/stm32cube.py @@ -56,6 +56,16 @@ md_CMSIS_path = "STM32YYxx_CMSIS_version.md" md_HAL_path = "STM32YYxx_HAL_Driver_version.md" +# Pattern list of files to skip +hal_skip_pattern = {"*.chm"} +cmsis_skip_pattern = {"iar", "arm"} +common_skip_pattern = { + ".github", + "CODE_OF_CONDUCT.md", + "CONTRIBUTING.md", + "SECURITY.md", +} + # stm32 def file to update stm32_def = "stm32_def.h" @@ -845,7 +855,11 @@ def updateCore(): HAL_serie_cube_path = ( cube_path / hal_src_path / f"STM32{serie}xx_HAL_Driver" ) - copyFolder(HAL_serie_cube_path, HAL_serie_core_path, {"*.chm"}) + copyFolder( + HAL_serie_cube_path, + HAL_serie_core_path, + hal_skip_pattern.union(common_skip_pattern), + ) # Update MD file updateMDFile(md_HAL_path, serie, cube_HAL_ver) # Commit all HAL files @@ -863,7 +877,11 @@ def updateCore(): deleteFolder(CMSIS_serie_dest_path) # Copy new one CMSIS_serie_cube_path = cube_path / cmsis_src_path / f"STM32{serie}xx" - copyFolder(CMSIS_serie_cube_path, CMSIS_serie_dest_path, {"iar", "arm"}) + copyFolder( + CMSIS_serie_cube_path, + CMSIS_serie_dest_path, + cmsis_skip_pattern.union(common_skip_pattern), + ) # Update MD file updateMDFile(md_CMSIS_path, serie, cube_CMSIS_ver) # Commit all CMSIS files From 8091319472793f362d8a8e62e08c9538b9d25b93 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 24 Nov 2023 10:36:31 +0100 Subject: [PATCH 52/83] chore(spi): avoid SPI_TRANSFER_TIMEOUT as argument SPI_TRANSFER_TIMEOUT is always passed as an argument while it is a constant definition. So simply function call and check. Signed-off-by: Frederic Pillon --- libraries/SPI/src/SPI.cpp | 8 ++- libraries/SPI/src/SPI.h | 5 -- libraries/SPI/src/utility/spi_com.c | 75 ++++++++++++++--------------- libraries/SPI/src/utility/spi_com.h | 10 +++- 4 files changed, 48 insertions(+), 50 deletions(-) diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index f42f2e88d7..04d77bded7 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -163,7 +163,7 @@ void SPIClass::setClockDivider(uint8_t divider) */ uint8_t SPIClass::transfer(uint8_t data, bool skipReceive) { - spi_transfer(&_spi, &data, sizeof(uint8_t), SPI_TRANSFER_TIMEOUT, skipReceive); + spi_transfer(&_spi, &data, sizeof(uint8_t), skipReceive); return data; } @@ -184,8 +184,7 @@ uint16_t SPIClass::transfer16(uint16_t data, bool skipReceive) tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } - spi_transfer(&_spi, (uint8_t *)&data, sizeof(uint16_t), - SPI_TRANSFER_TIMEOUT, skipReceive); + spi_transfer(&_spi, (uint8_t *)&data, sizeof(uint16_t), skipReceive); if (_spiSettings.bitOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); @@ -208,8 +207,7 @@ uint16_t SPIClass::transfer16(uint16_t data, bool skipReceive) void SPIClass::transfer(void *buf, size_t count, bool skipReceive) { if ((count != 0) && (buf != NULL)) { - spi_transfer(&_spi, ((uint8_t *)buf), count, - SPI_TRANSFER_TIMEOUT, skipReceive); + spi_transfer(&_spi, ((uint8_t *)buf), count, skipReceive); } } diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index 1c8bbc11cd..f6dba43b29 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -41,11 +41,6 @@ extern "C" { #define SPI_TRANSMITRECEIVE false #define SPI_TRANSMITONLY true -// Defines a default timeout delay in milliseconds for the SPI transfer -#ifndef SPI_TRANSFER_TIMEOUT - #define SPI_TRANSFER_TIMEOUT 1000 -#endif - class SPISettings { public: constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index bd582681bd..ce4e83864d 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -502,69 +502,68 @@ void spi_deinit(spi_t *obj) * @param obj : pointer to spi_t structure * @param buffer : tx data to send before reception * @param len : length in byte of the data to send and receive - * @param Timeout: Timeout duration in tick * @param skipReceive: skip receiving data after transmit or not * @retval status of the send operation (0) in case of error */ -spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, - uint32_t Timeout, bool skipReceive) +spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, bool skipReceive) { spi_status_e ret = SPI_OK; uint32_t tickstart, size = len; SPI_TypeDef *_SPI = obj->handle.Instance; uint8_t *tx_buffer = buffer; - if ((len == 0) || (Timeout == 0U)) { - return Timeout > 0U ? SPI_ERROR : SPI_TIMEOUT; - } - tickstart = HAL_GetTick(); + if (len == 0) { + ret = SPI_ERROR; + } else { + tickstart = HAL_GetTick(); #if defined(SPI_CR2_TSIZE) - /* Start transfer */ - LL_SPI_SetTransferSize(_SPI, size); - LL_SPI_Enable(_SPI); - LL_SPI_StartMasterTransfer(_SPI); + /* Start transfer */ + LL_SPI_SetTransferSize(_SPI, size); + LL_SPI_Enable(_SPI); + LL_SPI_StartMasterTransfer(_SPI); #endif - while (size--) { + while (size--) { #if defined(SPI_SR_TXP) - while (!LL_SPI_IsActiveFlag_TXP(_SPI)); + while (!LL_SPI_IsActiveFlag_TXP(_SPI)); #else - while (!LL_SPI_IsActiveFlag_TXE(_SPI)); + while (!LL_SPI_IsActiveFlag_TXE(_SPI)); #endif - LL_SPI_TransmitData8(_SPI, *tx_buffer++); + LL_SPI_TransmitData8(_SPI, *tx_buffer++); - if (!skipReceive) { + if (!skipReceive) { #if defined(SPI_SR_RXP) - while (!LL_SPI_IsActiveFlag_RXP(_SPI)); + while (!LL_SPI_IsActiveFlag_RXP(_SPI)); #else - while (!LL_SPI_IsActiveFlag_RXNE(_SPI)); + while (!LL_SPI_IsActiveFlag_RXNE(_SPI)); #endif - *buffer++ = LL_SPI_ReceiveData8(_SPI); - } - if ((Timeout != HAL_MAX_DELAY) && (HAL_GetTick() - tickstart >= Timeout)) { - ret = SPI_TIMEOUT; - break; + *buffer++ = LL_SPI_ReceiveData8(_SPI); + } + if ((SPI_TRANSFER_TIMEOUT != HAL_MAX_DELAY) && + (HAL_GetTick() - tickstart >= SPI_TRANSFER_TIMEOUT)) { + ret = SPI_TIMEOUT; + break; + } } - } #if defined(SPI_IFCR_EOTC) - // Add a delay before disabling SPI otherwise last-bit/last-clock may be truncated - // See https://github.com/stm32duino/Arduino_Core_STM32/issues/1294 - // Computed delay is half SPI clock - delayMicroseconds(obj->disable_delay); - - /* Close transfer */ - /* Clear flags */ - LL_SPI_ClearFlag_EOT(_SPI); - LL_SPI_ClearFlag_TXTF(_SPI); - /* Disable SPI peripheral */ - LL_SPI_Disable(_SPI); + // Add a delay before disabling SPI otherwise last-bit/last-clock may be truncated + // See https://github.com/stm32duino/Arduino_Core_STM32/issues/1294 + // Computed delay is half SPI clock + delayMicroseconds(obj->disable_delay); + + /* Close transfer */ + /* Clear flags */ + LL_SPI_ClearFlag_EOT(_SPI); + LL_SPI_ClearFlag_TXTF(_SPI); + /* Disable SPI peripheral */ + LL_SPI_Disable(_SPI); #else - /* Wait for end of transfer */ - while (LL_SPI_IsActiveFlag_BSY(_SPI)); + /* Wait for end of transfer */ + while (LL_SPI_IsActiveFlag_BSY(_SPI)); #endif - + } return ret; } diff --git a/libraries/SPI/src/utility/spi_com.h b/libraries/SPI/src/utility/spi_com.h index 7562c08118..b0a920936d 100644 --- a/libraries/SPI/src/utility/spi_com.h +++ b/libraries/SPI/src/utility/spi_com.h @@ -78,6 +78,13 @@ typedef struct spi_s spi_t; #define SPI_SPEED_CLOCK_DIV128_MHZ ((uint32_t)128) #define SPI_SPEED_CLOCK_DIV256_MHZ ((uint32_t)256) +// Defines a default timeout delay in milliseconds for the SPI transfer +#ifndef SPI_TRANSFER_TIMEOUT +#define SPI_TRANSFER_TIMEOUT 1000 +#elif SPI_TRANSFER_TIMEOUT <= 0 +#error "SPI_TRANSFER_TIMEOUT cannot be less or equal to 0!" +#endif + ///@brief specifies the SPI mode to use //Mode Clock Polarity (CPOL) Clock Phase (CPHA) //SPI_MODE0 0 0 @@ -103,8 +110,7 @@ typedef enum { /* Exported functions ------------------------------------------------------- */ void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb); void spi_deinit(spi_t *obj); -spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, - uint32_t Timeout, bool skipReceive); +spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, bool skipReceive); uint32_t spi_getClkFreq(spi_t *obj); #ifdef __cplusplus From 0b9c63d1b1338b96cdf2b3d30567874469ed1984 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 24 Nov 2023 15:44:41 +0100 Subject: [PATCH 53/83] chore(spi): remove virtual function specifier Signed-off-by: Frederic Pillon --- libraries/SPI/src/SPI.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index f6dba43b29..136a8d2f68 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -122,21 +122,21 @@ class SPIClass { _spi.pin_ssel = (ssel); }; - virtual void begin(void); + void begin(void); void end(void); /* This function should be used to configure the SPI instance in case you * don't use default parameters. */ void beginTransaction(SPISettings settings); - virtual void endTransaction(void); + void endTransaction(void); /* Transfer functions: must be called after initialization of the SPI * instance with begin() or beginTransaction(). */ - virtual uint8_t transfer(uint8_t data, bool skipReceive = SPI_TRANSMITRECEIVE); - virtual uint16_t transfer16(uint16_t data, bool skipReceive = SPI_TRANSMITRECEIVE); - virtual void transfer(void *buf, size_t count, bool skipReceive = SPI_TRANSMITRECEIVE); + uint8_t transfer(uint8_t data, bool skipReceive = SPI_TRANSMITRECEIVE); + uint16_t transfer16(uint16_t data, bool skipReceive = SPI_TRANSMITRECEIVE); + void transfer(void *buf, size_t count, bool skipReceive = SPI_TRANSMITRECEIVE); /* These methods are deprecated and kept for compatibility. * Use SPISettings with SPI.beginTransaction() to configure SPI parameters. From 9df4fe06d4e15bf132dc7fa7246aa363ee3ca7ff Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 24 Nov 2023 10:45:21 +0100 Subject: [PATCH 54/83] feat(spi): add transfer api with tx/rx buffer Fixes #2205 Signed-off-by: Frederic Pillon --- libraries/SPI/README.md | 32 +++++++++++++++++++++-------- libraries/SPI/src/SPI.cpp | 26 ++++++++++++++++++----- libraries/SPI/src/SPI.h | 5 +++++ libraries/SPI/src/utility/spi_com.c | 21 +++++++++++-------- libraries/SPI/src/utility/spi_com.h | 2 +- 5 files changed, 62 insertions(+), 24 deletions(-) diff --git a/libraries/SPI/README.md b/libraries/SPI/README.md index 59564fd7e5..7a0595c1cc 100644 --- a/libraries/SPI/README.md +++ b/libraries/SPI/README.md @@ -7,16 +7,18 @@ User have 2 possibilities about the management of the CS pin: * the CS pin is managed directly by the user code before to transfer the data (like the Arduino SPI library) * the user uses a hardware CS pin linked to the SPI peripheral -### New API functions +## New API functions -* `SPIClass::SPIClass(uint8_t mosi, uint8_t miso, uint8_t sclk, uint8_t ssel)`: alternative class constructor -_Params_ SPI `mosi` pin -_Params_ SPI `miso` pin -_Params_ SPI `sclk` pin -_Params_ (optional) SPI `ssel` pin. This pin must be an hardware CS pin. If you configure this pin, the chip select will be managed by the SPI peripheral. +#### Alternative class constructor +* `SPIClass::SPIClass(uint8_t mosi, uint8_t miso, uint8_t sclk, uint8_t ssel)` + +_Param_ SPI `mosi` pin - * `SPI_HandleTypeDef *getHandle(void)`: Could be used to mix Arduino API and STM32Cube HAL API (ex: DMA). **Use at your own risk.** +_Param_ SPI `miso` pin +_Param_ SPI `sclk` pin + +_Params_ (optional) SPI `ssel` pin. This pin must be an hardware CS pin. If you configure this pin, the chip select will be managed by the SPI peripheral. ##### Example @@ -35,9 +37,15 @@ void setup() { } ``` -### Extended API +#### Transfer with Tx/Rx buffer + +* `void transfer(const void *tx_buf, void *rx_buf, size_t count)` :Transfer several bytes. One constant buffer used to send and one to receive data. -* All `transfer()` API's have a new bool argument `skipReceive`. It allows to skip receive data after transmitting. Value can be `SPI_TRANSMITRECEIVE` or `SPI_TRANSMITONLY`. Default `SPI_TRANSMITRECEIVE`. + _Param_ `tx_buf`: constant array of Tx bytes that is filled by the user before starting the SPI transfer. If NULL, default dummy 0xFF bytes will be clocked out. + + _Param_ `rx_buf`: array of Rx bytes that will be filled by the slave during the SPI transfer. If NULL, the received data will be discarded. + + _Param_ `count`: number of bytes to send/receive. #### Change default `SPI` instance pins It is also possible to change the default pins used by the `SPI` instance using above API: @@ -63,3 +71,9 @@ It is also possible to change the default pins used by the `SPI` instance using SPI.setMOSI(PC2); // using pin number PYn SPI.begin(2); ``` + +* `SPI_HandleTypeDef *getHandle(void)`: Could be used to mix Arduino API and STM32Cube HAL API (ex: DMA). **Use at your own risk.** + +## Extended API + +* All defaustatndard `transfer()` API's have a new bool argument `skipReceive`. It allows to skip receive data after transmitting. Value can be `SPI_TRANSMITRECEIVE` or `SPI_TRANSMITONLY`. Default `SPI_TRANSMITRECEIVE`. diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index 04d77bded7..2c6e798b33 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -163,7 +163,7 @@ void SPIClass::setClockDivider(uint8_t divider) */ uint8_t SPIClass::transfer(uint8_t data, bool skipReceive) { - spi_transfer(&_spi, &data, sizeof(uint8_t), skipReceive); + spi_transfer(&_spi, &data, (!skipReceive) ? &data : NULL, sizeof(uint8_t)); return data; } @@ -184,7 +184,7 @@ uint16_t SPIClass::transfer16(uint16_t data, bool skipReceive) tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); data = tmp; } - spi_transfer(&_spi, (uint8_t *)&data, sizeof(uint16_t), skipReceive); + spi_transfer(&_spi, (uint8_t *)&data, (!skipReceive) ? (uint8_t *)&data : NULL, sizeof(uint16_t)); if (_spiSettings.bitOrder) { tmp = ((data & 0xff00) >> 8) | ((data & 0xff) << 8); @@ -206,11 +206,27 @@ uint16_t SPIClass::transfer16(uint16_t data, bool skipReceive) */ void SPIClass::transfer(void *buf, size_t count, bool skipReceive) { - if ((count != 0) && (buf != NULL)) { - spi_transfer(&_spi, ((uint8_t *)buf), count, skipReceive); - } + spi_transfer(&_spi, (uint8_t *)buf, (!skipReceive) ? (uint8_t *)buf : NULL, count); + +} + +/** + * @brief Transfer several bytes. One constant buffer used to send and + * one to receive data. + * begin() or beginTransaction() must be called at least once before. + * @param tx_buf: array of Tx bytes that is filled by the user before starting + * the SPI transfer. If NULL, default dummy 0xFF bytes will be + * clocked out. + * @param rx_buf: array of Rx bytes that will be filled by the slave during + * the SPI transfer. If NULL, the received data will be discarded. + * @param count: number of bytes to send/receive. + */ +void SPIClass::transfer(const void *tx_buf, void *rx_buf, size_t count) +{ + spi_transfer(&_spi, ((const uint8_t *)tx_buf), ((uint8_t *)rx_buf), count); } + /** * @brief Not implemented. */ diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index 136a8d2f68..1105991dc7 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -138,6 +138,11 @@ class SPIClass { uint16_t transfer16(uint16_t data, bool skipReceive = SPI_TRANSMITRECEIVE); void transfer(void *buf, size_t count, bool skipReceive = SPI_TRANSMITRECEIVE); + /* Expand SPI API + * https://github.com/arduino/ArduinoCore-API/discussions/189 + */ + void transfer(const void *tx_buf, void *rx_buf, size_t count); + /* These methods are deprecated and kept for compatibility. * Use SPISettings with SPI.beginTransaction() to configure SPI parameters. */ diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index ce4e83864d..b92b44aea9 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -500,17 +500,18 @@ void spi_deinit(spi_t *obj) * @brief This function is implemented by user to send/receive data over * SPI interface * @param obj : pointer to spi_t structure - * @param buffer : tx data to send before reception + * @param tx_buffer : tx data to send before reception + * @param rx_buffer : rx data to receive if not numm * @param len : length in byte of the data to send and receive - * @param skipReceive: skip receiving data after transmit or not * @retval status of the send operation (0) in case of error */ -spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, bool skipReceive) +spi_status_e spi_transfer(spi_t *obj, const uint8_t *tx_buffer, uint8_t *rx_buffer, + uint16_t len) { spi_status_e ret = SPI_OK; uint32_t tickstart, size = len; SPI_TypeDef *_SPI = obj->handle.Instance; - uint8_t *tx_buffer = buffer; + uint8_t *tx_buf = (uint8_t *)tx_buffer; if (len == 0) { ret = SPI_ERROR; @@ -530,15 +531,17 @@ spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, bool skipRe #else while (!LL_SPI_IsActiveFlag_TXE(_SPI)); #endif - LL_SPI_TransmitData8(_SPI, *tx_buffer++); + LL_SPI_TransmitData8(_SPI, tx_buf ? *tx_buf++ : 0XFF); - if (!skipReceive) { #if defined(SPI_SR_RXP) - while (!LL_SPI_IsActiveFlag_RXP(_SPI)); + while (!LL_SPI_IsActiveFlag_RXP(_SPI)); #else - while (!LL_SPI_IsActiveFlag_RXNE(_SPI)); + while (!LL_SPI_IsActiveFlag_RXNE(_SPI)); #endif - *buffer++ = LL_SPI_ReceiveData8(_SPI); + if (rx_buffer) { + *rx_buffer++ = LL_SPI_ReceiveData8(_SPI); + } else { + LL_SPI_ReceiveData8(_SPI); } if ((SPI_TRANSFER_TIMEOUT != HAL_MAX_DELAY) && (HAL_GetTick() - tickstart >= SPI_TRANSFER_TIMEOUT)) { diff --git a/libraries/SPI/src/utility/spi_com.h b/libraries/SPI/src/utility/spi_com.h index b0a920936d..c6e287b8d5 100644 --- a/libraries/SPI/src/utility/spi_com.h +++ b/libraries/SPI/src/utility/spi_com.h @@ -110,7 +110,7 @@ typedef enum { /* Exported functions ------------------------------------------------------- */ void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb); void spi_deinit(spi_t *obj); -spi_status_e spi_transfer(spi_t *obj, uint8_t *buffer, uint16_t len, bool skipReceive); +spi_status_e spi_transfer(spi_t *obj, const uint8_t *tx_buffer, uint8_t *rx_buffer, uint16_t len); uint32_t spi_getClkFreq(spi_t *obj); #ifdef __cplusplus From e268a5a632668c941c97efb81e844d25739fc1fc Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 29 Nov 2023 09:41:01 +0100 Subject: [PATCH 55/83] system(F4) update STM32F4xx HAL Drivers to v1.8.2 Included in STM32CubeF4 FW v1.28.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 436 +- .../Inc/stm32f4xx_hal_adc.h | 58 +- .../Inc/stm32f4xx_hal_adc_ex.h | 30 +- .../Inc/stm32f4xx_hal_can.h | 53 +- .../Inc/stm32f4xx_hal_cec.h | 136 +- .../Inc/stm32f4xx_hal_cortex.h | 1 + .../Inc/stm32f4xx_hal_crc.h | 2 +- .../Inc/stm32f4xx_hal_dac.h | 32 +- .../Inc/stm32f4xx_hal_dac_ex.h | 9 +- .../Inc/stm32f4xx_hal_def.h | 2 + .../Inc/stm32f4xx_hal_dfsdm.h | 24 +- .../Inc/stm32f4xx_hal_dsi.h | 12 +- .../Inc/stm32f4xx_hal_eth.h | 42 +- .../Inc/stm32f4xx_hal_fmpi2c.h | 143 +- .../Inc/stm32f4xx_hal_fmpi2c_ex.h | 4 +- .../Inc/stm32f4xx_hal_fmpsmbus.h | 139 +- .../Inc/stm32f4xx_hal_fmpsmbus_ex.h | 6 +- .../Inc/stm32f4xx_hal_hcd.h | 26 +- .../Inc/stm32f4xx_hal_irda.h | 4 +- .../Inc/stm32f4xx_hal_lptim.h | 8 +- .../Inc/stm32f4xx_hal_ltdc.h | 16 +- .../Inc/stm32f4xx_hal_nand.h | 45 +- .../Inc/stm32f4xx_hal_nor.h | 2 +- .../Inc/stm32f4xx_hal_pcd.h | 12 +- .../Inc/stm32f4xx_hal_pcd_ex.h | 14 +- .../Inc/stm32f4xx_hal_pwr.h | 13 +- .../Inc/stm32f4xx_hal_rcc.h | 5 +- .../Inc/stm32f4xx_hal_rcc_ex.h | 108 +- .../Inc/stm32f4xx_hal_rng.h | 6 +- .../Inc/stm32f4xx_hal_rtc.h | 9 +- .../Inc/stm32f4xx_hal_rtc_ex.h | 16 +- .../Inc/stm32f4xx_hal_sai.h | 4 +- .../Inc/stm32f4xx_hal_sai_ex.h | 4 +- .../Inc/stm32f4xx_hal_smartcard.h | 4 +- .../Inc/stm32f4xx_hal_smbus.h | 36 +- .../Inc/stm32f4xx_hal_spdifrx.h | 56 +- .../Inc/stm32f4xx_hal_sram.h | 2 +- .../Inc/stm32f4xx_hal_tim.h | 93 +- .../Inc/stm32f4xx_hal_tim_ex.h | 19 +- .../Inc/stm32f4xx_hal_uart.h | 33 +- .../Inc/stm32f4xx_hal_usart.h | 6 +- .../Inc/stm32f4xx_ll_adc.h | 51 +- .../Inc/stm32f4xx_ll_cortex.h | 10 + .../Inc/stm32f4xx_ll_crc.h | 4 +- .../Inc/stm32f4xx_ll_dac.h | 138 +- .../Inc/stm32f4xx_ll_fmc.h | 4 +- .../Inc/stm32f4xx_ll_fmpi2c.h | 135 +- .../Inc/stm32f4xx_ll_fsmc.h | 2 +- .../Inc/stm32f4xx_ll_i2c.h | 44 +- .../Inc/stm32f4xx_ll_lptim.h | 90 +- .../Inc/stm32f4xx_ll_rng.h | 19 +- .../Inc/stm32f4xx_ll_rtc.h | 22 +- .../Inc/stm32f4xx_ll_sdmmc.h | 8 +- .../Inc/stm32f4xx_ll_tim.h | 177 +- .../Inc/stm32f4xx_ll_usart.h | 220 +- .../Inc/stm32f4xx_ll_usb.h | 250 +- .../STM32F4xx_HAL_Driver/Release_Notes.html | 15646 +++++----------- .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 7 +- .../Src/stm32f4xx_hal_adc.c | 260 +- .../Src/stm32f4xx_hal_adc_ex.c | 134 +- .../Src/stm32f4xx_hal_can.c | 92 +- .../Src/stm32f4xx_hal_cec.c | 57 +- .../Src/stm32f4xx_hal_cortex.c | 10 + .../Src/stm32f4xx_hal_crc.c | 4 +- .../Src/stm32f4xx_hal_cryp.c | 126 +- .../Src/stm32f4xx_hal_dac.c | 127 +- .../Src/stm32f4xx_hal_dac_ex.c | 43 +- .../Src/stm32f4xx_hal_dfsdm.c | 28 +- .../Src/stm32f4xx_hal_dma2d.c | 22 +- .../Src/stm32f4xx_hal_dsi.c | 379 +- .../Src/stm32f4xx_hal_eth.c | 85 +- .../Src/stm32f4xx_hal_exti.c | 8 +- .../Src/stm32f4xx_hal_fmpi2c.c | 1509 +- .../Src/stm32f4xx_hal_fmpsmbus.c | 209 +- .../Src/stm32f4xx_hal_hash.c | 2 +- .../Src/stm32f4xx_hal_hcd.c | 757 +- .../Src/stm32f4xx_hal_i2c.c | 251 +- .../Src/stm32f4xx_hal_irda.c | 19 +- .../Src/stm32f4xx_hal_lptim.c | 24 +- .../Src/stm32f4xx_hal_ltdc.c | 8 +- .../Src/stm32f4xx_hal_ltdc_ex.c | 21 +- .../Src/stm32f4xx_hal_nand.c | 104 +- .../Src/stm32f4xx_hal_nor.c | 208 +- .../Src/stm32f4xx_hal_pcd.c | 98 +- .../Src/stm32f4xx_hal_pcd_ex.c | 22 +- .../Src/stm32f4xx_hal_pwr.c | 51 +- .../Src/stm32f4xx_hal_qspi.c | 12 +- .../Src/stm32f4xx_hal_rcc.c | 4 +- .../Src/stm32f4xx_hal_rcc_ex.c | 24 + .../Src/stm32f4xx_hal_rng.c | 29 +- .../Src/stm32f4xx_hal_rtc.c | 94 +- .../Src/stm32f4xx_hal_rtc_ex.c | 41 +- .../Src/stm32f4xx_hal_sai.c | 28 +- .../Src/stm32f4xx_hal_sai_ex.c | 4 +- .../Src/stm32f4xx_hal_sd.c | 22 +- .../Src/stm32f4xx_hal_sdram.c | 36 +- .../Src/stm32f4xx_hal_smartcard.c | 21 +- .../Src/stm32f4xx_hal_smbus.c | 22 +- .../Src/stm32f4xx_hal_spdifrx.c | 56 +- .../Src/stm32f4xx_hal_spi.c | 132 +- .../Src/stm32f4xx_hal_sram.c | 40 +- .../Src/stm32f4xx_hal_tim.c | 189 +- .../Src/stm32f4xx_hal_tim_ex.c | 58 +- ...tm32f4xx_hal_timebase_rtc_alarm_template.c | 8 +- ...m32f4xx_hal_timebase_rtc_wakeup_template.c | 8 +- .../Src/stm32f4xx_hal_timebase_tim_template.c | 2 +- .../Src/stm32f4xx_hal_uart.c | 174 +- .../Src/stm32f4xx_hal_usart.c | 26 +- .../Src/stm32f4xx_ll_adc.c | 116 +- .../Src/stm32f4xx_ll_crc.c | 2 +- .../Src/stm32f4xx_ll_dac.c | 74 +- .../Src/stm32f4xx_ll_fmc.c | 5 +- .../Src/stm32f4xx_ll_fmpi2c.c | 16 +- .../Src/stm32f4xx_ll_fsmc.c | 3 +- .../Src/stm32f4xx_ll_lptim.c | 7 +- .../Src/stm32f4xx_ll_rng.c | 4 +- .../Src/stm32f4xx_ll_rtc.c | 2 +- .../Src/stm32f4xx_ll_tim.c | 71 +- .../Src/stm32f4xx_ll_usart.c | 6 +- .../Src/stm32f4xx_ll_usb.c | 522 +- .../STM32F4xx_HAL_Driver/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../{mini-st.css => mini-st_2020.css} | 365 +- .../STM32F4xx_HAL_Driver/_htmresc/st_logo.png | Bin 18616 -> 0 bytes .../_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 125 files changed, 10293 insertions(+), 15087 deletions(-) create mode 100644 system/Drivers/STM32F4xx_HAL_Driver/_htmresc/favicon.png rename system/Drivers/STM32F4xx_HAL_Driver/_htmresc/{mini-st.css => mini-st_2020.css} (77%) delete mode 100644 system/Drivers/STM32F4xx_HAL_Driver/_htmresc/st_logo.png create mode 100644 system/Drivers/STM32F4xx_HAL_Driver/_htmresc/st_logo_2020.png diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 934f1f971b..aa00ff4d2c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,16 +37,12 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -113,6 +109,9 @@ extern "C" { #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 #endif /* STM32U5 */ +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ /** * @} */ @@ -140,7 +139,8 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) @@ -214,6 +214,11 @@ extern "C" { #endif #endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + /** * @} */ @@ -234,10 +239,12 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#if defined(STM32C0) +#if defined(STM32H5) || defined(STM32C0) #else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ #endif /** * @} @@ -280,7 +287,13 @@ extern "C" { #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -345,7 +358,8 @@ extern "C" { #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif @@ -530,6 +544,9 @@ extern "C" { #define OB_USER_nBOOT0 OB_USER_NBOOT0 #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ /** @@ -574,6 +591,106 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + /** * @} */ @@ -641,14 +758,16 @@ extern "C" { #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH @@ -670,9 +789,9 @@ extern "C" { #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H5) #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ -#endif /* STM32U5 */ +#endif /* STM32U5 || STM32H5 */ #if defined(STM32U5) #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 @@ -686,7 +805,25 @@ extern "C" { */ #if defined(STM32U5) #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB #endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ /** * @} */ @@ -867,7 +1004,8 @@ extern "C" { #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -1005,7 +1143,7 @@ extern "C" { #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1101,6 +1239,26 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H5) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA */ + #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK @@ -1111,12 +1269,12 @@ extern "C" { #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 */ +#endif /* STM32F7 || STM32H7 || STM32L0 */ /** * @} @@ -1283,7 +1441,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) || defined(STM32MP2) +#if defined(STM32U5) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -1396,30 +1554,40 @@ extern "C" { #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ @@ -1427,6 +1595,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1590,7 +1760,8 @@ extern "C" { #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1599,8 +1770,10 @@ extern "C" { #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode @@ -1634,16 +1807,21 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ - )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1768,6 +1946,17 @@ extern "C" { #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP @@ -1776,6 +1965,8 @@ extern "C" { #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY @@ -1786,6 +1977,7 @@ extern "C" { #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif @@ -1794,6 +1986,20 @@ extern "C" { * @} */ +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA */ + +/** + * @} + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ @@ -1819,7 +2025,8 @@ extern "C" { #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback @@ -2076,7 +2283,8 @@ extern "C" { #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) @@ -2248,8 +2456,10 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ /** * @} */ @@ -2408,7 +2618,9 @@ extern "C" { #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE @@ -2417,8 +2629,12 @@ extern "C" { #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 @@ -2454,8 +2670,8 @@ extern "C" { #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -2959,6 +3175,11 @@ extern "C" { #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE @@ -3423,7 +3644,8 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3568,6 +3790,92 @@ extern "C" { #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE #endif /* STM32U5 */ +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + /** * @} */ @@ -3584,9 +3892,9 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ - defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32C0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3621,6 +3929,13 @@ extern "C" { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER @@ -3639,6 +3954,11 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h index 072ea91f05..c3a94a6e2f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h @@ -21,7 +21,7 @@ #define __STM32F4xx_ADC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -101,11 +101,11 @@ typedef struct If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) - or in Continuous mode (DMA transfer unlimited, whatever number of conversions). - Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). - This parameter can be set to ENABLE or DISABLE. */ -}ADC_InitTypeDef; + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). + This parameter can be set to ENABLE or DISABLE. */ +} ADC_InitTypeDef; @@ -130,7 +130,7 @@ typedef struct sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ -}ADC_ChannelConfTypeDef; +} ADC_ChannelConfTypeDef; /** * @brief ADC Configuration multi-mode structure definition @@ -150,7 +150,7 @@ typedef struct is interrupt mode or in polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ -}ADC_AnalogWDGConfTypeDef; +} ADC_AnalogWDGConfTypeDef; /** * @brief HAL ADC state machine: ADC states definition (bitfields) @@ -217,7 +217,7 @@ typedef struct void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -}ADC_HandleTypeDef; +} ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** @@ -401,7 +401,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ - /** @defgroup ADC_EOCSelection ADC EOC Selection +/** @defgroup ADC_EOCSelection ADC EOC Selection * @{ */ #define ADC_EOC_SEQ_CONV 0x00000000U @@ -562,10 +562,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ /* Initialization/de-initialization functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ @@ -580,25 +580,25 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca * @{ */ /* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} @@ -608,8 +608,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} */ @@ -618,7 +618,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * @{ */ /* Peripheral State functions ***************************************************/ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h index b0a4eb724d..8ce8484dda 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h @@ -21,7 +21,7 @@ #define __STM32F4xx_ADC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -106,7 +106,7 @@ typedef struct If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ -}ADC_InjectionConfTypeDef; +} ADC_InjectionConfTypeDef; /** * @brief ADC Configuration multi-mode structure definition @@ -119,7 +119,7 @@ typedef struct This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ -}ADC_MultiModeTypeDef; +} ADC_MultiModeTypeDef; /** * @} @@ -264,20 +264,20 @@ typedef struct */ /* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); /* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h index aa4a40d0bc..b4c229b209 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h @@ -102,21 +102,25 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ @@ -205,7 +209,11 @@ typedef struct /** * @brief CAN handle Structure definition */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 typedef struct __CAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ { CAN_TypeDef *Instance; /*!< Register base address */ @@ -294,11 +302,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to #define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ #define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ #define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ #define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ #define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ @@ -329,7 +337,8 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to #define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ -#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with + silent mode */ /** * @} */ @@ -644,7 +653,8 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)); HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ @@ -658,7 +668,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca */ /* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig); /** * @} @@ -674,14 +684,16 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox); HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); -uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo); /** * @} @@ -729,8 +741,8 @@ void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); /** @@ -806,7 +818,8 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); #define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) -#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \ + CAN_TX_MAILBOX2)) #define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) #define IS_CAN_DLC(DLC) ((DLC) <= 8U) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h index 9d6c226a74..2abdc3b5b0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h @@ -48,61 +48,70 @@ extern "C" { typedef struct { uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. - It can be one of @ref CEC_Signal_Free_Time + It can be one of CEC_Signal_Free_Time and belongs to the set {0,...,7} where 0x0 is the default configuration else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, - it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE - or CEC_EXTENDED_TOLERANCE */ + it can be a value of CEC_Tolerance : + it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */ - uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. + uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising + Error stops the reception. CEC_NO_RX_STOP_ON_BRE: reception is not stopped. CEC_RX_STOP_ON_BRE: reception is stopped. */ - uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the + uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an + Error-Bit is generated on the CEC line upon Bit Rising Error detection. CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ - uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the + uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an + Error-Bit is generated on the CEC line upon Long Bit Period Error detection. CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ - uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line + uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an + Error-Bit generation on the CEC line upon an error detected on a broadcast message. - It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values: + It supersedes BREGEN and LBPEGEN bits for a broadcast message error + handling. It can take two values: 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. - a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE - and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. + a) BRE detection: error-bit generation on the CEC line if + BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. b) LBPE detection: error-bit generation on the CEC line if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. - no error-bit generation in case neither a) nor b) are satisfied. Additionally, - there is no error-bit generation in case of Short Bit Period Error detection in - a broadcast message while LSTN bit is set. */ + no error-bit generation in case neither a) nor b) are satisfied. + Additionally, there is no error-bit generation in case of Short Bit + Period Error detection in a broadcast message while LSTN bit is set. */ - uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts. + uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts. CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. - CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ + CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end + of message transmission/reception. */ - uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values: + uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode. + It can take two values: - CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its - own address (OAR). Messages addressed to different destination are ignored. + CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed + to its own address (OAR). Messages addressed to different destination + are ignored. Broadcast messages are always received. - CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own - address (OAR) with positive acknowledge. Messages addressed to different destination - are received, but without interfering with the CEC bus: no acknowledge sent. */ + CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its + own address (OAR) with positive acknowledge. Messages addressed to + different destination are received, but without interfering with the + CEC bus: no acknowledge sent. */ - uint16_t OwnAddress; /*!< Own addresses configuration - This parameter can be a value of @ref CEC_OWN_ADDRESS */ + uint16_t OwnAddress; /*!< Own addresses configuration + This parameter can be a value of CEC_OWN_ADDRESS */ uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ @@ -111,7 +120,8 @@ typedef struct /** * @brief HAL CEC State definition - * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition). + * @note HAL CEC State value is a combination of 2 different substates: gState and RxState + (see CEC_State_Definition). * - gState contains CEC state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -159,37 +169,37 @@ typedef struct __CEC_HandleTypeDef typedef struct #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ { - CEC_TypeDef *Instance; /*!< CEC registers base address */ + CEC_TypeDef *Instance; /*!< CEC registers base address */ - CEC_InitTypeDef Init; /*!< CEC communication parameters */ + CEC_InitTypeDef Init; /*!< CEC communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ - uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ + uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ - uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ + uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ - HAL_LockTypeDef Lock; /*!< Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management and also related to Tx operations. - This parameter can be a value of @ref HAL_CEC_StateTypeDef */ + This parameter can be a value of HAL_CEC_StateTypeDef */ HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. - This parameter can be a value of @ref HAL_CEC_StateTypeDef */ + This parameter can be a value of HAL_CEC_StateTypeDef */ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register - in case error is reported */ + in case error is reported */ #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) void (* TxCpltCallback)(struct __CEC_HandleTypeDef - *hcec); /*!< CEC Tx Transfer completed callback */ + *hcec); /*!< CEC Tx Transfer completed callback */ void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, - uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ - void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ + uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ + void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ - void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ - void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ + void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ + void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ } CEC_HandleTypeDef; @@ -202,7 +212,7 @@ typedef enum { HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ - HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ + HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ } HAL_CEC_CallbackIDTypeDef; @@ -212,7 +222,8 @@ typedef enum */ typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, - uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */ + uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed + callback function */ #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ /** * @} @@ -358,16 +369,16 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_OWN_ADDRESS CEC Own Address * @{ */ -#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ -#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ -#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ -#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ -#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ -#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ -#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ -#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ -#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ -#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ +#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ +#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ +#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ +#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ +#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ +#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ +#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ +#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ +#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ +#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ @@ -421,8 +432,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags * @{ */ -#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ - CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) +#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ + CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) /** * @} */ @@ -430,7 +441,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag * @{ */ -#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) +#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) /** * @} */ @@ -438,7 +449,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag * @{ */ -#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) +#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) /** * @} */ @@ -622,7 +633,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) * @retval none */ -#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) +#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \ + (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) /** * @} @@ -660,8 +672,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); */ /* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - uint8_t *pData, uint32_t Size); -uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); + const uint8_t *pData, uint32_t Size); +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec); void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); @@ -675,8 +687,8 @@ void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); * @{ */ /* Peripheral State functions ************************************************/ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec); +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec); /** * @} */ @@ -731,8 +743,9 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) -#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ - ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) +#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \ + (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ + ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) @@ -789,4 +802,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #endif #endif /* STM32F4xxHAL_CEC_H */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h index 8643779a20..51ab367800 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h @@ -286,6 +286,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ +void HAL_CORTEX_ClearEvent(void); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h index 41edbe381c..ac36ed8c43 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h @@ -157,7 +157,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h index a79ca73a17..3ee217afa0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h @@ -78,19 +78,19 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); #if defined(DAC_CHANNEL2_SUPPORT) - void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); #endif /* DAC_CHANNEL2_SUPPORT */ - void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; @@ -404,7 +404,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); @@ -430,8 +430,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA * @{ */ /* Peripheral Control functions ***********************************************/ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ @@ -440,8 +441,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); /** * @} @@ -477,4 +478,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #endif /* STM32F4xx_HAL_DAC_H */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h index db10990297..1bb5ce4563 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h @@ -81,6 +81,7 @@ extern "C" { * @} */ + /** * @} */ @@ -147,19 +148,18 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); #if defined(DAC_CHANNEL2_SUPPORT) -#endif HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac); +#endif /* DAC_CHANNEL2_SUPPORT */ #if defined(DAC_CHANNEL2_SUPPORT) -#endif void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); - +#endif /* DAC_CHANNEL2_SUPPORT */ /** * @} @@ -202,4 +202,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); #endif #endif /* STM32F4xx_HAL_DAC_EX_H */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h index 59720256c6..7c2f96fbaa 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -54,7 +54,9 @@ typedef enum /* Exported macro ------------------------------------------------------------*/ +#if !defined(UNUSED) #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ #define HAL_MAX_DELAY 0xFFFFFFFFU diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h index ad39ff6cb2..2b0f1937d0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h @@ -811,11 +811,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); @@ -827,7 +827,7 @@ void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); * @{ */ /* Channel state function *****************************************************/ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /** * @} */ @@ -887,16 +887,16 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef* awdParam); + const DFSDM_Filter_AwdParamTypeDef* awdParam); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); @@ -917,8 +917,8 @@ void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); * @{ */ /* Filter state functions *****************************************************/ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h index 6da96681c3..6b51ecb2db 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h @@ -976,7 +976,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper enabling */ \ + /* Delay after an DSI wrapper enabling */ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ UNUSED(tmpreg); \ } while(0U) @@ -989,7 +989,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ __IO uint32_t tmpreg = 0x00U; \ CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper disabling*/ \ + /* Delay after an DSI wrapper disabling*/ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ UNUSED(tmpreg); \ } while(0U) @@ -1271,10 +1271,10 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) -#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\ - || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) -#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\ - || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\ + || ((Vsync) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\ + || ((Hsync) == DSI_HSYNC_ACTIVE_LOW)) #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ ((VideoModeType) == DSI_VID_MODE_BURST)) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h index ba5a09bbc8..91fdb62be5 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h @@ -171,6 +171,7 @@ typedef struct * */ +#ifdef HAL_ETH_USE_PTP /** * @brief ETH Timeupdate structure definition */ @@ -182,6 +183,7 @@ typedef struct /** * */ +#endif /* HAL_ETH_USE_PTP */ /** * @brief DMA Receive Descriptors Wrapper structure definition @@ -347,7 +349,6 @@ typedef struct uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers. This parameter can be a value of @ref ETH_Burst_Mode */ - FunctionalState DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */ FunctionalState ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode */ @@ -407,6 +408,7 @@ typedef enum * */ +#ifdef HAL_ETH_USE_PTP /** * @brief HAL ETH PTP Update type enum definition */ @@ -418,13 +420,13 @@ typedef enum /** * */ +#endif /* HAL_ETH_USE_PTP */ /** * @brief ETH Init Structure definition */ typedef struct { - uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ @@ -443,6 +445,7 @@ typedef struct * */ +#ifdef HAL_ETH_USE_PTP /** * @brief ETH PTP Init Structure definition */ @@ -470,6 +473,7 @@ typedef struct /** * */ +#endif /* HAL_ETH_USE_PTP */ /** * @brief HAL State structures definition @@ -538,7 +542,7 @@ typedef struct __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management and also related to Tx operations. This parameter can - be a value of @ref HAL_ETH_StateTypeDef */ + be a value of @ref ETH_State_Codes */ __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine This parameter can be a value of @ref ETH_Error_Code.*/ @@ -595,14 +599,12 @@ typedef enum { HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ - HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */ HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */ HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */ - } HAL_ETH_CallbackIDTypeDef; /** @@ -1298,7 +1300,7 @@ TDES7 | Transmit Time Stamp High [31:0] * @} */ -/** @defgroup HAL_ETH_StateTypeDef ETH States +/** @defgroup ETH_State_Codes ETH States * @{ */ #define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */ @@ -1902,6 +1904,7 @@ TDES7 | Transmit Time Stamp High [31:0] * enabled @ref ETH_MAC_Interrupts * @retval None */ + #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \ |= (__INTERRUPT__)) @@ -1921,8 +1924,8 @@ TDES7 | Transmit Time Stamp High [31:0] * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts * @retval The state of ETH MAC IT (SET or RESET). */ -#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\ - ( __INTERRUPT__)) == ( __INTERRUPT__)) +#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\ + ( __INTERRUPT__)) == ( __INTERRUPT__)) /*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */ #define ETH_WAKEUP_EXTI_LINE 0x00080000U @@ -1991,6 +1994,7 @@ TDES7 | Transmit Time Stamp High [31:0] (__FLAG__)) == (__FLAG__)) ? SET : RESET) #define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__)) + /** * @} */ @@ -2059,7 +2063,7 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue); HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue); @@ -2095,12 +2099,14 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t /* MAC L2 Packet Filtering APIs **********************************************/ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); -HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig); HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); -HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, + const uint8_t *pMACAddr); /* MAC Power Down APIs *****************************************************/ -void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, + const ETH_PowerDownConfigTypeDef *pPowerDownConfig); void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); @@ -2112,11 +2118,11 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi * @{ */ /* Peripheral State functions **************************************************/ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); +HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth); /** * @} */ @@ -2140,5 +2146,3 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); #endif #endif /* STM32F4xx_HAL_ETH_H */ - - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h index 400b923ebb..60ed94b812 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h @@ -119,8 +119,6 @@ typedef enum HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_FMPI2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_FMPI2C_StateTypeDef; @@ -208,6 +206,7 @@ typedef struct __FMPI2C_HandleTypeDef DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */ + HAL_LockTypeDef Lock; /*!< FMPI2C locking object */ __IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */ @@ -218,6 +217,10 @@ typedef struct __FMPI2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */ + __IO uint32_t Devaddress; /*!< FMPI2C Target device address */ + + __IO uint32_t Memaddress; /*!< FMPI2C Target memory address */ + #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Master Tx Transfer completed callback */ @@ -276,7 +279,7 @@ typedef enum typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); /*!< pointer to an FMPI2C callback function */ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, - uint16_t AddrMatchCode); + uint16_t AddrMatchCode); /*!< pointer to an FMPI2C Address Match callback function */ #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ @@ -458,10 +461,10 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint */ #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET) #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ @@ -513,7 +516,7 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ - (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified FMPI2C flag is set or not. * @param __HANDLE__ specifies the FMPI2C Handle. @@ -540,7 +543,7 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint */ #define FMPI2C_FLAG_MASK (0x0001FFFFU) #define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ - (__FLAG__)) == (__FLAG__)) ? SET : RESET) + (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the FMPI2C Handle. @@ -560,8 +563,8 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint * @retval None */ #define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? \ - ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ - ((__HANDLE__)->Instance->ICR = (__FLAG__))) + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified FMPI2C peripheral. * @param __HANDLE__ specifies the FMPI2C Handle. @@ -604,7 +607,7 @@ void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, - pFMPI2C_CallbackTypeDef pCallback); + pFMPI2C_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback); @@ -620,64 +623,64 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); + uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); + uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout); + uint32_t Timeout); /******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); + uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); + uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress); /******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); + uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); + uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); /** * @} */ @@ -706,9 +709,9 @@ void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); * @{ */ /* Peripheral State, Mode and Error functions *********************************/ -HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c); -HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c); -uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); +HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(const FMPI2C_HandleTypeDef *hfmpi2c); +HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(const FMPI2C_HandleTypeDef *hfmpi2c); +uint32_t HAL_FMPI2C_GetError(const FMPI2C_HandleTypeDef *hfmpi2c); /** * @} @@ -733,28 +736,28 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); */ #define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT)) + ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT)) #define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE)) + ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE)) #define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \ - ((MASK) == FMPI2C_OA2_MASK01) || \ - ((MASK) == FMPI2C_OA2_MASK02) || \ - ((MASK) == FMPI2C_OA2_MASK03) || \ - ((MASK) == FMPI2C_OA2_MASK04) || \ - ((MASK) == FMPI2C_OA2_MASK05) || \ - ((MASK) == FMPI2C_OA2_MASK06) || \ - ((MASK) == FMPI2C_OA2_MASK07)) + ((MASK) == FMPI2C_OA2_MASK01) || \ + ((MASK) == FMPI2C_OA2_MASK02) || \ + ((MASK) == FMPI2C_OA2_MASK03) || \ + ((MASK) == FMPI2C_OA2_MASK04) || \ + ((MASK) == FMPI2C_OA2_MASK05) || \ + ((MASK) == FMPI2C_OA2_MASK06) || \ + ((MASK) == FMPI2C_OA2_MASK07)) #define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \ - ((CALL) == FMPI2C_GENERALCALL_ENABLE)) + ((CALL) == FMPI2C_GENERALCALL_ENABLE)) #define IS_FMPI2C_NO_STRETCH(STRETCH) (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE)) + ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE)) #define IS_FMPI2C_MEMADD_SIZE(SIZE) (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT)) + ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT)) #define IS_TRANSFER_MODE(MODE) (((MODE) == FMPI2C_RELOAD_MODE) || \ ((MODE) == FMPI2C_AUTOEND_MODE) || \ @@ -766,25 +769,25 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); ((REQUEST) == FMPI2C_NO_STARTSTOP)) #define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_FIRST_FRAME) || \ - ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \ - ((REQUEST) == FMPI2C_NEXT_FRAME) || \ - ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == FMPI2C_LAST_FRAME) || \ - ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP) || \ - IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == FMPI2C_NEXT_FRAME) || \ + ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == FMPI2C_LAST_FRAME) || \ + ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP) || \ + IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) #define IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_OTHER_FRAME) || \ - ((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME)) + ((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME)) #define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ - FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ - FMPI2C_CR2_RD_WRN))) + (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ + FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ + FMPI2C_CR2_RD_WRN))) #define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) \ - >> 16U)) + >> 16U)) #define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) \ - >> 16U)) + >> 16U)) #define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) #define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)) #define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)) @@ -793,19 +796,19 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); #define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) #define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ - (uint16_t)(0xFF00U))) >> 8U))) + (uint16_t)(0xFF00U))) >> 8U))) #define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) #define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ - (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ - (~FMPI2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ - (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & \ - (~FMPI2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ + (~FMPI2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START) | \ + (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN))) #define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \ - ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET) #define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h index 8b90f40752..995b5d3f4c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h @@ -115,12 +115,12 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE)) + ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE)) #define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \ - (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA)) + (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA)) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h index 6d1ff4b19c..84c5400240 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h @@ -101,8 +101,6 @@ typedef struct #define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} @@ -208,7 +206,7 @@ typedef enum typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< pointer to an FMPSMBUS callback function */ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, - uint16_t AddrMatchCode); + uint16_t AddrMatchCode); /*!< pointer to an FMPSMBUS Address Match callback function */ #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ @@ -372,9 +370,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE #define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ - FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) #define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ - FMPSMBUS_IT_RXI) + FMPSMBUS_IT_RXI) #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) /** @@ -423,10 +421,10 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus */ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ @@ -512,6 +510,7 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus * @param __HANDLE__ specifies the FMPSMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: + * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) * @arg @ref FMPSMBUS_FLAG_AF NACK received flag * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag @@ -524,7 +523,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus * * @retval None */ -#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPSMBUS_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified FMPSMBUS peripheral. * @param __HANDLE__ specifies the FMPSMBUS Handle. @@ -557,84 +558,84 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus */ #define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \ - ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) + ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) #define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \ - ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) + ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) #define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) + ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) #define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \ - ((MASK) == FMPSMBUS_OA2_MASK01) || \ - ((MASK) == FMPSMBUS_OA2_MASK02) || \ - ((MASK) == FMPSMBUS_OA2_MASK03) || \ - ((MASK) == FMPSMBUS_OA2_MASK04) || \ - ((MASK) == FMPSMBUS_OA2_MASK05) || \ - ((MASK) == FMPSMBUS_OA2_MASK06) || \ - ((MASK) == FMPSMBUS_OA2_MASK07)) + ((MASK) == FMPSMBUS_OA2_MASK01) || \ + ((MASK) == FMPSMBUS_OA2_MASK02) || \ + ((MASK) == FMPSMBUS_OA2_MASK03) || \ + ((MASK) == FMPSMBUS_OA2_MASK04) || \ + ((MASK) == FMPSMBUS_OA2_MASK05) || \ + ((MASK) == FMPSMBUS_OA2_MASK06) || \ + ((MASK) == FMPSMBUS_OA2_MASK07)) #define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \ - ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) + ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) #define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \ - ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) + ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) #define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \ - ((PEC) == FMPSMBUS_PEC_ENABLE)) + ((PEC) == FMPSMBUS_PEC_ENABLE)) #define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \ - ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ - ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) + ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ + ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) #define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ - ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ - ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ - ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ - ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ - FMPSMBUS_RELOAD_MODE ))) + ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ + ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ + ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ + ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ + FMPSMBUS_RELOAD_MODE ))) #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ - ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ - ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ - ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) + ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ + ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) #define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ - ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ - ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) + ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ + ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) #define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) + ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) #define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ - FMPI2C_CR1_PECEN))) + (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ + FMPI2C_CR1_PECEN))) #define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ - FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ - FMPI2C_CR2_RD_WRN))) + (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ + FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ + FMPI2C_CR2_RD_WRN))) #define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ - (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ - (~FMPI2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & \ - (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ - (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ + (~FMPI2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ + (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) @@ -643,7 +644,7 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus #define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN) #define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ - ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) #define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) #define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) @@ -676,13 +677,13 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, - pFMPSMBUS_CallbackTypeDef pCallback); + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, + pFMPSMBUS_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - pFMPSMBUS_AddrCallbackTypeDef pCallback); + pFMPSMBUS_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ /** @@ -699,7 +700,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf */ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout); + uint32_t Timeout); /** * @} */ @@ -709,14 +710,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, */ /******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions); + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions); + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); @@ -749,8 +750,8 @@ void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); */ /* Peripheral State and Errors functions **************************************************/ -uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus); -uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); +uint32_t HAL_FMPSMBUS_GetState(const FMPSMBUS_HandleTypeDef *hfmpsmbus); +uint32_t HAL_FMPSMBUS_GetError(const FMPSMBUS_HandleTypeDef *hfmpsmbus); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h index 001dc54733..e83a598dd8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h @@ -104,9 +104,9 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == \ - FMPSMBUS_FASTMODEPLUS_SCL) || \ - (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \ - FMPSMBUS_FASTMODEPLUS_SDA)) + FMPSMBUS_FASTMODEPLUS_SCL) || \ + (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \ + FMPSMBUS_FASTMODEPLUS_SDA)) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h index 9cd148626c..a6fee35e45 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h @@ -159,6 +159,10 @@ typedef struct #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ + ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) + #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) @@ -167,6 +171,9 @@ typedef struct #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) #define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN) /** * @} */ @@ -248,6 +255,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping); +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr); + +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num); + /* Non-Blocking mode: Interrupt */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd); @@ -277,16 +289,13 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions * @{ */ -HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd); -HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum); -HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum); -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd); +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum); uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); -/** - * @} - */ /** * @} @@ -307,6 +316,9 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** * @} */ +/** + * @} + */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #ifdef __cplusplus diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h index 0d1c5f15a3..5735215dc1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h @@ -593,8 +593,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); * @{ */ /* Peripheral State functions **************************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h index 7a41ee9da0..fba2d52c0d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h @@ -689,9 +689,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); * @{ */ /* Reading operation functions ************************************************/ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -727,7 +727,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ * @{ */ /* Peripheral State functions ************************************************/ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h index ab951d3ea7..78349ebbf4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h @@ -338,14 +338,14 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer /** @defgroup LTDC_Pixelformat LTDC Pixel format * @{ */ -#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h index 26f650256f..9fc12a0189 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h @@ -109,9 +109,8 @@ typedef struct FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This parameter is mandatory for some NAND parts after the read command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. - Example: Toshiba THTH58BYG3S0HBAI6. This parameter could be ENABLE or DISABLE - Please check the Read Mode sequnece in the NAND device datasheet */ + Please check the Read Mode sequence in the NAND device datasheet */ } NAND_DeviceConfigTypeDef; /** @@ -131,7 +130,7 @@ typedef struct __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ - NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ + NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ @@ -219,27 +218,27 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ @@ -269,8 +268,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, * @{ */ /* NAND State functions *******************************************************/ -HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand); +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand); /** * @} */ @@ -290,7 +289,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); #define NAND_DEVICE2 0x80000000UL #else #define NAND_DEVICE 0x80000000UL -#endif +#endif /* NAND_SECOND_BANK */ #define NAND_WRITE_TIMEOUT 0x01000000UL #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h index cc7f1b5e50..427c2ccd1a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h @@ -238,7 +238,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); */ /* NOR State functions ********************************************************/ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor); HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h index 92488b2fe7..de1ec24186 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h @@ -190,14 +190,14 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ @@ -368,9 +368,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); /** * @} */ @@ -379,7 +381,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions * @{ */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h index 72ded2b6ca..0c6f2e01dd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h @@ -51,15 +51,21 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \ + || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); -#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h index 3b9ad5a390..c391153ba1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @@ -114,6 +114,8 @@ typedef struct */ #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) + /** * @} */ @@ -123,6 +125,7 @@ typedef struct */ #define PWR_STOPENTRY_WFI ((uint8_t)0x01) #define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) /** * @} */ @@ -401,8 +404,14 @@ void HAL_PWR_DisableSEVOnPend(void); ((MODE) == PWR_PVD_MODE_NORMAL)) #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \ + ((ENTRY) == PWR_STOPENTRY_WFE) || \ + ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h index dcf5814451..c348e5effa 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -660,7 +660,6 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) @@ -683,7 +682,6 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) @@ -708,7 +706,6 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) @@ -1407,7 +1404,7 @@ void HAL_RCC_CSSCallback(void); ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) +#define IS_RCC_PLLM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h index dbcc98cd29..735c8f7c62 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -526,7 +526,7 @@ typedef struct * @{ */ #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U -#define RCC_I2SCLKSOURCE_EXT 0x00000001U +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC /** * @} */ @@ -1665,6 +1665,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x22E017FFU) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) @@ -1696,7 +1697,12 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F469xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) +#endif /* STM32F427xx || STM32F429xx || STM32F469xx */ +#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) @@ -1721,7 +1727,12 @@ typedef struct * @brief Force or release AHB3 peripheral reset. * @{ */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) +#endif /* STM32F469xx || STM32F479xx */ #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) @@ -1738,6 +1749,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) @@ -1783,6 +1795,15 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x0C777933U) +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F429xx) || defined(STM32F439xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) +#endif /* STM32F429xx || STM32F439xx */ +#if defined(STM32F427xx) || defined(STM32F437xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00777933U) +#endif /* STM32F427xx || STM32F437xx */ #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) @@ -2590,6 +2611,12 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#if defined (STM32F405xx) || defined (STM32F415xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206011FFU) +#endif /* STM32F405xx || STM32F415xx */ +#if defined (STM32F407xx) || defined (STM32F417xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x226011FFU) +#endif /* STM32F407xx || STM32F417xx */ #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) @@ -2615,7 +2642,12 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#if defined (STM32F415xx) || defined (STM32F417xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) +#endif /* STM32F415xx || STM32F417xx */ +#if defined (STM32F405xx) || defined (STM32F407xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) +#endif /* STM32F405xx || STM32F407xx */ #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) #if defined(STM32F407xx)|| defined(STM32F417xx) @@ -2644,7 +2676,7 @@ typedef struct * @brief Force or release AHB3 peripheral reset. * @{ */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) @@ -2657,6 +2689,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) @@ -2698,6 +2731,7 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) @@ -3097,7 +3131,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) @@ -3114,7 +3148,7 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) @@ -3127,7 +3161,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) @@ -3148,7 +3182,7 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00077931U) #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) @@ -3413,6 +3447,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x80601087U) #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) @@ -3445,6 +3480,12 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#if defined (STM32F410Rx) || defined (STM32F410Cx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31624A18U) +#endif /* STM32F410Rx || STM32F410Cx */ +#if defined (STM32F410Tx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31620A18U) +#endif /* STM32F410Tx */ #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) @@ -3462,6 +3503,12 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#if defined (STM32F410Rx) || defined (STM32F410Cx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00155131U) +#endif /* STM32F410Rx || STM32F410Cx */ +#if defined (STM32F410Tx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00055111U) +#endif /* STM32F410Tx */ #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) /** @@ -3754,6 +3801,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) @@ -3769,7 +3817,7 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) @@ -3792,6 +3840,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) @@ -3811,6 +3860,7 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00177931U) #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) @@ -4430,6 +4480,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206010FFU) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) @@ -4451,7 +4502,7 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000081U) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) @@ -4468,7 +4519,7 @@ typedef struct * @brief Force or release AHB3 peripheral reset. * @{ */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) @@ -4484,6 +4535,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x3FFFC9FFU) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) @@ -4531,6 +4583,7 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00C77933U) #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) @@ -5343,6 +5396,18 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#if defined (STM32F412Zx) || defined(STM32F413xx) || defined (STM32F423xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x006010FFU) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined (STM32F412Cx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x00601087U) +#endif /* STM32F412Cx */ +#if defined (STM32F412Vx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) +#endif /* STM32F412Vx */ +#if defined (STM32F412Rx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060108FU) +#endif /* STM32F412Rx */ #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ @@ -5374,10 +5439,11 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C0U) #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) #if defined(STM32F423xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000D0U) #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) #endif /* STM32F423xx */ @@ -5396,7 +5462,7 @@ typedef struct * @{ */ #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) @@ -5423,6 +5489,12 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFECBFFU) +#endif /* STM32F413xx || STM32F423xx */ +#if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x17E6C9FFU) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) @@ -5486,6 +5558,12 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#if defined(STM32F413xx)|| defined(STM32F423xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x035779F3U) +#endif /* STM32F413xx || STM32F423xx */ +#if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x01177933U) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #if defined(STM32F413xx) || defined(STM32F423xx) #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) @@ -6101,7 +6179,7 @@ typedef struct * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin * used as I2S clock source. */ -#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (__SOURCE__))) /** @brief Macro to get the I2S clock source (I2SCLK). diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h index 7d4dca1ebd..87279ef79c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h @@ -304,7 +304,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); @@ -317,8 +317,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h index 24affc5428..9d58161fe0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -489,6 +489,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to (__HANDLE__)->Instance->WPR = 0xFFU; \ } while(0U) +/** + * @brief Check whether the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U) /** * @brief Enable the RTC ALARMA peripheral. @@ -772,6 +778,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); RTC_DR_MT | RTC_DR_MU | \ RTC_DR_DT | RTC_DR_DU | \ RTC_DR_WDU)) +#define RTC_ISR_RESERVED_MASK ((uint32_t)(RTC_FLAGS_MASK | RTC_ISR_INIT)) #define RTC_INIT_MASK 0xFFFFFFFFU #define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) #define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h index ff5f14d498..bee4e320bc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -162,7 +162,7 @@ typedef struct * @{ */ #define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U -#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG +#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE /** @@ -635,18 +635,6 @@ typedef struct */ #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__)) -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper 1 interrupt - * @arg RTC_IT_TAMP2: Tamper 2 interrupt - * @note RTC_IT_TAMP2 is not applicable to all devices. - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) - /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h index 6c23f93c15..368316d20a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h @@ -748,8 +748,8 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); * @{ */ /* Peripheral State functions ************************************************/ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai); -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h index c6fdd56612..75ba6d20f5 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h @@ -71,8 +71,8 @@ extern "C" { */ /* Extended features functions ************************************************/ -void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai); -uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai); +void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai); +uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h index 135f40261e..7aa4ce34b8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h @@ -671,8 +671,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc); * @{ */ /* Peripheral State functions **************************************************/ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc); +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h index ea92afa30c..d0ffed83cb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h @@ -150,35 +150,35 @@ typedef enum */ typedef struct __SMBUS_HandleTypeDef { - I2C_TypeDef *Instance; /*!< SMBUS registers base address */ + I2C_TypeDef *Instance; /*!< SMBUS registers base address */ - SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ + SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ - uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ + uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ - uint16_t XferSize; /*!< SMBUS transfer size */ + uint16_t XferSize; /*!< SMBUS transfer size */ - __IO uint16_t XferCount; /*!< SMBUS transfer counter */ + __IO uint16_t XferCount; /*!< SMBUS transfer counter */ __IO uint32_t XferOptions; /*!< SMBUS transfer options this parameter can - be a value of @ref SMBUS_OPTIONS */ + be a value of @ref SMBUS_XferOptions_definition */ __IO uint32_t PreviousState; /*!< SMBUS communication Previous state and mode - context for internal usage */ + context for internal usage */ - HAL_LockTypeDef Lock; /*!< SMBUS locking object */ + HAL_LockTypeDef Lock; /*!< SMBUS locking object */ - __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */ + __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */ - __IO HAL_SMBUS_ModeTypeDef Mode; /*!< SMBUS communication mode */ + __IO HAL_SMBUS_ModeTypeDef Mode; /*!< SMBUS communication mode */ - __IO uint32_t ErrorCode; /*!< SMBUS Error code */ + __IO uint32_t ErrorCode; /*!< SMBUS Error code */ - __IO uint32_t Devaddress; /*!< SMBUS Target device address */ + __IO uint32_t Devaddress; /*!< SMBUS Target device address */ - __IO uint32_t EventCount; /*!< SMBUS Event counter */ + __IO uint32_t EventCount; /*!< SMBUS Event counter */ - uint8_t XferPEC; /*!< SMBUS PEC data in reception mode */ + uint8_t XferPEC; /*!< SMBUS PEC data in reception mode */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ @@ -604,6 +604,10 @@ void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_AbortCpltCallback(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + /** * @} */ @@ -718,10 +722,6 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); * @} */ -/** -* @} -*/ - #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h index 7ea04aa900..386903bcf0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h @@ -56,7 +56,8 @@ typedef struct uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input. This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */ - uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B. + uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status + from channel A or B. This parameter can be a value of @ref SPDIFRX_Channel_Selection */ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). @@ -65,16 +66,19 @@ typedef struct uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ - uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_PT_Mask */ + uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PT_Mask */ - uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame. + uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not + into the received frame. This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. This parameter can be a value of @ref SPDIFRX_V_Mask */ - uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame. + uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not + into the received frame. This parameter can be a value of @ref SPDIFRX_PE_Mask */ } SPDIFRX_InitTypeDef; @@ -89,17 +93,20 @@ typedef struct uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ - uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_PT_Mask */ + uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PT_Mask */ - uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ + uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_V_Mask */ + This parameter can be a value of @ref SPDIFRX_V_Mask */ - uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_PE_Mask */ + uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PE_Mask */ } SPDIFRX_SetDataFormatTypeDef; @@ -151,7 +158,8 @@ typedef struct decremented when a sample is received. NbSamplesReceived = RxBufferSize-RxBufferCount) */ - DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */ + DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information + DMA handle parameters */ DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */ @@ -162,9 +170,11 @@ typedef struct __IO uint32_t ErrorCode; /* SPDIFRX Error code */ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed callback */ + void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed + callback */ void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */ - void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */ + void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed + callback */ void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */ void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */ void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */ @@ -172,9 +182,6 @@ typedef struct #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } SPDIFRX_HandleTypeDef; -/** - * @} - */ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) /** @@ -194,9 +201,12 @@ typedef enum /** * @brief HAL SPDIFRX Callback pointer definition */ -typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */ +typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback + function */ #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ - +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants * @{ @@ -260,8 +270,10 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< /** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask * @{ */ -#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */ -#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/ +#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied + into the SPDIF_DR */ +#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied + into the SPDIF_DR, zeros are written instead*/ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h index e135aa1378..a6e61110ee 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h @@ -209,7 +209,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); */ /* SRAM State functions ******************************************************/ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h index 8c81414fad..1a8357cddb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h @@ -385,29 +385,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1654,6 +1653,10 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3)) @@ -1705,7 +1708,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -1896,7 +1898,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} @@ -1918,7 +1920,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -1940,7 +1943,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -1992,7 +1996,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @{ */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); @@ -2025,21 +2029,26 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, @@ -2049,7 +2058,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ @@ -2086,17 +2095,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @{ */ /* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); /** * @} */ @@ -2110,9 +2119,9 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h index 39fb500f67..561e9bbe87 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h @@ -74,9 +74,8 @@ typedef struct #if defined (TIM2) #if defined(TIM8) #define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */ -#else -#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ #endif /* TIM8 */ +#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ #define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */ #define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */ #endif /* TIM2 */ @@ -205,7 +204,7 @@ typedef struct * @{ */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); @@ -238,7 +237,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -257,7 +257,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -291,9 +292,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); + const TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); /** * @} @@ -316,8 +317,8 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); * @{ */ /* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h index c5f5d3e348..e6ce82fca7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h @@ -137,12 +137,23 @@ typedef enum /** * @brief HAL UART Reception type definition * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : + * This parameter can be a value of @ref UART_Reception_Type_Values : * HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_TOIDLE = 0x01U, */ typedef uint32_t HAL_UART_RxTypeTypeDef; +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -166,6 +177,8 @@ typedef struct __UART_HandleTypeDef __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ @@ -381,7 +394,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @} */ -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values +/** @defgroup UART_Reception_Type_Values UART Reception type values * @{ */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ @@ -390,6 +403,16 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @} */ +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) +/** + * @} + */ + /** * @} */ @@ -734,6 +757,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); + /* Transfer Abort functions */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); @@ -775,8 +800,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); * @{ */ /* Peripheral State functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h index b64e95dc0c..655f8482ee 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h @@ -544,8 +544,8 @@ void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); * @{ */ /* Peripheral State functions ************************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); /** * @} */ @@ -624,7 +624,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup USART_Private_Functions USART Private Functions +/** @addtogroup USART_Private_Functions * @{ */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h index 44e8af28d3..43b4a1ed54 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h @@ -684,8 +684,8 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode -* @{ -*/ + * @{ + */ #define LL_ADC_REG_CONV_SINGLE 0x00000000UL /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** @@ -808,8 +808,8 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode -* @{ -*/ + * @{ + */ #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** @@ -1866,12 +1866,12 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { /* Retrieve address of register DR */ - data_reg_addr = (uint32_t)&(ADCx->DR); + data_reg_addr = (uint32_t) & (ADCx->DR); } else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ { /* Retrieve address of register CDR */ - data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); + data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); } return data_reg_addr; @@ -1879,8 +1879,11 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis #else __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { + /* Prevent unused argument compilation warning */ + (void)Register; + /* Retrieve address of register DR */ - return (uint32_t)&(ADCx->DR); + return (uint32_t) & (ADCx->DR); } #endif @@ -2145,11 +2148,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { -/* Note: On this STM32 series, ADC group regular external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_REG_StartConversionExtTrig(). */ + /* Note: On this STM32 series, ADC group regular external trigger edge */ + /* is used to perform a ADC conversion start. */ + /* This function does not set external trigger edge. */ + /* This feature is set using function */ + /* @ref LL_ADC_REG_StartConversionExtTrig(). */ MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); } @@ -2588,10 +2591,10 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); - return (uint32_t) (READ_BIT(*preg, - ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) - ); + return (uint32_t)(READ_BIT(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ); } /** @@ -2780,11 +2783,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { -/* Note: On this STM32 series, ADC group injected external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ + /* Note: On this STM32 series, ADC group injected external trigger edge */ + /* is used to perform a ADC conversion start. */ + /* This function does not set external trigger edge. */ + /* This feature is set using function */ + /* @ref LL_ADC_INJ_StartConversionExtTrig(). */ MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); } @@ -4015,7 +4018,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } /** @@ -4030,7 +4033,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } #if defined(ADC_MULTIMODE_SUPPORT) @@ -4546,7 +4549,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); } #endif /* ADC_MULTIMODE_SUPPORT */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h index d478e13019..3861f55ffd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h @@ -371,6 +371,16 @@ __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } +/** + * @brief Clear pending events. + * @retval None + */ +__STATIC_INLINE void LL_LPM_ClearEvent(void) +{ + __SEV(); + __WFE(); +} + /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h index 0a280062b8..8ada06d580 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). */ -__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->DR)); } @@ -173,7 +173,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) * @{ */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h index ea1500ba58..4bff015f18 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h @@ -118,10 +118,10 @@ extern "C" { /* DAC registers bits positions */ #if defined(DAC_CHANNEL2_SUPPORT) -#endif #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos +#endif /* DAC_CHANNEL2_SUPPORT */ /* Miscellaneous data */ #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 @@ -429,7 +429,7 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval 1...2 (value "2" depending on DAC channel 2 availability) */ @@ -449,36 +449,26 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. */ #if defined(DAC_CHANNEL2_SUPPORT) -#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1UL) \ - ? ( \ - LL_DAC_CHANNEL_1 \ - ) \ - : \ - (((__DECIMAL_NB__) == 2UL) \ - ? ( \ - LL_DAC_CHANNEL_2 \ - ) \ - : \ - ( \ - 0UL \ - ) \ - ) \ +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1UL) \ + ? (LL_DAC_CHANNEL_1) \ + : \ + (((__DECIMAL_NB__) == 2UL) \ + ? (LL_DAC_CHANNEL_2) \ + : \ + (0UL) \ + ) \ ) #else -#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1UL) \ - ? ( \ - LL_DAC_CHANNEL_1 \ - ) \ - : \ - ( \ - 0UL \ - ) \ +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1UL) \ + ? (LL_DAC_CHANNEL_1) \ + : \ + (0UL) \ ) #endif /* DAC_CHANNEL2_SUPPORT */ @@ -514,12 +504,10 @@ typedef struct * @arg @ref LL_DAC_RESOLUTION_8B * @retval DAC conversion data (unit: digital value) */ -#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ - __DAC_VOLTAGE__,\ - __DAC_RESOLUTION__) \ -((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ -) +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ + ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ + ) /** * @} @@ -534,6 +522,7 @@ typedef struct /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions * @{ */ + /** * @brief Set the conversion trigger source for the selected DAC channel. * @note For conversion trigger source to be effective, DAC trigger @@ -549,7 +538,7 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -582,7 +571,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -594,7 +583,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 */ -__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -611,7 +600,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param WaveAutoGeneration This parameter can be one of the following values: * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE @@ -636,14 +625,14 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -665,7 +654,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param NoiseLFSRMask This parameter can be one of the following values: * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 @@ -699,7 +688,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 @@ -715,7 +704,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -737,7 +726,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param TriangleAmplitude This parameter can be one of the following values: * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 @@ -772,7 +761,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 @@ -788,7 +777,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -804,7 +793,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputBuffer This parameter can be one of the following values: * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE @@ -827,13 +816,13 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -859,7 +848,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -880,7 +869,7 @@ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -900,11 +889,11 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -938,7 +927,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Register This parameter can be one of the following values: * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED @@ -946,7 +935,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED * @retval DAC register address */ -__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ @@ -973,7 +962,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -992,7 +981,7 @@ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -1012,11 +1001,11 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1040,7 +1029,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -1059,7 +1048,7 @@ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -1079,11 +1068,11 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1110,7 +1099,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -1131,7 +1120,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None @@ -1155,7 +1144,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None @@ -1179,7 +1168,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x00 and Max_Data=0xFF * @retval None @@ -1267,11 +1256,11 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); @@ -1293,7 +1282,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); } @@ -1305,7 +1294,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); } @@ -1397,7 +1386,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); } @@ -1409,7 +1398,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); } @@ -1424,8 +1413,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) * @{ */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); /** @@ -1452,4 +1441,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); #endif #endif /* STM32F4xx_LL_DAC_H */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h index 3dc863d46c..dda9d895a4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h @@ -369,7 +369,7 @@ typedef struct delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ } FMC_NAND_InitTypeDef; -#endif +#endif /* FMC_Bank3 || FMC_Bank2_3 */ #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) /** @@ -1388,7 +1388,7 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); -uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h index dcc001605e..a3c14b6ef2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h @@ -295,7 +295,7 @@ typedef struct #define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ #define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | \ - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) + FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ #define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ @@ -343,7 +343,7 @@ typedef struct #define LL_FMPI2C_FMPSMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ #define LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | \ - FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB + FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ /** * @} @@ -452,7 +452,7 @@ __STATIC_INLINE void LL_FMPI2C_Disable(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE) == (FMPI2C_CR1_PE)) ? 1UL : 0UL); } @@ -501,7 +501,7 @@ __STATIC_INLINE void LL_FMPI2C_SetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx, uint32_ * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_DNF) >> FMPI2C_CR1_DNF_Pos); } @@ -536,7 +536,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF) != (FMPI2C_CR1_ANFOFF)) ? 1UL : 0UL); } @@ -569,7 +569,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN) == (FMPI2C_CR1_TXDMAEN)) ? 1UL : 0UL); } @@ -602,7 +602,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN) == (FMPI2C_CR1_RXDMAEN)) ? 1UL : 0UL); } @@ -617,7 +617,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) * @arg @ref LL_FMPI2C_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(const FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction) { uint32_t data_reg_addr; @@ -665,7 +665,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableClockStretching(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH) != (FMPI2C_CR1_NOSTRETCH)) ? 1UL : 0UL); } @@ -698,7 +698,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL); } @@ -733,7 +733,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableGeneralCall(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN) == (FMPI2C_CR1_GCEN)) ? 1UL : 0UL); } @@ -761,7 +761,7 @@ __STATIC_INLINE void LL_FMPI2C_SetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx, * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_ADD10)); } @@ -810,7 +810,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN) == (FMPI2C_OAR1_OA1EN)) ? 1UL : 0UL); } @@ -866,7 +866,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN) == (FMPI2C_OAR2_OA2EN)) ? 1UL : 0UL); } @@ -891,7 +891,7 @@ __STATIC_INLINE void LL_FMPI2C_SetTiming(FMPI2C_TypeDef *FMPI2Cx, uint32_t Timin * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_PRESC) >> FMPI2C_TIMINGR_PRESC_Pos); } @@ -902,7 +902,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLL) >> FMPI2C_TIMINGR_SCLL_Pos); } @@ -913,7 +913,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLH) >> FMPI2C_TIMINGR_SCLH_Pos); } @@ -924,7 +924,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SDADEL) >> FMPI2C_TIMINGR_SDADEL_Pos); } @@ -935,7 +935,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLDEL) >> FMPI2C_TIMINGR_SCLDEL_Pos); } @@ -972,7 +972,7 @@ __STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t Periphe * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetMode(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN)); } @@ -1021,7 +1021,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN) == (FMPI2C_CR1_ALERTEN)) ? 1UL : 0UL); } @@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN) == (FMPI2C_CR1_PECEN)) ? 1UL : 0UL); } @@ -1082,7 +1082,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) * @retval None */ __STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, - uint32_t TimeoutB) + uint32_t TimeoutB) { MODIFY_REG(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA | FMPI2C_TIMEOUTR_TIDLE | FMPI2C_TIMEOUTR_TIMEOUTB, TimeoutA | TimeoutAMode | (TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos)); @@ -1111,7 +1111,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_ * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA)); } @@ -1143,7 +1143,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uin * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIDLE)); } @@ -1171,7 +1171,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_ * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTB) >> FMPI2C_TIMEOUTR_TIMEOUTB_Pos); } @@ -1225,7 +1225,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint * @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(const FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) { return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == \ (ClockTimeout)) ? 1UL : 0UL); @@ -1267,7 +1267,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_TX(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE) == (FMPI2C_CR1_TXIE)) ? 1UL : 0UL); } @@ -1300,7 +1300,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_RX(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE) == (FMPI2C_CR1_RXIE)) ? 1UL : 0UL); } @@ -1333,7 +1333,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE) == (FMPI2C_CR1_ADDRIE)) ? 1UL : 0UL); } @@ -1366,7 +1366,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_NACK(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE) == (FMPI2C_CR1_NACKIE)) ? 1UL : 0UL); } @@ -1399,7 +1399,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_STOP(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE) == (FMPI2C_CR1_STOPIE)) ? 1UL : 0UL); } @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_TC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE) == (FMPI2C_CR1_TCIE)) ? 1UL : 0UL); } @@ -1489,7 +1489,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_ERR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE) == (FMPI2C_CR1_ERRIE)) ? 1UL : 0UL); } @@ -1510,7 +1510,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXE) == (FMPI2C_ISR_TXE)) ? 1UL : 0UL); } @@ -1523,7 +1523,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXIS) == (FMPI2C_ISR_TXIS)) ? 1UL : 0UL); } @@ -1536,7 +1536,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_RXNE) == (FMPI2C_ISR_RXNE)) ? 1UL : 0UL); } @@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDR) == (FMPI2C_ISR_ADDR)) ? 1UL : 0UL); } @@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_NACKF) == (FMPI2C_ISR_NACKF)) ? 1UL : 0UL); } @@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_STOPF) == (FMPI2C_ISR_STOPF)) ? 1UL : 0UL); } @@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TC) == (FMPI2C_ISR_TC)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TCR) == (FMPI2C_ISR_TCR)) ? 1UL : 0UL); } @@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BERR) == (FMPI2C_ISR_BERR)) ? 1UL : 0UL); } @@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ARLO) == (FMPI2C_ISR_ARLO)) ? 1UL : 0UL); } @@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_OVR) == (FMPI2C_ISR_OVR)) ? 1UL : 0UL); } @@ -1655,7 +1655,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_PECERR) == (FMPI2C_ISR_PECERR)) ? 1UL : 0UL); } @@ -1670,7 +1670,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TIMEOUT) == (FMPI2C_ISR_TIMEOUT)) ? 1UL : 0UL); } @@ -1686,7 +1686,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMP * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ALERT) == (FMPI2C_ISR_ALERT)) ? 1UL : 0UL); } @@ -1699,7 +1699,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2 * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BUSY) == (FMPI2C_ISR_BUSY)) ? 1UL : 0UL); } @@ -1860,7 +1860,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND) == (FMPI2C_CR2_AUTOEND)) ? 1UL : 0UL); } @@ -1895,7 +1895,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableReloadMode(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD) == (FMPI2C_CR2_RELOAD)) ? 1UL : 0UL); } @@ -1919,7 +1919,7 @@ __STATIC_INLINE void LL_FMPI2C_SetTransferSize(FMPI2C_TypeDef *FMPI2Cx, uint32_t * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES) >> FMPI2C_CR2_NBYTES_Pos); } @@ -1996,7 +1996,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R) != (FMPI2C_CR2_HEAD10R)) ? 1UL : 0UL); } @@ -2024,7 +2024,7 @@ __STATIC_INLINE void LL_FMPI2C_SetTransferRequest(FMPI2C_TypeDef *FMPI2Cx, uint3 * @arg @ref LL_FMPI2C_REQUEST_WRITE * @arg @ref LL_FMPI2C_REQUEST_READ */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN)); } @@ -2048,7 +2048,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Sl * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_SADD)); } @@ -2092,13 +2092,20 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx) * @retval None */ __STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, - uint32_t TransferSize, uint32_t EndMode, uint32_t Request) + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & FMPI2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & FMPI2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << FMPI2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** @@ -2111,7 +2118,7 @@ __STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t * @arg @ref LL_FMPI2C_DIRECTION_WRITE * @arg @ref LL_FMPI2C_DIRECTION_READ */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_DIR)); } @@ -2122,7 +2129,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDCODE) >> FMPI2C_ISR_ADDCODE_Pos << 1); } @@ -2152,7 +2159,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE) == (FMPI2C_CR2_PECBYTE)) ? 1UL : 0UL); } @@ -2165,7 +2172,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->PECR, FMPI2C_PECR_PEC)); } @@ -2176,7 +2183,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(const FMPI2C_TypeDef *FMPI2Cx) { return (uint8_t)(READ_BIT(FMPI2Cx->RXDR, FMPI2C_RXDR_RXDATA)); } @@ -2202,8 +2209,8 @@ __STATIC_INLINE void LL_FMPI2C_TransmitData8(FMPI2C_TypeDef *FMPI2Cx, uint8_t Da * @{ */ -ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); -ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx); +ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, const LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); +ErrorStatus LL_FMPI2C_DeInit(const FMPI2C_TypeDef *FMPI2Cx); void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h index 8b0ceb75f9..5fb1c4f256 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h @@ -304,7 +304,7 @@ typedef struct delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ } FSMC_NAND_InitTypeDef; -#endif +#endif /* FSMC_Bank2_3 */ #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h index babba6bf9d..92d4a74a1a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h @@ -263,7 +263,7 @@ typedef struct * @} */ -/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper +/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported Macros Helper * @{ */ @@ -869,7 +869,7 @@ __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, /** * @brief Configure peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBUS LL_I2C_SetMode\n * CR1 SMBTYPE LL_I2C_SetMode\n @@ -889,7 +889,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) /** * @brief Get peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBUS LL_I2C_GetMode\n * CR1 SMBTYPE LL_I2C_GetMode\n @@ -908,7 +908,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -926,7 +926,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -944,7 +944,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert * @param I2Cx I2C Instance. @@ -957,7 +957,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC * @param I2Cx I2C Instance. @@ -970,7 +970,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC * @param I2Cx I2C Instance. @@ -983,7 +983,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC * @param I2Cx I2C Instance. @@ -1166,7 +1166,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx) /** * @brief Enable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Bus Error detection (BERR) @@ -1187,7 +1187,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) /** * @brief Disable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Bus Error detection (BERR) @@ -1370,7 +1370,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR * @param I2Cx I2C Instance. @@ -1383,7 +1383,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1396,7 +1396,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -1435,7 +1435,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Host address reception (Slave mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: No SMBus Host address * SET: SMBus Host address received. @@ -1451,7 +1451,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Device default address reception (Slave mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: No SMBus Device default address * SET: SMBus Device default address received. @@ -1583,7 +1583,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1596,7 +1596,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -1774,7 +1774,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx) /** * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This feature is cleared by hardware when the PEC byte is transferred or compared, * or by a START or STOP condition, it is also cleared by software. @@ -1789,7 +1789,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare * @param I2Cx I2C Instance. @@ -1802,7 +1802,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare * @param I2Cx I2C Instance. @@ -1815,7 +1815,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC * @param I2Cx I2C Instance. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h index 9495e019f2..273d89dc7b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h @@ -315,14 +315,27 @@ typedef struct * @{ */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM +/** +@endcond + */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions * @{ */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); /** * @} @@ -352,7 +365,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } @@ -398,7 +411,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); } @@ -427,7 +440,7 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto * @param LPTIMx Low-Power Timer instance * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } @@ -454,7 +467,7 @@ __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t Compare * @param LPTIMx Low-Power Timer instance * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP)); } @@ -469,7 +482,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval Counter value */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); } @@ -497,7 +510,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); } @@ -546,7 +559,7 @@ __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Wavefo * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); } @@ -573,7 +586,7 @@ __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polari * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); } @@ -617,7 +630,7 @@ __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Presc * @arg @ref LL_LPTIM_PRESCALER_DIV64 * @arg @ref LL_LPTIM_PRESCALER_DIV128 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); } @@ -683,7 +696,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } @@ -744,7 +757,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM1_TRGO * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM5_TRGO */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); } @@ -759,7 +772,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_FILTER_4 * @arg @ref LL_LPTIM_TRIG_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); } @@ -773,7 +786,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); } @@ -809,7 +822,7 @@ __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t Clo * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); } @@ -851,7 +864,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockF * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -866,7 +879,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_CLK_FILTER_4 * @arg @ref LL_LPTIM_CLK_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); } @@ -904,7 +917,7 @@ __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t Enc * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -943,7 +956,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } @@ -956,13 +969,14 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) * @{ */ + /** * @brief Clear the compare match flag (CMPMCF) - * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM + * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); } @@ -973,18 +987,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** * @brief Clear the autoreload match flag (ARRMCF) - * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); } @@ -995,7 +1009,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } @@ -1017,7 +1031,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } @@ -1040,7 +1054,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } @@ -1063,7 +1077,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } @@ -1086,7 +1100,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } @@ -1109,7 +1123,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } @@ -1150,7 +1164,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } @@ -1183,7 +1197,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } @@ -1216,7 +1230,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } @@ -1249,7 +1263,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } @@ -1282,7 +1296,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } @@ -1315,7 +1329,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } @@ -1348,7 +1362,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h index 151cb4a728..21c7330ce6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h @@ -38,6 +38,7 @@ extern "C" { */ /* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -145,7 +146,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); } @@ -164,7 +165,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); } @@ -175,7 +176,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); } @@ -186,7 +187,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); } @@ -197,7 +198,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); } @@ -208,7 +209,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); } @@ -274,7 +275,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); } @@ -293,7 +294,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval Generated 32-bit random value */ -__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_REG(RNGx->DR)); } @@ -306,7 +307,7 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h index 180cc15f14..74a0aee089 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -1030,7 +1030,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1064,7 +1064,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1134,7 +1134,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1184,7 +1184,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1326,7 +1326,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll DR YT LL_RTC_DATE_GetYear\n @@ -1360,7 +1360,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1407,7 +1407,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll DR MT LL_RTC_DATE_GetMonth\n @@ -1449,7 +1449,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll DR DT LL_RTC_DATE_GetDay\n @@ -1511,7 +1511,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h index 35c47e3c04..8bd32f4163 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h @@ -300,10 +300,14 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U #define SDMMC_CARD_LOCKED 0x02000000U -#ifndef SDMMC_DATATIMEOUT -#define SDMMC_DATATIMEOUT 0xFFFFFFFFU +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#endif /* SDMMC_SWDATATIMEOUT */ + #define SDMMC_0TO7BITS 0x000000FFU #define SDMMC_8TO15BITS 0x0000FF00U #define SDMMC_16TO23BITS 0x00FF0000U diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h index 61148e4e44..a11f561933 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h @@ -562,10 +562,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!> 16U) >> TIM_CCMR1_IC1PSC_Pos))) -/** - * @} - */ - - /** * @} */ @@ -1143,7 +1135,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } @@ -1176,7 +1168,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval Inverted state of bit (0 or 1). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } @@ -1210,7 +1202,7 @@ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSo * @arg @ref LL_TIM_UPDATESOURCE_REGULAR * @arg @ref LL_TIM_UPDATESOURCE_COUNTER */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); } @@ -1237,7 +1229,7 @@ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulse * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); } @@ -1281,7 +1273,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) { uint32_t counter_mode; @@ -1323,7 +1315,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } @@ -1360,7 +1352,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); } @@ -1387,7 +1379,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) * @param TIMx Timer instance * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CNT)); } @@ -1400,7 +1392,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_COUNTERDIRECTION_UP * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); } @@ -1427,7 +1419,7 @@ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) * @param TIMx Timer instance * @retval Prescaler value between Min_Data=0 and Max_Data=65535 */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->PSC)); } @@ -1456,7 +1448,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload * @param TIMx Timer instance * @retval Auto-reload value */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->ARR)); } @@ -1483,7 +1475,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep * @param TIMx Timer instance * @retval Repetition counter value */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->RCR)); } @@ -1524,6 +1516,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); } +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check @@ -1562,7 +1565,7 @@ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAR * @arg @ref LL_TIM_CCDMAREQUEST_CC * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); } @@ -1656,7 +1659,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH4 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) { return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } @@ -1757,7 +1760,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_PWM1 * @arg @ref LL_TIM_OCMODE_PWM2 */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -1815,7 +1818,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCPOLARITY_HIGH * @arg @ref LL_TIM_OCPOLARITY_LOW */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); @@ -1876,7 +1879,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCIDLESTATE_LOW * @arg @ref LL_TIM_OCIDLESTATE_HIGH */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); @@ -1941,7 +1944,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH4 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2005,7 +2008,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH4 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2078,7 +2081,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH4 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2181,7 +2184,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -2197,7 +2200,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -2213,7 +2216,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -2229,7 +2232,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -2329,7 +2332,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_TRC */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2380,7 +2383,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2455,7 +2458,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2512,7 +2515,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_IC_POLARITY_FALLING * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> @@ -2553,7 +2556,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } @@ -2569,7 +2572,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -2585,7 +2588,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -2601,7 +2604,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -2617,7 +2620,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -2664,7 +2667,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } @@ -2813,7 +2816,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } @@ -2974,7 +2977,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } @@ -3017,7 +3020,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } @@ -3190,7 +3193,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } @@ -3212,7 +3215,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } @@ -3234,7 +3237,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } @@ -3256,7 +3259,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } @@ -3278,7 +3281,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } @@ -3300,7 +3303,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } @@ -3322,7 +3325,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } @@ -3344,7 +3347,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } @@ -3367,7 +3370,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } @@ -3390,7 +3393,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } @@ -3413,7 +3416,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } @@ -3436,7 +3439,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } @@ -3476,7 +3479,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } @@ -3509,7 +3512,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } @@ -3542,7 +3545,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } @@ -3575,7 +3578,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } @@ -3608,7 +3611,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } @@ -3641,7 +3644,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } @@ -3674,7 +3677,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } @@ -3707,7 +3710,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } @@ -3747,7 +3750,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } @@ -3780,7 +3783,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } @@ -3813,7 +3816,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } @@ -3846,7 +3849,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } @@ -3879,7 +3882,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } @@ -3912,7 +3915,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } @@ -3945,7 +3948,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } @@ -4054,19 +4057,19 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) * @{ */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h index e07c232680..ed83b6c6ec 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h @@ -345,7 +345,7 @@ typedef struct * @} */ -/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported Macros Helper * @{ */ @@ -432,7 +432,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); } @@ -510,7 +510,7 @@ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32 * @arg @ref LL_USART_DIRECTION_TX * @arg @ref LL_USART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -544,7 +544,7 @@ __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) * @arg @ref LL_USART_PARITY_EVEN * @arg @ref LL_USART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -571,7 +571,7 @@ __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Me * @arg @ref LL_USART_WAKEUP_IDLELINE * @arg @ref LL_USART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); } @@ -598,7 +598,7 @@ __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataW * @arg @ref LL_USART_DATAWIDTH_8B * @arg @ref LL_USART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); } @@ -625,14 +625,14 @@ __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t Ov * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); } /** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput * @param USARTx USART Instance @@ -649,7 +649,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 /** * @brief Retrieve Clock pulse of the last data bit output configuration * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput * @param USARTx USART Instance @@ -657,14 +657,14 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); } /** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_SetClockPhase * @param USARTx USART Instance @@ -680,7 +680,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc /** * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_GetClockPhase * @param USARTx USART Instance @@ -688,14 +688,14 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc * @arg @ref LL_USART_PHASE_1EDGE * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); } /** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_SetClockPolarity * @param USARTx USART Instance @@ -711,7 +711,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C /** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_GetClockPolarity * @param USARTx USART Instance @@ -719,14 +719,14 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C * @arg @ref LL_USART_POLARITY_LOW * @arg @ref LL_USART_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); } /** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function @@ -754,7 +754,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, /** * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput * @param USARTx USART Instance @@ -767,7 +767,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput * @param USARTx USART Instance @@ -780,13 +780,13 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); } @@ -817,7 +817,7 @@ __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_STOPBITS_1_5 * @arg @ref LL_USART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); } @@ -875,14 +875,14 @@ __STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t Nod * @param USARTx USART Instance * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); } /** * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl * @param USARTx USART Instance @@ -895,7 +895,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl * @param USARTx USART Instance @@ -908,7 +908,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl * @param USARTx USART Instance @@ -921,7 +921,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl * @param USARTx USART Instance @@ -934,7 +934,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n * CR3 CTSE LL_USART_SetHWFlowCtrl @@ -953,7 +953,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard /** * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n * CR3 CTSE LL_USART_GetHWFlowCtrl @@ -964,7 +964,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard * @arg @ref LL_USART_HWCONTROL_CTS * @arg @ref LL_USART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -997,7 +997,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); } @@ -1042,7 +1042,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) { uint32_t usartdiv = 0x0U; uint32_t brrresult = 0x0U; @@ -1077,7 +1077,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t Pe /** * @brief Enable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_EnableIrda * @param USARTx USART Instance @@ -1090,7 +1090,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) /** * @brief Disable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_DisableIrda * @param USARTx USART Instance @@ -1103,20 +1103,20 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) /** * @brief Indicate if IrDA mode is enabled - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_IsEnabledIrda * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); } /** * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode * @param USARTx USART Instance @@ -1132,7 +1132,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P /** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode * @param USARTx USART Instance @@ -1140,7 +1140,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P * @arg @ref LL_USART_IRDA_POWER_NORMAL * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); } @@ -1148,7 +1148,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) /** * @brief Set Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler * @param USARTx USART Instance @@ -1163,13 +1163,13 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P /** * @brief Return Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler * @param USARTx USART Instance * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -1184,7 +1184,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) /** * @brief Enable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK * @param USARTx USART Instance @@ -1197,7 +1197,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Disable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK * @param USARTx USART Instance @@ -1210,20 +1210,20 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); } /** * @brief Enable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_EnableSmartcard * @param USARTx USART Instance @@ -1236,7 +1236,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) /** * @brief Disable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_DisableSmartcard * @param USARTx USART Instance @@ -1249,13 +1249,13 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard mode is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); } @@ -1263,7 +1263,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) /** * @brief Set Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler * @param USARTx USART Instance @@ -1278,13 +1278,13 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler * @param USARTx USART Instance * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -1292,7 +1292,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) /** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime * @param USARTx USART Instance @@ -1307,13 +1307,13 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime * @param USARTx USART Instance * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); } @@ -1328,7 +1328,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) /** * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex * @param USARTx USART Instance @@ -1341,7 +1341,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex * @param USARTx USART Instance @@ -1354,13 +1354,13 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); } @@ -1375,7 +1375,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) /** * @brief Set LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen * @param USARTx USART Instance @@ -1391,7 +1391,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 /** * @brief Return LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen * @param USARTx USART Instance @@ -1399,14 +1399,14 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LINBREAK_DETECT_10B * @arg @ref LL_USART_LINBREAK_DETECT_11B */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); } /** * @brief Enable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_EnableLIN * @param USARTx USART Instance @@ -1419,7 +1419,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) /** * @brief Disable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_DisableLIN * @param USARTx USART Instance @@ -1432,13 +1432,13 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) /** * @brief Indicate if LIN mode is enabled - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); } @@ -1493,7 +1493,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1531,7 +1531,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also set the UART/USART in LIN mode. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function @@ -1571,7 +1571,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - IREN bit in the USART_CR3 register, * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1610,7 +1610,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) * This function also configures Stop bits to 1.5 bits and * sets the USART in Smartcard mode (SCEN bit). * Clock Output is also enabled (CLKEN). - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1652,7 +1652,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1734,7 +1734,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); } @@ -1745,7 +1745,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); } @@ -1756,7 +1756,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); } @@ -1767,7 +1767,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); } @@ -1778,7 +1778,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); } @@ -1789,7 +1789,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); } @@ -1800,7 +1800,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); } @@ -1811,33 +1811,33 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); } /** * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD)); } /** * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); } @@ -1848,7 +1848,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); } @@ -1859,7 +1859,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); } @@ -1983,7 +1983,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx) /** * @brief Clear LIN Break Detection Flag - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll SR LBD LL_USART_ClearFlag_LBD * @param USARTx USART Instance @@ -1996,7 +1996,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) /** * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll SR CTS LL_USART_ClearFlag_nCTS * @param USARTx USART Instance @@ -2072,7 +2072,7 @@ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) /** * @brief Enable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD * @param USARTx USART Instance @@ -2100,7 +2100,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS * @param USARTx USART Instance @@ -2168,7 +2168,7 @@ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) /** * @brief Disable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD * @param USARTx USART Instance @@ -2196,7 +2196,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS * @param USARTx USART Instance @@ -2213,7 +2213,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); } @@ -2224,7 +2224,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); } @@ -2235,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); } @@ -2246,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); } @@ -2257,20 +2257,20 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); } /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); } @@ -2281,20 +2281,20 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); } /** * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); } @@ -2335,7 +2335,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); } @@ -2368,7 +2368,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); } @@ -2380,7 +2380,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx) { /* return address of DR register */ return ((uint32_t) &(USARTx->DR)); @@ -2400,7 +2400,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) { return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); } @@ -2411,7 +2411,7 @@ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) { return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); } @@ -2489,10 +2489,10 @@ __STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h index a7114cd02a..caabcf332e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -37,18 +37,24 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ +#ifndef HAL_USB_TIMEOUT +#define HAL_USB_TIMEOUT 0xF000000U +#endif /* define HAL_USB_TIMEOUT */ + +#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS +#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ /** * @brief USB Mode definition */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) typedef enum { - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 -} USB_OTG_ModeTypeDef; + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; /** * @brief URB States definition @@ -61,7 +67,7 @@ typedef enum URB_NYET, URB_ERROR, URB_STALL -} USB_OTG_URBStateTypeDef; +} USB_URBStateTypeDef; /** * @brief Host channel States definition @@ -71,13 +77,14 @@ typedef enum HC_IDLE = 0, HC_XFRC, HC_HALTED, + HC_ACK, HC_NAK, HC_NYET, HC_STALL, HC_XACTERR, HC_BBLERR, HC_DATATGLERR -} USB_OTG_HCStateTypeDef; +} USB_HCStateTypeDef; /** @@ -85,40 +92,41 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t Host_channels; /*!< Host Channels number. + uint8_t Host_channels; /*!< Host Channels number. This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t dma_enable; /*!< USB DMA state. + If DMA is not supported this parameter shall be set by default to zero */ - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ -} USB_OTG_CfgTypeDef; +} USB_CfgTypeDef; typedef struct { @@ -140,25 +148,25 @@ typedef struct uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint8_t even_odd_frame; /*!< IFrame parity This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ uint16_t tx_fifo_num; /*!< Transmission FIFO number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - uint32_t xfer_len; /*!< Current transfer length */ - uint32_t xfer_size; /*!< requested transfer size */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ -} USB_OTG_EPTypeDef; +} USB_EPTypeDef; typedef struct { @@ -179,8 +187,13 @@ typedef struct (HCD_DEVICE_SPEED_xxx) */ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ + uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ - uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ uint8_t ep_type; /*!< Endpoint Type. This parameter can be any value of @ref USB_LL_EP_Type */ @@ -193,7 +206,7 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - uint32_t XferSize; /*!< OTG Channel transfer size. */ + uint32_t XferSize; /*!< OTG Channel transfer size. */ uint32_t xfer_len; /*!< Current transfer length. */ @@ -208,15 +221,21 @@ typedef struct uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ uint32_t ErrCnt; /*!< Host channel error count. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ -} USB_OTG_HCTypeDef; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -244,18 +263,6 @@ typedef struct * @} */ -/** @defgroup USB_LL Device Speed - * @{ - */ -#define USBD_HS_SPEED 0U -#define USBD_HSINFS_SPEED 1U -#define USBH_HS_SPEED 0U -#define USBD_FS_SPEED 2U -#define USBH_FSLS_SPEED 1U -/** - * @} - */ - /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed * @{ */ @@ -319,7 +326,7 @@ typedef struct /** * @} */ - +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ @@ -331,6 +338,18 @@ typedef struct * @} */ +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + /** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed * @{ */ @@ -341,18 +360,30 @@ typedef struct * @} */ -/** @defgroup USB_LL_EP_Type USB Low Layer EP Type +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type * @{ */ -#define EP_TYPE_CTRL 0U -#define EP_TYPE_ISOC 1U -#define EP_TYPE_BULK 2U -#define EP_TYPE_INTR 3U -#define EP_TYPE_MSK 3U +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U /** * @} */ +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines * @{ */ @@ -375,6 +406,16 @@ typedef struct * @} */ +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines * @{ */ @@ -390,16 +431,21 @@ typedef struct #define HCCHAR_BULK 2U #define HCCHAR_INTR 3U -#define HC_PID_DATA0 0U -#define HC_PID_DATA2 1U -#define HC_PID_DATA1 2U -#define HC_PID_SETUP 3U - #define GRXSTS_PKTSTS_IN 2U #define GRXSTS_PKTSTS_IN_XFER_COMP 3U #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_CH_HALTED 7U +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + #define TEST_J 1U #define TEST_K 2U #define TEST_SE0_NAK 3U @@ -423,13 +469,9 @@ typedef struct + USB_OTG_HOST_CHANNEL_BASE\ + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #define EP_ADDR_MSK 0xFU - -#ifndef USE_USB_DOUBLE_BUFFER -#define USE_USB_DOUBLE_BUFFER 1U -#endif /* USE_USB_DOUBLE_BUFFER */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -460,55 +502,55 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); -uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html index 1fa103755e..997f338633 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html @@ -1,11459 +1,4189 @@ - - - - - - - - Release Notes for STM32F4xx HAL Drivers - -
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        Back to - Release page

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        Release - - - - Notes for STM32F4xx HAL Drivers

        -

        Copyright 2017 - STMicroelectronics

        -

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        - - - - - - -
        - - - - - - - - - -
        -

        Update - - - - History

        V1.8.1 - / 24-June-2022

        -
        -

        Main - - - - - Changes
        -

        -
        -
        • General updates to fix HAL ETH defects and implementation enhancements.

        • HAL - updates

          - - -
            -
          • HAL ETH update
            • Remove useless assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)) from static function ETH_MACAddressConfig().
            • Replace hard coded Rx buffer size (1000U) by macro ETH_RX_BUF_SIZE.
            • Correct -bit positions when getting MAC and DMA configurations and replace -�UnicastSlowProtocolPacketDetect� by �UnicastPausePacketDetect� in the -MAC default configuration structure.
            • Ensure a delay of 4 TX_CLK/RX_CLK cycles between two successive write operations to the same register.
            • Disable DMA transmission in both HAL_ETH_Stop_IT() and HAL_ETH_Stop() APIs.

        V1.8.0 - / 11-February-2022

        -
        -

        Main - - - - - Changes
        -

        -
        -
          -
        • General updates to fix known defects and implementation enhancements.
          • -
        • All source files: update disclaimer to add reference to the new license agreement.
          -
          • -
        • The following changes done on the HAL drivers require an update of the application code based on older HAL versions
          • Rework of HAL Ethernet driver to resolve problems and improve performance (compatibility break). 
          • A new HAL Ethernet driver has been redesigned with new APIs, to bypass limitations with previous HAL Ethernet driver version.
          • The new HAL Ethernet driver is the -recommended version. It is located as usual in -Drivers/STM32F4xx_HAL_Driver/Src and Drivers/STM32F4xx_HAL_Driver/Inc -folders. 
            • It can be enabled through switch HAL_ETH_MODULE_ENABLED in stm32f4xx_hal_conf.h
          • The legacy HAL Ethernet driver is also -present in the release in Drivers/STM32F4xx_HAL_Driver/Src/Legacy and -Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software -compatibility reasons.
            • Its usage is not recommended as -deprecated. It can however be enabled through switch -HAL_ETH_LEGACY_MODULE_ENABLED in stm32f4xx_hal_conf.h
          -

        • HAL - updates

          - - -
            - - - - -
          • HAL ETH update -
              -
            • Entire receive process reworked.
            • Resolve the problem of received data corruption.
            • Implement transmission in interrupt mode.
            • Handle one interrupt for multiple transmitted packets.
            • Implement APIs to handle PTP feature.
            • Implement APIs to handle Timestamp feature.
            • Add support of receive buffer unavailable.
              • -
            • Update HAL_ETH_IRQHandler() to handle receive buffer unavailable.
              • - -
            • -
          • HAL SMBUS update
            • -
              -
            • Update to fix issue of mismatched data -received by master in case of data size to be transmitted by the slave -is greater than the data size to be received by the master.
              • -
                -
              • Add flush on TX register.
                • -
              -
            -
          • HAL TIM update
            • -
              -
            • __LL_TIM_CALC_PSC() macro update to round up the evaluate value when the fractional part of the division is greater than 0.5.
              • -
            - -
          • HAL LPTIM update
            • -
              -
            • Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()
              • -
            -
          • HAL UART update
            • -
              -
            • Add const qualifier for read only pointers.
              • -
            • Improve header description of UART_WaitOnFlagUntilTimeout() function.
              • -
            • Add a check on the UART parity before enabling the parity error interruption.
              • -
            • Fix typo in UART_IT_TXE bit description.
              -
              • - -
            -
          • HAL IRDA update
            • -
              -
            • Improve header description of IRDA_WaitOnFlagUntilTimeout() function.
              • -
            • Add a check on the IRDA parity before enabling the parity error interrupt.
              • -
            • Add const qualifier for read only pointers.
              • -
            -
          • HAL SMARTCARD update
            • -
              -
            • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function
              • -
            • Add const qualifier for read only pointers.
              • -
            -
          • HAL NOR update
            • -
              -
            • Apply adequate commands according to the command set field value
              • -
            • command set 1 for Micron JS28F512P33
              • -
            • command set 2 for Micron M29W128G and Cypress S29GL128P
              • -
            • Add new command operations:
              • -
                -
              • NOR_CMD_READ_ARRAY
                • -
              • NOR_CMD_WORD_PROGRAM
                • -
              • NOR_CMD_BUFFERED_PROGRAM
                • -
              • NOR_CMD_CONFIRM
                • -
              • NOR_CMD_BLOCK_ERASE
                • -
              • NOR_CMD_BLOCK_UNLOCK
                • -
              • NOR_CMD_READ_STATUS_REG
                • -
              • NOR_CMD_CLEAR_STATUS_REG
                • -
              -
            • Update some APIs in order to be compliant for memories with different command set, the updated APIs are:
              • -
                -
              • HAL_NOR_Init()
                • -
              • HAL_NOR_Read_ID()
                • -
              • HAL_NOR_ReturnToReadMode()
                • -
              • HAL_NOR_Read()
                • -
              • HAL_NOR_Program()
                • -
              • HAL_NOR_ReadBuffer()
                • -
              • HAL_NOR_ProgramBuffer()
                • -
              • HAL_NOR_Erase_Block()
                • -
              • HAL_NOR_Erase_Chip()
                • -
              • HAL_NOR_GetStatus()
                • -
              -
            • Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.
              • -
            -
          • HAL SDMMC update
            • -
              -
            • Take into account the voltage range in the CMD1 command.
              • -
            • Add new LL function to have correct response for MMC driver.
              • -
            • Update the driver to have all fields correctly initialized.
              • -
            • Add an internal variable to manage the power class and call it before to update speed of bus width.
              • -
            • Add new API to get the value of the Extended CSD register and populate the ExtCSD field of the MMC handle.
              • -
            • In HAL_MMC_InitCard(), call to SDIO_PowerState_ON() moved after -__HAL_MMC_ENABLE() to ensure MMC clock is enabled before the call to -HAL_Delay() from within SDIO_PowerState_ON().
              • -
            -
          • HAL DMA update
            • -
              -
            • Manage the case of an invalid value of CallbackID passed to the HAL_DMA_RegisterCallback() API.
              • -
            -
          • HAL LTDC update
            • -
              -
            • Update HAL_LTDC_DeInit() to fix MCU Hang up during LCD turn OFF.
              • -
            - -
          • HAL I2C update
            • -
              -
            • Update to fix issue detected due to low system frequency execution (HSI).
              • -
            • Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA
              • -
            • Update HAL I2C Master Receive IT process to safe manage data N= 2 and N= 3.
              • -
                -
              • Disable RxNE interrupt if nothing to do.
                • -
              -
            -
          • HAL USART update
            • -
              -
            • Improve header description of USART_WaitOnFlagUntilTimeout() function.
              • -
            • Add a check on the USART parity before enabling the parity error interrupt.
              • -
            • Add const qualifier for read only pointers.
              • -
            -
          • HAL/LL ADC update
            • -
              -
            • Update LL_ADC_IsActiveFlag_MST_EOCS() API to get the appropriate flag.
              • -
            • Better performance by removing multiple volatile reads or writes in interrupt handler.
              • -
            -
          • HAL FMPI2C update
            -
            • -
              -
            • Update to handle errors in polling mode.
              • -
                -
              • Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.
                • -
              -
            -
          • HAL EXTI update
            • -
              -
            • Update HAL_EXTI_GetConfigLine() API to fix wrong calculation of GPIOSel value.
              • -
            -
          • HAL QSPI update
            • -
              -
            • Update HAL_QSPI_Abort() and  -HAL_QSPI_Abort_IT() APIs to check on QSPI BUSY flag status before -executing the abort procedure.
              • -
            - -
          • HAL/LL RTC cleanup
            • -
              -
            • Use bits definitions from CMSIS Device header file instead of hard-coded values.
              • -
            • Wrap comments to be 80-character long and correct typos.
              • -
            • Move constants RTC_IT_TAMP. from hal_rtc.h to hal_rtc_ex.h.
              • -
            • Gather all instructions related to exiting the "init" mode into new function RTC_ExitInitMode().
              • -
            • Add -new macro -assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, -sTamper->Trigger)) to check tamper filtering is disabled in case -tamper events are triggered on signal edges.
              • -
            • Rework functions HAL_RTCEx_SetTamper() and HAL_RTCEx_SetTamper_IT() to:
              • -
                -
              • Write in TAFCR register in one single access instead of two.
                • -
              • Avoid modifying user structure sTamper.
                • -
              -
            • Remove functions LL_RTC_EnablePushPullMode() and LL_RTC_DisablePushPullMode() as related to non-supported features.
              • -
            • Remove any reference to non-supported features (e.g., LL_RTC_ISR_TAMP3F).
              • -
            • Remove -useless conditional defines as corresponding features are supported by -all part-numbers (e.g., #if defined(RTC_TAFCR_TAMPPRCH)).
              • -
            -
          • HAL USB OTG update
            • -
              - - -
            • Fix USB_FlushRxFifo() and USB_FlushTxFifo() APIs by adding check on AHB master IDLE state before flushing the USB FIFO
              • -
            • Fix to avoid resetting host channel direction during channel halt
              • -
            • Fix to report correct received amount of data with USB DMA enabled
              • -
            • Fix to avoid compiler optimization on count variable used for USB HAL timeout loop check
              • -
            • Add missing registered callbacks check for HAL_HCD_HC_NotifyURBChange_Callback()
              • -
            • Add new API HAL_PCD_SetTestMode() APIs to handle USB device high speed Test modes
              • -
            • Setting SNAK for EPs not required during device reset
              • -
            • Update USB IRQ handler to enable EP OUT disable
              • -
            • Add support of USB IN/OUT Iso incomplete
              • -
            • Fix USB BCD data contact timeout
              -
              -
              • - -
            -
          -
          • + + + + + + + Release Notes for STM32F4xx HAL Drivers + + + + + + +
          +
          +
          +

          Release Notes for STM32F4xx HAL Drivers

          +

          Copyright © 2017 STMicroelectronics
          +

          + +
          +

          Purpose

          +

          The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

          +

          The Portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

          +

          The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provide basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not Fully Portable across the STM32 families; the availability of some functions depend on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

          +
            +
          • New set of inline function for direct and atomic register access
            • +
          • One-shot operations that can be used by the HAL drivers or from application level.
            • +
          • Fully Independent from HAL and can be used in standalone usage (without HAL drivers)
            • +
          • Full features coverage of the all the supported peripherals.
          -

          V1.7.13 - / 16-July-2021

          -
          -

          Main - - - - - Changes
          -

          -
          -
          • -

            HAL - updates

            - -
              -
            • HAL EXTI - update -
              • Update - HAL_EXTI_GetConfigLine() - API to set default - configuration value of - Trigger and GPIOSel - before checking each - corresponding registers.
              -
              • -
            • HAL GPIO - update -
              • Update - HAL_GPIO_Init() API to - avoid the configuration - of PUPDR register when - Analog mode is selected.
              -
              • -
            • HAL DMA - update -
              • Update - HAL_DMA_IRQHandler() API - to set the DMA state - before unlocking access - to the DMA handle.
              -
              • -
            • HAL/LL ADC - update -
              • Update - LL_ADC_DeInit() API to - clear missing SQR3 - register.
              • Update - LL_ADC_DMA_GetRegAddr() - API to prevent unused - argument compilation - warning.
              • Update HAL - timeout mechanism to - avoid false timeout - detection in case of - preemption.
              -
              • -
            • HAL CAN - update -
              • Update - HAL_CAN_Init() API to be - aligned with referance - manual and to avoid - timeout error:
              -
              • -
            • HAL/LL - RTC_BKP update -
              • Update - __HAL_RTC_�(__HANDLE__, - �) macros to access - registers through - (__HANDLE__)->Instance - pointer and avoid - �unused variable� - warnings.
              • Correct month - management in - IS_LL_RTC_MONTH() macro.
              -
              • -
            • HAL RNG - update -
              • Update timeout - mechanism to avoid false - timeout detection in - case of preemption.
              -
              • -
            • HAL QSPI - update -
              • ES0305 - workaround disabled for - STM32412xx devices.
              -
              • -
            • HAL I2C - update -
              • Update - HAL_I2C_Mem_Write_DMA() - and - HAL_I2C_Mem_Read_DMA() - APIs to initialize - Devaddress, Memaddress - and EventCount - parameters.
              • Update to - prevent several calls of - Start bit: -
                • Update - I2C_MemoryTransmit_TXE_BTF() - API to increment - EventCount.
                -
              • Update to - avoid I2C interrupt in - endless loop: -
                • Update - HAL_I2C_Master_Transmit_IT(), - HAL_I2C_Master_Receive_IT(), - - HAL_I2C_Master_Transmit_DMA() - - and - HAL_I2C_Master_Receive_DMA() - APIs to unlock the - I2C peripheral - before generating - the start.
                -
              • Update to use - the right macro to clear - I2C ADDR flag inside - I2C_Slave_ADDR() API as - it�s indicated in the - reference manual.
              • Update - I2C_IsAcknowledgeFailed() - API to avoid I2C in busy - state if NACK received - after transmitting - register address.
              • Update - HAL_I2C_EV_IRQHandler() - and - I2C_MasterTransmit_BTF() - APIs to correctly manage - memory transfers: -
                • Add check - on memory mode - before calling - callbacks - procedures.
                -
              -
              • -
            • LL USART - update -
              • Handling of - UART concurrent register - access in case of race - condition between Tx and - Rx transfers (HAL UART - and LL LPUART)
              -
              • -
            • HAL SMBUS - update -
              • Updated - HAL_SMBUS_ER_IRQHandler() - API to return the - correct error code - �SMBUS_FLAG_PECERR� in - case of packet error - occurs.
              -
              • -
            • HAL/LL SPI - update -
              • Updated to fix - MISRA-C 2012 Rule-13.2.
              • Update - LL_SPI_TransmitData8() - API to avoid casting the - result to 8 bits.
              -
              • -
            • HAL UART - update -
              • Fix wrong - comment related to RX - pin configuration within - the description section
              • Correction on - UART ReceptionType - management in case of - ReceptionToIdle API are - called from RxEvent - callback
              • Handling of - UART concurrent register - access in case of race - condition between Tx and - Rx transfers (HAL UART - and LL LPUART) -
                • Update CAN - Initialization - sequence to set - "request - initialization" bit - before exit from - sleep mode.
                -
              -
              • -
            • HAL USB - update -
              • HAL PCD: add - fix transfer complete - for IN Interrupt - transaction in single - buffer mode
              • Race condition - in USB PCD control - endpoint receive ISR.
              -
            -

          V1.7.12 - / 26-March-2021

          -

          Main - - - - - Changes

          -
            -
          • HAL
            • -
              -
            • HAL/LL - USART update
              • -
                -
              • Fix typo in - USART_Receive_IT() and - USART_TransmitReceive_IT() - APIs to avoid possible - compilation issues if the - UART driver files are not - included.
                • -
              -
            -
          -

          V1.7.11 - / 12-February-2021

          -

          Main - - - - - Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • Added - - - - new HAL - - - - FMPSMBUS extended driver - - - - - to support FMPSMBUS fast Mode - Plus.
            • -
          • Removed - - - - �register� keyword to be - compliant with new C++ rules:
            • -
              -
            • The register - storage class specifier was - deprecated in C++11 and - removed in C++17.
              • -
            -
          • HAL
            • -
              -
            • HAL update
              • -
            • General - updates to fix known defects - and enhancements - implementation.
              • -
            • Added new - defines for ARM compiler V6:
              • -
                -
              • __weak
                • -
              • __packed
                • -
              • __NOINLINE
                • -
              -
            • Updated HAL TimeBase - TIM, RTC alarm and RTC WakeUp - templates for more robustness
              • -
                -
              • Updated Hal_Init_Tick() - API to propoerty - store the priority when - using the non-default time - base.
                • -
              -
            • Updated - PPP_MODULE_ENABLED for - FMPSMBUS.
              • -
            • HAL/LL ADC update
              • -
                -
              • Updated to - add include of the LL ADC - driver.
                • -
              • Updated the - following APIs to set status - HAL_ADC_STATE_ERROR_INTERNAL - and error code - HAL_ADC_ERROR_INTERNAL when - error occurs:
                • -
                  -
                • HAL_ADC_Start()
                  • -
                • HAL_ADC_Start_IT()
                  • -
                • HAL_ADC_Start_DMA()
                  • -
                • HAL_ADCEx_InjectedStart()
                  • -
                • HAL_ADCEx_InjectedStart_IT()
                  • -
                • HAL_ADCEx_MultiModeStart_DMA()
                  • -
                -
              • Updated HAL_ADC_Stop_DMA() - API to check if DMA state is - Busy before calling HAL_DMA_Abort() - - - - - API to avoid DMA internal - error.
                • -
              • Updated - IS_ADC_CHANNEL to support - temperature sensor for:
                • -
                  -
                • STM32F411xE
                  • -
                • STM32F413xx
                  • -
                • STM32F423xx
                  • -
                -
              • Fixed wrong - defined values for:
                • -
                  -
                • LL_ADC_MULTI_REG_DMA_LIMIT_3
                  • -
                • LL_ADC_MULTI_REG_DMA_UNLMT_3
                  • -
                -
              • Added - __LL_ADC_CALC_VREFANALOG_VOLTAGE() - macro to evaluate analog - reference voltage.
                • -
              • Removed - __LL_ADC_CALC_TEMPERATURE() - macro for STM32F4x9 devices - as the TS_CAL2 is not - available.
                • -
              -
            • HAL/LL DAC update
              • -
                -
              • Added restruction - on DAC Channel 2 defines and - parametres.
                • -
              • HAL_DAC_MSPINIT_CB_ID - - - - - and HAL_DAC_MSPDEINIT_CB_ID - used instead of - HAL_DAC_MSP_INIT_CB_ID and - HAL_DAC_MSP_DEINIT_CB_ID.
                • -
              • Updated to - support dual mode:
                • -
                  -
                • Added two - new APIs:
                  • -
                    -
                  • HAL_DACEx_DualStart()
                    • -
                  • HAL_DACEx_DualStop()
                    • -
                  -
                -
              • Added - position bit definition to - be used instead of - __DAC_MASK_SHIFT macro
                • -
                  -
                • __DAC_MASK_SHIFT - - - - macro has been removed.
                  • -
                -
              • Updated HAL_DAC_Start_DMA() - API to return HAL_ERROR when - error occurs.
                • -
              • Updated HAL_DAC_Stop_DMA() - API to not return HAL_ERROR - when DAC is already - disabled.
                • -
              -
            • HAL CEC update
              • -
                -
              • Updated HAL_CEC_IRQHandler() - API to avoid appending an - extra byte to the end of a - message.
                • -
              -
            • HAL/LL GPIO update
              • -
                -
              • Updated - IS_GPIO_AF() to - add missing values for - STM32F401xC and STM32F401xE - devices:
                • -
                  -
                • GPIO_AF3_TIM9
                  • -
                • GPIO_AF3_TIM10
                  • -
                • GPIO_AF3_TIM11
                  • -
                -
              • Updated - LL/HAL GPIO_TogglePin() - APIs to allow multi Pin�s - toggling.
                • -
              • Updated HAL_GPIO_Init() - API to avoid the - configuration of PUPDR - register when Analog mode is - selected.
                • -
              -
            • HAL/LL RCC update
              • -
                -
              • Updated HAL_RCC_OscConfig() - API to add missing checks - and to don�t return - HAL_ERROR if request repeats - the current PLL - configuration.
                • -
              • Updated - IS_RCC_PLLN_VALUE(VALUE) - macro in case of STM32F411xE - device in order to - be aligned with reference - manual.
                • -
              -
            • HAL SD update
              • -
                -
              • Update - function SD_FindSCR() - to resolve issue of FIFO - blocking when reading.
                • -
              • Update - read/write functions in DMA - mode in - - - - order to - force the DMA direction, - updated functions:
                • -
                  -
                • HAL_SD_ReadBlocks_DMA()
                  • -
                • HAL_SD_WriteBlocks_DMA()
                  • -
                -
              • Add the - block size settings in the - initialization functions and - remove it from read/write - transactions to avoid - repeated and inefficient - reconfiguration, updated - functions:
                • -
                  -
                • HAL_SD_InitCard()
                  • -
                • HAL_SD_GetCardStatus()
                  • -
                • HAL_SD_ConfigWideBusOperation() 
                  • -
                • HAL_SD_ReadBlocks()
                  • -
                • HAL_SD_WriteBlocks()
                  • -
                • HAL_SD_ReadBlocks_IT()
                  • -
                • HAL_SD_WriteBlocks_IT()
                  • -
                • HAL_SD_ReadBlocks_DMA()
                  • -
                • HAL_SD_WriteBlocks_DMA()
                  • -
                -
              -
            • HAL MMC update
              • -
                -
              • Add the - block size settings in the - initialization function and - remove it from read/write - transactions to avoid - repeated and inefficient - reconfiguration, updated - functions:
                • -
                  -
                • HAL_MMC_InitCard()
                  • -
                • HAL_MMC_ReadBlocks()
                  • -
                • HAL_MMC_WriteBlocks()
                  • -
                • HAL_MMC_ReadBlocks_IT()
                  • -
                • HAL_MMC_WriteBlocks_IT()
                  • -
                • HAL_MMC_ReadBlocks_DMA()
                  • -
                • HAL_MMC_WriteBlocks_DMA()
                  • -
                -
              • Update - read/write functions in DMA - mode in - - - - order to - force the DMA direction, - updated functions:
                • -
                  -
                • HAL_MMC_ReadBlocks_DMA()
                  • -
                • HAL_MMC_WriteBlocks_DMA()
                  • -
                -
              • Deploy new - functions MMC_ReadExtCSD() - and SDMMC_CmdSendEXTCSD - () that read and check the - sectors number of the - device in order to resolve - the issue of wrongly reading - big memory size.
                • -
              -
            • HAL NAND - update
              • -
                -
              • Update - functions - HAL_NAND_Read_SpareArea_16b() - and - HAL_NAND_Write_SpareArea_16b() - to fix column address - calculation issue.
                • -
              -
            • LL SDMMC - update
              • -
                -
              • Update the - definition of - SDMMC_DATATIMEOUT constant in - - - - order to - allow the user to redefine - it in his proper - application.
                • -
              • Remove - 'register' storage class - specifier from LL SDMMC - driver.
                • -
              • Deploy new - functions MMC_ReadExtCSD() - and SDMMC_CmdSendEXTCSD - () that read and check the - sectors number of the device - in order to resolve the - issue of wrongly reading big - memory size.
                • -
              -
            • HAL SMBUS update
              • -
                -
              • Support for - Fast Mode Plus to be SMBUS - rev 3 compliant.
                • -
              • Added HAL_FMPSMBUSEx_EnableFastModePlus() - and HAL_FMPSMBUSEx_DisableFastModePlus() - - - - - APIs to manage Fm+.
                • -
              • Updated SMBUS_MasterTransmit_BTF() - , SMBUS_MasterTransmit_TXE() - - - - - and SMBUS_MasterReceive_BTF() - - - - - APIs to allow stop - generation when CurrentXferOptions - is different from - SMBUS_FIRST_FRAME and - SMBUS_NEXT_FRAME.
                • -
              • Updated SMBUS_ITError() - API to correct the twice - call of HAL_SMBUS_ErrorCallback.
                • -
              -
            • HAL SPI update
              • -
                -
              • Updated HAL_SPI_Init() - API
                • -
                  -
                • To avoid - setting the BaudRatePrescaler - in case of Slave Motorola - Mode.
                  • -
                • Use the bit-mask - for SPI configuration.
                  • -
                -
              • Updated - Transmit/Receive processes - in half-duplex mode
                • -
                  -
                • Disable - the SPI instance before - setting BDIOE bit.
                  • -
                -
              • Fixed wrong - timeout management
                • -
              • Calculate - Timeout based on a software - loop to avoid blocking issue - if Systick - is disabled.
                • -
              -
            • HAL - SPDIFRX update
              • -
                -
              • Remove - 'register' storage class - specifier from HAL SPDIFRX - driver.
                • -
              -
            • HAL I2S update
              • -
                -
              • Updated - I2SEx APIs to correctly - support circular transfers
                • -
                  -
                • Updated - I2SEx_TxRxDMACplt() - API to manage DMA circular - mode.
                  • -
                -
              • Updated - HAL_I2SEx_TransmitReceive_DMA() - API to set hdmatx - (transfert - callback and half) to NULL.
                • -
              -
            • HAL SAI update
              • -
                -
              • Updated to - avoid the incorrect - left/right synchronization.
                • -
                  -
                • Updated HAL_SAI_Transmit_DMA() - API to follow the sequence - described in the reference - manual for slave - transmitter mode.
                  • -
                -
              • Updated HAL_SAI_Init() - API to correct the formula - in case of SPDIF is wrong.
                • -
              -
            • HAL CRYP update
              • -
                -
              • Updated HAL_CRYP_SetConfig() - and HAL_CRYP_GetConfig() - - - - - APIs to set/get the - continent of KeyIVConfigSkip - correctly.
                • -
              -
            • HAL EXTI update
              • -
                -
              • __EXTI_LINE__ - - - - is now used instead of - __LINE__ which is a standard - C macro.
                • -
              -
            • HAL DCMI
              • -
                -
              • Support of - HAL callback registration - feature for DCMI extended - driver.
                • -
              -
            • HAL/LL TIM update
              • -
                -
              • Updated HAL_TIMEx_OnePulseN_Start() - and HAL_TIMEx_OnePulseN_Stop() - - - - - APIs (pooling and IT mode) - to take into consideration - all OutputChannel - parameters.
                • -
              • Corrected - reversed description of - TIM_LL_EC_ONEPULSEMODE One - Pulse Mode.
                • -
              • Updated LL_TIM_GetCounterMode() - API to return the correct - counter mode.
                • -
              -
            • HAL/LL - SMARTCARD update
              • -
                -
              • Fixed - invalid initialization of - SMARTCARD configuration by - removing FIFO mode - configuration as it is not - member of SMARTCARD_InitTypeDef - Structure.
                • -
              • Fixed typos - in SMARTCARD State - definition description
                • -
              -
            • HAL/LL IRDA update
              • -
                -
              • Fixed typos - in IRDA State definition - description
                • -
              -
            • LL USART update
              • -
                -
              • Remove - useless check on maximum BRR - value by removing - IS_LL_USART_BRR_MAX() - macro.
                • -
              • Update - USART polling and - interruption processes to - fix issues related to - accesses out of user - specified buffer.
                • -
              -
            • HAL USB update
              • -
                -
              • Enhanced - USB OTG host HAL with USB - DMA is enabled:
                • -
                  -
                • fixed - ping and data toggle - issue,
                  • -
                • reworked - Channel error report - management
                  • -
                -
              -
            -
          -

          V1.7.10 - - - - / 22-October-2020

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects.
            • -
          • HAL/LL - - - - I2C update
            • -
          -
            -
              -
            •   Update - to fix hardfault - issue with HAL_I2C_Mem_Write_DMA() - API:
              • -
                -
              •   - Abort the right ongoing DMA - transfer when memory write - access request operation - failed: fix typo �hdmarx� - replaced by �hdmatx�
                • -
              -
            -
          -

          V1.7.9 - - - - / 14-August-2020

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • HAL/LL - - - - I2C update
            • -
          -
            -
              -
            •   Update - HAL_I2C_ER_IRQHandler() - API to fix acknowledge failure - issue with I2C memory IT - processes
              • -
                -
              •   Add - stop condition generation - when NACK occurs.
                • -
              -
            •   Update - I2C_DMAXferCplt(), - - - - - I2C_DMAError() and - I2C_DMAAbort() APIs to fix hardfault - issue when hdmatx - and hdmarx - parameters in i2c handle - aren't initialized (NULL - pointer).
              • -
                -
              •   Add - additional check on - hi2c->hdmtx - and hi2c->hdmarx - before resetting DMA Tx/Rx - complete callbacks
                • -
              -
            •   Update - Sequential transfer APIs to - adjust xfermode - condition.
              • -
                -
              •   - - - - - Replace hi2c->XferCount - < MAX_NBYTE_SIZE by - hi2c->XferCount - <= MAX_NBYTE_SIZE which - corresponds to a case - without reload
                • -
              -
            -
          -
            -
          •  HAL/LL - - - - USB update
            • -
              -
            •   Bug - - - - fix: USB_ReadPMA() - and USB_WritePMA() - - - - - by ensuring 16-bits access to - USB PMA memory
              • -
            •   Bug - - - - fix: correct USB RX count - calculation
              • -
            •   Fix - USB Bulk transfer double - buffer mode
              • -
            •   Remove - register keyword from USB - defined macros as no more - supported by C++ compiler
              • -
            •   Minor - rework on USBD_Start() - and USBD_Stop() - - - - - APIs: stopping device will be - handled by HAL_PCD_DeInit() - - - - - API.
              • -
            •   Remove - non used API for USB device - mode.
              • -
            -
          -

          V1.7.8 - - - - / 12-February-2020

          -

          Main Changes

          -
            -
          • Add - new HAL FMPSMBUS and LL - - - - FMPI2C drivers
            • -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          -
            -
          • Update - - - - HAL CRYP driver to support block - by block decryption without - reinitializes the IV and KEY for - each call.
            • -
          • Improve - - - - code quality by fixing - MisraC-2012 violations
            • -
          • HAL/LL - - - - USB update
            • -
              -
            •  Add - handling USB host babble error - interrupt
              • -
            •  Fix - Enabling ULPI interface for - platforms that integrates USB - HS PHY
              • -
            •  Fix - Host data toggling for IN Iso - transfers
              • -
            •  Ensure - to disable USB EP during - endpoint deactivation
              • -
            -
          • HAL - - - - CRYP update
            • -
              -
            •  Update - HAL CRYP driver to support - block by block decryption - without initializing the IV - and KEY at each call.
              • -
                -
              • Add new - CRYP Handler parameters: "KeyIVConfig" - and "SizesSum"
                • -
              • Add new - CRYP init - parameter: "KeyIVConfigSkip"
                • -
              -
            -
          • HAL - - - - I2S update
            • -
              -
            • Update - HAL_I2S_DMAStop() - API to be more safe
              • -
                -
              • Add a check - on BSY, TXE and RXNE flags - before disabling the I2S
                • -
              -
            • Update - HAL_I2S_DMAStop() - API to fix multi-call transfer - issue(to avoid re-initializing - the I2S for the next - transfer).
              • -
                -
              • Add - __HAL_I2SEXT_FLUSH_RX_DR() - and __HAL_I2S_FLUSH_RX_DR() - macros to flush the - remaining data inside DR - registers.
                • -
              • Add new ErrorCode - define: - HAL_I2S_ERROR_BUSY_LINE_RX
                • -
              -
            -
          -

          V1.7.7 - - - - / 06-December-2019

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • HAL - - - - Generic update
            • -
              -
            • HAL_SetTickFreq(): update to - restore the previous tick - frequency when HAL_InitTick() - - - - - configuration failed.
              • -
            -
          • HAL/LL - - - - GPIO update
            • -
              -
            • Update GPIO - initialization sequence to - - - - avoid unwanted pulse on GPIO Pin's
              • -
            -
          • HAL - - - - EXTI update
            • -
          -
            -
              -
            • General - update to enhance HAL EXTI - driver robustness 
              • -
                -
              • Add - additional assert check on - EXTI config lines
                • -
              • Update to - compute EXTI line mask - before read/write access - to EXTI registers
                -
                -
                • -
              -
            • Update EXTI - callbacks management to be - compliant with reference - manual: only one PR - register for rising and - falling interrupts.
              • -
                -
              • Update - parameters in EXTI_HandleTypeDef - structure: merge HAL - EXTI RisingCallback - and FallingCallback - in only one PendingCallback
                • -
              • Remove - HAL_EXTI_RISING_CB_ID and - HAL_EXTI_FALLING_CB_ID - values from EXTI_CallbackIDTypeDef - enumeration.
                -
                -
                • -
              -
            • Update - HAL_EXTI_IRQHandler() - API to serve interrupts - correctly.
              • -
                -
              • Update to - compute EXTI line mask - before handle - EXTI interrupt.
                • -
              -
            • Update to - support GPIO port - interrupts:
              • -
                -
              • Add new "GPIOSel" - parameter in EXTI_ConfigTypeDef - structure
                • -
              -
            -
          • HAL/LL - - - - RCC update
            • -
              -
            • Update HAL_RCCEx_PeriphCLKConfig() - API to support PLLI2S - configuration for STM32F42xxx - and STM32F43xxx devices
              • -
            • Update the HAL_RCC_ClockConfig() - and HAL_RCC_DeInit() - - - - - API to don't overwrite the - custom tick priority
              • -
            • Fix LL_RCC_DeInit() - failure detected with gcc - compiler and high optimization - level is selected(-03)
              • -
            • Update HAL_RCC_OscConfig() - API to don't return - HAL_ERROR if request repeats - the current PLL configuration
              • -
            -
          • HAL - - - - ADC update
            • -
              -
            • Update LL_ADC_REG_Init() - to fix wrong ADC CR1 register - configuration
              • -
                -
              • The ADC - sequencer length is part - of ADC SQR1 - register not of ADC CR1 - register
                • -
              -
            -
          • HAL - - - - CRYP update
            • -
              -
            • Update HAL_CRYP_Encrypt() - and HAL_CRYP_Decrypt() - - - - - APIs to take into - consideration the datatype fed - to the DIN register (1-, 8-, - 16-, or 32-bit data) when - padding the last block of the - payload, in case the size of - this last block is less than - 128 bits.
              • -
            -
          • HAL - - - - RNG update
            • -
              -
            • Update HAL_RNG_IRQHandler() - API to fix error code - management issue: error code - is assigned - "HAL_RNG_ERROR_CLOCK" in case - of clock error and - "HAL_RNG_ERROR_SEED" in case - of seed error, not the - opposite.
              • -
            -
          • HAL - - - - DFSDM update
            • -
              -
            • Update DFSDM_GetChannelFromInstance() - API to remove unreachable - check condition
              • -
            -
          • HAL - - - - DMA update
            • -
              -
            • Update HAL_DMA_Start_IT() - API to omit the FIFO error
              • -
            -
          • HAL - - - - FLASH update
            • -
              -
            • Update FLASH_Program_DoubleWord() - API to fix with EWARM high - level optimization issue
              • -
            -
          • HAL - - - - QSPI update
            • -
              -
            • Remove Lock - mechanism from HAL_QSPI_Init() - and HAL_QSPI_DeInit() - - - - - APIs
              • -
            -
          • HAL - - - - HASH update
            • -
              -
            • Null pointer - on handler "hhash" - is now checked before - accessing structure member "hhash->Init.DataType" - in the following API:
              • -
                -
              • HAL_HASH_Init()
                • -
              -
            • Following interrupt-based - APIs have been added. - Interrupt mode could allow the - MCU to enter "Sleep" mode - while a data block is being - processed. Please refer to the - "##### How to use this driver - #####" section for details - about their use.
              • -
                -
              • HAL_HASH_SHA1_Accmlt_IT()
                • -
              • HAL_HASH_MD5_Accmlt_IT()
                • -
              • HAL_HASHEx_SHA224_Accmlt_IT()
                • -
              • HAL_HASHEx_SHA256_Accmlt_IT()
                • -
              -
            • Following aliases - have been added (just for - clarity sake) as they - shall be used at the end - of the computation of a - multi-buffers message and not - at the start:
              • -
                -
              • HAL_HASH_SHA1_Accmlt_End() - to be used instead of - HAL_HASH_SHA1_Start()
                • -
              • HAL_HASH_MD5_Accmlt_End() - to be used instead of - HAL_HASH_MD5_Start()
                • -
              • HAL_HASH_SHA1_Accmlt_End_IT() - to be used instead of - HAL_HASH_SHA1_Start_IT()
                • -
              • HAL_HASH_MD5_Accmlt_End_IT() - to be used instead of - HAL_HASH_MD5_Start_IT()
                • -
              • HAL_HASHEx_SHA224_Accmlt_End() - to be used instead of - HAL_HASHEx_SHA224_Start()
                • -
              • HAL_HASHEx_SHA256_Accmlt_End() - to be used instead of - HAL_HASHEx_SHA256_Start()
                • -
              -
            -
          -
            -
              -
                -
              • HAL_HASHEx_SHA224_Accmlt_End_IT() - to be used instead of - HAL_HASHEx_SHA224_Start_IT()
                • -
              • HAL_HASHEx_SHA256_Accmlt_End_IT() - to be used instead of - HAL_HASHEx_SHA256_Start_IT()
                • -
              -
            -
          -
            -
              -
            • MISRAC-2012 - rule R.5.1 (identifiers - shall be distinct in the first - 31 characters) constrained the - naming of the above listed - aliases (e.g. - HAL_HASHEx_SHA256_Accmlt_End() - could not be named - HAL_HASHEx_SHA256_Accumulate_End(). - - - - - Otherwise the name would have - conflicted with - HAL_HASHEx_SHA256_Accumulate_End_IT()). - In - - - - - order to - have aligned names following - APIs have been renamed:
              • -
            -
          -
            -
              -
                -
                  -
                • HAL_HASH_MD5_Accumulate() - renamed - HAL_HASH_MD5_Accmlt()
                  • -
                • HAL_HASH_SHA1_Accumulate() - renamed - HAL_HASH_SHA1_Accmlt()
                  • -
                • HAL_HASHEx_SHA224_Accumulate() - renamed - HAL_HASHEx_SHA224_Accmlt()
                  • -
                -
              -
            -
          -
            -
              -
                -
                  -
                • HAL_HASHEx_SHA256_Accumulate() - renamed - HAL_HASHEx_SHA256_Accmlt()
                  • -
                -
              -
            -
          -
            -
              -
            • HASH handler - state is no more - reset to HAL_HASH_STATE_READY - once DMA has been started - in the following APIs:
              • -
                -
              • HAL_HASH_MD5_Start_DMA()
                • -
              • HAL_HMAC_MD5_Start_DMA()
                • -
              • HAL_HASH_SHA1_Start_DMA()
                • -
              • HAL_HMAC_SHA1_Start_DMA()
                • -
              -
            • HASH phase - state is now set to - HAL_HASH_PHASE_READY once - the digest has been read - in the following APIs:
              • -
                -
              • HASH_IT()
                • -
              • HMAC_Processing()
                • -
              • HASH_Start()
                • -
              • HASH_Finish()
                • -
              -
            • Case of a - large buffer scattered around - in memory each piece of which - is not necessarily a multiple - - - - of 4 bytes in length.
              • -
                -
              • In section - "##### How to use this - driver #####", sub-section - "*** Remarks on message - length ***" added to provide - recommendations to follow in - such case.
                • -
              • No - modification of the driver - as the root-cause is at - design-level.
                • -
              -
            -
          -
            -
          • HAL CAN - - - - update
            • -
              -
            • HAL_CAN_GetRxMessage() update to - get the correct value for the - RTR (type of frame for - the message that will be - transmitted) field in the CAN_RxHeaderTypeDef - structure.
              • -
            -
          • HAL - - - - DCMI update
            • -
              -
            • Add new HAL_DCMI_ConfigSyncUnmask() - API to set embedded - synchronization delimiters - unmasks.
              • -
            -
          • HAL - - - - RTC update
            • -
              -
            • Following IRQ - handlers' implementation has - been aligned with the - STM32Cube firmware - specification (in case of - interrupt lines shared by - multiple events, first check - the IT enable bit is set then - check the IT flag is set too):
              • -
                -
              • HAL_RTC_AlarmIRQHandler()
                • -
              • HAL_RTCEx_WakeUpTimerIRQHandler()
                • -
              • HAL_RTCEx_TamperTimeStampIRQHandler()
                • -
              -
            -
          -
            -
          • HAL - - - - WWDG update
            • -
              -
            • In "##### - WWDG Specific features #####" - descriptive comment section:
              • -
                -
              • Maximal prescaler - value has been corrected (8 - instead of 128).
                • -
              • Maximal APB - frequency has been corrected - (42MHz instead of 56MHz) and - possible timeout values - updated.
                • -
              -
            -
          • HAL - - - - DMA2D update
            • -
          -
            -
              -
            • Add the - following API's to Start DMA2D - CLUT Loading.
              • -
                -
              • HAL_DMA2D_CLUTStartLoad() - Start DMA2D CLUT Loading.
                • -
              • HAL_DMA2D_CLUTStartLoad_IT() - Start DMA2D CLUT Loading - with interrupt enabled.
                • -
              -
            • The following - old wrong services will be - kept in the HAL DCMI driver - for legacy purpose and a - specific Note is added:
              • -
                -
              • HAL_DMA2D_CLUTLoad() - can be replaced with - HAL_DMA2D_CLUTStartLoad()
                • -
              • HAL_DMA2D_CLUTLoad_IT() can - - - - - be replaced with - HAL_DMA2D_CLUTStartLoad_IT()
                • -
              • HAL_DMA2D_ConfigCLUT() - can be omitted as the config - can be performed using - the HAL_DMA2D_CLUTStartLoad() - API.
                • -
              -
            -
          -
            -
          • HAL - - - - SDMMC update
            • -
              -
            • Fix  - typo in "FileFormatGroup" - parameter in the HAL_MMC_CardCSDTypeDef - and HAL_SD_CardCSDTypeDef - structures 
              • -
            • Fix an - improve handle state and - error management
              • -
            • Rename the - defined MMC card capacity type - to be more meaningful:
              • -
                -
              • Update MMC_HIGH_VOLTAGE_CARD to - - - - - MMC LOW_CAPACITY_CARD
                • -
              • Update MMC_DUAL_VOLTAGE_CRAD - to MMC_HIGH_CAPACITY_CARD
                • -
              -
            • Fix - management of peripheral - flags depending on commands - or data transfers
              • -
                -
              • Add new - defines - "SDIO_STATIC_CMD_FLAGS" - and "SDIO_STATIC_DATA_FLAGS" 
                • -
              • Updates HAL - - - - SD and HAL MMC drivers to - manage the new SDIO static - flags.
                -
                -
                • -
              -
            • Due to - limitation SDIO hardware flow - control indicated in Errata - Sheet:
              • -
                -
              • In 4-bits - bus wide mode, do not use - the HAL_SD_WriteBlocks_IT() - or HAL_SD_WriteBlocks() - - - - - APIs otherwise underrun will - occur and it isn't possible - to activate the flow - control.
                • -
              • Use DMA - mode when using 4-bits bus - wide mode or decrease the - SDIO_CK frequency.
                • -
              -
            -
          • HAL - - - - UART update
            • -
              -
            • Update UART - polling processes to handle - efficiently the Lock mechanism
              • -
                -
              •  Move - the process unlock at the - top of the HAL_UART_Receive() - and HAL_UART_Transmit() - - - - - API.
                • -
              -
            • Fix baudrate - calculation error for clock - higher than 172Mhz
              • -
                -
              • Add a - forced cast on - UART_DIV_SAMPLING8() and - UART_DIV_SAMPLING16() - macros.
                • -
              • Remove - useless parenthesis from - UART_DIVFRAQ_SAMPLING8(), - UART_DIVFRAQ_SAMPLING16(), - UART_BRR_SAMPLING8() and - UART_BRR_SAMPLING16() macros - to solve some MISRA - warnings.
                • -
              -
            • Update UART - interruption handler to manage - correctly the overrun interrupt
              • -
                -
              • Add in - the HAL_UART_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
                • -
              -
            • Fix baudrate - calculation error UART9 - and UART10
              • -
                -
              • In UART_SetConfig() - API fix UART9 and UART10 - clock source when computing - baudrate - values by adding a check on - these instances and setting - clock sourcePCLK2 instead of - PCLK1.
                • -
              -
            • Update UART_SetConfig() - API
              • -
                -
              • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the - UART_BRR_SAMPLING8() and - UART_BRR_SAMPLING8() - macros 
                • -
              -
            -
          • HAL - - - - USART update
            • -
              -
            • Fix baudrate - calculation error for clock - higher than 172Mhz
              • -
                -
              • Add a - forced cast on USART_DIV() - macro.
                • -
              • Remove - useless parenthesis - from USART_DIVFRAQ() - macro to solve some MISRA - warnings.
                • -
              -
            • Update USART - interruption handler to manage - correctly the overrun interrupt
              • -
                -
              • Add in - the HAL_USART_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
                • -
              -
            • Fix baudrate - calculation error UART9 - and UART10
              • -
                -
              • In USART_SetConfig() - API fix UART9 and UART10 - clock source when computing - baudrate - values by adding a check on - these instances and setting - clock sourcePCLK2 instead of - PCLK1.
                • -
              -
            • Update USART_SetConfig() - API
              • -
                -
              • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the USART_BRR() - macro
                • -
              -
            -
          • HAL - - - - IRDA update
            • -
              -
            • Fix baudrate - calculation error for clock - higher than 172Mhz
              • -
                -
              • Add a - forced cast on IRDA_DIV() - macro.
                • -
              • Remove - useless parenthesis - from IRDA_DIVFRAQ() - macro to solve some - MISRA warnings.
                • -
              -
            • Update IRDA - interruption handler to manage - correctly the overrun interrupt
              • -
                -
              • Add in - the HAL_IRDA_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
                • -
              -
            • Fix baudrate - calculation error UART9 - and UART10
              • -
                -
              • In IRDA_SetConfig() - API fix UART9 and UART10 - clock source when computing - baudrate - values by adding a check on - these instances and setting - clock sourcePCLK2 instead of - PCLK1.
                • -
              -
            • Update IRDA_SetConfig() - API
              • -
                -
              • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the IRDA_BRR() - macro
                • -
              -
            -
          • HAL - - - - SMARTCARD update
            • -
              -
            • Fix baudrate - calculation error for clock - higher than 172Mhz
              • -
                -
              • Add a - forced cast on SMARTCARD_DIV() - macro.
                • -
              • Remove useless parenthesis - - - - - from SMARTCARD_DIVFRAQ() - macro to solve some - MISRA warnings.
                • -
              -
            • Update - SMARTCARD interruption handler - to manage correctly the - overrun interrupti
              • -
                -
              • Add in - the HAL_SMARTCARD_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
                • -
              -
            • Update SMARTCARD_SetConfig() - API
              • -
                -
              • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the - SMARTCARD_BRR() macro
                • -
              -
            -
          • HAL - - - - TIM update
            • -
              -
            • Add new - macros to enable and disable - the fast mode when using the - one pulse mode to output a - waveform with a minimum delay
              • -
                -
              • __HAL_TIM_ENABLE_OCxFAST() - and __HAL_TIM_DISABLE_OCxFAST().
                • -
              -
            • Update - Encoder interface mode to - keep TIM_CCER_CCxNP - bits low
              • -
                -
              • Add TIM_ENCODERINPUTPOLARITY_RISING - - - - - and - TIM_ENCODERINPUTPOLARITY_FALLING - definitions to determine - encoder input polarity.
                • -
              • Add - IS_TIM_ENCODERINPUT_POLARITY() - macro to check the - encoder input polarity.
                • -
              • Update HAL_TIM_Encoder_Init() - API 
                • -
                  -
                • Replace - IS_TIM_IC_POLARITY() - macro by - IS_TIM_ENCODERINPUT_POLARITY() - macro.
                  • -
                -
              -
            • Update TIM - remapping input configuration - in HAL_TIMEx_RemapConfig() - API
              • -
                -
              • Remove - redundant check on - LPTIM_OR_TIM5_ITR1_RMP bit - and replace it by check on - LPTIM_OR_TIM9_ITR1_RMP bit.
                • -
              -
            • Update HAL_TIMEx_MasterConfigSynchronization() - API to avoid functional errors - and assert fails when using - some TIM instances as input - trigger.
              • -
                -
              • Replace IS_TIM_SYNCHRO_INSTANCE() - macro by - IS_TIM_MASTER_INSTANCE() - macro. 
                • -
              • Add IS_TIM_SLAVE_INSTANCE() - macro to check on - TIM_SMCR_MSM bit.
                • -
              -
            • Add lacking - TIM input remapping definition 
              • -
                -
              • Add - LL_TIM_TIM11_TI1_RMP_SPDIFRX - and - LL_TIM_TIM2_ITR1_RMP_ETH_PTP.
                • -
              • Add lacking - definition for linked - LPTIM_TIM input trigger remapping  
                • -
                  -
                • Add - following definitions - - - - - : - LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO, - LL_TIM_TIM9_ITR1_RMP_LPTIM, - - - - LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO, - - - - - LL_TIM_TIM5_ITR1_RMP_LPTIM, - - - - LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO - - - - and - LL_TIM_TIM1_ITR2_RMP_LPTIM.
                  • -
                • Add a new - mechanism in LL_TIM_SetRemap() - API to remap TIM1, TIM9, - and TIM5 input - triggers mapped on LPTIM - register. 
                  • -
                -
              -
            -
          • HAL - - - - LPTIM update
            • -
              -
            • Add a polling - mechanism to check - on LPTIM_FLAG_XXOK flags - in different API 
              • -
                -
              • Add  - LPTIM_WaitForFlag() API to - wait for flag set.
                • -
              • Perform new - checks on - HAL_LPTIM_STATE_TIMEOUT.
                • -
              -
            • Add lacking - definitions of LPTIM input - trigger remapping and its - related API
              • -
                -
                  -
                • LL_LPTIM_INPUT1_SRC_PAD_AF, - - - - - LL_LPTIM_INPUT1_SRC_PAD_PA4, - - - - LL_LPTIM_INPUT1_SRC_PAD_PB9 - - - - and - LL_LPTIM_INPUT1_SRC_TIM_DAC.
                  • -
                • Add a new - API LL_LPTIM_SetInput1Src() - to access to the LPTIM_OR - register and remap the - LPTIM input trigger.
                  • -
                -
              -
            • Perform a new - check on indirect EXTI23 line - associated to the LPTIM wake - up timer
              • -
                -
              • Condition - the use of the LPTIM Wake-up - Timer associated EXTI - line configuration's - macros by EXTI_IMR_MR23 - bit in different API - - - - :
                • -
                  -
                • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE/DDISABLE_FALLING_EDGE()
                  • -
                • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()
                  • -
                • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() 
                  • -
                • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()
                  • -
                • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
                  • -
                • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
                  • -
                • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()
                  • -
                • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()
                  • -
                • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() 
                  • -
                -
              • Update HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop_IT(), - - - - - HAL_LPTIM_Counter_Start_IT() - - - - - and HAL_LPTIM_Counter_Stop_IT() - - - - - API by adding Enable/Disable - rising edge trigger on - the LPTIM Wake-up Timer - Exti - line.
                • -
              • Add - __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() - in the end of the HAL_LPTIM_IRQHandler() - - - - - API conditioned by - EXTI_IMR_MR23 bit.
                • -
              -
            -
          • HAL - - - - I2C update
            • -
              -
            • Update - HAL_I2C_EV_IRQHandler() - API to fix I2C send break - issue 
              • -
                -
              • Add - additional check on - hi2c->hdmatx, - hdmatx->XferCpltCallback, - hi2c->hdmarx, - hdmarx->XferCpltCallback - in I2C_Master_SB() - API to avoid enabling - DMA request when IT - mode is used.
                • -
              -
            • Update - HAL_I2C_ER_IRQHandler() - API to fix acknowledge failure - issue with I2C memory IT - processes
              • -
                -
              •  Add stop - - - - - condition generation when - NACK occurs.
                • -
              -
            • Update - HAL_I2C_Init() - API to force software reset - before setting new I2C - configuration
              • -
            • Update HAL - I2C processes to report ErrorCode - when wrong I2C start condition - occurs
              • -
                -
              •  Add - new ErrorCode - define: HAL_I2C_WRONG_START
                • -
              •  Set ErrorCode - parameter in I2C handle - to HAL_I2C_WRONG_START
                • -
              -
            • Update I2C_DMAXferCplt(), - - - - - I2C_DMAError() and - I2C_DMAAbort() APIs to fix hardfault - issue when hdmatx - and hdmarx parameters - - - - - in i2c handle aren't - initialized (NULL pointer).
              • -
                -
              • Add - additional check on - hi2c->hdmtx - and hi2c->hdmarx - before resetting DMA - Tx/Rx complete callbacks
                • -
              -
            -
          • HAL - - - - FMPI2C update
            • -
              -
            • Fix HAL - FMPI2C slave interrupt - handling issue with I2C - sequential transfers.
              • -
                -
              • Update - FMPI2C_Slave_ISR_IT() - and FMPI2C_Slave_ISR_DMA() - APIs to check on STOP - condition and handle it - before clearing the ADDR - flag
                • -
              -
            -
          • HAL - - - - NAND update
            • -
              -
            • Update - HAL_NAND_Write_Page_8b(), - - - - HAL_NAND_Write_Page_16b() - and  - HAL_NAND_Write_SpareArea_16b() - to manage correctly the time - out condition.
              • -
            -
          • HAL - - - - SAI update
            • -
              -
            • Optimize SAI_DMATxCplt() - and SAI_DMARxCplt() - - - - - APIs to check on "Mode" - parameter instead of CIRC - bit in the CR register.
              • -
            • Remove unused - SAI_FIFO_SIZE define
              • -
            • Update HAL_SAI_Receive_DMA() - programming sequence to be inline - with reference manual
              • -
            -
          -

          V1.7.6 - - - - / 12-April-2019

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • HAL - - - - I2C update
            • -
              -
            • Fix I2C send - break issue in IT processes
              • -
                -
              • Add - additional check on - hi2c->hdmatx - and hi2c->hdmarx to - - - - - avoid the DMA request - enable when IT mode is used.
                • -
              -
            -
          • HAL - - - - SPI update
            • -
              -
            • Update to - implement Erratasheet: - BSY bit may stay high at the - end of a data transfer in - Slave mode
              • -
            -
          • LL - - - - LPTIM update
            • -
              -
            • Fix - compilation errors with LL_LPTIM_WriteReg() - and LL_LPTIM_ReadReg() - - - - - macros
              • -
            -
          • HAL - - - - SDMMC update
            • -
              -
            • Fix - preprocessing compilation - issue with SDIO - STA STBITERR interrupt
              • -
            -
          • HAL/LL - - - - USB update
            • -
              -
            • Updated USB_WritePacket(), - - - - - USB_ReadPacket() - - - - - APIs to prevent compilation - warning with GCC GNU v8.2.0
              • -
            • Rework USB_EPStartXfer() - API to enable the USB endpoint - before unmasking the TX FiFo - empty interrupt in case DMA is - not used
              • -
            • USB HAL_HCD_Init() - and HAL_PCD_Init() - - - - - APIs updated to avoid enabling - USB DMA feature for OTG FS - instance, USB DMA feature is - available only on OTG HS - Instance
              • -
            • Remove - duplicated line in hal_hcd.c - header file comment section -
              • -
            • Rework USB - HAL driver to use instance PCD_SPEED_xxx, - HCD_SPEED_xx - speeds instead of OTG register - Core speed definition during - the instance initialization
              • -
            • Software - Quality improvement with a fix - of CodeSonar - warning on PCD_Port_IRQHandler() - and  HCD_Port_IRQHandler() - - - - - interrupt handlers
              • -
            -
          -

          V1.7.5 - - - - / 08-February-2019

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • General - - - - updates to fix CodeSonar - compilation warnings
            • -
          • General - - - - updates to fix SW4STM32 - compilation errors under Linux
            • -
          • General - - - - updates to fix the user manual - .chm files
            • -
          • Add - support of HAL callback - registration feature
            • -
          -
            -
          • Add - new HAL - - - - EXTI driver
            • -
          • Add - new HAL - - - - SMBUS driver
            • -
          • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on older HAL versions
            • -
              -
            • Rework of HAL - CRYP driver (compatibility - break)
              • -
                -
              • HAL CRYP - driver has been redesigned - with new API's, to bypass - limitations on data - Encryption/Decryption - management present with - previous HAL CRYP driver - version.
                • -
              • The new HAL - CRYP driver is the - recommended version. It is - located as usual in - Drivers/STM32F4xx_HAL_Driver/Src - and - Drivers/STM32f4xx_HAL_Driver/Inc - folders. It can be enabled - through switch - HAL_CRYP_MODULE_ENABLED in - stm32f4xx_hal_conf.h
                • -
              • The legacy - HAL CRYP driver is no longer - supported.
                • -
              -
            • Add new AutoReloadPreload - field in TIM_Base_InitTypeDef - structure to allow the - possibilities to enable or - disable the TIM Auto Reload - Preload.
              • -
            -
          -
            -
          • HAL/LL - - - - Generic update
            • -
              -
            • Add support - of HAL callback - registration feature
              • -
                -
              • The feature - disabled by default is - available for the following - HAL drivers:
                • -
                  -
                • ADC, - CAN, CEC, CRYP, DAC, - DCMI, DFSDM, DMA2D, DSI, - ETH, HASH, HCD, I2C, - FMPI2C, SMBUS,
                  - UART, USART, IRDA, - SMARTCARD, LPTIM, LTDC, - MMC, NAND, NOR, - PCCARD, PCD, QSPI, RNG,
                  -                   RTC, - SAI, SD, SDRAM, SRAM, - SPDIFRX, SPI, I2S, TIM, - and WWDG
                  • -
                -
              • The feature - may be enabled individually - per HAL PPP driver - by setting the corresponding - definition USE_HAL_PPP_REGISTER_CALLBACKS - - - - - to 1U in - stm32f4xx_hal_conf.h project - configuration file (template - file - stm32f4xx_hal_conf_template.h - available from  - - - - Drivers/STM32F4xx_HAL_Driver/Inc)
                • -
              • Once enabled - - - - , the user - application may resort to HAL_PPP_RegisterCallback() - - - - - to register specific - callback function(s) and - unregister it(them) with HAL_PPP_UnRegisterCallback().
                • -
              -
            • General - updates to fix MISRA 2012 - compilation errors
              • -
                -
              • Replace HAL_GetUID() - API by HAL_GetUIDw0(), - HAL_GetUIDw1() and - HAL_GetUIDw2()
                • -
              • HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() - macros implementation update
                • -
              • "stdio.h" - include updated with "stddef.h"
                • -
              -
            -
          • HAL - - - - GPIO  - - - - update
            • -
              -
            • Add missing - define for SPI3 alternate - function "GPIO_AF5_SPI3" for - STM32F401VE devices
              • -
            • Remove - "GPIO_AF9_TIM14" from defined - alternate function list for - STM32F401xx devices
              • -
            • HAL_GPIO_TogglePin() reentrancy - robustness improvement
              • -
            • HAL_GPIO_DeInit() API update - to avoid potential pending - interrupt after call
              • -
            • Update - GPIO_GET_INDEX() - API for more compliance with - STM32F412Vx/STM32F412Rx/STM32F412Cx - devices
              • -
            • Update - GPIO_BRR registers with - Reference Manual regarding - registers and bit definition - values
              • -
            -
          • HAL - - - - CRYP update
            • -
              -
            • The CRYP_InitTypeDef - is no more - supported, changed by CRYP_ConfigTypedef - to allow changing parameters - using HAL_CRYP_setConfig() - API without reinitialize the - CRYP IP using the HAL_CRYP_Init() - - - - - API
              • -
            • New - parameters added in the CRYP_ConfigTypeDef - structure: B0 and DataWidthUnit
              • -
            • Input data - size parameter is added in the - CRYP_HandleTypeDef - structure
              • -
            • Add new APIs - to manage the CRYP - configuration:
              • -
                -
              •  HAL_CRYP_SetConfig()
                • -
              • HAL_CRYP_GetConfig()
                • -
              -
            • Add new APIs - to manage the Key derivation:
              • -
                -
              • HAL_CRYPEx_EnableAutoKeyDerivation()
                • -
              • HAL_CRYPEx_DisableAutoKeyDerivation()
                • -
              -
            • Add new APIs - to encrypt and decrypt data:
              • -
                -
              • HAL_CRYP_Encypt()
                • -
              • HAL_CRYP_Decypt()
                • -
              • HAL_CRYP_Encypt_IT()
                • -
              • HAL_CRYP_Decypt_IT()
                • -
              • HAL_CRYP_Encypt_DMA()
                • -
              • HAL_CRYP_Decypt_DMA()
                • -
              -
            • Add new APIs - to generate TAG:
              • -
                -
              • HAL_CRYPEx_AESGCM_GenerateAuthTAG()
                • -
              • HAL_CRYPEx_AESCCM_Generago teAuthTAG()
                • -
              -
            -
          • HAL - - - - LPTIM update
            • -
              -
            • Remove - useless LPTIM Wakeup EXTI - related macros from HAL_LPTIM_TimeOut_Start_IT() - API
              • -
            -
          • HAL - - - - I2C update
            • -
              -
            • I2C API - changes for MISRA-C 2012 - compliancy:
              • -
                -
              • Rename - HAL_I2C_Master_Sequential_Transmit_IT() - to - HAL_I2C_Master_Seq_Transmit_IT()
                • -
              • Rename - HAL_I2C_Master_Sequentiel_Receive_IT() - to - HAL_I2C_Master_Seq_Receive_IT()
                • -
              • Rename - HAL_I2C_Slave_Sequentiel_Transmit_IT() - to - HAL_I2C_Slave_Seq_Transmit_IT() -
                • -
              • Rename - HAL_I2C_Slave_Sequentiel_Receive_DMA() - to - HAL_I2C_Slave_Seq_Receive_DMA()
                • -
              -
            • SMBUS defined - flags are removed as not used - by the HAL I2C driver
              • -
                -
              • I2C_FLAG_SMBALERT
                • -
              • I2C_FLAG_TIMEOUT
                • -
              • I2C_FLAG_PECERR
                • -
              • I2C_FLAG_SMBHOST
                • -
              • I2C_FLAG_SMBDEFAULT
                • -
              -
            • Add support - of I2C repeated start feature - in DMA Mode:
              • -
                -
              • With the - following new API's
                • -
                  -
                • HAL_I2C_Master_Seq_Transmit_DMA()
                  • -
                • HAL_I2C_Master_Seq_Receive_DMA()
                  • -
                • HAL_I2C_Slave_Seq_Transmit_DMA()
                  • -
                • HAL_I2C_Slave_Seq_Receive_DMA()
                  • -
                -
              -
            • Add new I2C - transfer options to easy - manage the sequential transfers
              • -
                -
              • I2C_FIRST_AND_NEXT_FRAME
                • -
              • I2C_LAST_FRAME_NO_STOP
                • -
              • I2C_OTHER_FRAME
                • -
              • I2C_OTHER_AND_LAST_FRAME
                • -
              -
            -
          • HAL - - - - FMPI2C update
            • -
              -
            • I2C API - changes for MISRA-C 2012 - compliancy:
              • -
                -
              • Rename - HAL_FMPI2C_Master_Sequential_Transmit_IT() - to - HAL_FMPI2C_Master_Seq_Transmit_IT()
                • -
              • Rename - HAL_FMPI2C_Master_Sequentiel_Receive_IT() - to - HAL_FMPI2C_Master_Seq_Receive_IT()
                • -
              • Rename - HAL_FMPI2C_Master_Sequentiel_Transmit_DMA() - to - HAL_FMPI2C_Master_Seq_Transmit_DMA() -
                • -
              • Rename - HAL_FMPI2C_Master_Sequentiel_Receive_DMA() - to - HAL_FMPI2C_Master_Seq_Receive_DMA()
                • -
              -
            • Rename - FMPI2C_CR1_DFN to - FMPI2C_CR1_DNF for more - compliance with Reference - Manual regarding registers and - bit definition naming
              • -
            • Add support - of I2C repeated start feature - in DMA Mode:
              • -
                -
              • With the - following new API's
                • -
                  -
                • HAL_FMPI2C_Master_Seq_Transmit_DMA()
                  • -
                • HAL_FMPI2C_Master_Seq_Receive_DMA()
                  • -
                • HAL_FMPI2C_Slave_Seq_Transmit_DMA()
                  • -
                • HAL_FMPI2C_Slave_Seq_Receive_DMA()
                  • -
                -
              -
            -
          • HAL - - - - FLASH update
            • -
              -
            • Update the FLASH_OB_GetRDP() - API to return the correct RDP - level
              • -
            -
          • HAL  - RCC - update
            • -
              -
            • Remove GPIOD - CLK macros for STM32F412Cx - devices (X = D)
              • -
            • Remove GPIOE - CLK macros for - STM32F412Rx\412Cx devices: (X - = E)
              • -
            • Remove - GPIOF/G CLK macros for - STM32F412Vx\412Rx\412Cx - devices (X= F or G)
              • -
                -
              • __HAL_RCC_GPIOX_CLK_ENABLE()
                • -
              • __HAL_RCC_GPIOX_CLK_DISABLE()
                • -
              • __HAL_RCC_GPIOX_IS_CLK_ENABLED()
                • -
              • __HAL_RCC_GPIOX_IS_CLK_DISABLED()
                • -
              • __HAL_RCC_GPIOX_FORCE_RESET()
                • -
              -
            -
          • HAL - - - - RNG update
            • -
              -
            • Update to - manage RNG error code:
              • -
                -
              • Add ErrorCode - parameter in HAL RNG Handler - structure
                • -
              -
            -
          • LL - - - - ADC update
            • -
              -
            • Add - __LL_ADC_CALC_TEMPERATURE() - helper macro to calculate the - temperature (unit: degree - Celsius) from ADC conversion - data of internal temperature - sensor.
              • -
            • Fix ADC - channels configuration issues - on STM32F413xx/423xx devices
              • -
                -
              • To allow - possibility to switch - between VBAT and TEMPERATURE - channels configurations
                • -
              -
            • HAL_ADC_Start(), HAL_ADC_Start_IT() - - - - - and HAL_ADC_Start_DMA() - - - - - update to prevention from - starting ADC2 or ADC3 once - multimode is enabled
              • -
            -
          • HAL - - - - DFSDM  - - - - update
            • -
              -
            • General - updates to be compliant with - DFSDM bits naming used in - CMSIS files.
              • -
            -
          • HAL - - - - CAN  - - - - update
            • -
              -
            • Update - possible values list for FilterActivation - parameter in CAN_FilterTypeDef - structure
              • -
                -
              • CAN_FILTER_ENABLE - - - - - instead of ENABLE
                • -
              • CAN_FILTER_DISABLE - - - - - instead of DISABLE
                • -
              -
            -
          • HAL - - - - CEC  - - - - update
            • -
              -
            • Update HAL - CEC State management method:
              • -
                -
              • Remove HAL_CEC_StateTypeDef - structure parameters
                • -
              • Add new - defines for CEC states
                • -
              -
            -
          • HAL - - - - DMA  - - - - update
            • -
              -
            • Add clean of - callbacks in HAL_DMA_DeInit() - API
              • -
            -
          • HAL - - - - DMA2D  - - - - update
            • -
              -
            • Remove unused - DMA2D_ColorTypeDef structure - to be compliant with MISRAC - 2012 Rule 2.3
              • -
            • General - update to use dedicated - defines for - DMA2D_BACKGROUND_LAYER and - DMA2D_FOREGROUND_LAYER instead - of numerical values: 0/1.
              • -
            -
          • HAL - - - - DSI  - - - - update
            • -
              -
            • Fix read - multibyte issue: remove extra - call to __HAL_UNLOCK__ from DSI_ShortWrite() - API.
              • -
            -
          -
            -
          • HAL/LL - - - - RTC update
            • -
          -
            -
              -
            • HAL/ LL drivers - optimization
              • -
                -
              • HAL driver: - remove unused variables
                • -
              • LL driver: - getter APIs optimization
                • -
              -
            -
          • HAL - - - - PWR update
            • -
              -
            • Remove the - followings API's as feature - not supported by - STM32F469xx/479xx devices
              • -
                -
              • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
                • -
              • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
                • -
              -
            -
          • HAL - - - - SPI update
            • -
              -
            • Update HAL_SPI_StateTypeDef - structure to add new state: - HAL_SPI_STATE_ABORT
              • -
            -
          • HAL/LL - - - - TIM update
            • -
              -
            • Add new AutoReloadPreload - field in TIM_Base_InitTypeDef - structure
              • -
                -
              • Refer to - the TIM examples to identify - the changes -
                • -
              -
            • Move the - following TIM structures from - stm32f4xx_hal_tim_ex.h into - stm32f4xx_hal_tim.h
              • -
                -
              • TIM_MasterConfigTypeDef
                • -
              • TIM_BreakDeadTimeConfigTypeDef
                • -
              -
            • Add new TIM - Callbacks API's:
              • -
                -
              • HAL_TIM_PeriodElapsedHalfCpltCallback()
                • -
              • HAL_TIM_IC_CaptureHalfCpltCallback()
                • -
              • HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
                • -
              • HAL_TIM_TriggerHalfCpltCallback()
                • -
              -
            • TIM API - changes for MISRA-C 2012 - compliancy:
              • -
                -
              • Rename HAL_TIM_SlaveConfigSynchronization - to HAL_TIM_SlaveConfigSynchro
                • -
              • Rename HAL_TIM_SlaveConfigSynchronization_IT - to HAL_TIM_SlaveConfigSynchro_IT
                • -
              • Rename HAL_TIMEx_ConfigCommutationEvent - to HAL_TIMEx_ConfigCommutEvent
                • -
              • Rename HAL_TIMEx_ConfigCommutationEvent_IT - to HAL_TIMEx_ConfigCommutEvent_IT
                • -
              • Rename HAL_TIMEx_ConfigCommutationEvent_DMA - to HAL_TIMEx_ConfigCommutEvent_DMA
                • -
              • Rename HAL_TIMEx_CommutationCallback - to HAL_TIMEx_CommutCallback
                • -
              • Rename HAL_TIMEx_DMACommutationCplt - to TIMEx_DMACommutationCplt
                • -
              -
            -
          -
            -
          • HAL/LL - - - - USB update
            • -
              -
            • Rework USB - interrupt handler and improve - HS DMA support in Device mode
              • -
            • Fix BCD - handling fr OTG - instance in device mode
              • -
            • cleanup - reference to low speed in - device mode
              • -
            • allow writing - TX FIFO in case of transfer - length is equal to available - space in the TX FIFO
              • -
            • Fix Toggle - OUT interrupt channel in host - mode
              • -
            • Update USB - OTG max number of endpoints (6 - FS and 9 HS instead of 5 and - 8)
              • -
            • Update USB - OTG IP to enable internal - transceiver when starting USB - device after committee BCD negotiation
              • -
            -
          • LL - - - - IWDG update
            • -
              -
            • Update LL - inline macros to use IWDGx - parameter instead of IWDG - instance defined in CMSIS device
              • -
            -
          -

          V1.7.4 - - - - / 02-February-2018

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • HAL update
            • -
              -
            • Update UNUSED() - macro implementation to avoid - GCC warning
              • -
                -
              • The warning - is detected when the UNUSED() - macro is called from C++ - file
                • -
              -
            • Update to - make RAMFUNC define as generic - type instead of HAL_StatusTypdef - type.
              • -
            -
          • HAL - - - - FLASH update
            • -
              -
            • Update - the prototypes of the - following APIs after change on - RAMFUNC defines 
              • -
                -
              • HAL_FLASHEx_StopFlashInterfaceClk()
                • -
              • HAL_FLASHEx_StartFlashInterfaceClk()
                • -
              • HAL_FLASHEx_EnableFlashSleepMode()
                • -
              • HAL_FLASHEx_DisableFlashSleepMode()
                • -
              -
            -
          • HAL - - - - SAI update
            • -
              -
            • Update HAL_SAI_DMAStop() - and HAL_SAI_Abort() - - - - - process to fix the lock/unlock - audio issue
              • -
            -
          -

          V1.7.3 - - - - / 22-December-2017

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on older HAL versions
            • -
              -
            • Rework of - HAL CAN driver - (compatibility break) 
              • -
                -
              • A new HAL - CAN driver has been - redesigned with new APIs, to - bypass limitations on CAN - Tx/Rx FIFO management - present with previous HAL - CAN driver version.
                • -
              • The new HAL - CAN driver is the - recommended version. It is - located as usual in - Drivers/STM32F4xx_HAL_Driver/Src - and - Drivers/STM32f4xx_HAL_Driver/Inc - folders. It can be enabled - through switch - HAL_CAN_MODULE_ENABLED in - stm32f4xx_hal_conf.h
                • -
              • The legacy - HAL CAN driver is also - present in the release in - Drivers/STM32F4xx_HAL_Driver/Src/Legacy - - - - and - Drivers/STM32F4xx_HAL_Driver/Inc/Legacy - folders for software - compatibility reasons. Its - usage is not recommended as - deprecated. It can - however be enabled through - switch - HAL_CAN_LEGACY_MODULE_ENABLED - in stm32f4xx_hal_conf.h
                • -
              -
            -
          • HAL update
            • -
              -
            • Update HAL - driver to allow user to change - systick - period to 1ms, 10 ms - or 100 ms :
              • -
                -
              • Add the - following API's - - - - :  
                • -
                  -
                • HAL_GetTickPrio(): - Returns a tick priority.
                  • -
                • HAL_SetTickFreq(): Sets - new tick frequency.
                  • -
                • HAL_GetTickFreq(): - Returns tick frequency.
                  • -
                -
              • Add HAL_TickFreqTypeDef - enumeration for the - different Tick Frequencies: - 10 Hz, 100 Hz and 1KHz - (default).
                • -
              -
            -
          • HAL - - - - CAN update
            • -
              -
            • Fields of CAN_InitTypeDef - structure are reworked:
              • -
                -
              • SJW to SyncJumpWidth, - BS1 to TimeSeg1, BS2 to - TimeSeg2, TTCM to TimeTriggeredMode, - ABOM to AutoBusOff, - AWUM to AutoWakeUp, - NART to AutoRetransmission - (inversed), RFLM to ReceiveFifoLocked - and TXFP to TransmitFifoPriority
                • -
              -
            • HAL_CAN_Init() is split - into both HAL_CAN_Init() - - - - - and HAL_CAN_Start() - - - - - API's
              • -
            • HAL_CAN_Transmit() is replaced - by HAL_CAN_AddTxMessage() - - - - - to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() - - - - - for polling until completion.
              • -
            • HAL_CAN_Transmit_IT() is replaced - by HAL_CAN_ActivateNotification() - - - - - to enable transmit IT, then HAL_CAN_AddTxMessage() - - - - - for place Tx request.
              • -
            • HAL_CAN_Receive() is replaced - by HAL_CAN_GetRxFifoFillLevel() - - - - - for polling until reception, - then HAL_CAN_GetRxMessage() - - - - -
              - to get Rx message.
              • -
            • HAL_CAN_Receive_IT() is replaced - by HAL_CAN_ActivateNotification() to - - - - - enable receive IT, then HAL_CAN_GetRxMessage()
              - in the receivecallback - to get Rx message
              • -
            • HAL_CAN_Slepp() is renamed - as HAL_CAN_RequestSleep()
              • -
            • HAL_CAN_TxCpltCallback() is split - into - HAL_CAN_TxMailbox0CompleteCallback(), -HAL_CAN_TxMailbox1CompleteCallback() -and HAL_CAN_TxMailbox2CompleteCallback().
              • -
            • HAL_CAN_RxCpltCallback is split - into HAL_CAN_RxFifo0MsgPendingCallback() - and - HAL_CAN_RxFifo1MsgPendingCallback().
              • -
            • More complete - "How to use the new driver" is - detailed in the driver header - section itself.
              • -
            -
          • HAL - - - - FMPI2C update
            • -
              -
            • Add new - option - FMPI2C_LAST_FRAME_NO_STOP for - the sequential transfer management
              • -
                -
              • This option - allows to manage a restart - condition after several call - of the same master - sequential interface. 
                • -
              -
            -
          • HAL - - - - RCC update
            • -
              -
            • Add new HAL macros
              • -
                -
              • __HAL_RCC_GET_RTC_SOURCE() - allowing to get the RTC - clock source
                • -
              • __HAL_RCC_GET_RTC_HSE_PRESCALER() - allowing to get the HSE - clock divider for RTC - peripheral
                • -
              -
            • Ensure reset - of CIR and CSR registers when - issuing HAL_RCC_DeInit()/LL_RCC_DeInit - functions
              • -
            • Update HAL_RCC_OscConfig() to - - - - - keep backup domain enabled - when configuring - respectively LSE and RTC - clock source
              • -
            • Add new HAL - interfaces allowing to control - the activation or deactivation - of PLLI2S and PLLSAI:
              • -
                -
              • HAL_RCCEx_EnablePLLI2S()
                • -
              • HAL_RCCEx_DisablePLLI2S()
                • -
              • HAL_RCCEx_EnablePLLSAI()
                • -
              • HAL_RCCEx_DisablePLLSAI()
                • -
              -
            -
          -
            -
          • LL - - - - RCC update 
            • -
              -
            • Add new LL - RCC macro
              • -
                -
              • LL_RCC_PLL_SetMainSource() allowing - to configure PLL main clock - source
                • -
              -
            -
          • LL - - - - FMC / LL FSMC update
            • -
              -
            • Add clear of - the PTYP bit to select the - PCARD mode in FMC_PCCARD_Init() - / FSMC_PCCARD_Init()
              • -
            -
          -

          V1.7.2 - - - - / 06-October-2017

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • Fix - compilation warning with - GCC compiler
            • -
          • Remove - - - - Date and version - from header files
            • -
          • Update - - - - HAL drivers to refer to the - new CMSIS bit position - defines instead of usage the - POSITION_VAL() - macro
            • -
          • HAL - - - - Generic update
            • -
              -
            • stm32f4xx_hal_def.h - - - - file changes: 
              • -
                -
              • Update - __weak and __packed defined - values for ARM compiler
                • -
              • Update - __ALIGN_BEGIN and - __ALIGN_END defined values - for ARM compiler
                • -
              -
            • stm32f4xx_ll_system.h - - - - - file: - add LL_SYSCFG_REMAP_SDRAM - define
              • -
            -
          • HAL - - - - ADC update
            • -
              -
            • Fix wrong - definition of ADC channel - temperature sensor for - STM32F413xx and STM32F423xx - devices.
              • -
            -
          • HAL - - - - DMA update
            • -
              -
            • Update values - - - - for the following defines: - DMA_FLAG_FEIF0_4 and - DMA_FLAG_DMEIF0_4 
              • -
            -
          • HAL - - - - DSI update
            • -
              -
            • Fix Extra - warning with SW4STM32 compiler
              • -
            • Fix DSI - display issue when using EWARM - w/ high level optimization 
              • -
            • Fix - MISRAC errors
              • -
            -
          • HAL - - - - FLASH update
            • -
              -
            • HAL_FLASH_Unlock() update to - return state error when the - FLASH is already unlocked
              • -
            -
          • HAL - - - - FMPI2C update
            • -
              -
            • Update - Interface APIs headers to - remove confusing message about - device address
              • -
            • Update - FMPI2C_WaitOnRXNEFlagUntilTimeout() - to resolve a race condition - between STOPF and RXNE Flags
              • -
            • Update - FMPI2C_TransferConfig() - to fix wrong bit management.
              • -
            • Update code - comments to use DMA stream - instead of DMA channel
              • -
            -
          -
            -
          • HAL - - - - PWR update
            • -
              -
            • HAL_PWR_EnableWakeUpPin() update - description to add support of - PWR_WAKEUP_PIN2 and - PWR_WAKEUP_PIN3
              • -
            -
          • HAL - - - - NOR update
            • -
              -
            • Add the - support of STM32F412Rx devices
              • -
            -
          • HAL - - - - I2C update
            • -
              -
            • Update - Interface APIs headers to - remove confusing mesage - about device address
              • -
            • Update - I2C_MasterReceive_RXNE() - and I2C_MasterReceive_BTF() - static APIs to fix bad - Handling of NACK in I2C master - receive process.
              • -
            -
          -
            -
          • HAL - - - - RCC update
            • -
              -
            • Update HAL_RCC_GetOscConfig() - API to:
              • -
                -
              • set PLLR in - the RCC_OscInitStruct
                • -
              • check on - null pointer
                • -
              -
            • Update HAL_RCC_ClockConfig() - API to:
              • -
                -
              • check on - null pointer
                • -
              • optimize code - - - - size by updating the - handling method of the SWS bits
                • -
              • update to use  - - - - - __HAL_FLASH_GET_LATENCY() - - - - flash macro instead of using - direct register access - to LATENCY bits in - FLASH ACR register.
                • -
              -
            • Update HAL_RCC_DeInit() -  and LL_RCC_DeInit() - - - - - APIs to
              • -
                -
              • Be able to - return HAL/LL status
                • -
              • Add checks - for HSI, PLL and PLLI2S -  ready - before modifying RCC CFGR - registers
                • -
              • Clear all - interrupt falgs
                • -
              • Initialize - systick - interrupt period
                • -
              -
            • Update HAL_RCC_GetSysClockFreq() - to avoid risk of rounding - error which may leads to a - wrong returned value. 
              • -
            -
          -

           

          -

           

          -
            -
          • HAL - - - - RNG update
            • -
              -
            • HAL_RNG_Init() remove - Lock()/Unlock()
              • -
            -
          • HAL - - - - MMC update
            • -
              -
            • HAL_MMC_Erase() - API: add missing () to - fix compilation warning - detected with SW4STM32 when - extra feature is enabled.
              • -
            -
          • HAL - - - - RTC update
            • -
              -
            • HAL_RTC_Init() API: update - to force the wait for synchro - before setting TAFCR register - when BYPSHAD bit in CR - register is 0.
              • -
            -
          • HAL - - - - SAI update
            • -
              -
            • Update HAL_SAI_DMAStop() - API to flush fifo - after disabling SAI
              • -
            -
          • HAL - - - - I2S update
            • -
              -
            • Update I2S - DMA fullduplex process to - handle I2S Rx and Tx DMA Half - transfer complete callback
              • -
            -
          • HAL - - - - TIM update
            • -
              -
            • Update HAL_TIMEx_OCN_xxxx() - and HAL_TIMEx_PWMN_xxx() - - - - - API description to remove - support of TIM_CHANNEL_4
              • -
            -
          • LL - - - - DMA update
            • -
              -
            • Update to - clear DMA flags using WRITE_REG() - instead SET_REG() API to avoid - read access to the IFCR - register that is write only.
              • -
            -
          • LL - - - - RTC update
            • -
              -
            • Fix warning - with static analyzer
              • -
            -
          • LL - - - - USART update
            • -
              -
            • Add assert - macros to check USART BaudRate - register
              • -
            -
          • LL - - - - I2C update
            • -
              -
            • Rename - IS_I2C_CLOCK_SPEED() - and IS_I2C_DUTY_CYCLE() - respectively to - IS_LL_I2C_CLOCK_SPEED() and - IS_LL_I2C_DUTY_CYCLE() to - avoid incompatible macros - redefinition.
              • -
            -
          • LL - - - - TIM update
            • -
              -
            • Update LL_TIM_EnableUpdateEvent() - API to clear UDIS bit in TIM - CR1 register instead of - setting it.
              • -
            • Update LL_TIM_DisableUpdateEvent() - API to set UDIS bit in TIM CR1 - register instead of clearing - it.
              • -
            -
          • LL - - - - USART update
            • -
              -
            • Fix MISRA - error w/ IS_LL_USART_BRR() - macro
              • -
            • Fix wrong - check when UART10 instance is - used
              • -
            -
          -

          V1.7.1 - - - - / 14-April-2017

          -

          Main Changes

          -
            -
          • Update - - - - CHM UserManuals - to support LL drivers
            • -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • HAL - - - - CAN update
            • -
              -
            • Add - management of overrun - error. 
              • -
            • Allow - possibility to receive - messages from the 2 RX FIFOs - in parallel via interrupt.
              • -
            • Fix message - - - - lost issue with specific - sequence of transmit requests.
              • -
            • Handle - transmission failure with - error callback, when NART is - enabled.
              • -
            • Add - __HAL_CAN_CANCEL_TRANSMIT() - call to abort transmission - when timeout is reached
              • -
            -
          -
            -
          • HAL - - - - PWR update
            • -
              -
            • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove - check on UDRDY flag
              • -
            -
          -
            -
          • LL - - - - ADC update
            • -
              -
            • Fix wrong ADC - group injected sequence configuration
              • -
                -
              • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() - - - - - API's update to take in - consideration the ADC number - of conversions
                • -
              • Update - the defined values for - ADC group injected seqencer - ranks 
                • -
              -
            -
          -

          V1.7.0 - - - - / 17-February-2017

          -

          Main Changes

          -
            -
          • Add - - - - Low Layer drivers allowing - performance and footprint optimization
            • -
              -
            • Low Layer drivers - APIs provide register level - programming: require deep - knowledge of peripherals - described in STM32F4xx - Reference Manuals
              • -
            • Low Layer - drivers are available for: - ADC, Cortex, CRC, DAC, - DMA, DMA2D, EXTI, GPIO, I2C, - IWDG, LPTIM, PWR, RCC, RNG, - RTC, SPI, TIM, USART, WWDG - peripherals and additionnal - Low Level Bus, System and - Utilities APIs.
              • -
            • Low Layer drivers - APIs are implemented as static - inline function in new Inc/stm32f4xx_ll_ppp.h files - - - - - for PPP peripherals, there is - no configuration file and each stm32f4xx_ll_ppp.h file - - - - - must be included in user code.
              • -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • Fix extra - - - - warnings with GCC compiler
            • -
          • HAL - drivers clean up: remove - double casting 'uint32_t' and 'U'
            • -
          • Add - new HAL - - - - MMC driver
            • -
          • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on older HAL versions
            • -
              -
            • HAL SD update
              • -
                -
              • Overall - rework of the driver for a - more - efficient implementation
                • -
                  -
                • Modify - initialization API and structures
                  • -
                • Modify - Read / Write sequences: - separate transfer process - and SD Cards state management 
                  • -
                • Adding - interrupt mode for Read / - Write operations
                  • -
                • Update - the HAL_SD_IRQHandler - function by optimizing the - management of interrupt errors
                  • -
                -
              • Refer to - the following example to - identify the changes: BSP - example and USB_Device/MSC_Standalone - application
                • -
              -
            • HAL NAND update
              • -
                -
              • Modify NAND_AddressTypeDef, - NAND_DeviceConfigTypeDef - and NAND_HandleTypeDef - structures fields
                • -
              • Add new HAL_NAND_ConfigDevice - API
                • -
              -
            • HAL DFSDM update
              • -
                -
              • Add - support of Multichannel - Delay feature
                • -
                  -
                • Add HAL_DFSDM_ConfigMultiChannelDelay - API
                  • -
                • The - following APIs are moved - to internal static - functions: HAL_DFSDM_ClockIn_SourceSelection, - HAL_DFSDM_ClockOut_SourceSelection, - HAL_DFSDM_DataInX_SourceSelection - (X=0,2,4,6), HAL_DFSDM_BitStreamClkDistribution_Config
                  • -
                -
              -
            • HAL I2S update
              • -
                -
              • Add specific - - - - - callback API to manage I2S - full duplex end of transfer - process:
                • -
                  -
                • HAL_I2S_TxCpltCallback() - and - HAL_I2S_RxCpltCallback() - API's will be replaced - with only - HAL_I2SEx_TxRxCpltCallback() - API. 
                  • -
                -
              -
            -
          • HAL - - - - update
            • -
              -
            • Modifiy default HAL_Delay - implementation to guarantee - minimum delay 
              • -
            -
          • HAL - - - - Cortex update
            • -
              -
            • Move HAL_MPU_Disable() - and HAL_MPU_Enable() - - - - - from stm32f4xx_hal_cortex.h to - stm32f4xx_hal_cortex.c
              • -
            • Clear the - whole MPU control register - in HAL_MPU_Disable() - API
              • -
            -
          • HAL - - - - FLASH update
            • -
              -
            • IS_FLASH_ADDRESS() - macro update to support OTP - range
              • -
            • FLASH_Program_DoubleWord(): Replace - 64-bit accesses with 2 - double-words operations
              • -
            -
          • LL - - - - GPIO update
            • -
              -
            • Update - IS_GPIO_PIN() - macro implementation to be - more safe
              • -
            -
          • LL - - - - RCC update
            • -
              -
            • Update - IS_RCC_PLLQ_VALUE() - macro implementation: the - minimum accepted value is - 2 instead of 4
              • -
            • Rename - RCC_LPTIM1CLKSOURCE_PCLK - define to - RCC_LPTIM1CLKSOURCE_PCLK1
              • -
            • Fix - compilation issue w/ - __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() - and - __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() - macros for STM32F401xx devices
              • -
            • Add the - following is clock - enabled macros for STM32F401xx - devices
              • -
                -
              •  __HAL_RCC_SDIO_IS_CLK_ENABLED()
                • -
              • __HAL_RCC_SPI4_IS_CLK_ENABLED()
                • -
              • __HAL_RCC_TIM10_IS_CLK_ENABLED()
                • -
              -
            • Add the - following is clock - enabled macros for STM32F410xx - devices
              • -
                -
              •  __HAL_RCC_CRC_IS_CLK_ENABLED()
                • -
              • __HAL_RCC_RNG_IS_CLK_ENABLED()
                • -
              -
            • Update HAL_RCC_DeInit() - to reset the RCC clock - configuration to the default - reset state.
              • -
            • Remove macros - to configure BKPSRAM from - STM32F401xx devices 
              • -
            • Update to - refer to AHBPrescTable[] - and APBPrescTable[] - - - - - tables defined in - system_stm32f4xx.c file - instead of APBAHBPrescTable[] - - - - - table.
              • -
            -
          • HAL - - - - FMPI2C update
            • -
              -
            • Add - FMPI2C_FIRST_AND_NEXT_FRAME - define in Sequential - Transfer Options
              • -
            -
          • HAL - - - - ADC update
            • -
              -
            • HAL_ADCEx_InjectedConfigChannel(): update the - external trigger injected - condition
              • -
            -
          • HAL - - - - DMA update
            • -
              -
            • HAL_DMA_Init(): update to - check compatibility between - FIFO threshold level and size - of the memory burst 
              • -
            -
          • HAL - - - - QSPI update
            • -
              -
            • QSPI_HandleTypeDef structure: - Update transfer parameters on - uint32_t instead of uint16_t
              • -
            -
          • HAL - - - - UART/USART/IrDA/SMARTCARD update
            • -
              -
            • DMA Receive - process; the code has been - updated to clear the USART - OVR flag before - enabling DMA receive - request.
              • -
            • UART_SetConfig() update to - manage correctly USART6 - instance that is not available - on STM32F410Tx devices
              • -
            -
          • HAL - - - - CAN update
            • -
              -
            • Remove Lock - mechanism from HAL_CAN_Transmit_IT() - and HAL_CAN_Receive_IT() - - - - - processes
              • -
            -
          • HAL - - - - TIM update
            • -
              -
            • Add - __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() - macro to disable Master output - without check on TIM channel - state. 
              • -
            • Update HAL_TIMEx_ConfigBreakDeadTime() - to fix TIM BDTR register - corruption.
              • -
            -
          • HAL - - - - I2C update
            • -
              -
            • Update - HAL_I2C_Master_Transmit() - and HAL_I2C_Slave_Transmit() - to avoid sending extra - bytes at the end of the - transmit processes
              • -
            • Update - HAL_I2C_Mem_Read() - API to fix wrong check on - misused parameter �Size�
              • -
            • Update - I2C_MasterReceive_RXNE() - and I2C_MasterReceive_BTF() - static APIs to enhance Master - sequential reception process.
              • -
            -
          • HAL - - - - SPI update
            • -
              -
            • Add transfer - abort APIs and associated - callbacks in interrupt mode
              • -
                -
              • HAL_SPI_Abort()
                • -
              • HAL_SPI_Abort_IT()
                • -
              • HAL_SPI_AbortCpltCallback()
                • -
              -
            -
          • HAL - - - - I2S update
            • -
              -
            • Add specific - - - - - callback API to manage I2S - full duplex end of transfer - process:
              • -
                -
              • HAL_I2S_TxCpltCallback() - and HAL_I2S_RxCpltCallback() - API's will be replaced with - only - HAL_I2SEx_TxRxCpltCallback() - API. 
                • -
              -
            • Update I2S - Transmit/Receive polling - process to manage Overrun - and Underrun errors
              • -
            • Move - the I2S clock input - frequency calculation to - HAL RCC driver.
              • -
            • Update the - HAL I2SEx driver to keep only - full duplex feature.
              • -
            • HAL_I2S_Init() - API updated to
              • -
                -
              • Fix wrong - I2S clock calculation when - PCM mode is used.
                • -
              • Return - state HAL_I2S_ERROR_PRESCALER when - the I2S clock is wrongly configured
                • -
              -
            -
          -
            -
          • HAL - - - - LTDC update
            • -
              -
            • Optimize HAL_LTDC_IRQHandler() - function by using direct - register read
              • -
            • Rename the - following API's
              • -
                -
              • HAL_LTDC_Relaod() by HAL_LTDC_Reload() 
                • -
              • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
                • -
              • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
                • -
              -
            • Add new - defines for LTDC layers - (LTDC_LAYER_1 / LTDC_LAYER_2)
              • -
            • Remove unused - asserts
              • -
            -
          • HAL - - - - USB PCD - update
            • -
              -
            • Flush all TX - FIFOs on USB Reset
              • -
            • Remove Lock - mechanism from HAL_PCD_EP_Transmit() - and HAL_PCD_EP_Receive() - - - - - API's
              • -
            -
          -
            -
          • LL - - - - USB update
            • -
              -
            • Enable DMA - Burst mode for USB OTG HS
              • -
            • Fix SD card - detection issue
              • -
            -
          • LL - - - - SDMMC update
            • -
              -
            • Add new SDMMC_CmdSDEraseStartAdd, - SDMMC_CmdSDEraseEndAdd, - SDMMC_CmdOpCondition - and SDMMC_CmdSwitch - functions
              • -
            -
          -

          V1.6.0 - - - - / 04-November-2016

          -

          Main Changes

          -
            -
          • Add support of STM32F413xx - and STM32F423xx - devices
            • -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • HAL - - - - CAN update
            • -
              -
            • Update to add - the support of 3 CAN management
              • -
            -
          • HAL - - - - CRYP update
            • -
              -
            • Update to add - the support of AES features
              • -
            -
          • HAL - - - - DFSDM update
            • -
              -
            • Add - definitions for new external - trigger filters
              • -
            • Add - definition for new Channels - 4, 5, 6 and 7
              • -
            • Add - functions and API for Filter - state configuration and management
              • -
            • Add new - functions: 
              • -
                -
              • HAL_DFSDM_BitstreamClock_Start()
                • -
              • HAL_DFSDM_BitstreamClock_Stop()
                • -
              • HAL_DFSDM_BitStreamClkDistribution_Config() 
                • -
              -
            -
          • HAL - - - - DMA
            • -
              -
            • Add the - support of DMA Channels from - 8 to 15
              • -
            • Update HAL_DMA_DeInit() - function with the check on - DMA stream instance
              • -
            -
          • HAL - - - - DSI update
            • -
          -
            -
              -
            • Update HAL_DSI_ConfigHostTimeouts() - and HAL_DSI_Init() - - - - - functions to avoid scratch in - DSI_CCR register
              • -
            -
          • HAL - - - - FLASH update
            • -
              -
            • Enhance FLASH_WaitForLastOperation() - function implementation
              • -
            • Update - __HAL_FLASH_GET_FLAG() - macro implementation
              • -
            -
          • HAL - - - - GPIO update
            • -
              -
            • Add - specific alternate functions - definitions
              • -
            -
          • HAL - - - - I2C update
            • -
              -
            • Update I2C_DMAError() - function implementation to - ignore DMA FIFO error
              • -
            -
          • HAL - - - - I2S update
            • -
              -
            • Enhance - HAL_I2S_Init() - implementation to test on - PCM_SHORT and PCM_LONG - standards
              • -
            -
          • HAL - - - - IRDA update
            • -
              -
            • Add new - functions and call backs for - Transfer Abort
              • -
                -
              • HAL_IRDA_Abort()
                • -
              • HAL_IRDA_AbortTransmit()
                • -
              • HAL_IRDA_AbortReceive()
                • -
              • HAL_IRDA_Abort_IT()
                • -
              • HAL_IRDA_AbortTransmit_IT()
                • -
              • HAL_IRDA_AbortReceive_IT()
                • -
              • HAL_IRDA_AbortCpltCallback()
                • -
              • HAL_IRDA_AbortTransmitCpltCallback()
                • -
              -
            -
          -
            -
              -
                -
              • HAL_IRDA_AbortReceiveCpltCallback()
                • -
              -
            -
          • HAL - - - - PCD update
            • -
          -
            -
              -
            • Update HAL_PCD_GetRxCount() -  function implementation
              • -
            -
          • HAL - - - - RCC update
            • -
              -
            • Update - __HAL_RCC_HSE_CONFIG() - macro implementation
              • -
            • Update __HAL_RCC_LSE_CONFIG() - macro implementation
              • -
            -
          • HAL - - - - SMARTCARD update
            • -
          -
            -
              -
            • Add new - functions and call backs for - Transfer Abort
              • -
                -
              • HAL_ SMARTCARD_Abort()
                • -
              • HAL_ SMARTCARD_AbortTransmit()
                • -
              • HAL_ SMARTCARD_AbortReceive()
                • -
              • HAL_ SMARTCARD_Abort_IT()
                • -
              • HAL_ SMARTCARD_AbortTransmit_IT()
                • -
              • HAL_ SMARTCARD_AbortReceive_IT()
                • -
              • HAL_ SMARTCARD_AbortCpltCallback()
                • -
              • HAL_ SMARTCARD_AbortTransmitCpltCallback()
                • -
              • HAL_ SMARTCARD_AbortReceiveCpltCallback()
                • -
              -
            -
          • HAL - - - - TIM update
            • -
              -
            • Update HAL_TIMEx_RemapConfig() - function to manage TIM - internal trigger remap: - LPTIM or TIM3_TRGO
              • -
            -
          • HAL - - - - UART update
            • -
              -
            • Add - Transfer abort functions and - callbacks
              • -
            -
          • HAL - - - - USART update
            • -
              -
            • Add - Transfer abort functions and - callbacks
              • -
            -
          -

          V1.5.2 - - - - / 22-September-2016

          -

          Main Changes

          -
            -
          • HAL - - - - I2C update
            • -
              -
            • Fix wrong - behavior in consecutive - transfers in case of single - byte transmission - (Master/Memory Receive
              - interfaces)
              • -
            • Update - HAL_I2C_Master_Transmit_DMA() - / - HAL_I2C_Master_Receive_DMA()/ - HAL_I2C_Slave_Transmit_DMA()
              - and - HAL_I2C_Slave_Receive_DMA() to - manage addressing phase - through interruption instead - of polling
              • -
            • Add - a check on I2C handle - state at start of all I2C - API's to ensure that I2C is ready
              • -
            • Update I2C - API's (Polling, IT and DMA - interfaces) to manage I2C XferSize - and XferCount - handle parameters instead of - API size parameter to help - user to get information of - counter in case of - error. 
              • -
            • Update Abort - functionality to manage DMA - use case
              • -
            -
          • HAL - - - - FMPI2C update
            • -
              -
            • Update to - disable Own Address - before setting the new Own - Address - configuration:
              • -
                -
              • Update - HAL_FMPI2C_Init() - to disable FMPI2C_OARx_EN - bit before any - configuration in OARx - registers
                • -
              -
            -
          • HAL - - - - CAN update
            • -
              -
            • Update CAN - receive processes to set CAN - RxMsg - FIFONumber - parameter
              • -
            -
          • HAL - - - - UART update
            • -
              -
            • Update UART - - - - handle TxXferCount - and RxXferCount parameters - - - - - as volatile to avoid - eventual issue with High Speed - optimization  
              • -
            -
          -

          V1.5.1 - - - - / 01-July-2016

          -

          Main Changes

          -
            -
          • HAL - - - - GPIO update
            • -
              -
            • HAL_GPIO_Init()/HAL_GPIO_DeInit() - API's: - update GPIO_GET_INDEX() - macro implementation to - support all GPIO's
              • -
            -
          • HAL - - - - SPI update
            • -
              -
            • Fix - regression issue: - retore HAL_SPI_DMAPause() - and HAL_SPI_DMAResume() API's -
              • -
            -
          • HAL - - - - RCC update
            • -
              -
            • Fix FSMC - macros compilation warnings - with STM32F412Rx devices
              • -
            -
          • HAL - - - - DMA update
            • -
              -
            • HAL_DMA_PollFortransfer() API clean - up
              -
              -
              • -
            -
          • HAL - - - - PPP update(PPP refers to - IRDA, UART, USART and SMARTCARD)
            • -
              -
            • Update - - - - HAL_PPP_IRQHandler() - to add a check on interrupt - source before managing the - error 
              • -
            -
          -
            -
          • HAL - - - - QSPI update
            • -
              -
            • Implement - workaround to fix the - limitation pronounced - - - - in - the Errata - sheet 2.1.8 section: - In some specific cases, - DMA2 data corruption - occurs when managing AHB - and APB2 peripherals in a - concurrent way
              • -
            -
          -

          V1.5.0 - - - - / 06-May-2016

          -

          Main Changes

          -
            -
          • Add support of STM32F412cx, - - - - - STM32F412rx, STM32F412vx and - STM32F412zx devices
            • -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • Add - new HAL driver for DFSDM peripheral
            • -
          • Enhance - - - - HAL delay and time base - implementation:
            • -
              -
            • Add new - drivers - stm32f4xx_hal_timebase_rtc_alarm_template.c - and - stm32f4xx_hal_timebase_rtc_wakeup_template.c - which override the native HAL - time base functions (defined - as weak) to either use the RTC - as time base tick source. For - more details about the usage - of these drivers, please refer - to HAL\HAL_TimeBase_RTC - examples and - - - - - FreeRTOS-based - - - - - applications
              • -
            -
          • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on HAL V1.4.4
            • -
              -
            • HAL UART, - USART, IRDA, SMARTCARD, SPI, - I2C,FMPI2C, - - - - - QSPI (referenced - as PPP here - - - - - below) drivers
              • -
                -
              • Add PPP - error management during DMA - process. This requires the - following updates - on user application:
                • -
                  -
                • Configure - and enable the PPP IRQ in - HAL_PPP_MspInit() - function
                  • -
                • In stm32f4xx_it.c - - - - - file, PPP_IRQHandler() - function: add - - - - - a call to HAL_PPP_IRQHandler() - - - - - function
                  • -
                • Add and - customize the Error - Callback API: HAL_PPP_ErrorCallback()
                  • -
                -
              -
            • HAL I2C, FMPI2C (referenced - as PPP here - - - - - below) drivers:
              • -
                -
              • Update to - avoid waiting on STOPF/BTF/AF - - - - - flag under DMA ISR by using - the PPP - - - - end of transfer interrupt in - the DMA transfer process. This - - - - - requires the following - updates on user - application:
                • -
                  -
                • Configure - and enable the PPP IRQ in - HAL_PPP_MspInit() - function
                  • -
                • In stm32f4xx_it.c - - - - - file, PPP_IRQHandler() - function: add - - - - - a call to HAL_PPP_IRQHandler() - - - - - function
                  • -
                -
              -
            • HAL I2C driver:
              • -
                -
              • I2C - transfer processes IT - update: NACK during - addressing phase is managed - through I2C Error - interrupt instead of - HAL state
                • -
              -
            -
          -
            -
              -
            • HAL IWDG driver: - rework overall driver for - better implementation
              • -
                -
              • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() - - - - - and HAL_IWDG_GetState() APIs
                • -
              -
            • HAL WWDG driver: - rework overall driver for - better implementation
              • -
                -
              • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() - - - - - and HAL_WWDG_GetState() - - - - - APIs 
                • -
              • Update - the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, - uint32_t counter) -  function and API -  by removing the -  "counter" parameter
                • -
              -
            • HAL QSPI - driver:  Enhance - the DMA transmit process - by using PPP TC - interrupt instead of waiting - on TC flag under DMA - ISR. This requires the - following updates on user - application:
              • -
                -
              • Configure - and enable the QSPI IRQ - in HAL_QSPI_MspInit() - function
                • -
              • In stm32f4xx_it.c - - - - - file, QSPI_IRQHandler() - function: add - - - - a call to HAL_QSPI_IRQHandler() - - - - - function
                • -
              -
            • HAL CEC - driver:  Overall - driver rework with - compatibility break versus - previous HAL version
              • -
                -
              • Remove HAL - CEC polling Process - functions: HAL_CEC_Transmit() - and HAL_CEC_Receive()
                • -
              • Remove HAL - CEC receive interrupt - process function HAL_CEC_Receive_IT() - and enable the "receive" -  mode during the Init - phase
                • -
              • Rename HAL_CEC_GetReceivedFrameSize() - funtion - to HAL_CEC_GetLastReceivedFrameSize()
                • -
              • Add new HAL - APIs: HAL_CEC_SetDeviceAddress() - and HAL_CEC_ChangeRxBuffer()
                • -
              • Remove - the 'InitiatorAddress' - field from the CEC_InitTypeDef - structure and manage - it as a parameter in - the HAL_CEC_Transmit_IT() - function
                • -
              • Add new - parameter 'RxFrameSize' - in HAL_CEC_RxCpltCallback() - function
                • -
              • Move CEC Rx - buffer pointer from CEC_HandleTypeDef - structure to CEC_InitTypeDef - structure
                • -
              -
            -
          -
            -
          • HAL - - - - RCC update
            • -
              -
            • Update HAL_RCC_ClockConfig() - function to adjust the SystemCoreClock
              • -
            • Rename macros - and Literals:
              • -
                -
              • RCC_PERIPHCLK_CK48 by RCC_PERIPHCLK_CLK48
                • -
              • IS_RCC_CK48CLKSOURCE by - - - - - IS_RCC_CLK48CLKSOURCE
                • -
              • RCC_CK48CLKSOURCE_PLLSAIP - - - - - by RCC_CLK48CLKSOURCE_PLLSAIP
                • -
              • RCC_SDIOCLKSOURCE_CK48 - - - - by RCC_SDIOCLKSOURCE_CLK48
                • -
              • RCC_CK48CLKSOURCE_PLLQ - - - - - by RCC_CLK48CLKSOURCE_PLLQ
                • -
              -
            • Update HAL_RCCEx_GetPeriphCLKConfig() - and HAL_RCCEx_PeriphCLKConfig() - - - - - functions to support TIM Prescaler - for STM32F411xx devices
              • -
            • HAL_RCCEx_PeriphCLKConfig() API: update - to fix the RTC clock - configuration issue
              • -
            -
          • HAL - - - - CEC update
            • -
              -
            • Overall - driver rework with break - of compatibility with HAL - V1.4.4
              • -
                -
              • Remove the - HAL CEC polling Process: HAL_CEC_Transmit() - and HAL_CEC_Receive()
                • -
              -
            -
          -
            -
              -
                -
              • Remove the - HAL CEC receive interrupt - process (HAL_CEC_Receive_IT()) - - - - - and manage the "Receive" - mode enable within the Init - phase
                • -
              • Rename HAL_CEC_GetReceivedFrameSize() - function to HAL_CEC_GetLastReceivedFrameSize() - - - - - function
                • -
              • Add new HAL - APIs: HAL_CEC_SetDeviceAddress() - and HAL_CEC_ChangeRxBuffer()
                • -
              • Remove - the 'InitiatorAddress' - field from the CEC_InitTypeDef - structure and manage - it as a parameter in - the HAL_CEC_Transmit_IT() - function
                • -
              • Add new - parameter 'RxFrameSize' - in HAL_CEC_RxCpltCallback() - function
                • -
              • Move CEC Rx - buffer pointer from CEC_HandleTypeDef - structure to CEC_InitTypeDef - structure
                • -
              -
            • Update driver - to implement the new CEC state - machine:
              • -
                -
              • Add - new "rxState" field - - - - - in CEC_HandleTypeDef - structure to provide the CEC state - - - - - information related to Rx Operations
                • -
              • Rename - "state" field in CEC_HandleTypeDef - structure to "gstate": - - - - CEC state - - - - - information related to - global Handle management and - Tx Operations
                • -
              • Update CEC - process to manage the new - CEC states.
                • -
              • Update - __HAL_CEC_RESET_HANDLE_STATE() - macro to handle the new CEC - state parameters (gState, - rxState)
                • -
              -
            -
          -
            -
          • HAL - - - - UART, USART, SMARTCARD and - IRDA (referenced - - - - as PPP here below) update
            • -
              -
            • Update - Polling management:
              • -
                -
              • The user - Timeout value must be - estimated for the overall - process duration: the - Timeout measurement is - cumulative
                • -
              -
            • Update DMA - process:
              • -
                -
              • Update the - management of PPP peripheral - errors during DMA process. - This requires the following - updates in user application:
                • -
                  -
                • Configure - and enable the PPP IRQ in - HAL_PPP_MspInit() - function
                  • -
                • In - stm32f4xx_it.c file, PPP_IRQHandler() - function: add a call to HAL_PPP_IRQHandler() - - - - - function
                  • -
                • Add and - customize the Error - Callback API: HAL_PPP_ErrorCallback()
                  • -
                -
              -
            -
          • HAL - - - - FMC update
            • -
              -
            • Update FMC_NORSRAM_Init() - to remove the Burst access - mode configuration
              • -
            • Update FMC_SDRAM_Timing_Init() - to fix initialization issue - when configuring 2 SDRAM banks
              • -
            -
          • HAL - - - - HCD update
            • -
              -
            • Update HCD_Port_IRQHandler() - to unmask disconnect IT only - when the port is disabled
              • -
            -
          • HAL - - - - I2C/FMPI2C - update
            • -
              -
            • Update Polling - - - - - management:
              • -
                -
              • The Timeout - value must be estimated for - the overall process - duration: the - Timeout measurement is - cumulative
                • -
              -
            • Add the - management of Abort - service: Abort DMA - transfer through interrupt
              • -
                -
              • In the case - of Master Abort IT transfer - usage:
                • -
                  -
                • Add new - - - - user HAL_I2C_AbortCpltCallback() - to inform user of the end - of abort process
                  • -
                • A new - abort state is defined in - the HAL_I2C_StateTypeDef structure
                  • -
                -
              -
            • Add the - management of I2C peripheral - errors, ACK failure and STOP - condition detection during DMA - process. This requires the - following updates on user - application:
              • -
                -
              • Configure - and enable the I2C IRQ in - HAL_I2C_MspInit() - function
                • -
              • In - stm32f4xx_it.c file, I2C_IRQHandler() - function: add a call to - HAL_I2C_IRQHandler() - function
                • -
              • Add and - customize the Error Callback - API: HAL_I2C_ErrorCallback()
                • -
              • Refer to - the I2C_EEPROM or - I2C_TwoBoards_ComDMA project - examples usage of the API
                • -
              -
            • NACK error - during addressing phase is - returned through interrupt - instead of previously through - I2C transfer API's
              • -
            • I2C - addressing phase is updated to - be managed using interrupt - instead of polling (Only - for HAL I2C driver)
              • -
                -
              • Add new - static functions to manage - I2C SB, ADDR and ADD10 flags
                • -
              -
            -
          • HAL - - - - SPI update
            • -
          -
            -
              -
            • Overall - driver optimization to improve - performance in - polling/interrupt mode to - reach maximum peripheral frequency
              • -
                -
              • Polling - mode:
                • -
                  -
                • Replace - the use of SPI_WaitOnFlagUnitTimeout() - function by "if" statement - to check on RXNE/TXE flage - while transferring data
                  • -
                -
              -
            -
          -
            -
              -
                -
              •  Interrupt - - - - mode:
                • -
                  -
                • Minimize - access on SPI registers
                  • -
                -
              • All modes:
                • -
                  -
                • Add the - USE_SPI_CRC switch to - minimize the number of - statements when CRC - calculation is disabled
                  • -
                • Update timeout - - - - - management to check on - global processes
                  • -
                • Update - error code management in - all processes
                  • -
                -
              -
            • Update DMA - process:
              • -
                -
              • Add the - management of SPI peripheral - errors during DMA process. - This requires the following - updates in the user - application:
                • -
                  -
                • Configure - and enable the SPI IRQ in - HAL_SPI_MspInit() - function
                  • -
                • In - stm32f4xx_it.c file, SPI_IRQHandler() - function: add a call to HAL_SPI_IRQHandler() - - - - - function
                  • -
                • Add and - customize the Error - Callback API: HAL_SPI_ErrorCallback()
                  • -
                • Refer to - the following example - which describe the - changes: SPI_FullDuplex_ComDMA
                  • -
                -
              -
            • Fix - regression in polling mode:
              • -
                -
              • Add - preparing data to transmit - in case of slave mode in HAL_SPI_TransmitReceive() - and HAL_SPI_Transmit()
                • -
              • Add to - manage properly the overrun - flag at the end of a HAL_SPI_TransmitReceive()
                • -
              -
            • Fix - regression in interrupt mode:
              • -
                -
              • Add a wait - on TXE flag in SPI_CloseTx_ISR() - and in SPI_CloseTxRx_ISR()
                • -
              • Add to - manage properly - the overrun flag in SPI_CloseRxTx_ISR() - and SPI_CloseRx_ISR()
                • -
              -
            -
          -
            -
          • HAL - - - - DMA2D update
            • -
              -
            • Update the - HAL_DMA2D_DeInit() - function to:
              • -
                -
              • Abort - transfer in case of ongoing - DMA2D transfer
                • -
              • Reset DMA2D - control registers
                • -
              -
            • Update - HAL_DMA2D_Abort() - to disable DMA2D interrupts - after stopping transfer
              • -
            • Optimize - HAL_DMA2D_IRQHandler() - by reading status registers - only once
              • -
            • Update - HAL_DMA2D_ProgramLineEvent() - function to:
              • -
                -
              • Return HAL - error state in case of wrong - line value
                • -
              • Enable line - interrupt after setting the - line watermark configuration
                • -
              -
            • Add new - HAL_DMA2D_CLUTLoad() - and HAL_DMA2D_CLUTLoad_IT() functions - - - - - to start DMA2D CLUT loading
              • -
                -
              • HAL_DMA2D_CLUTLoading_Abort() - function to abort the DMA2D - CLUT loading
                • -
              • HAL_DMA2D_CLUTLoading_Suspend() - function to suspend the - DMA2D CLUT loading
                • -
              • HAL_DMA2D_CLUTLoading_Resume() - function to resume the DMA2D - CLUT loading
                • -
              -
            • Add new DMA2D - dead time management:
              • -
                -
              • HAL_DMA2D_EnableDeadTime() - function to enable DMA2D - dead time feature
                • -
              • HAL_DMA2D_DisableDeadTime() - function to disable DMA2D - dead time feature
                • -
              • HAL_DMA2D_ConfigDeadTime() - function to configure dead - time
                • -
              -
            • Update the - name of DMA2D Input/Output - color mode defines to be more - - - - clear for - user (DMA2D_INPUT_XXX for - input layers Colors, - DMA2D_OUTPUT_XXX for output - framebuffer Colors)
              • -
            -
          -
            -
          • HAL - - - - LTDC update
            • -
          -
            -
              -
            • Update HAL_LTDC_IRQHandler() - to manage the case of reload - interrupt
              • -
            • Add new - callback API HAL_LTDC_ReloadEventCallback()
              • -
            • Add HAL_LTDC_Reload() - to configure LTDC reload - feature
              • -
            • Add new No - Reload LTDC variant APIs
              • -
                -
              • HAL_LTDC_ConfigLayer_NoReload() to - configure the LTDC Layer - according to the specified - without reloading
                • -
              • HAL_LTDC_SetWindowSize_NoReload() to set - the LTDC window size without - reloading
                • -
              • HAL_LTDC_SetWindowPosition_NoReload() to set - the LTDC window position - without reloading
                • -
              • HAL_LTDC_SetPixelFormat_NoReload() to - reconfigure the pixel format - without reloading
                • -
              • HAL_LTDC_SetAlpha_NoReload() to - reconfigure the layer alpha - value without reloading
                • -
              • HAL_LTDC_SetAddress_NoReload() to - reconfigure the frame buffer - Address without reloading
                • -
              • HAL_LTDC_SetPitch_NoReload() to - reconfigure the pitch for - specific cases
                • -
              • HAL_LTDC_ConfigColorKeying_NoReload() to - configure the color keying - without reloading
                • -
              • HAL_LTDC_EnableColorKeying_NoReload() to enable - the color keying without - reloading
                • -
              • HAL_LTDC_DisableColorKeying_NoReload() to - disable the color keying - without reloading
                • -
              • HAL_LTDC_EnableCLUT_NoReload() to enable - the color lookup table - without reloading
                • -
              • HAL_LTDC_DisableCLUT_NoReload() to - disable the color lookup - table without reloading
                • -
              • Note: Variant - functions with �_NoReload� - post fix allows to set the - LTDC configuration/settings - without immediate reload. - This is useful in case when - the program requires to - modify several LTDC settings - (on one or both layers) then - applying (reload) these - settings in one shot by - calling the function �HAL_LTDC_Reload�
                • -
              -
            -
          • HAL - - - - RTC update 
            • -
              -
            • Add new - timeout implementation based - on cpu - cycles - for ALRAWF, ALRBWF - and WUTWF flags
              • -
            -
          -
            -
          • HAL - - - - SAI update
            • -
              -
            • Update SAI - state in case of TIMEOUT error - within the HAL_SAI_Transmit() - / HAL_SAI_Receive()
              • -
            • Update HAL_SAI_IRQHandler:
              • -
                -
              • Add error - management in case DMA - errors through XferAbortCallback() - and HAL_DMA_Abort_IT()
                • -
              • Add error - management in case of IT
                • -
              -
            • Move SAI_BlockSynchroConfig() - and SAI_GetInputClock() - - - - - functions to - stm32f4xx_hal_sai.c/.h files - (extension files are kept - empty for projects - compatibility reason)
              • -
            -
          -
            -
          • HAL - - - - DCMI update
            • -
              -
            • Rename DCMI_DMAConvCplt - to DCMI_DMAXferCplt
              • -
            • Update HAL_DCMI_Start_DMA() - function to Enable the - DCMI peripheral
              • -
            • Add new - timeout implementation based - on cpu - cycles for DCMI stop
              • -
            • Add HAL_DCMI_Suspend() - function to suspend DCMI - capture
              • -
            • Add HAL_DCMI_Resume() - function to resume capture - after DCMI suspend
              • -
            • Update lock - mechanism for DCMI process
              • -
            • Update HAL_DCMI_IRQHandler() - function to:
              • -
                -
              • Add error - management in case DMA - errors through XferAbortCallback() - and HAL_DMA_Abort_IT()
                • -
              • Optimize - code by using direct - register read
                • -
              -
            -
          -
            -
          • HAL - - - - DMA - update
            • -
              -
            • Add new APIs - HAL_DMA_RegisterCallback() - and HAL_DMA_UnRegisterCallback - to register/unregister the - different callbacks identified - by the enum - typedef HAL_DMA_CallbackIDTypeDef
              • -
            • Add new API HAL_DMA_Abort_IT() - to abort DMA transfer under - interrupt context
              • -
                -
              • The new - registered Abort callback is - called when DMA transfer - abortion is completed
                • -
              -
            • Add the check - of compatibility between FIFO - threshold level and size of - the memory burst in the HAL_DMA_Init() - API
              • -
            • Add new Error - Codes: HAL_DMA_ERROR_PARAM, - HAL_DMA_ERROR_NO_XFER and - HAL_DMA_ERROR_NOT_SUPPORTED
              • -
            • Remove all - DMA states related to - MEM0/MEM1 in HAL_DMA_StateTypeDef
              • -
            -
          • HAL - - - - IWDG - update
            • -
              -
            • Overall - rework of the driver for a - more - efficient implementation
              • -
                -
              • Remove the - following APIs:
                • -
                  -
                • HAL_IWDG_Start()
                  • -
                • HAL_IWDG_MspInit()
                  • -
                • HAL_IWDG_GetState()
                  • -
                -
              • Update - implementation:
                • -
                  -
                • HAL_IWDG_Init(): this - function insures the - configuration and the - start of the IWDG counter
                  • -
                • HAL_IWDG_Refresh(): this - function insures the - reload of the IWDG counter
                  • -
                -
              • Refer to - the following example to - identify the changes: IWDG_Example
                • -
              -
            -
          • HAL - - - - LPTIM - update
            • -
              -
            • Update HAL_LPTIM_TimeOut_Start_IT() - and HAL_LPTIM_Counter_Start_IT( - ) APIs to configure WakeUp - Timer EXTI interrupt to be - able to wakeup - MCU from low power mode by - pressing the EXTI line.
              • -
            • Update HAL_LPTIM_TimeOut_Stop_IT() - and HAL_LPTIM_Counter_Stop_IT( - ) APIs to disable WakeUp - Timer EXTI interrupt. 
              • -
            -
          • HAL - - - - NOR update
            • -
              -
            • Update - NOR_ADDR_SHIFT macro implementation
              • -
            -
          • HAL - - - - PCD update
            • -
              -
            • Update HAL_PCD_IRQHandler() - to get HCLK frequency before - setting TRDT value
              • -
            -
          • HAL - - - - QSPI - update
            • -
          -
            -
              -
            • Update to - manage QSPI error management - during DMA process
              • -
            • Improve the - DMA transmit process by using - QSPI TC interrupt instead of - waiting loop on TC flag under - DMA ISR
              • -
            • These two - improvements require the - following updates on user - application:
              • -
                -
              • Configure - and enable the QSPI IRQ in HAL_QSPI_MspInit() - function
                • -
              • In - stm32f4xx_it.c file, QSPI_IRQHandler() - function: add a call to HAL_QSPI_IRQHandler() - - - - function
                • -
              • Add and - customize the Error Callback - API: HAL_QSPI_ErrorCallback()
                • -
              -
            • Add the - management of non-blocking - transfer abort service: HAL_QSPI_Abort_IT(). - - - - - In this case the user must:
              • -
                -
              • Add new - callback HAL_QSPI_AbortCpltCallback() - to inform user at the end of - abort process
                • -
              • A new value - of State in the HAL_QSPI_StateTypeDef - provides the current state - during the abort phase
                • -
              -
            • Polling - management update:
              • -
                -
              • The Timeout - value user must be estimated - for the overall process - duration: the - Timeout measurement is - cumulative. 
                • -
              -
            • Refer to the - following examples, which - describe the changes:
              • -
                -
              • QSPI_ReadWrite_DMA
                • -
              • QSPI_MemoryMapped
                • -
              • QSPI_ExecuteInPlace
                • -
              -
            -
          -
            -
              -
            • Add two new - APIs for the QSPI fifo - threshold:
              • -
                -
              • HAL_QSPI_SetFifoThreshold(): - configure the FIFO threshold - of the QSPI
                • -
              • HAL_QSPI_GetFifoThreshold(): give the - current FIFO threshold
                • -
              -
            • Fix wrong - data size management in HAL_QSPI_Receive_DMA()
              • -
            -
          -
            -
          • HAL - - - - ADC update
            • -
              -
            • Add new - __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() - macro for STM32F42x and - STM32F43x devices to - provide the possibility - to convert VrefInt - channel when both VrefInt - and Vbat - channels are selected.
              • -
            -
          • HAL - - - - SPDIFRX update
            • -
              -
            • Overall driver - update for wait on flag - management optimization 
              • -
            -
          • HAL - - - - WWDG update 
            • -
              -
            • Overall - rework of the driver for more - efficient implementation
              • -
                -
              • Remove the - following APIs:
                • -
                  -
                • HAL_WWDG_Start()
                  • -
                • HAL_WWDG_Start_IT()
                  • -
                • HAL_WWDG_MspDeInit()
                  • -
                • HAL_WWDG_GetState()
                  • -
                -
              • Update - implementation:
                • -
                  -
                • HAL_WWDG_Init()
                  • -
                    -
                  • A new - - - - parameter in the Init - Structure: EWIMode
                    • -
                  -
                • HAL_WWDG_MspInit()
                  • -
                • HAL_WWDG_Refresh() 
                  • -
                    -
                  • This - function insures the - reload of the counter
                    • -
                  • The - "counter" parameter has - been removed
                    • -
                  -
                • HAL_WWDG_IRQHandler()
                  • -
                • HAL_WWDG_EarlyWakeupCallback() is the - new prototype of HAL_WWDG_WakeUpCallback()
                  • -
                -
              -
            • Refer to the - following example to identify - the changes: WWDG_Example
              • -
            -
          -

          V1.4.4 - - - - / 22-January-2016

          -

          Main Changes

          -
            -
          • HAL - - - - Generic update
            • -
              -
            • stm32f4xx_hal_conf_template.h
              • -
                -
              • Optimize - HSE Startup Timeout value - from 5000ms to 100 ms
                • -
              • Add new - define LSE_STARTUP_TIMEOUT
                • -
              • Add new - define USE_SPI_CRC for code - cleanup when the CRC - calculation is disabled.
                • -
              -
            • Update HAL - drivers to support MISRA C - 2004 rule 10.6
              • -
            • Add new - template driver to - configure timebase - using TIMER :
              • -
                -
              • stm32f4xx_hal_timebase_tim_template.c
                • -
              -
            -
          -
            -
          • HAL - - - - CAN update
            • -
              -
            • Update HAL_CAN_Transmit() - and HAL_CAN_Transmit_IT() - - - - - functions to unlock - process when all Mailboxes are - busy
              • -
            -
          -
            -
          • HAL - - - - DSI update
            • -
              -
            • Update HAL_DSI_SetPHYTimings() - functions to use the correct - mask
              • -
            -
          • HAL - - - - UART update
            • -
              -
            • Several - update on HAL UART driver to - implement the new UART state - machine: 
              • -
                -
              • Add new - field in UART_HandleTypeDef - structure: "rxState", - - - - - UART state information - related to Rx Operations
                • -
              • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": - - - - UART state information - related to global Handle - management and Tx Operations
                • -
              • Update UART - process to manage the new - UART states.
                • -
              • Update - __HAL_UART_RESET_HANDLE_STATE() - macro to handle the new UART - state parameters (gState, - rxState)
                • -
              -
            • Update - UART_BRR_SAMPLING16() and - UART_BRR_SAMPLING8() Macros to - fix wrong baudrate - calculation.
              • -
            -
          -
            -
          • HAL - - - - IRDA update
            • -
              -
            • Several - update on HAL IRDA driver to - implement the new UART state - machine: 
              • -
                -
              • Add new - field in IRDA_HandleTypeDef - structure: "rxState", - - - - - IRDA state information - related to Rx Operations
                • -
              • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": - - - - IRDA state information - related to global Handle - management and Tx Operations
                • -
              • Update IRDA - process to manage the new - UART states.
                • -
              • Update - __HAL_IRDA_RESET_HANDLE_STATE() - macro to handle the new IRDA - state parameters (gState, - rxState)
                • -
              -
            • Removal of - IRDA_TIMEOUT_VALUE define
              • -
            • Update IRDA_BRR() - Macro to fix wrong baudrate - calculation
              • -
            -
          • HAL - - - - SMARTCARD update
            • -
              -
            • Several - update on HAL SMARTCARD driver - to implement the new UART - state machine: 
              • -
                -
              • Add new - field in SMARTCARD_HandleTypeDef - structure: "rxState", - - - - - SMARTCARDstate - information related to Rx Operations
                • -
              • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": - - - - SMARTCARDstate - information related to - global Handle management and - Tx Operations
                • -
              • Update SMARTCARD - - - - - process to manage the new - UART states.
                • -
              • Update - __HAL_SMARTCARD_RESET_HANDLE_STATE() - macro to handle the - new SMARTCARD state - parameters (gState, - rxState)
                • -
              -
            • Update - SMARTCARD_BRR() - macro to fix wrong baudrate - calculation
              • -
            -
          -
            -
          • HAL  - RCC - update
            • -
              -
            • Add new - default define value for HSI - calibration - "RCC_HSICALIBRATION_DEFAULT"
              • -
            • Optimize - Internal oscillators and PLL - startup timeout 
              • -
            • Update to - avoid the disable for HSE/LSE - oscillators before setting the - new RCC HSE/LSE configuration - and add the following notes in - HAL_RCC_OscConfig() - API description:
              • -
            -
          -

               - - - -       -     -     -     -       * - @note   Transitions LSE - Bypass to LSE On and LSE On to LSE - Bypass are not
          -               - - - - -     -     -     -     -     -      - *         -     supported by this - API. User should request a - transition to LSE Off
          -               - - - - -     -     -     -     -     -      - *         -     first and then LSE - On or LSE Bypass.
          -               - - - - -     -     -     -     -     -      * - @note   Transition HSE - Bypass to HSE On and HSE On to HSE - Bypass are not
          -               - - - - -     -     -     -     -     -      - *         -     supported by this - API. User should request a - transition to HSE Off
          -               - - - - -     -     -     -         -      - *         -     first and then HSE - On or HSE Bypass.

          -
            -
              -
            • Optimize - the HAL_RCC_ClockConfig() - API implementation.
              • -
            -
          -
            -
          • HAL - - - - DMA2D update
            • -
              -
            • Update - HAL_DMA2D_Abort() - Function to end current DMA2D - transfer properly
              • -
            • Update - HAL_DMA2D_PollForTransfer() - function to add poll for - background CLUT loading (layer - 0 and layer 1).
              • -
            • Update - HAL_DMA2D_PollForTransfer() - to set the corresponding ErrorCode - in case of error occurrence
              • -
            • Update - HAL_DMA2D_ConfigCLUT() - function to fix wrong CLUT - size and color mode settings
              • -
            • Removal of - useless macro __HAL_DMA2D_DISABLE()
              • -
            • Update - HAL_DMA2D_Suspend() - to manage correctly the case - where no transfer is on going
              • -
            • Update - HAL_DMA2D_Resume() to - - - - - manage correctly the case - where no transfer is on going
              • -
            • Update - HAL_DMA2D_Start_IT() - to enable all required - interrupts before enabling the - transfer.
              • -
            • Add - HAL_DMA2D_CLUTLoad_IT() - Function to allow loading a - CLUT with interruption model.
              • -
            •  Update - HAL_DMA2D_IRQHandler() - to manage the following - cases :
              -
              -
              • -
                -
              • CLUT - transfer complete
                • -
              • CLUT access - error
                • -
              • Transfer - watermark reached
                • -
              -
            • Add new - Callback APIs:
              • -
                -
              •  HAL_DMA2D_LineEventCallback() - to signal a transfer - watermark reached event
                • -
              •  HAL_DMA2D_CLUTLoadingCpltCallback() - to signal a CLUT loading - complete event
                • -
              -
            -
          -
            -
              -
            • Miscellaneous - Improvement:
              • -
                -
              • Add - "HAL_DMA2D_ERROR_CAE" new - define for CLUT Access error - management.
                • -
              • Add     �assert_param� - used for parameters check is - now done on the top of the - exported functions : before - locking the process using - __HAL_LOCK
                • -
              -
            -
          -

           

          -
            -
          • HAL - - - - I2C update
            • -
              -
            • Add support - of I2C repeated start feature:
              • -
                -
              • With the - following new API's
                • -
                  -
                • HAL_I2C_Master_Sequential_Transmit_IT()
                  • -
                • HAL_I2C_Master_Sequential_Receive_IT()
                  • -
                • HAL_I2C_Master_Abort_IT()
                  • -
                • HAL_I2C_Slave_Sequential_Transmit_IT()
                  • -
                • HAL_I2C_Slave_Sequential_Receive_IT()
                  • -
                • HAL_I2C_EnableListen_IT()
                  • -
                • HAL_I2C_DisableListen_IT()
                  • -
                -
              • Add new - user callbacks:
                • -
                  -
                • HAL_I2C_ListenCpltCallback()
                  • -
                • HAL_I2C_AddrCallback()
                  • -
                -
              -
            • Update to - generate STOP condition when a - acknowledge failure error is detected
              • -
            • Several - update on HAL I2C driver to - implement the new I2C state - machine: 
              • -
                -
              • Add new API - to get the I2C mode: - HAL_I2C_GetMode()
                • -
              • Update I2C - process to manage the new - I2C states.
                • -
              -
            • Fix wrong behaviour - in single byte transmission 
              • -
            • Update I2C_WaitOnFlagUntilTimeout() to - - - - - manage the NACK feature.
              • -
            • Update  I2C - transmission process to - support the case data size - equal 0
              • -
            -
          -
            -
          • HAL - - - - FMPI2C update
            • -
              -
            • Add support - of FMPI2C repeated start - feature:
              • -
                -
              • With the - following new API's
                • -
                  -
                • HAL_FMPI2C_Master_Sequential_Transmit_IT()
                  • -
                • HAL_FMPI2C_Master_Sequential_Receive_IT()
                  • -
                • HAL_FMPI2C_Master_Abort_IT()
                  • -
                • HAL_FMPI2C_Slave_Sequential_Transmit_IT()
                  • -
                • HAL_FMPI2C_Slave_Sequential_Receive_IT()
                  • -
                • HAL_FMPI2C_EnableListen_IT()
                  • -
                • HAL_FMPI2C_DisableListen_IT()
                  • -
                -
              • Add new - user callbacks:
                • -
                  -
                • HAL_FMPI2C_ListenCpltCallback()
                  • -
                • HAL_FMPI2C_AddrCallback()
                  • -
                -
              -
            • Several - update on HAL I2C driver to - implement the new I2C state - machine: 
              • -
                -
              • Add new API - to get the FMPI2C mode: - HAL_FMPI2C_GetMode()
                • -
              • Update - FMPI2C process to manage the - new FMPI2C states.
                • -
              -
            -
          -
            -
          • HAL - - - - SPI update
            • -
              -
            • Major Update - to improve performance in - polling/interrupt mode to - reach max frequency:
              • -
                -
              • Polling mode - - - - :
                • -
                  -
                • Replace - use of SPI_WaitOnFlagUnitTimeout() - funnction - by "if" statement to check - on RXNE/TXE flage - while transferring data.
                  • -
                • Use API - data pointer instead of - SPI handle data pointer.
                  • -
                • Use a Goto - implementation instead of - "if..else" - statements.
                  • -
                -
              -
            -
          -
            -
              -
                -
              • Interrupt - mode
                • -
                  -
                • Minimize - access on SPI registers.
                  • -
                • Split the - SPI modes into dedicated - static functions to - minimize checking - statements under HAL_IRQHandler():
                  • -
                    -
                  • 1lines/2lines - - - - modes
                    • -
                  • 8 bit/ - 16 bits data formats
                    • -
                  • CRC - calculation - enabled/disabled.
                    • -
                  -
                • Remove - waiting loop under ISR - when closing - - - -  the - communication.
                  • -
                -
              • All - modes:  
                • -
                  -
                • Adding - switch USE_SPI_CRC to - minimize number of - statements when CRC - calculation is disabled.
                  • -
                • Update - Timeout management to - check on global process.
                  • -
                • Update - Error code management in - all processes.
                  • -
                -
              -
            • Add note to - the max frequencies reached in - all modes.
              • -
            • Add note - about Master Receive mode restrictions :
              • -
                -
              • Master - - - - Receive mode restriction:
                -       - (#) In Master - unidirectional receive-only - mode (MSTR =1, BIDIMODE=0, - RXONLY=0) or
                -           - - - - - bidirectional receive mode - (MSTR=1, BIDIMODE=1, - BIDIOE=0), to ensure that - the SPI
                -           - - - - does not initiate a new - transfer the following - procedure has to be - respected:
                -           - - - - (##) HAL_SPI_DeInit()
                -           - - - - (##) HAL_SPI_Init() - - - -
                • -
              -
            -
          -
            -
          • HAL - - - - SAI update
            • -
              -
            • Update for - proper management of the - external synchronization input - selection
              • -
                -
              • update - of HAL_SAI_Init - () funciton
                • -
              • update - definition of SAI_Block_SyncExt - and SAI_Block_Synchronization - groups
                • -
              -
            • Update - SAI_SLOTACTIVE_X -  defines - values
              • -
            • Update HAL_SAI_Init() - function for proper companding - mode management
              • -
            • Update SAI_Transmit_ITxxBit() - functions to add the check on - transfer counter before - writing new data to SAIx_DR - registers
              • -
            • Update SAI_FillFifo() - function to avoid issue when - the number of data to transmit - is smaller than the FIFO size
              • -
            • Update HAL_SAI_EnableRxMuteMode() - function for proper mute - management
              • -
            • Update SAI_InitPCM() - function to support 24bits - configuration
              • -
            -
          • HAL - - - - ETH update
            • -
              -
            • Removal of - ETH MAC debug register defines
              • -
            -
          • HAL - - - - FLASH update
            • -
              -
            • Update FLASH_MassErase() - function to apply correctly - voltage range parameter
              • -
            -
          • HAL - - - - I2S update
            • -
              -
            • Update I2S_DMATxCplt() - and I2S_DMARxCplt() to manage - properly FullDuplex - mode without any risk of - missing data.
              • -
            -
          • LL - - - - FMC update
            • -
              -
            • Update the FMC_NORSRAM_Init() - function to use BurstAccessMode - field properly
              • -
            -
          • LL - - - - FSMC  - - - - update
            • -
              -
            • Update the FSMC_NORSRAM_Init() - function to use BurstAccessMode - field properly
              • -
            -
          -


          -
          -

          -

          V1.4.4 - / 11-December-2015

          -

          Main Changes

          -
            -
          • HAL - - - - Generic update
            • -
              -
            • Update HAL - weak empty callbacks to - prevent unused argument - compilation warnings with some - compilers by calling the - following line:
              • -
                -
              • UNUSED(hppp);
                • -
              -
            • STM32Fxxx_User_Manual.chm - - - - - files regenerated for HAL - V1.4.3
              • -
            -
          • HAL - - - - ETH update 
            • -
              -
            • Update HAL_ETH_Init() - function to add timeout on the - Software reset management
              • -
            -
          -

          V1.4.2 - - - - / 10-November-2015

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • One - - - - change done on the HAL CRYP - requires an update on the - application code based on HAL - V1.4.1
            • -
              -
            • Update HAL_CRYP_DESECB_Decrypt() - API to invert pPlainData - and pCypherData - parameters
              • -
            -
          • HAL - - - - generic - update
            • -
              -
            • Update HAL - weak empty callbacks to - prevent unused argument - compilation warnings with some - compilers by calling the - following line:
              • -
                -
              • UNUSED(hppp);
                • -
              -
            -
          -
            -
          • HAL - - - - CORTEX update
            • -
              -
            • Remove - duplication for - __HAL_CORTEX_SYSTICKCLK_CONFIG() - macro
              • -
            -
          -
            -
          • HAL - - - - HASH update
            • -
              -
            • Rename HAL_HASH_STATETypeDef - to HAL_HASH_StateTypeDef
              • -
            • Rename HAL_HASH_PhaseTypeDef - to HAL_HASH_PhaseTypeDef
              • -
            -
          • HAL - - - - RCC update
            • -
              -
            • Add new - macros __HAL_RCC_PPP_IS_CLK_ENABLED() - to check on Clock - enable/disable status
              • -
            • Update - __HAL_RCC_USB_OTG_FS_CLK_DISABLE() - macro to remove the disable - for the SYSCFG
              • -
            • Update HAL_RCC_MCOConfig() - API to use new defines for the - GPIO Speed
              • -
            • Generic - update to improve the - PLL VCO min - value(100MHz): PLLN, PLLI2S - and PLLSAI min value is 50 - instead of 192
              • -
            -
          • HAL - - - - FLASH update
            • -
              -
            • __HAL_FLASH_INSTRUCTION_CACHE_RESET() - macro: update to reset -  ICRST bit in - the ACR register after - setting it.
              • -
            • Update to - support until 15 FLASH wait - state (FLASH_LATENCY_15) for - STM32F446xx devices -
              • -
            -
          -

          �  - - - - - HAL CRYP update

          -
            -
              -
            • Update HAL_CRYP_DESECB_Decrypt() - API to fix the inverted pPlainData - and pCypherData - parameters issue
              • -
            -
          • HAL - - - - I2S update
            • -
              -
            • Update - HAL_I2S_Init() - API to call - __HAL_RCC_I2S_CONFIG() macro - when external I2S clock is - selected
              • -
            -
          • HAL - - - - LTDC update
            • -
              -
            • Update HAL_LTDC_SetWindowPosition() - API to configure - Immediate reload register - instead of vertical blanking - reload register.
              • -
            -
          • HAL - - - - TIM update
            • -
              -
            • Update HAL_TIM_ConfigClockSource() - API to check only the - required parameters
              • -
            -
          • HAL - - - - NAND update
            • -
              -
            • Update - HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() - APIs to manage correctly the - NAND Page access
              • -
            -
          • HAL - - - - CAN update
            • -
              -
            • Update to use - "=" instead of "|=" to clear - flags in the MSR, TSR, RF0R - and RF1R registers
              • -
            -
          • HAL - - - - HCD update
            • -
              -
            • Fix typo in - __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() - macro implementation
              • -
            -
          • HAL - - - - PCD update
            • -
              -
            • Update HAL_PCD_IRQHandler() - API to avoid issue - when DMA mode enabled for - Status Phase IN stage
              • -
            -
          • LL - - - - FMC update
            • -
              -
            • Update the FMC_NORSRAM_Extended_Timing_Init() - API to remove the check - on CLKDIvison - and DataLatency - parameters
              • -
            • Update the FMC_NORSRAM_Init() - API to add a check on the PageSize - parameter for STM32F42/43xx - devices
              • -
            -
          • LL - - - - FSMC update
            • -
              -
            • Update the FSMC_NORSRAM_Extended_Timing_Init() - API to remove the check - on CLKDIvison - and DataLatency - parameters
              • -
            -
          -

          V1.4.1 - - - - / 09-October-2015

          -

          Main Changes

          -
            -
          • HAL - - - - DSI update
            • -
              -
            • Update TCCR - register assigned value - in HAL_DSI_ConfigHostTimeouts() - function
              • -
            • Update WPCR - register assigned value - in HAL_DSI_Init(), - - - - - HAL_DSI_SetSlewRateAndDelayTuning(), - - - - - HAL_DSI_SetSlewRateAndDelayTuning(), - - - - - HAL_DSI_SetLowPowerRXFilter() - - - - - / HAL_DSI_SetSDD(), - - - - - HAL_DSI_SetLanePinsConfiguration(), - - - - - HAL_DSI_SetPHYTimings(), - - - - - HAL_DSI_ForceTXStopMode(), - - - - - HAL_DSI_ForceRXLowPower(), - - - - - HAL_DSI_ForceDataLanesInRX(), - - - - - HAL_DSI_SetPullDown() - - - - - and HAL_DSI_SetContentionDetectionOff() - - - - - functions
              • -
            • Update - DSI_HS_PM_ENABLE define value
              • -
            • Implement - workaround for the hardware - limitation: �The time to - activate the clock between HS - transmissions is not - calculated correctly�
              • -
            -
          -

          V1.4.0 - - - - / 14-August-2015

          -

          Main Changes

          -
            -
          • Add - support of STM32F469xx, STM32F479xx, - STM32F410Cx, STM32F410Rx - and STM32F410Tx  - devices
            • -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • Add - new HAL drivers for DSI and LPTIM - - - - - peripherals
            • -
          -
            -
          • HAL - - - - ADC update
            • -
              -
            • Rename - ADC_CLOCKPRESCALER_PCLK_DIV2 - define to - ADC_CLOCK_SYNC_PCLK_DIV2
              • -
            • Rename - ADC_CLOCKPRESCALER_PCLK_DIV4 - define to - ADC_CLOCK_SYNC_PCLK_DIV4
              • -
            • Rename - ADC_CLOCKPRESCALER_PCLK_DIV6 - define to - ADC_CLOCK_SYNC_PCLK_DIV6
              • -
            • Rename - ADC_CLOCKPRESCALER_PCLK_DIV8 - define to - ADC_CLOCK_SYNC_PCLK_DIV8
              • -
            -
          • HAL - - - - CORTEX update
            • -
              -
            • Add specific - API for MPU management
              • -
                -
              • add MPU_Region_InitTypeDef - structure
                • -
              • add new - function HAL_MPU_ConfigRegion()
                • -
              -
            -
          • HAL - - - - DMA update
            • -
              -
            • Overall driver - update for code optimization
              • -
                -
              • add StreamBaseAddress - and StreamIndex - new fields in the DMA_HandleTypeDef - structure
                • -
              • add DMA_Base_Registers - private structure
                • -
              • add static - function DMA_CalcBaseAndBitshift()
                • -
              • update HAL_DMA_Init() - function to use the new - added static function
                • -
              • update HAL_DMA_DeInit() - function to optimize clear - flag operations
                • -
              • update HAL_DMA_Start_IT() - function to optimize - interrupts enable
                • -
              • update HAL_DMA_PollForTransfer() - function to optimize check - on flags
                • -
              • update HAL_DMA_IRQHandler() - function to optimize - interrupt flag management
                • -
              -
            -
          • HAL - - - - FLASH update
            • -
              -
            • update HAL_FLASH_Program_IT() - function by removing the - pending flag clear
              • -
            • update HAL_FLASH_IRQHandler() - function to improve erase - operation procedure
              • -
            • update FLASH_WaitForLastOperation() - function by checking on end of - operation flag
              • -
            -
          • HAL - - - - GPIO update
            • -
              -
            • Rename - GPIO_SPEED_LOW define to - GPIO_SPEED_FREQ_LOW
              • -
            • Rename - GPIO_SPEED_MEDIUM define to - GPIO_SPEED_FREQ_MEDIUM
              • -
            • Rename - GPIO_SPEED_FAST define to - GPIO_SPEED_FREQ_HIGH
              • -
            • Rename - GPIO_SPEED_HIGH define to - GPIO_SPEED_FREQ_VERY_HIGH
              • -
            -
          • HAL - - - - I2S update
            • -
              -
            • Move - I2S_Clock_Source defines to - extension file to properly add - the support of STM32F410xx devices
              • -
            -
          • HAL - - - - LTDC update
            • -
              -
            • rename HAL_LTDC_LineEvenCallback() - function to HAL_LTDC_LineEventCallback()
              • -
            • add new - function HAL_LTDC_SetPitch()
              • -
            • add new - functions HAL_LTDC_StructInitFromVideoConfig() - and HAL_LTDC_StructInitFromAdaptedCommandConfig() - - - - - applicable only to STM32F469xx - and STM32F479xx devices
              • -
            -
          • HAL - - - - PWR update
            • -
              -
            • move - __HAL_PWR_VOLTAGESCALING_CONFIG() - macro to extension file
              • -
            • move - PWR_WAKEUP_PIN2 define to - extension file
              • -
            • add - PWR_WAKEUP_PIN3 define, - applicable only to STM32F10xx - devices
              • -
            • add new - functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() - and HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), - - - - - applicable only to STM32F469xx - and STM32F479xx devices
              • -
            -
          -
            -
          • HAL - - - - RTC update
            • -
              -
            • Update HAL_RTCEx_SetWakeUpTimer() - and HAL_RTCEx_SetWakeUpTimer_IT() - - - - - functions to properly check on - the WUTWF flag
              • -
            -
          • HAL - - - - TIM update
            • -
              -
            • add new - defines TIM_SYSTEMBREAKINPUT_HARDFAULT,  - - - - TIM_SYSTEMBREAKINPUT_PVD - - - - - and - TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, - applicable only to STM32F410xx - devices
              • -
            -
          -

          V1.3.2 - - - - / 26-June-2015

          -

          Main Changes

          -
            -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • One - - - - changes - done on the HAL may require an - update on the application code - based on HAL V1.3.1
            • -
              -
            • HASH IT - process: update to call the HAL_HASH_InCpltCallback() - at the end of the complete - buffer instead of every each - 512 bits
              • -
            -
          -
            -
          • HAL - - - - RCC update
            • -
              -
            • HAL_RCCEx_PeriphCLKConfig() updates:
              • -
                -
              • Update the - LSE check condition after - backup domain reset: - update to check LSE - ready flag when LSE - oscillator is already - enabled instead of check on - LSE oscillator only when LSE - is used as RTC clock source
                • -
              • Use the - right macro to check the - PLLI2SQ parameters -
                • -
              -
            -
          -
            -
          • HAL - - - - RTC update
            • -
              -
            • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() - macro: fix implementation - issue
              • -
            • __HAL_RTC_ALARM_GET_IT(), - - - - - __HAL_RTC_ALARM_CLEAR_FLAG(), - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), - - - - - __HAL_RTC_TIMESTAMP_CLEAR_FLAG() - - - - and - __HAL_RTC_TAMPER_CLEAR_FLAG() - macros implementation changed: - remove unused cast
              • -
            • IS_RTC_TAMPER() - macro: update to use literal - instead of hardcoded - value 
              • -
            • Add new - parameter SecondFraction - in RTC_TimeTypeDef - structure
              • -
            • HAL_RTC_GetTime() API update - to support the new - parameter SecondFraction -
              • -
            -
          • HAL - - - - ADC update
            • -
              -
            • Add new - literal: - ADC_INJECTED_SOFTWARE_START to - be used as possible value for - the ExternalTrigInjecConvEdge - parameter in the ADC_InitTypeDef - structure to select the ADC - software trigger mode.
              • -
            -
          • HAL - - - - FLASH update
            • -
              -
            • FLASH_OB_GetRDP() API update - to return uint8_t instead of FlagStatus
              • -
            •  __HAL_FLASH_GET_LATENCY() - new macro add to get the flash - latency
              • -
            -
          • HAL - - - - SPI update
            • -
              -
            • Fix the wrong - definition of - HAL_SPI_ERROR_FLAG literal
              • -
            -
          • HAL - - - - I2S update
            • -
              -
            • HAL_I2S_Transmit() - API update to check on busy - flag only for I2S slave mode
              • -
            -
          • HAL - - - - CRC update
            • -
              -
            • __HAL_CRC_SET_IDR() - macro implementation change to - use WRITE_REG() instead of - MODIFY_REG()
              • -
            -
          • HAL - - - - DMA2D update
            • -
              -
            • HAL_DMA2D_ConfigLayer() - API update to use "=" instead - of "|=" to erase BGCOLR and - FGCOLR registers before - setting the new configuration
              • -
            -
          • HAL - - - - HASH update
            • -
              -
            • HAL_HASH_MODE_Start_IT() (MODE - - - - stands for MD5, SHA1, - SHA224 and SHA36) updates:
              • -
                -
              • Fix processing - - - - - fail for small input buffers
                • -
              • Update to - unlock the process and - call return - HAL_OK at the end of - HASH processing to avoid - incorrectly repeating software
                • -
              • Update to - properly manage the HashITCounter
                • -
              • Update to - call the HAL_HASH_InCpltCallback() - at the end of the complete - buffer instead of every each - 512 bits
                • -
              -
            • __HAL_HASH_GET_FLAG() - update to  check the - right register when the DINNE - flag  is selected
              • -
            • HAL_HASH_SHA1_Accumulate() - updates:
              • -
                -
              • Add - a call to the new - IS_HASH_SHA1_BUFFER_SIZE() - macro to check the size - parameter. 
                • -
              • Add the - following note in API description
                • -
              -
            -
          -
          -

           * - - - - - @note  - - - - - Input buffer - size in bytes must be a multiple - of 4 otherwise the digest - computation is corrupted.

          -
          -
            -
          • HAL - - - - RTC update
            • -
              -
            • Update to - define hardware - independent literals names:
              • -
                -
              • Rename - RTC_TAMPERPIN_PC13 by - - - -  RTC_TAMPERPIN_DEFAULT
                • -
              • Rename - RTC_TAMPERPIN_PA0 by - RTC_TAMPERPIN_POS1
                • -
              • Rename - RTC_TAMPERPIN_PI8 by - RTC_TAMPERPIN_POS1
                • -
              • Rename - RTC_TIMESTAMPPIN_PC13 by - RTC_TIMESTAMPPIN_DEFAULT
                • -
              • Rename - RTC_TIMESTAMPPIN_PA0 by - RTC_TIMESTAMPPIN_POS1
                • -
              • Rename - RTC_TIMESTAMPPIN_PI8 by - RTC_TIMESTAMPPIN_POS1
                • -
              -
            -
          • HAL - - - - ETH update
            • -
              -
            • Remove - duplicated IS_ETH_DUPLEX_MODE() - and IS_ETH_RX_MODE() macros
              • -
            • Remove - illegal space - ETH_MAC_READCONTROLLER_FLUSHING - macro
              • -
            • Update - ETH_MAC_READCONTROLLER_XXX - defined values (XXX can be - IDLE, READING_DATA and - READING_STATUS)
              • -
            -
          • HAL - - - - PCD update
            • -
              -
            • HAL_PCD_IRQHandler API: fix the - bad Configuration of - Turnaround Time
              • -
            -
          • HAL - - - - HCD update
            • -
              -
            • Update to use - local variable in USB - Host channel re-activation
              • -
            -
          • LL - - - - FMC update
            • -
              -
            • FMC_SDRAM_SendCommand() API: remove - the following line: return - HAL_ERROR;
              • -
            -
          • LL - - - - USB update
            • -
              -
            • USB_FlushTxFifo API: - update to flush all Tx FIFO
              • -
            • Update to use - local variable in USB - Host channel re-activation
              • -
            -
          -

          V1.3.1 - - - - / 25-Mars-2015

          -

          Main Changes

          -
            -
          • HAL - - - - PWR update
            • -
              -
            • Fix - compilation issue with - STM32F417xx product: - update STM32F17xx - by STM32F417xx
              • -
            -
          • HAL - - - - SPI update
            • -
              -
            • Remove unused - variable to avoid warning with - TrueSTUDIO 
              • -
            -
          • HAL - - - - I2C update
            • -
              -
            • I2C - Polling/IT/DMA processes: move - the wait loop on busy - flag at the top of the - processes, to ensure that - software not perform any write - access to I2C_CR1 register - before hardware - clearing STOP bit and to - avoid - - - - - also the - waiting loop on BUSY flag - under I2C/DMA ISR.
              • -
            • Update busy - flag Timeout value
              • -
            • I2C Master - Receive Processes update to - disable ACK before generate - the STOP 
              • -
            -
          • HAL - - - - DAC update
            • -
              -
            • Fix V1.3.0 - regression issue with DAC - software trigger configuration
              • -
            -
          -

          V1.3.0 - - - - / 09-Mars-2015

          -

          Main Changes

          -
            -
          • Add - support of STM32F446xx devices
            • -
          • General - - - - updates to fix known defects and - enhancements implementation
            • -
          • Add - new HAL drivers for CEC, - QSPI, FMPI2C and SPDIFRX - - - - peripherals
            • -
          • Two - - - - changes done on the HAL - requires an update on the - application code based on HAL - V1.2.0
            • -
              -
            • Overall SAI - driver rework to have - exhaustive support of the - peripheral features: details - are provided in HAL SAI update - - - - section below --> Compatibility - - - - - with previous version is impacted
              • -
            • CRYP driver - updated to support multi instance,so - user must ensure that the - new parameter Instance is - initalized - in his application(CRYPHandle.Instance - = CRYP) 
              • -
            -
          -
            -
          • HAL - - - - Generic update
            • -
              -
            • stm32f4xx_hal_def.h
              • -
                -
              • Remove NULL - definition and add - include for stdio.h
                • -
              -
            • stm32_hal_legacy.h
              • -
                -
              • Update method - - - - to manage deference in - alias implementation between - all STM32 families
                • -
              -
            • stm32f4xx_hal_ppp.c
              • -
                -
              • HAL_PPP_Init(): update - to force the - HAL_PPP_STATE_RESET before - calling the HAL_PPP_MspInit()
                • -
              -
            -
          -
            -
          • HAL - - - - RCC update
            • -
              -
            • Add new - function HAL_RCCEx_GetPeriphCLKFreq()
              • -
            • Move RCC_PLLInitTypeDef - structure to extension file - and add the new PLLR field - specific to STM32F446xx devices
              • -
            • Move the - following functions to - extension file and add a - __weak attribute in generic driver - - - - : this - update is related to new - system clock source (PLL/PLLR) - added and only available for - STM32F44xx devices
              • -
                -
              • HAL_RCC_OscConfig()
                • -
              • HAL_RCC_GetSysClockFreq()
                • -
              • HAL_RCC_GetOscConfig()
                • -
              -
            • Move the - following macro to extension - file as they have device - dependent implementation
              • -
                -
              • __HAL_RCC_PLL_CONFIG()
                • -
              • __HAL_RCC_PLLI2S_CONFIG()
                • -
              • __HAL_RCC_I2S_CONFIG()
                • -
              -
            • Add new - structure RCC_PLLI2SInitTypeDef - containing new PLLI2S - division factors used only w/ - STM32F446xx devices
              • -
            • Add new - structure RCC_PLLSAIInitTypeDef - containing new PLLSAI - division factors used only w/ - STM32F446xx devices
              • -
            • Add new RCC_PeriphCLKInitTypeDef - to support the peripheral - source clock selection for (I2S, - - - - SAI, SDIO, FMPI2C, CEC, - SPDIFRX and CLK48)
              • -
            • Update the HAL_RCCEx_PeriphCLKConfig() - and HAL_RCCEx_GetPeriphCLKConfig() - - - - - functions to support the - new peripherals Clock source - selection
              • -
            • Add __HAL_RCC_PLL_CONFIG() - macro (the number of parameter - and the implementation depend - on the device part number)
              • -
            • Add __HAL_RCC_PLLI2S_CONFIG() - macro(the number of parameter - and the implementation depend - on device part number)
              • -
            • Update __HAL_RCC_PLLSAI_CONFIG() - macro to support new PLLSAI - factors (PLLSAIM and - PLLSAIP)
              • -
            • Add new - macros for clock - enable/Disable for the - following peripherals (CEC, - - - - SPDIFRX, SAI2, QUADSPI)
              • -
            • Add the - following new macros for clock - source selection - - - - :
              • -
                -
              • __HAL_RCC_SAI1_CONFIG() - / - __HAL_RCC_GET_SAI1_SOURCE()
                • -
              • __HAL_RCC_SAI2_CONFIG() - / - __HAL_RCC_GET_SAI2_SOURCE()
                • -
              • __HAL_RCC_I2S1_CONFIG() - / - __HAL_RCC_GET_I2S1_SOURCE()
                • -
              • __HAL_RCC_I2S2_CONFIG() - / - __HAL_RCC_GET_I2S2_SOURCE()
                • -
              • __HAL_RCC_CEC_CONFIG() - / - __HAL_RCC__GET_CEC_SOURCE() -
                • -
              • __HAL_RCC_FMPI2C1_CONFIG() - / - __HAL_RCC_GET_FMPI2C1_SOURCE() -
                • -
              • __HAL_RCC_SDIO_CONFIG() - / - __HAL_RCC_GET_SDIO_SOURCE() -
                • -
              • __HAL_RCC_CLK48_CONFIG() - / - __HAL_RCC_GET_CLK48_SOURCE() -
                • -
              • __HAL_RCC_SPDIFRXCLK_CONFIG() - / - __HAL_RCC_GET_SPDIFRX_SOURCE()
                • -
              -
            • __HAL_RCC_PPP_CLK_ENABLE(): - - - - - Implement workaround to cover - RCC limitation regarding - peripheral enable delay
              • -
            • HAL_RCC_OscConfig() fix - issues: 
              • -
                -
              • Add a check - on LSERDY flag when - LSE_BYPASS is selected as - new state for LSE - oscillator.
                • -
              -
            • Add - new possible value RCC_PERIPHCLK_PLLI2S - - - - to be selected as PeriphClockSelection - parameter in the - - - - -  RCC_PeriphCLKInitTypeDef - structure to allow the - possibility to output the - PLLI2S on MCO without - activating the I2S or the SAI.
              • -
            • __HAL_RCC_HSE_CONFIG() -  macro: add - the comment below:
              • -
            -
          -
          -

           * - - - - - @note   Transition - HSE Bypass to HSE On and HSE - On to HSE Bypass are not - supported by this macro.
          -  *         - - - - User should request a - transition to HSE Off first - and then HSE On or HSE Bypass.

          -
          -
            -
              -
            • __HAL_RCC_LSE_CONFIG()  macro: add - the comment below:
              • -
            -
          -
          -

            * - - - - - @note   Transition - LSE Bypass to LSE On and LSE - On to LSE Bypass are not - supported by this macro.
          -   - *         - User should request a - transition to LSE Off first - and then LSE On or LSE Bypass.

          -
          -
            -
              -
            • Add the - following new macros for - PLL source and PLLM selection - - - - :
              • -
                -
              • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
                • -
              • __HAL_RCC_PLL_PLLM_CONFIG()
                • -
              -
            • Macros - rename:
              • -
                -
              • HAL_RCC_OTGHS_FORCE_RESET() -by HAL_RCC_USB_OTG_HS_FORCE_RESET()
                • -
              • HAL_RCC_OTGHS_RELEASE_RESET() -by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
                • -
              • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() -by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
                • -
              • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() -by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
                • -
              • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() -by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
                • -
              • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() -by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
                • -
              -
            • Add __HAL_RCC_SYSCLK_CONFIG() - new macro to configure the - system clock source (SYSCLK)
              • -
            • __HAL_RCC_GET_SYSCLK_SOURCE() - updates:
              • -
                -
              • Add new RCC - Literals:
                • -
                  -
                • RCC_SYSCLKSOURCE_STATUS_HSI
                  • -
                • RCC_SYSCLKSOURCE_STATUS_HSE
                  • -
                • RCC_SYSCLKSOURCE_STATUS_PLLCLK
                  • -
                • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
                  • -
                -
              •  Update - - - - macro description to refer - to the literals above -
                • -
              -
            -
          • HAL - - - - PWR update
            • -
              -
            • Add new - define PWR_WAKEUP_PIN2
              • -
            • Add new API - to Control/Get VOS bits - of CR register
              • -
                -
              • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
                • -
              • HAL_PWREx_GetVoltageRange()
                • -
              -
            • __HAL_PWR_ - VOLTAGESCALING_CONFIG(): Implement - workaround to cover VOS - limitation delay when PLL is - enabled after setting the VOS - configuration
              • -
            -
          • HAL - - - - GPIO update
            • -
              -
            • Add the new - Alternate functions literals - related to remap for SPI, - - - - USART, I2C, SPDIFRX, CEC - and QSPI
              • -
            • HAL_GPIO_DeInit(): - - - - Update to check if GPIO - Pin x is already used in EXTI - mode on another GPIO Port - before De-Initialize the EXTI - registers
              • -
            -
          • HAL - - - - FLASH update
            • -
              -
            • __HAL_FLASH_INSTRUCTION_CACHE_RESET() - macro: update to reset -  ICRST bit in - the ACR register after - setting it.
              • -
            • __HAL_FLASH_DATA_CACHE_RESET() macro: - - - - - update to reset -  DCRST bit in the ACR - register after setting it.
              • -
            -
          • HAL - - - - ADC update
            • -
              -
            • Add new - literal: ADC_SOFTWARE_START to - be used as possible value for - the ExternalTrigConv - parameter in the ADC_InitTypeDef - structure to select the ADC - software trigger mode.
              • -
            • IS_ADC_CHANNEL() - macro update to don't assert - stop the ADC_CHANNEL_TEMPSENSOR - value
              • -
            • HAL_ADC_PollForConversion(): update to - manage particular case when - ADC configured in DMA mode and - ADC sequencer with several - ranks and polling for end of - each conversion
              • -
            • HAL_ADC_Start()/HAL_ADC_Start_IT() - /HAL_ADC_Start_DMA() - - - - - update:
              • -
                -
              • unlock the - process before starting the - ADC software conversion.
                • -
              • Optimize - the ADC stabilization delays
                • -
              -
            • __HAL_ADC_GET_IT_SOURCE() - update macro implementation
              • -
            • Add more - details in 'How to use this - driver' section
              • -
            -
          • HAL - - - - DAC update
            • -
              -
            • Add new macro - to check if the specified DAC - interrupt source is enabled or - disabled
              • -
                -
              • __HAL_DAC_GET_IT_SOURCE()
                • -
              -
            • HAL_DACEx_TriangleWaveGeneration() update to - use DAC CR bit mask definition
              • -
            • HAL_DACEx_NoiseWaveGeneration() update to - use DAC CR bit mask definition
              • -
            -
          • HAL - - - - CAN update
            • -
              -
            • CanTxMsgTypeDef structure: - update to use uint8_t Data[8] - - - - - instead of - uint32_t Data[8]
              • -
            • CanRxMsgTypeDef structure: - update to use uint8_t Data[8] - instead of - uint32_t Data[8]
              • -
            -
          -
            -
          • HAL - - - - RTC update
            • -
              -
            • Update to - use CMSIS mask definition - instead of hardcoded values (EXTI_IMR_IM17, - EXTI_IMR_IM19..)
              • -
            -
          • HAL - - - - LTDC update
            • -
              -
            • LTDC_SetConfig() update to - allow the drawing - of partial bitmap in - active layer.
              • -
            -
          • HAL - - - - USART update
            • -
              -
            • HAL_USART_Init() fix USART - baud rate configuration - issue: USART baud rate is - twice Higher than expected
              • -
            -
          • HAL - - - - SMARTCARD update
            • -
              -
            • HAL_SMARTCARD_Transmit_IT() update to - force the disable for the ERR - interrupt to avoid the OVR - interrupt
              • -
            • HAL_SMARTCARD_IRQHandler() - update check condition - for transmission end
              • -
            • Clean up: - remove the following - literals that aren't used in - smartcard mode
              • -
                -
              • SMARTCARD_PARITY_NONE
                • -
              • SMARTCARD_WORDLENGTH_8B
                • -
              • SMARTCARD_STOPBITS_1
                • -
              • SMARTCADR_STOPBITS_2
                • -
              -
            -
          • HAL - - - - SPI update
            • -
              -
            • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TarnsmitReceive_DMA() - update to unlock - the process before - enabling the SPI peripheral
              • -
            • HAL_SPI_Transmit_DMA() update to - manage correctly the DMA RX - stream in SPI Full duplex mode
              • -
            • Section - SPI_Exported_Functions_Group2 update - to remove duplication in *.chm - UM
              • -
            -
          • HAL - - - - CRYP update
            • -
              -
            • Update to - manage multi instance:
              • -
                -
              • Add new - parameter Instance in the CRYP_HandleTypeDef - Handle structure.
                • -
              • Add new - parameter in all HAL CRYP - macros
                • -
                  -
                • example: __HAL_CRYP_ENABLE() -  updated by - __HAL_CRYP_ENABLE(__HANDLE__)
                  • -
                -
              -
            -
          • HAL - - - - DCMI update
            • -
              -
            • Add an - extension - driver stm32f4xx_hal_dcmi_ex.c/h - to manage the support of new - Black and White feature -
              • -
            • Add  __weak attribute - for HAL_DCMI_Init() - function and add a new - implementation in the - extension driver to manage the - black and white configuration - only available in the  - STM32F446xx devices. -
              • -
            • Move DCMI_InitTypeDef - structure to extension driver - and add the - following new fields - related to black and white - feature: ByteSelectMode, ByteSelectStart, LineSelectMode - and LineSelectStart
              • -
            -
          • HAL - - - - PCD update
            • -
              -
            • Add the - support of LPM feature
              • -
                -
              • add PCD_LPM_StateTypeDef - enum
                • -
              • update PCD_HandleTypeDef - structure to support the LPM - feature
                • -
              • add new - functions HAL_PCDEx_ActivateLPM(), - - - - - HAL_PCDEx_DeActivateLPM() - - - - - and HAL_PCDEx_LPM_Callback() - - - - - in the - stm32f4xx_hal_pcd_ex.h/.c - files
                • -
              -
            -
          • HAL - - - - TIM update
            • -
              -
            • Add  - TIM_TIM11_SPDIFRX - - - - define
              • -
            -
          • HAL - - - - SAI update
            • -
              -
            • Add - stm32f4xx_hal_sai_ex.h/.c - files for the SAI_BlockSynchroConfig() - and the SAI_GetInputClock() - - - - - management
              • -
            • Add new - defines HAL_SAI_ERROR_AFSDET, - HAL_SAI_ERROR_LFSDET, - HAL_SAI_ERROR_CNREADY, - HAL_SAI_ERROR_WCKCFG, - HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code - group
              • -
            • Add new - defines SAI_SYNCEXT_DISABLE, - SAI_SYNCEXT_IN_ENABLE, - SAI_SYNCEXT_OUTBLOCKA_ENABLE, - SAI_SYNCEXT_OUTBLOCKB_ENABLE - for the SAI External - synchronization
              • -
            • Add new - defines SAI_I2S_STANDARD, - SAI_I2S_MSBJUSTIFIED, - SAI_I2S_LSBJUSTIFIED, - SAI_PCM_LONG and SAI_PCM_SHORT - for the SAI Supported protocol
              • -
            • Add new - defines - SAI_PROTOCOL_DATASIZE_16BIT, - SAI_PROTOCOL_DATASIZE_16BITEXTENDED, - SAI_PROTOCOL_DATASIZE_24BIT - and - SAI_PROTOCOL_DATASIZE_32BIT - for SAI protocol data size
              • -
            • Add SAI - Callback prototype definition
              • -
            • Update SAI_InitTypeDef - structure by adding new - fields: SynchroExt, - Mckdiv, - MonoStereoMode, - CompandingMode, - TriState
              • -
            • Update SAI_HandleTypeDef - structure:
              • -
                -
              • remove - uint16_t *pTxBuffPtr, - *pRxBuffPtr, - TxXferSize, - RxXferSize, - TxXferCount - and RxXferCount - and replace them - respectively by uint8_t *pBuffPtr, - uint16_t XferSize and - - - - - uint16_t XferCount
                • -
              • add mutecallback - field
                • -
              • add struct - __SAI_HandleTypeDef - *hsai field
                • -
              -
            • Remove - SAI_CLKSOURCE_PLLR and - SAI_CLOCK_PLLSRC defines
              • -
            • Add - SAI_CLKSOURCE_NA define
              • -
            • Add - SAI_AUDIO_FREQUENCY_MCKDIV - define
              • -
            • Add - SAI_SPDIF_PROTOCOL define
              • -
            • Add - SAI_SYNCHRONOUS_EXT define
              • -
            • Add new - functions HAL_SAI_InitProtocol(), - - - - - HAL_SAI_Abort(), - - - - - HAL_SAI_EnableTxMuteMode(), - - - - - HAL_SAI_DisableTxMuteMode(), - - - - - HAL_SAI_EnableRxMuteMode(), - - - - - HAL_SAI_DisableRxMuteMode()
              • -
            • Update HAL_SAI_Transmit(), - - - - - HAL_SAI_Receive(), - - - - - HAL_SAI_Transmit_IT(), - - - - - HAL_SAI_Receive_IT(), - - - - - HAL_SAI_Transmit_DMA(), - - - - - HAL_SAI_Receive_DMA() - - - - - functions to use uint8_t *pData - instead of uint16_t *pData - --> This update is mainly - impacting the compatibility - with previous driver - version.
              • -
            -
          • HAL - - - - I2S update
            • -
              -
            • Split the - following - functions between Generic - and Extended API based on full - duplex management and add the - attribute __weak in the - Generic API
              • -
                -
              • HAL_I2S_Init(), -HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle() -
                • -
              -
            • Move the - following static functions - from generic to extension driver
              • -
                -
              •  I2S_DMARxCplt() - and I2S_DMATxCplt()
                • -
              -
            • Remove static - attribute from I2S_Transmit_IT() - and I2S_Receive_IT() functions
              • -
            • Move I2SxEXT() - macro to extension file
              • -
            • Add - I2S_CLOCK_PLLR and - I2S_CLOCK_PLLSRC defines for - I2S clock source
              • -
            • Add new - function I2S_GetInputClock()
              • -
            -
          • HAL - - - - LL FMC update
            • -
              -
            • Add WriteFifo - and PageSize - fields in the FMC_NORSRAM_InitTypeDef - structure
              • -
            • Add - FMC_PAGE_SIZE_NONE, - FMC_PAGE_SIZE_128, - FMC_PAGE_SIZE_256, - FMC_PAGE_SIZE_1024, - FMC_WRITE_FIFO_DISABLE, - FMC_WRITE_FIFO_ENABLE defines
              • -
            • Update FMC_NORSRAM_Init(), - - - - - FMC_NORSRAM_DeInit() - - - - - and FMC_NORSRAM_Extended_Timing_Init() functions
              • -
            -
          • HAL - - - - LL USB update
            • -
              -
            • Update USB_OTG_CfgTypeDef - structure to support LPM, lpm_enable - field added
              • -
            • Update USB_HostInit() - and USB_DevInit() - - - - - functions to support the VBUS - Sensing B activation
              • -
            -
          -

          V1.2.0 - - - - / 26-December-2014

          -

          Main Changes

          -
            -
          • Maintenance - - - - release to fix known defects - and enhancements implementation
            • -
          -
            -
          • Macros - - - - and literals renaming to - ensure compatibles across - STM32 series, - backward compatibility - maintained thanks to new added - file stm32_hal_legacy.h under - - - - /Inc/Legacy
            • -
          • Add - *.chm UM for all drivers, a UM - is provided for each superset RPN
            • -
          • Update - - - - drivers to be C++ compliant
            • -
          • Several - - - - update on source code - formatting, for better UM - generation (i.e. - Doxygen - tags updated)
            • -
          • Two - - - - changes done on the HAL - requires an update on the - application code based on HAL - V1.1.0
            • -
              -
            • LSI_VALUE constant has - been corrected in - stm32f4xx_hal_conf.h file, its - value changed from 40 KHz - to 32 KHz
              • -
            • UART, USART, - IRDA and SMARTCARD - (referenced as PPP - here below) drivers: - in DMA transmit process, the - code has been updated to avoid - waiting on TC flag under DMA - ISR, PPP TC interrupt - is used instead. Below the - update to be done on user - application:
              • -
                -
              • Configure - and enable the USART IRQ in - HAL_PPP_MspInit() - function
                • -
              • In - stm32f4xx_it.c file, PPP_IRQHandler() - function: add a call to HAL_PPP_IRQHandler() - - - - function
                • -
              -
            -
          -
            -
          • HAL - - - - generic - update
            • -
          -
            -
              -
            • stm32f4xx_hal_def.h
              • -
                -
              • Update NULL - definition to fix C++ - compilation issue
                • -
              • Add UNUSED() - macro
                • -
              • Add a new - define __NOINLINE to be used - for the no inline code - independent from tool chain
                • -
              -
            • stm32f4xx_hal_conf_template.h
              • -
                -
              • LSI_VALUE constant - has been corrected, - its value changed from 40 KHz - to 32 KHz
                • -
              -
            -
          -
            -
              -
            • Update all - macros and literals naming to - be uper - case
              • -
            • ErrorCode parameter in - PPP_HandleTypeDef - structure updated - to uint32_t instead - of enum HAL_PPP_ErrorTypeDef
              • -
            • Remove the - - - - unused FLAG and IT assert macros
              • -
            -
          • HAL - - - - ADC update
            • -
              -
            • Fix temperature - - - - - sensor channel configuration - issue for STM32F427/437xx - - - - -  and STM32F429/439xx - - - - devices
              • -
            -
          • HAL - - - - DAC update
            • -
              -
            • HAL_DAC_ConfigChannel(): update the - access to the DAC peripheral - registers via the hdac - handle instance
              • -
            • HAL_DAC_IRQHandler(): update to - check on both DAC_FLAG_DMAUDR1 - and DAC_FLAG_DMAUDR2
              • -
            • HAL_DACEx_NoiseWaveGenerate(): update to - reset DAC CR register before - setting the new DAC - configuration
              • -
            • HAL_DACEx_TriangleWaveGenerate(): update to - reset DAC CR register before - setting the new DAC - configuration
              • -
            -
          • HAL - - - - CAN update
            • -
              -
            • Unlock the - CAN process when communication - error occurred
              • -
            -
          • HAL - - - - CORTEX update
            • -
              -
            • Add new macro - IS_NVIC_DEVICE_IRQ() - to check on negative values of - IRQn - parameter
              • -
            -
          -

          �  - - - - - HAL CRYP update

          -
            -
              -
            • HAL_CRYP_DESECB_Decrypt_DMA(): fix the - inverted pPlainData - and pCypherData - parameters issue
              • -
            • CRYPEx_GCMCCM_SetInitVector(): remove - the IVSize - parameter as the key length - 192bits and 256bits are not - supported by this version
              • -
            • Add restriction for - - - - - the CCM Encrypt/Decrypt API's - that only DataType - equal to 8bits is supported
              • -
            • HAL_CRYPEx_AESGCM_Finish():
              • -
                -
              • Add restriction - - - - - that the implementation is - limited to 32bits inputs - data length  (Plain/Cyphertext, - - - - Header) compared with GCM stadards - specifications (800-38D)
                • -
              • Update Size - parameter on 32bits instead - of 16bits
                • -
              • Fix issue - with 16-bit Data Type: - update to use intrinsic __ROR() - instead of __REV16()
                • -
              -
            -
          -

          �  - - - - - HAL DCMI update

          -
            -
              -
            • HAL_DCMI_ConfigCROP(): Invert - assert macros to check Y0 and - Ysize - parameters
              • -
            -
          -

          �  - - - - - HAL DMA update

          -
            -
              -
            • HAL_DMA_Init(): Update to - - - - - clear the DBM bit in the - SxCR - register before setting the - new configuration
              • -
            • DMA_SetConfig(): - add to clear the DBM - bit in the SxCR - register
              • -
            -
          -

          �  - - - - - HAL FLASH update

          -
            -
              -
            • Add "HAL_" - prefix in the defined values - for the FLASH error code
              • -
                -
              • Example: FLASH_ERROR_PGP - renamed by HAL_FLASH_ERROR_PGP
                • -
              -
            • Clear the - - - - Flash ErrorCode - in the FLASH_WaitForLastOperation() - function
              • -
            • Update FLASH_SetErrorCode() - function to use "|=" - operant to update the Flash ErrorCode - parameter in the FLASH handle
              • -
            • IS_FLASH_ADDRESS(): Update the - macro check using '<=' - condition instead of '<'
              • -
            • IS_OPTIONBYTE(): Update the - macro check using '<=' - condition instead of '<'
              • -
            • Add "FLASH_" - - - - - prefix in the defined values - of FLASH Type Program - parameter
              • -
                -
              • Example: TYPEPROGRAM_BYTE - renamed by FLASH_TYPEPROGRAM_BYTE
                • -
              -
            • Add "FLASH_" - - - - - prefix in the defined values - of FLASH Type Erase parameter
              • -
                -
              • Example: TYPEERASE_SECTORS - renamed by FLASH_TYPEERASE_SECTORS
                • -
              -
            • Add "FLASH_" - - - - - prefix in the defined values - of FLASH Voltage Range - parameter
              • -
                -
              • Example: VOLTAGE_RANGE_1 - renamed by FLASH_VOLTAGE_RANGE_1
                • -
              -
            • Add "OB_" - - - - - prefix in the defined values - of FLASH WRP State parameter
              • -
                -
              • Example: WRPSTATE_ENABLE - renamed by OB_WRPSTATE_ENABLE
                • -
              -
            • Add "OB_" - - - - - prefix in the defined values - of the FLASH PCROP State - parameter
              • -
                -
              • PCROPSTATE_DISABLE  - updated by OB_PCROP_STATE_DISABLE
                • -
              • PCROPSTATE_ENABLE -  updated by OB_PCROP_STATE_ENABLE
                • -
              -
            • Change - "OBEX" prefix by - "OPTIONBYTE" prefix in these - defines:
              • -
                -
              • OBEX_PCROP - - - - by OPTIONBYTE_PCROP 
                • -
              • OBEX_BOOTCONFIG - - - - by OPTIONBYTE_BOOTCONFIG
                • -
              -
            -
          -

          �  - - - - - HAL ETH update

          -
            -
              -
            • Fix macros - naming typo
              • -
            -
          -
            -
              -
                -
              • Update - __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() - by - __HAL_ETH_EXTI_SET_RISING_EDGE_TRIGGER()
                • -
              • Update - __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() -by __HAL_ETH_EXTI_SET_FALLING_EDGE_TRIGGER()
                • -
              -
            -
          -

          �  - - - - - HAL PWR update

          -
            -
              -
            • Add new API - to manage SLEEPONEXIT and - SEVONPEND bits of SCR register
              • -
                -
              • HAL_PWR_DisableSleepOnExit()
                • -
              • HAL_PWR_EnableSleepOnExit()
                • -
              • HAL_PWR_EnableSEVOnPend()
                • -
              • HAL_PWR_DisableSEVOnPend()
                • -
              -
            • HAL_PWR_EnterSTOPMode()
              • -
                -
              • Update to - - - - clear the CORTEX SLEEPDEEP - bit of SCR register - before entering in sleep mode
                • -
              • Update - usage of __WFE() - in low power entry function: - if there is a pending event, - calling __WFE() will not - enter the CortexM4 core to - sleep mode. The solution is - to made the call below; the - first __WFE() - is always ignored and clears - the event if one was already - pending, the second is - always applied
                • -
              -
            -
          -
          -

          __SEV()
          -           __WFE()
          -           __WFE()

          -
          -
            -
              -
            • Add - new PVD configuration modes
              • -
                -
              • PWR_PVD_MODE_NORMAL
                • -
              • PWR_PVD_MODE_EVENT_RISING 
                • -
              • PWR_PVD_MODE_EVENT_FALLING
                • -
              • PWR_PVD_MODE_EVENT_RISING_FALLING
                • -
              -
            • Add new - macros to manage PVD Trigger
              • -
                -
              • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()
                • -
              • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(
                • -
              • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()
                • -
              • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
                • -
              • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
                • -
              • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
                • -
              -
            • PVD macros:
              • -
                -
              • Remove the - __EXTILINE__ parameter
                • -
              • Update to - use prefix "__HAL_PWR_PVD_" - instead of  prefix - "__HAL_PVD"
                • -
              -
            -
          -
            -
              -
            • Rename HAL_PWR_PVDConfig() - by HAL_PWR_ConfigPVD()
              • -
            • Rename HAL_PWREx_ActivateOverDrive() - by HAL_PWREx_EnableOverDrive() - - - - -
              • -
            • Rename HAL_PWREx_DeactivateOverDrive() - by HAL_PWREx_DisableOverDrive() - - - - -
              • -
            -
          • HAL - - - - GPIO update
            • -
              -
            • HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call - to the CMSIS assert macro - to check GPIO instance: - IS_GPIO_ALL_INSTANCE() 
              • -
            • HAL_GPIO_WritePin(): update to - write in BSRR register
              • -
            • Rename GPIO_GET_SOURCE() - by GET_GPIO_INDEX() and - - - - move this later to file  - stm32f4xx_hal_gpio_ex.h
              • -
            • Add new - define for alternate function - GPIO_AF5_SPI3 for - STM32F429xx/439xx and - STM32F427xx/437xx devices
              • -
            -
          • HAL - - - - HASH update
            • -
              -
            • HAL_HASH_MD5_Start_IT(): - - - - - fix input - address management issue
              • -
            -
          • HAL - - - - RCC update
            • -
              -
            • Rename the - following Macros
              • -
                -
              • __PPP_CLK_ENABLE()  - - - - - by - __HAL_RCC_PPP_CLK_ENABLE()
                • -
              • __PPP_CLK_DISABLE()  - - - - - by - __HAL_RCC_PPP_CLK_DISABLE()
                • -
              • __PPP_FORCE_RESET()  - - - - - by - __HAL_RCC_PPP_FORCE_RESET()
                • -
              • __PPP_RELEASE_RESET()  - - - - - by - __HAL_RCC_PPP_RELEASE_RESET()
                • -
              • __PPP_CLK_SLEEP_ENABLE() - by - __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
                • -
              • __PPP_CLK_SLEEP_DISABLE() - by - __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
                • -
              -
            • IS_RCC_PLLSAIN_VALUE() - macro: update the check - condition
              • -
            • Add - description of RCC known Limitations
              • -
            • Rename HAL_RCC_CCSCallback() - by HAL_RCC_CSSCallback()
              • -
            • HAL_RCC_OscConfig() fix - issues: 
              • -
                -
              • Remove the - disable of HSE - oscillator when - HSE_BYPASS is used as - system clock source or as - PPL clock source
                • -
              • Add a check - on HSERDY flag - when HSE_BYPASS is - selected as new state - for HSE oscillator.
                • -
              -
            • Rename - __HAL_RCC_I2SCLK() - by __HAL_RCC_I2S_Config()
              • -
            -
          -

          �  - - - - - HAL I2S update

          -
            -
              -
            • HAL_I2S_Init(): add check - on I2S instance - using CMSIS macro IS_I2S_ALL_INSTANCE() 
              • -
            • HAL_I2S_IRQHandler() - update for compliancy w/ C++
              • -
            • Add use - of tmpreg - variable in __HAL_I2S_CLEAR_OVRFLAG() - and __HAL_I2S_CLEAR_UDRFLAG() - macro for compliancy with C++
              • -
            • HAL_I2S_GetError(): update to - return uint32_t instead of - HAL_I2S_ErrorTypeDef - enumeration
              • -
            -
          -

          �  - - - - - HAL I2C update

          -
            -
              -
            • Update to - - - - - clear the POS bit in the - CR1 register at the end - of HAL_I2C_Master_Read_IT() - and HAL_I2C_Mem_Read_IT() - process
              • -
            • Rename - HAL_I2CEx_DigitalFilter_Config()  - - - - by - HAL_I2CEx_ConfigDigitalFilter() -
              • -
            • Rename - HAL_I2CEx_AnalogFilter_Config()  - - - - by - HAL_I2CEx_ConfigAnalogFilter() -
              • -
            • Add use - of tmpreg - variable in __HAL_I2C_CLEAR_ADDRFLAG() - and __HAL_I2C_CLEAR_STOPFLAG() - macro for compliancy with - C++
              • -
            -
          • HAL - - - - IrDA update
            • -
              -
            • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, IrDA TC - interrupt is used instead. - Below the update to be done on - user application:
              • -
                -
              • Configure - and enable the USART IRQ in - HAL_IRDA_MspInit() - function
                • -
              • In - stm32f4xx_it.c file, UASRTx_IRQHandler() - function: add a call to HAL_IRDA_IRQHandler() - - - - function
                • -
              -
            • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under IRDA ISR, IrDA TC - interrupt is used instead. No - impact on user application
              • -
            • Rename - Macros: add prefix "__HAL"
              • -
                -
              • __IRDA_ENABLE() - by __HAL_IRDA_ENABLE()
                • -
              • __IRDA_DISABLE() - by __HAL_IRDA_DISABLE()
                • -
              -
            • Add new user - macros to manage the sample - method feature
              • -
                -
              • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
                • -
              • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
                • -
              -
            • HAL_IRDA_Transmit_IT(): update to - remove the enable of the - parity error interrupt
              • -
            • Add use - of tmpreg - variable in __HAL_IRDA_CLEAR_PEFLAG() - macro for compliancy with - C++
              • -
            • HAL_IRDA_Transmit_DMA() update to - follow the - right procedure - "Transmission using DMA"  - in the reference manual
              • -
                -
              • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
                • -
              -
            -
          • HAL - - - - IWDG update
            • -
              -
            • Rename the - defined IWDG keys: 
              • -
                -
              • KR_KEY_RELOAD - - - - by IWDG_KEY_RELOAD
                • -
              • KR_KEY_ENABLE - - - - by IWDG_KEY_ENABLE
                • -
              • KR_KEY_EWA - by - IWDG_KEY_WRITE_ACCESS_ENABLE
                • -
              • KR_KEY_DWA - by - IWDG_KEY_WRITE_ACCESS_DISABLE
                • -
              -
            •  Add new - macros - __HAL_IWDG_RESET_HANDLE_STATE() - and - __HAL_IWDG_CLEAR_FLAG() 
              • -
            • Update - __HAL_IWDG_ENABLE_WRITE_ACCESS() - and - __HAL_IWDG_DISABLE_WRITE_ACCESS() - as private macro
              • -
            -
          -

          �  - - - - - HAL SPI update

          -
            -
              -
            • HAL_SPI_TransmitReceive_DMA() update to - remove the  DMA Tx Error - Callback initialization when - SPI RxOnly - mode is selected
              • -
            • Add use of UNUSED(tmpreg) - in __HAL_SPI_CLEAR_MODFFLAG(), - __HAL_SPI_CLEAR_OVRFLAG(), - __HAL_SPI_CLEAR_FREFLAG() to - fix "Unused variable" warning - with TrueSTUDIO.
              • -
            • Rename - Literals: remove "D" from - "DISABLED" and "ENABLED"
              • -
                -
              • SPI_TIMODE_DISABLED by - - - - - SPI_TIMODE_DISABLE
                • -
              • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
                • -
              • SPI_CRCCALCULATION_DISABLED - by - - - - -  SPI_CRCCALCULATION_DISABLE
                • -
              • SPI_CRCCALCULATION_ENABLED - by - - - - -  SPI_CRCCALCULATION_ENABLE
                • -
              -
            • Add use - of tmpreg - variable in __HAL_SPI_CLEAR_MODFFLAG(), - - - - - __HAL_SPI_CLEAR_FREFLAG() and - __HAL_SPI_CLEAR_OVRFLAG() - macros for compliancy - with C++
              • -
            -
          -

          �  - - - - - HAL SDMMC update

          -
            -
              -
            • IS_SDIO_ALL_INSTANCE() -  macro moved to CMSIS - files
              • -
            -
          • HAL - - - - LTDC update
            • -
              -
            • HAL_LTDC_ConfigCLUT: optimize - the function when pixel format -is LTDC_PIXEL_FORMAT_AL44 
              • -
                -
              • Update the - size of color look up table - to 16 instead of 256 when - the pixel format - is LTDC_PIXEL_FORMAT_AL44 -
                • -
              -
            -
          • HAL - - - - NAND update
            • -
              -
            • Rename NAND - Address structure to NAND_AddressTypeDef - instead of NAND_AddressTypedef
              • -
            • Update the - used algorithm of these functions
              • -
                -
              • HAL_NAND_Read_Page()
                • -
              • HAL_NAND_Write_Page()
                • -
              • HAL_NAND_Read_SpareArea()
                • -
              • HAL_NAND_Write_SpareArea()
                • -
              -
            • HAL_NAND_Write_Page(): move - initialization of tickstart - before while loop
              • -
            • HAL_NAND_Erase_Block(): add whait - until NAND status is ready - before exiting this function
              • -
            -
          • HAL - - - - NOR update
            • -
              -
            • Rename NOR - Address structure to NOR_AddressTypeDef - instead of NOR_AddressTypedef
              • -
            • NOR Status - literals renamed
              • -
                -
              • NOR_SUCCESS - by HAL_NOR_STATUS_SUCCESS
                • -
              • NOR_ONGOING - by HAL_NOR_STATUS_ONGOING
                • -
              • NOR_ERROR - by HAL_NOR_STATUS_ERROR
                • -
              • NOR_TIMEOUT - by HAL_NOR_STATUS_TIMEOUT
                • -
              -
            • HAL_NOR_GetStatus() update to - fix Timeout issue - and exit from waiting - loop when timeout occurred
              • -
            -
          • HAL - - - - PCCARD update
            • -
              -
            • Rename PCCARD - Address structure to HAL_PCCARD_StatusTypeDef - instead of CF_StatusTypedef
              • -
            • PCCARD Status - literals renamed
              • -
                -
              • CF_SUCCESS - by HAL_PCCARD_STATUS_SUCCESS
                • -
              • CF_ONGOING - by HAL_PCCARD_STATUS_ONGOING
                • -
              • CF_ERROR - by HAL_PCCARD_STATUS_ERROR
                • -
              • CF_TIMEOUT - by HAL_PCCARD_STATUS_TIMEOUT
                • -
              -
            • Update "CF" - by "PCCARD" in functions, - literals - and macros
              • -
            -
          • HAL - - - - PCD update
            • -
              -
            • Rename functions
              • -
                -
              • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
                • -
              • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
                • -
              -
            • Rename literals
              • -
                -
              • USB_FS_EXTI_TRIGGER_RISING_EDGE - - - - - by - USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
                • -
              • USB_FS_EXTI_TRIGGER_FALLING_EDGE - - - - - by - USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
                • -
              • USB_FS_EXTI_TRIGGER_BOTH_EDGE() - by - USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
                • -
              • USB_HS_EXTI_TRIGGER_RISING_EDGE - - - - - by - USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 
                • -
              • USB_HS_EXTI_TRIGGER_FALLING_EDGE - - - - - by - USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
                • -
              • USB_HS_EXTI_TRIGGER_BOTH_EDGE - - - - - by - USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
                • -
              • USB_HS_EXTI_LINE_WAKEUP - - - - - by - USB_OTG_HS_EXTI_LINE_WAKEUP
                • -
              • USB_FS_EXTI_LINE_WAKEUP - - - - - by - USB_OTG_FS_EXTI_LINE_WAKEUP
                • -
              -
            • Rename USB - EXTI macros (FS, HS - - - - referenced as SUBBLOCK - here below)
              • -
                -
              • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() -  by  - __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()  
                • -
              • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
                • -
              • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG() 
                • -
              • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
                • -
              • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
                • -
              • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
                • -
              • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
                • -
              • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT()  - - - - - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT()                                       -
                • -
              -
            -
          -
            -
          • HAL - - - - RNG update
            • -
              -
            • Add new functions
              • -
                -
              • HAL_RNG_GenerateRandomNumber(): to - generate a 32-bits random - number, - return - random value in argument and - return HAL status.
                • -
              • HAL_RNG_GenerateRandomNumber_IT(): to -  start generation of - the 32-bits random - number, user should call - the HAL_RNG_ReadLastRandomNumber() - - - - - function under the HAL_RNG_ReadyCallback() - - - - to get the generated random - value.
                • -
              • HAL_RNG_ReadLastRandomNumber(): to - return the last random value - stored in the RNG handle
                • -
              -
            • HAL_RNG_GetRandomNumber(): return - value update (obsolete), - replaced by HAL_RNG_GenerateRandomNumber()
              • -
            • HAL_RNG_GetRandomNumber_IT(): wrong - implementation (obsolete), - replaced by HAL_RNG_GenerateRandomNumber_IT()
              • -
            • __HAL_RNG_CLEAR_FLAG() - macro (obsolete), replaced by - new __HAL_RNG_CLEAR_IT() macro
              • -
            • Add new - define for RNG ready - interrupt:  RNG_IT_DRDY
              • -
            -
          • HAL - - - - RTC update
            • -
              -
            • HAL_RTC_GetTime() and HAL_RTC_GetDate(): - - - - - add the comment below
              • -
            -
          -
          -
          -

            - - - - - * @note You must call HAL_RTC_GetDate() - after HAL_RTC_GetTime() - - - - - to unlock the values
          -             - - - - - * in the higher-order - calendar shadow registers to - ensure consistency between - the time and date values.
          -             - - - - - * Reading RTC current time - locks the values in calendar - shadow registers until - Current date is read. 

          -
          -
          -
            -
              -
            • Rename - literals: add prefix "__HAL"
              • -
                -
              • FORMAT_BIN by HAL_FORMAT_BIN
                • -
              • FORMAT_BCD - by HAL_FORMAT_BCD
                • -
              -
            • Rename macros - (ALARM, WAKEUPTIMER and - TIMESTAMP referenced - as SUBBLOCK here - below)
              • -
                -
              • __HAL_RTC_EXTI_ENABLE_IT() - by  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
                • -
              • __HAL_RTC_EXTI_DISABLE_IT() - by  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_IT()
                • -
              • __HAL_RTC_EXTI_CLEAR_FLAG() - by  __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()
                • -
              • __HAL_RTC_EXTI_GENERATE_SWIT() - by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
                • -
              -
            • Add new - macros (ALARM, - WAKEUPTIMER and TAMPER_TIMESTAMP - - - - referenced as SUBBLOCK - here below)
              • -
                -
              • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE() 
                • -
              • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
                • -
              • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
                • -
              • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
                • -
              • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
                • -
              • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
                • -
              • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
                • -
              •  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
                • -
              •  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
                • -
              •  __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
                • -
              -
            -
          • HAL - - - - SAI update
            • -
              -
            • Update - SAI_STREOMODE by SAI_STEREOMODE
              • -
            • Update FIFO - status Level defines in upper - case
              • -
            • Rename - literals: remove "D" from - "DISABLED" and "ENABLED"
              • -
                -
              • SAI_OUTPUTDRIVE_DISABLED - - - - -  by - SAI_OUTPUTDRIVE_DISABLE
                • -
              • SAI_OUTPUTDRIVE_ENABLED - - - - -  by - SAI_OUTPUTDRIVE_ENABLE
                • -
              • SAI_MASTERDIVIDER_ENABLED  by - SAI_MASTERDIVIDER_ENABLE
                • -
              • SAI_MASTERDIVIDER_DISABLED  by - SAI_MASTERDIVIDER_DISABLE
                • -
              -
            -
          -
            -
          • HAL - - - - SD update
            • -
              -
            • Rename - SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
              • -
            • SD_PowerON() updated to - add 1ms required power up - waiting time before starting - the SD initialization sequence
              • -
            • SD_DMA_RxCplt()/SD_DMA_TxCplt(): - - - - - add a call to - HAL_DMA_Abort()
              • -
            • HAL_SD_ReadBlocks() update to - set the defined - DATA_BLOCK_SIZE as SDIO DataBlockSize - parameter
              • -
            • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() - update to call the HAL_DMA_Start_IT() - - - - function with DMA Datalength - set to BlockSize/4  - - - - - as the DMA is - configured in word 
              • -
            -
          • HAL - - - - SMARTCARD update 
            • -
              -
            • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, SMARTCARD - TC interrupt is used instead. - Below the update to be done on - user application:
              • -
                -
              • Configure - and enable the USART IRQ in - HAL_SAMRTCARD_MspInit() - function
                • -
              • In - stm32f4xx_it.c file, UASRTx_IRQHandler() - function: add a call to HAL_SMARTCARD_IRQHandler() - - - - - function
                • -
              -
            • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under SMARTCARD - ISR, SMARTCARD TC - interrupt is used instead. No - impact on user application
              • -
            • Rename - macros: add prefix "__HAL"
              • -
                -
              • __SMARTCARD_ENABLE() - by __HAL_SMARTCARD_ENABLE()
                • -
              • __SMARTCARD_DISABLE() - by __HAL_SMARTCARD_DISABLE()
                • -
              • __SMARTCARD_ENABLE_IT() - by - __HAL_SMARTCARD_ENABLE_IT()
                • -
              • __SMARTCARD_DISABLE_IT() - by - __HAL_SMARTCARD_DISABLE_IT()
                • -
              • __SMARTCARD_DMA_REQUEST_ENABLE() - by - __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
                • -
              • __SMARTCARD_DMA_REQUEST_DISABLE() - by - __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
                • -
              -
            • Rename - literals: remove "D" from - "DISABLED" and "ENABLED"
              • -
                -
              • SMARTCARD_NACK_ENABLED by - - - - - SMARTCARD_NACK_ENABLE
                • -
              • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
                • -
              -
            • Add new user - macros to manage the sample - method feature
              • -
                -
              • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
                • -
              • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
                • -
              -
            • Add use - of tmpreg - variable in - __HAL_SMARTCARD_CLEAR_PEFLAG() - macro for compliancy with - C++
              • -
            • HAL_SMARTCARD_Transmit_DMA() update to - follow the - right procedure - "Transmission using DMA"  - in the reference manual
              • -
                -
              • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
                • -
              -
            -
          • HAL - - - - TIM update
            • -
              -
            • Add - TIM_CHANNEL_ALL as possible - value for all Encoder - Start/Stop APIs Description
              • -
            • HAL_TIM_OC_ConfigChannel() remove call - to IS_TIM_FAST_STATE() assert - macro
              • -
            • HAL_TIM_PWM_ConfigChannel() add a call - to IS_TIM_FAST_STATE() assert - macro to check the OCFastMode - parameter
              • -
            • HAL_TIM_DMADelayPulseCplt() Update to - set the TIM Channel before to - call  HAL_TIM_PWM_PulseFinishedCallback()
              • -
            • HAL_TIM_DMACaptureCplt() update to - set the TIM Channel before to - call  HAL_TIM_IC_CaptureCallback()
              • -
            • TIM_ICx_ConfigChannel() update - to fix Timer CCMR1 register - corruption when setting ICFilter - parameter
              • -
            • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() - update to abort the DMA - transfer for the specifc - TIM channel
              • -
            • Add new - function for TIM Slave - configuration in IT mode: - HAL_TIM_SlaveConfigSynchronization_IT() 
              • -
            • HAL_TIMEx_ConfigBreakDeadTime() add an - assert check on Break & DeadTime - parameters values
              • -
            • HAL_TIMEx_OCN_Start_IT() add the - enable of Break Interrupt for - all output modes
              • -
            • Add new - macros to ENABLE/DISABLE URS - bit in TIM CR1 register:
              • -
                -
              • __HAL_TIM_URS_ENABLE()
                • -
              • __HAL_TIM_URS_DISABLE()
                • -
              -
            • Add new macro - for TIM Edge modification: - __HAL_TIM_SET_CAPTUREPOLARITY()
              • -
            -
          • HAL - - - - UART update
            • -
              -
            • Add IS_LIN_WORD_LENGTH() - and - IS_LIN_OVERSAMPLING()  - macros: to check respectively - WordLength - and OverSampling - parameters in LIN mode
              • -
            • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, UART TC - interrupt is used instead. - Below the update to be done on - user application:
              • -
                -
              • Configure - and enable the USART IRQ in - HAL_UART_MspInit() - function
                • -
              • In - stm32f4xx_it.c file, USARTx_IRQHandler() - function: add a call to HAL_UART_IRQHandler() - - - - function
                • -
              -
            • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under UART ISR, UART - TC interrupt is used instead. - No impact on user application
              • -
            • Rename - macros:
              • -
                -
              • __HAL_UART_ONEBIT_ENABLE() - by - __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
                • -
              • __HAL_UART_ONEBIT_DISABLE() - by - __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
                • -
              -
            • Rename - literals:
              • -
                -
              • UART_WAKEUPMETHODE_IDLELINE by - - - - - UART_WAKEUPMETHOD_IDLELINE
                • -
              • UART_WAKEUPMETHODE_ADDRESSMARK by -UART_WAKEUPMETHOD_ADDRESSMARK
                • -
              -
            • Add use - of tmpreg - variable in __HAL_UART_CLEAR_PEFLAG() - macro for compliancy with - C++
              • -
            • HAL_UART_Transmit_DMA() update to - follow the right procedure - "Transmission using DMA" in - the reference manual
              • -
                -
              • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
                • -
              -
            -
          • HAL - - - - USART update
            • -
              -
            • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, USART TC - interrupt is used instead. - Below the update to be done on - user application:
              • -
                -
              • Configure - and enable the USART IRQ in - HAL_USART_MspInit() - function
                • -
              • In - stm32f4xx_it.c file, USARTx_IRQHandler() - function: add a call to HAL_USART_IRQHandler() - - - - - function
                • -
              -
            • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under USART ISR, - USART TC interrupt is used - instead. No impact on user - application
              • -
            • HAL_USART_Init() update - to enable the USART - oversampling by 8 by default - in order to reach max USART - frequencies
              • -
            • USART_DMAReceiveCplt() update - to set the new USART state - after checking on the - old state
              • -
            • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() - update to - follow the - right procedure - "Transmission using DMA"  - in the reference manual
              • -
                -
              • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
                • -
              -
            • Rename - macros:
              • -
                -
              • __USART_ENABLE() - by __HAL_USART_ENABLE()
                • -
              • __USART_DISABLE() - by __HAL_USART_DISABLE()
                • -
              • __USART_ENABLE_IT() - by __HAL_USART_ENABLE_IT()
                • -
              • __USART_DISABLE_IT() - by __HAL_USART_DISABLE_IT()
                • -
              -
            • Rename - literals: remove "D" from - "DISABLED" and "ENABLED"
              • -
                -
              • USART_CLOCK_DISABLED by - - - - - USART_CLOCK_DISABLE
                • -
              • USART_CLOCK_ENABLED by - - - - - USART_CLOCK_ENABLE
                • -
              • USARTNACK_ENABLED - - - - by USART_NACK_ENABLE
                • -
              • USARTNACK_DISABLED - - - - by USART_NACK_DISABLE
                • -
              -
            • Add new user - macros to manage the sample - method feature
              • -
                -
              • __HAL_USART_ONE_BIT_SAMPLE_ENABLE()
                • -
              • __HAL_USART_ONE_BIT_SAMPLE_DISABLE()
                • -
              -
            • Add use - of tmpreg - variable in __HAL_USART_CLEAR_PEFLAG() - macro for compliancy with - C++
              • -
            -
          • HAL - - - - WWDG update
            • -
              -
            • Add new - parameter in - __HAL_WWDG_ENABLE_IT() - macro
              • -
            • Add new - macros to manage WWDG IT & - correction:
              • -
                -
              • __HAL_WWDG_DISABLE()
                • -
              • __HAL_WWDG_DISABLE_IT()
                • -
              • __HAL_WWDG_GET_IT()
                • -
              • __HAL_WWDG_GET_IT_SOURCE()
                • -
              -
            -
          -

          V1.1.0 - - - - / 19-June-2014

          -

          Main Changes

          -
            -
          • Add - support of STM32F411xE devices
            • -
          -
            -
          • HAL - - - - generic - update
            • -
              -
            • Enhance HAL - delay and time base implementation
              • -
                -
              • Systick timer is - used by default as source of - time base, but user can - eventually implement his - proper time base source (a general - - - - purpose - timer for example or other - time source)
                • -
              • Functions - affecting time base - configurations are declared - as __Weak to make override - possible in case of other - implementations in user - file, for more details - please refer to HAL_TimeBase - example
                • -
              -
            • Fix flag - clear procedure: use atomic - write operation "=" instead of - ready-modify-write operation - "|=" or "&="
              • -
            • Fix on - Timeout management, Timeout - value set to 0 passed to API - automatically exits the - function after checking the - flag without any wait
              • -
            • Common update - for the following - communication peripherals: - SPI, UART, USART and IRDA
              • -
                -
              • Add DMA - circular mode support
                • -
              • Remove lock - from recursive process
                • -
              -
            • Add new macro - __HAL_RESET_HANDLE_STATE to - reset a given handle state
              • -
            • Add a new - attribute for functions - executed from internal SRAM - and depending from - Compiler implementation
              • -
            • When USE_RTOS - == 1 (in - stm32l0xx_hal_conf.h), the - __HAL_LOCK() - is not defined instead of - being defined empty
              • -
            • Miscellaneous - comments and formatting update
              • -
            • stm32f4xx_hal_conf_template.h
              • -
                -
              • Add a new - define for LSI default value - LSI_VALUE
                • -
              • Add a new - define for LSE default value - LSE_VALUE
                • -
              • Add a new - define for Tick interrupt - priority TICK_INT_PRIORITY - (needed for the enhanced - time base implementation)
                • -
              -
            • Important - - - - - Note: - aliases has been added for any - API naming change, to keep - compatibility with previous version
              • -
            -
          • HAL - - - - GPIO update
            • -
          -
            -
              -
            • Add a new - macro __HAL_GPIO_EXTI_GENERATE_SWIT() - to manage the generation of - software interrupt on selected - EXTI line
              • -
            • HAL_GPIO_Init(): use - temporary variable when - modifying the registers, to - avoid unexpected transition in - the GPIO pin configuration
              • -
            • Remove - IS_GET_GPIO_PIN macro
              • -
            • Add a new - function HAL_GPIO_LockPin()
              • -
            • Private Macro - __HAL_GET_GPIO_SOURCE renamed - into GET_GPIO_SOURCE
              • -
            • Add the - support of STM32F411xx devices - - - - - : add the - new Alternate functions values - related to new remap added for - SPI, USART, I2C
              • -
            • Update the - following HAL GPIO macros - description: rename EXTI_Linex - by GPIO_PIN_x
              • -
                -
              • __HAL_GPIO_EXTI_CLEAR_IT()
                • -
              • __HAL_GPIO_EXTI_GET_IT()
                • -
              • __HAL_GPIO_EXTI_CLEAR_FLAG()
                • -
              • __HAL_GPIO_EXTI_GET_FLAG()
                • -
              -
            -
          -

          �  - - - - - HAL DMA update

          -
            -
              -
            • Fix in HAL_DMA_PollForTransfer() - to:
              • -
                -
              • set DMA - error code in case of - HAL_ERROR status
                • -
              • set HAL - Unlock before DMA state update
                • -
              -
            -
          -

          �  - - - - - HAL DMA2D - update

          -
            -
              -
            • Add - configuration of source - address in case of A8 or A4 - M2M_PFC DMA2D mode
              • -
            -
          • HAL - - - - FLASH update
            • -
          -
            -
              -
            • Functions - reorganization update, - depending on the features - supported by each STM32F4 device
              • -
            • Add new - driver - (stm32f4xx_hal_flash_ramfunc.h/.c) - to manage function executed - from RAM, these functions are - available only for STM32F411xx - Devices
              • -
                -
              • FLASH_StopFlashInterfaceClk()  : - Stop the flash interface - while System Run
                • -
              • FLASH_StartFlashInterfaceClk() : Stop the - flash interface while System - Run
                • -
              • FLASH_EnableFlashSleepMode() : Enable - the flash sleep while System - Run
                • -
              • FLASH_DisableFlashSleepMode() :  - Disable the flash sleep - while System Run
                • -
              -
            -
          -
            -
          • HAL - - - - PWR update
            • -
          -
            -
              -
            • HAL_PWR_PVDConfig(): add clear - of the EXTI trigger before new - configuration
              • -
            • Fix in HAL_PWR_EnterSTANDBYMode() - to not clear Wakeup flag - (WUF), which need to be - cleared at application level - before to call this function
              • -
            • HAL_PWR_EnterSLEEPMode()
              • -
                -
              • Remove - disable and enable of SysTick - Timer
                • -
              • Update - usage of __WFE() - in low power entry function: - if there is a pending event, - calling __WFE() will not - enter the CortexM4 core to - sleep mode. The solution is - to made the call below; the - first __WFE() - is always ignored and clears - the event if one was already - pending, the second is - always applied
                • -
              -
            -
          -
          -

          __SEV()
          -           __WFE()
          -           __WFE()

          -
          -
            -
              -
            • Add new macro - for software event generation - __HAL_PVD_EXTI_GENERATE_SWIT()
              • -
            • Remove the - following defines form Generic - driver and add them under - extension driver because they - are only used within extension - functions.
              • -
                -
              • CR_FPDS_BB: - used within HAL_PWREx_EnableFlashPowerDown() - function
                • -
              • CSR_BRE_BB: - used within HAL_PWREx_EnableBkUpReg() - function
                • -
              -
            • Add the - support of STM32F411xx devices - add the define STM32F411xE
              • -
                -
              • For - STM32F401xC, STM32F401xE and - STM32F411xE devices add the - following functions used to - enable or disable the low - voltage mode for regulators
                • -
              -
            -
          -
            -
              -
                -
                  -
                • HAL_PWREx_EnableMainRegulatorLowVoltage()
                  • -
                • HAL_PWREx_DisableMainRegulatorLowVoltage()
                  • -
                • HAL_PWREx_EnableLowRegulatorLowVoltage()
                  • -
                • HAL_PWREx_DisableLowRegulatorLowVoltage()
                  • -
                -
              -
            • For - STM32F42xxx/43xxx devices, add - a new function for Under - Driver management as the macro - already added for this mode is - not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()
              • -
            -
          -
            -
          • HAL - - - - RCC update
            • -
              -
            • In HAL_RCC_ClockConfig() - function: update the AHB clock - divider before clock switch to - new source
              • -
            • Allow to - calibrate the HSI when it is - used as system clock source
              • -
            • Rename the - following macros
              • -
                -
              • __OTGFS_FORCE_RESET - - - - ()  by - __USB_OTG_FS_FORCE_RESET()
                • -
              • __OTGFS_RELEASE_RESET - - - - ()  by  -__USB_OTG_FS_RELEASE_RESET()
                • -
              • __OTGFS_CLK_SLEEP_ENABLE - - - - - ()  by  -__USB_OTG_FS_CLK_SLEEP_ENABLE()
                • -
              • __OTGFS_CLK_SLEEP_DISABLE - - - - - () by  __USB_OTG_FS_CLK_SLEEP_DISABLE()
                • -
              -
            -
          -

           

          -
            -
              -
            • Add new field - PLLI2SM in - RCC_PLLI2SInitTypeDef - structure, this division - factor is added for PLLI2S VCO - input clock only STM32F411xE - devices => the FW - compatibility is broken vs. - STM32F401xx devices
              • -
            • Update HAL_RCCEx_PeriphCLKConfig() - and  HAL_RCCEx_GetPeriphCLKConfig()  - - - - - functions to support the new - PLLI2SM
              • -
            • Add new - function to manage the new LSE - mode - - - - - : HAL_RCCEx_SelectLSEMode()
              • -
            • Reorganize - the macros depending from - Part number used and make them - more clear
              • -
            -
          -

          �  HAL - - - - UART update

          -
            -
              -
            • Add new - macros to control CTS and RTS
              • -
            • Add specific - macros to manage the flags - cleared only by a software sequence
              • -
                -
              • __HAL_UART_CLEAR_PEFLAG()
                • -
              • __HAL_UART_CLEAR_FEFLAG()
                • -
              • __HAL_UART_CLEAR_NEFLAG()
                • -
              • __HAL_UART_CLEAR_OREFLAG()
                • -
              • __HAL_UART_CLEAR_IDLEFLAG()
                • -
              -
            • Add several - enhancements without affecting - the driver functionalities -
              • -
                -
              • Remove the - check on RXNE set after - reading the Data in the DR - register
                • -
              • Update the - transmit processes to use - TXE instead of TC
                • -
              • Update HAL_UART_Transmit_IT() - to enable UART_IT_TXE - instead of UART_IT_TC
                • -
              -
            -
          -

          �  - - - - - HAL USART - update

          -
            -
              -
            • Add specific - macros to manage the flags - cleared only by a software sequence
              • -
                -
              • __HAL_USART_CLEAR_PEFLAG()
                • -
              • __HAL_USART_CLEAR_FEFLAG()
                • -
              • __HAL_USART_CLEAR_NEFLAG()
                • -
              • __HAL_USART_CLEAR_OREFLAG()
                • -
              • __HAL_USART_CLEAR_IDLEFLAG()
                • -
              -
            • Update HAL_USART_Transmit_IT() - to enable USART_IT_TXE - instead of USART_IT_TC
              • -
            -
          -

          �  - - - - - HAL IRDA update

          -
            -
              -
            • Add specific - macros to manage the flags - cleared only by a software sequence
              • -
                -
              • __HAL_IRDA_CLEAR_PEFLAG()
                • -
              • __HAL_ - IRDA _CLEAR_FEFLAG()
                • -
              • __HAL_ - IRDA _CLEAR_NEFLAG()
                • -
              • __HAL_ - IRDA _CLEAR_OREFLAG()
                • -
              • __HAL_ - IRDA _CLEAR_IDLEFLAG()
                • -
              -
            • Add several - enhancements without affecting - the driver functionalities
              • -
            -
          -
            -
              -
                -
              • Remove the - check on RXNE set after - reading the Data in the DR - register
                • -
              • Update HAL_IRDA_Transmit_IT() - to enable IRDA_IT_TXE - instead of IRDA_IT_TC
                • -
              -
            • Add the - following APIs used within DMA - process -
              • -
                -
              • HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef - *hirda);
                • -
              • HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef - *hirda);
                • -
              • HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef - *hirda); -
                • -
              • void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef - *hirda);
                • -
              • void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef - *hirda);
                • -
              -
            -
          -

          �  - - - - - HAL SMARTCARD - update

          -
            -
              -
            • Add specific - macros to manage the flags - cleared only by a software sequence
              • -
                -
              • __HAL_SMARTCARD_CLEAR_PEFLAG()
                • -
              • __HAL_SMARTCARD_CLEAR_FEFLAG()
                • -
              • __HAL_SMARTCARD_CLEAR_NEFLAG()
                • -
              • __HAL_SMARTCARD_CLEAR_OREFLAG()
                • -
              • __HAL_SMARTCARD_CLEAR_IDLEFLAG()
                • -
              -
            • Add several - enhancements without affecting - the driver functionalities
              • -
                -
              • Add a new - state HAL_SMARTCARD_STATE_BUSY_TX_RX - and all processes has been - updated accordingly
                • -
              • Update HAL_SMARTCARD_Transmit_IT() - to enable SMARTCARD_IT_TXE - instead of SMARTCARD_IT_TC
                • -
              -
            -
          -
            -
          • HAL - - - - SPI update
            • -
              -
            • Bugs fix
              • -
                -
              • SPI - interface is used in - synchronous polling mode: at - high clock rates like SPI prescaler - 2 and 4, calling
                - HAL_SPI_TransmitReceive() - returns with error - HAL_TIMEOUT                 -
                • -
              • HAL_SPI_TransmitReceive_DMA() does not - clean up the TX DMA, so any - subsequent SPI calls return - the DMA error
                • -
              • HAL_SPI_Transmit_DMA() is failing - when data size is equal to 1 - byte -
                • -
              -
            • Add the - following APIs used within the - DMA process
              • -
            -
          -
            -
              -
                -
              • HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef - *hspi);
                • -
              • HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef - *hspi);
                • -
              • HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef - *hspi);
                • -
              • void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
                • -
              • void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
                • -
              • void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
                • -
              -
            -
          -
            -
          • HAL - - - - RNG update
            • -
              -
                -
              • Add a - conditional define to make - this driver visible for all - STM32F4xx devices except - STM32F401xx and STM32F411xx - Devices.
                • -
              -
            -
          • HAL - - - - CRC update
            • -
              -
                -
              • These - macros are added to - read/write the CRC IDR - register: __HAL_CRC_SET_IDR() - and __HAL_CRC_GET_IDR()
                • -
              -
            -
          -
            -
          • HAL - - - - DAC update
            • -
              -
            • Enhance the - DMA channel configuration when - used with DAC
              • -
            -
          • HAL - - - - TIM update
            • -
              -
            • HAL_TIM_IRQHandler(): update to - check the input capture - channel 3 and 4 in CCMR2 - instead of CCMR1
              • -
            • __HAL_TIM_PRESCALER() - updated to use '=' instead of - '|='
              • -
            • Add the - following macro in TIM HAL - driver
              • -
                -
              • __HAL_TIM_GetCompare() -
                • -
              • __HAL_TIM_GetCounter() -
                • -
              • __HAL_TIM_GetAutoreload() -
                • -
              • __HAL_TIM_GetClockDivision() -
                • -
              • __HAL_TIM_GetICPrescaler()
                • -
              -
            -
          • HAL - - - - SDMMC update
            • -
          -
            -
              -
            • Use of CMSIS - constants instead of magic values
              • -
            • Miscellaneous - update in functions internal - coding
              • -
            -
          • HAL - - - - NAND update
            • -
              -
            • Fix - - - - issue of macros returning - wrong address for NAND blocks
              • -
            • Fix - - - - issue for read/write NAND - page/spare area
              • -
            -
          • HAL - - - - NOR update
            • -
              -
            • Add - - - - the NOR address bank macro - used within the API
              • -
            • Update - - - - NOR API implementation to - avoid the use of NOR address - bank hard coded
              • -
            -
          • HAL - - - - HCD update
            • -
              -
            • HCD_StateTypeDef structure - members renamed
              • -
            • These macro are renamed
              • -
                -
              • __HAL_GET_FLAG(__HANDLE__, - - - - - __INTERRUPT__)    - - - - by - __HAL_HCD_GET_FLAG(__HANDLE__, - __INTERRUPT__)
                • -
              • __HAL_CLEAR_FLAG(__HANDLE__, - - - - - __INTERRUPT__) by - __HAL_HCD_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) 
                • -
              • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  - - - - - by - __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)  -
                • -
              -
            -
          • HAL - - - - PCD update
            • -
              -
            • HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() - - - - - renamed into HAL_PCDEx_SetTxFiFo() - - - - - and HAL_PCDEx_SetRxFiFo() - - - - - and moved to the extension - files - stm32f4xx_hal_pcd_ex.h/.c
              • -
            • PCD_StateTypeDef structure - members renamed
              • -
            • Fix incorrect - masking of TxFIFOEmpty
              • -
            • stm32f4xx_ll_usb.c: - - - - fix issue in HS mode
              • -
            • New macros added
              • -
                -
              • __HAL_PCD_IS_PHY_SUSPENDED()
                • -
              • __HAL_USB_HS_EXTI_GENERATE_SWIT()
                • -
              • __HAL_USB_FS_EXTI_GENERATE_SWIT()
                • -
              -
            • These macro are renamed
              • -
                -
              • __HAL_GET_FLAG(__HANDLE__, - - - - - __INTERRUPT__)    - - - - by - __HAL_PCD_GET_FLAG(__HANDLE__, - __INTERRUPT__)
                • -
              • __HAL_CLEAR_FLAG(__HANDLE__, - - - - - __INTERRUPT__) by - __HAL_PCD_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) 
                • -
              • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  - - - - - by - __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)  -
                • -
              • __HAL_PCD_UNGATE_CLOCK(__HANDLE__) - - - - - by - __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
                • -
              • __HAL_PCD_GATE_CLOCK(__HANDLE__) - - - - - by - __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)
                • -
              -
            -
          • HAL - - - - ETH update
            • -
              -
            • Update HAL_ETH_GetReceivedFrame_IT() - function to return HAL_ERROR - if the received packet is not - complete
              • -
            • Use HAL_Delay() - instead of counting loop
              • -
            •  __HAL_ETH_MAC_CLEAR_FLAG() - macro is removed: the MACSR - register is read only
              • -
            • Add the - following macros used to Wake - up the device from STOP mode - by Ethernet event - - - - :
              • -
                -
              • __HAL_ETH_EXTI_ENABLE_IT()
                • -
              • __HAL_ETH_EXTI_DISABLE_IT()
                • -
              • __HAL_ETH_EXTI_GET_FLAG()
                • -
              • __HAL_ETH_EXTI_CLEAR_FLAG()
                • -
              • __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()
                • -
              • __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()
                • -
              • __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()
                • -
              -
            -
          • HAL - - - - WWDG update
            • -
              -
            • Update macro - parameters to use underscore: - __XXX__
              • -
            • Use of CMSIS - constants instead of magic values
              • -
            • Use - MODIFY_REG macro in HAL_WWDG_Init()
              • -
            • Add - IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() - and HAL_WWDG_DeInit()
              • -
            -
          • HAL - - - - IWDG update
            • -
              -
            • Use WRITE_REG - instead of SET_BIT for all - IWDG macros
              • -
            • __HAL_IWDG_CLEAR_FLAG - - - - - removed: no IWDG flag cleared - by access to SR register
              • -
            • Use - MODIFY_REG macro in HAL_IWDG_Init()
              • -
            • Add - IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()Add - - - - - the following macros used to - Wake
              • -
            -
          -

          V1.0.0 - - - - / 18-February-2014

          -

          Main Changes

          -
            -
          • First - - - - official release 
            • -
          -
          -

          For - - - - - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

          -
        -

         

        -
        -
        -

        -
        -
        -

         

        -
        -
        - \ No newline at end of file +
        +
        +

        Update History

        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and implementation enhancements.
          • +
        • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
          • +
        • HAL Generic update +
            +
          • Allow redefinition of macro UNUSED(x).
            • +
          • +
        • HAL RCC update +
            +
          • Correct the configuration macro of I2S clock source and the value of I2S external clock source.
            • +
          • Set the minimum value of PLLM.
            • +
          • Update the rest values for the macro __HAL_RCC_Axxx_FORCE_RESET() to avoid setting reserved bits.
            • +
          • +
        • HAL PWR update +
            +
          • Add a call to UNUSED() macro to avoid the generation of a warning related to the unused argument ‘Regulator’.
            • +
          • Add PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR mode to avoid systematic clear of event in HAL_PWR_EnterSLEEPMode() and HAL_PWR_EnterSTOPMode().
            • +
          • +
        • HAL Cortex update +
            +
          • Add the following new HAL/LL CORTEX APIs to clear PWR pending event: +
              +
            • LL_LPM_ClearEvent().
              • +
            • HAL_CORTEX_ClearEvent().
              • +
            • +
          • +
        • HAL EXTI update +
            +
          • Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine.
            • +
          • +
        • HAL/LL ADC update +
            +
          • Cast both LL_ADC_REG_ReadConversionData6() and LL_ADC_REG_ReadConversionData8() returned values from uint16_t to uint8_t to be consistent with prototypes.
            • +
          • Add a call to UNUSED() macro in LL_ADC_DMA_GetRegAddr() API to prevent compilation warning due to unused ‘Register’ parameter.
            • +
          • +
        • HAL DAC update +
            +
          • Fix incorrect word ‘surcharged’ in functions headers.
            • +
          • Updated DAC buffer calibration according to RM.
            • +
          • +
        • HAL CEC update +
            +
          • Better performance by removing multiple volatile reads or writes in interrupt handler.
            • +
          • +
        • HAL RTC update +
            +
          • Check if the RTC calendar has been previously initialized before entering initialization mode.
            • +
          • Remove macro __HAL_RTC_TAMPER_GET_IT() as it is redundant with macro __HAL_RTC_TAMPER_GET_FLAG() and create an alias into the stm32_hal_legacy.h file.
            • +
          • Correct misleading note about shadow registers.
            • +
          • +
        • HAL CRYP update +
            +
          • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment.
            • +
          • +
        • HAL HASH update +
            +
          • HAL code quality enhancement for MISRA-C2012 Rule-2.2_c.
            • +
          • +
        • HAL TIM update +
            +
          • Align TIM_TIM2_ETH_PTP definition with the reference manual specification.
            • +
          • Improve driver robustness against wrong period values.
            • +
          • Improve driver robustness against wrong DMA related parameters.
            • +
          • Improve period configuration parameter check.
            • +
          • Remove Lock management from callback management functions.
            • +
          • Remove multiple volatile reads or writes in interrupt handler for better performance.
            • +
          • Improve HAL TIM driver’s operational behavior.
            • +
          • Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init().
            • +
          • +
        • HAL LPTIM update +
            +
          • Apply same naming rules to clear FLAG related functions.
            • +
          • Remove Lock management from callback management functions.
            • +
          • +
        • HAL CAN update +
            +
          • Removal of never reached code.
            • +
          • Improve protection against bad inputs.
            • +
          • +
        • HAL DSI update +
            +
          • Update to align DSI ULPS entry and exit sequences with reference manual.
            • +
          • +
        • HAL ETH update +
            +
          • Update Rx descriptor tail pointer management to avoid race condition.
            • +
          • +
        • HAL UART update +
            +
          • New API HAL_UARTEx_GetRxEventType() to retrieve the type of event that has led the RxEventCallback execution.
            • +
          • Removal of HAL_LOCK/HAL_UNLOCK() calls in HAL UART Tx and Rx APIs.
            • +
          • Removal of __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
            • +
          • Avoid ORE flag to be cleared by a transmit process in polling mode.
            • +
          • Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.
            • +
          • +
        • HAL USART update +
            +
          • Removal of __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
            • +
          • +
        • HAL I2C update +
            +
          • Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA.
            • +
          • Update I2C_MemoryTransmit_TXE_BTF process to disable TXE and BTF interrupts if nothing to do.
            • +
          • Clear TXE Flag at the end of transfer.
            • +
          • Move polling code of HAL memory interface through interrupt management to prevent timeout issue using HAL MEM interface through FreeRTOS.
            • +
          • Update I2C_IsErrorOccurred to return error if timeout is detected.
            • +
          • Clear the ADDRF flag only when direction is confirmed as changed, to prevent that the ADDRF flag is cleared too early when the restart is received.
            • +
          • Update HAL_I2C_Master_Transmit_IT to return HAL_BUSY instead of HAL_ERROR when timeout occur and I2C_FLAG_BUSY is SET.
            • +
          • Clear ACK bit once 3 bytes to read remain to be able to send the NACK once the transfer ends.
            • +
          • Duplicate the test condition after timeout detection to avoid false timeout detection.
            • +
          • Update HAL_I2C_IsDeviceReady() API to support 10_bit addressing mode: macro I2C_GENERATE_START is updated.
            • +
          • Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
            • +
          • Update the HAL I2C driver to disactivate all interrupts after the end of transaction.
            • +
          • Update HAL_I2C_Init API to clear ADD10 bit in 7 bit addressing mode.
            • +
          • Solve Slave No stretch not functional by using HAL Slave interface.
            • +
          • Update HAL_FMPI2C_Mem_Write_IT API to initialize XferSize at 0.
            • +
          • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice.
            • +
          • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE.
            • +
          • Clear ACK bit once 3 bytes to read remain to be able to send the NACK once the transfer ends.
            • +
          • Remove the unusable code in function HAL_I2C_IsDeviceReady.
            • +
          • Update HAL_I2C_Master_Abort_IT to support memory abort transfer.
            • +
          • Update LL_I2C_HandleTranfer function to prevent undefined behavior of volatile usage before updating the CR2 register.
            • +
          • Update I2C_WaitOnFlagUntilTimeout to handle error case.
            • +
          • Update the HAL I2C driver to reset PreviousState to I2C_STATE_NONE at the end of transfer.
            • +
          • +
        • HAL SMBUS update +
            +
          • Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master.
            • +
          • Add flush on TX register.
            • +
          • Change previous state from HAL_SMBUS_STATE_READY to HAL_SMBUS_STATE_NONE at the end of transfer.
            • +
          • Update HAL SMBUS driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
            • +
          • +
        • HAL SAI update +
            +
          • Improve audio quality (avoid potential glitch).
            • +
          • Fix incorrect word ‘surcharged’.
            • +
          • +
        • HAL SPI update +
            +
          • Fix driver to don’t update state in case of error (HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT).
            • +
          • Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of one byte transaction.
            • +
          • Update IT API to enable interrupts after process unlock.
            • +
          • Add wait on flag TXE to be set at the end of transaction to be aligned with reference manual.
            • +
          • +
        • HAL SPDIFRX update +
            +
          • Prevent hard fault by checking DMA usage.
            • +
          • Tuning of default SPDIFRX timeout.
            • +
          • +
        • HAL USB OTG update +
            +
          • ll_usb.c fix added to USB_ClearInterrupts(), should write “1” to clear the interrupt status bits of OTG_FS_GINTSTS register.
            • +
          • ll_usb.c: remove useless software setting to setup the frame interval at 80%.
            • +
          • ll_usb.c, hal_hcd.c: adding support of hub split transactions.
            • +
          • ll_usb.c: improve delay management to set core mode.
            • +
          • ll_usb.c, hal_pcd.c: fix device connection in case battery charging used with HS instance linked to internal FS PHY.
            • +
          • ll_usb.c: increase timeout value to allow core reset to complete.
            • +
          • +
        • HAL IRDA update +
            +
          • Removal of __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
            • +
          • +
        • HAL SMARTCARD update +
            +
          • Removal of __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
            • +
          • +
        • HAL SDMMC update +
            +
          • Update HAL SD processes to manage STBITERR flag.
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix HAL ETH defects and implementation enhancements.
          • +
        • HAL updates +
            +
          • HAL ETH update +
              +
            • Remove useless assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)) from static function ETH_MACAddressConfig().
              • +
            • Replace hard coded Rx buffer size (1000U) by macro ETH_RX_BUF_SIZE.
              • +
            • Correct bit positions when getting MAC and DMA configurations and replace ‘UnicastSlowProtocolPacketDetect’ by ‘UnicastPausePacketDetect’ in the MAC default configuration structure.
              • +
            • Ensure a delay of 4 TX_CLK/RX_CLK cycles between two successive write operations to the same register.
              • +
            • Disable DMA transmission in both HAL_ETH_Stop_IT() and HAL_ETH_Stop() APIs.
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and implementation enhancements.
          • +
        • All source files: update disclaimer to add reference to the new license agreement.
          • +
        • The following changes done on the HAL drivers require an update of the application code based on older HAL versions +
            +
          • Rework of HAL Ethernet driver to resolve problems and improve performance (compatibility break).
            • +
          • A new HAL Ethernet driver has been redesigned with new APIs, to bypass limitations with previous HAL Ethernet driver version.
            • +
          • The new HAL Ethernet driver is the recommended version. It is located as usual in Drivers/STM32F4xx_HAL_Driver/Src and Drivers/STM32F4xx_HAL_Driver/Inc folders. +
              +
            • It can be enabled through switch HAL_ETH_MODULE_ENABLED in stm32f4xx_hal_conf.h
              • +
            • +
          • The legacy HAL Ethernet driver is also present in the release in Drivers/STM32F4xx_HAL_Driver/Src/Legacy and Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software compatibility reasons. +
              +
            • Its usage is not recommended as deprecated. It can however be enabled through switch HAL_ETH_LEGACY_MODULE_ENABLED in stm32f4xx_hal_conf.h
              • +
            • +
          • +
        • HAL update +
            +
          • HAL ETH update +
              +
            • Entire receive process reworked.
              • +
            • Resolve the problem of received data corruption.
              • +
            • Implement transmission in interrupt mode.
              • +
            • Handle one interrupt for multiple transmitted packets.
              • +
            • Implement APIs to handle PTP feature.
              • +
            • Implement APIs to handle Timestamp feature.
              • +
            • Add support of receive buffer unavailable.
              • +
            • Update HAL_ETH_IRQHandler() to handle receive buffer unavailable.
              • +
            • +
          • HAL SMBUS update +
              +
            • Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master. +
                +
              • Add flush on TX register.
                • +
              • +
            • +
          • HAL TIM update +
              +
            • __LL_TIM_CALC_PSC() macro update to round up the evaluate value when the fractional part of the division is greater than 0.5.
              • +
            • +
          • HAL LPTIM update +
              +
            • Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()
              • +
            • +
          • HAL UART update +
              +
            • Add const qualifier for read only pointers.
              • +
            • Improve header description of UART_WaitOnFlagUntilTimeout() function.
              • +
            • Add a check on the UART parity before enabling the parity error interruption.
              • +
            • Fix typo in UART_IT_TXE bit description.
              • +
            • +
          • HAL IRDA update +
              +
            • Improve header description of IRDA_WaitOnFlagUntilTimeout() function.
              • +
            • Add a check on the IRDA parity before enabling the parity error interrupt.
              • +
            • Add const qualifier for read only pointers.
              • +
            • +
          • HAL SMARTCARD update +
              +
            • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function
              • +
            • Add const qualifier for read only pointers.
              • +
            • +
          • HAL NOR update +
              +
            • Apply adequate commands according to the command set field value
              • +
            • command set 1 for Micron JS28F512P33
              • +
            • command set 2 for Micron M29W128G and Cypress S29GL128P
              • +
            • Add new command operations: +
                +
              • NOR_CMD_READ_ARRAY
                • +
              • NOR_CMD_WORD_PROGRAM
                • +
              • NOR_CMD_BUFFERED_PROGRAM
                • +
              • NOR_CMD_CONFIRM
                • +
              • NOR_CMD_BLOCK_ERASE
                • +
              • NOR_CMD_BLOCK_UNLOCK
                • +
              • NOR_CMD_READ_STATUS_REG
                • +
              • NOR_CMD_CLEAR_STATUS_REG
                • +
              • +
            • Update some APIs in order to be compliant for memories with different command set, the updated APIs are: +
                +
              • HAL_NOR_Init()
                • +
              • HAL_NOR_Read_ID()
                • +
              • HAL_NOR_ReturnToReadMode()
                • +
              • HAL_NOR_Read()
                • +
              • HAL_NOR_Program()
                • +
              • HAL_NOR_ReadBuffer()
                • +
              • HAL_NOR_ProgramBuffer()
                • +
              • HAL_NOR_Erase_Block()
                • +
              • HAL_NOR_Erase_Chip()
                • +
              • HAL_NOR_GetStatus()
                • +
              • +
            • Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.
              • +
            • +
          • HAL SDMMC update +
              +
            • Take into account the voltage range in the CMD1 command.
              • +
            • Add new LL function to have correct response for MMC driver.
              • +
            • Update the driver to have all fields correctly initialized.
              • +
            • Add an internal variable to manage the power class and call it before to update speed of bus width.
              • +
            • Add new API to get the value of the Extended CSD register and populate the ExtCSD field of the MMC handle.
              • +
            • In HAL_MMC_InitCard(), call to SDIO_PowerState_ON() moved after __HAL_MMC_ENABLE() to ensure MMC clock is enabled before the call to HAL_Delay() from within SDIO_PowerState_ON().
              • +
            • +
          • HAL DMA update +
              +
            • Manage the case of an invalid value of CallbackID passed to the HAL_DMA_RegisterCallback() API.
              • +
            • +
          • HAL LTDC update +
              +
            • Update HAL_LTDC_DeInit() to fix MCU Hang up during LCD turn OFF.
              • +
            • +
          • HAL I2C update +
              +
            • Update to fix issue detected due to low system frequency execution (HSI).
              • +
            • Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA
              • +
            • Update HAL I2C Master Receive IT process to safe manage data N= 2 and N= 3. +
                +
              • Disable RxNE interrupt if nothing to do.
                • +
              • +
            • +
          • HAL USART update +
              +
            • Improve header description of USART_WaitOnFlagUntilTimeout() function.
              • +
            • Add a check on the USART parity before enabling the parity error interrupt.
              • +
            • Add const qualifier for read only pointers.
              • +
            • +
          • HAL/LL ADC update +
              +
            • Update LL_ADC_IsActiveFlag_MST_EOCS() API to get the appropriate flag.
              • +
            • Better performance by removing multiple volatile reads or writes in interrupt handler.
              • +
            • +
          • HAL FMPI2C update +
              +
            • Update to handle errors in polling mode. +
                +
              • Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.
                • +
              • +
            • +
          • HAL EXTI update +
              +
            • Update HAL_EXTI_GetConfigLine() API to fix wrong calculation of GPIOSel value.
              • +
            • +
          • HAL QSPI update +
              +
            • Update HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() APIs to check on QSPI BUSY flag status before executing the abort procedure.
              • +
            • +
          • HAL/LL RTC cleanup +
              +
            • Use bits definitions from CMSIS Device header file instead of hard-coded values.
              • +
            • Wrap comments to be 80-character long and correct typos.
              • +
            • Move constants RTC_IT_TAMP. from hal_rtc.h to hal_rtc_ex.h.
              • +
            • Gather all instructions related to exiting the “init” mode into new function RTC_ExitInitMode().
              • +
            • Add new macro assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)) to check tamper filtering is disabled in case tamper events are triggered on signal edges.
              • +
            • Rework functions HAL_RTCEx_SetTamper() and HAL_RTCEx_SetTamper_IT() to: +
                +
              • Write in TAFCR register in one single access instead of two.
                • +
              • Avoid modifying user structure sTamper.
                • +
              • +
            • Remove functions LL_RTC_EnablePushPullMode() and LL_RTC_DisablePushPullMode() as related to non-supported features.
              • +
            • Remove any reference to non-supported features (e.g., LL_RTC_ISR_TAMP3F).
              • +
            • Remove useless conditional defines as corresponding features are supported by all part-numbers (e.g., #if defined(RTC_TAFCR_TAMPPRCH)).
              • +
            • +
          • HAL USB OTG update +
              +
            • Fix USB_FlushRxFifo() and USB_FlushTxFifo() APIs by adding check on AHB master IDLE state before flushing the USB FIFO
              • +
            • Fix to avoid resetting host channel direction during channel halt
              • +
            • Fix to report correct received amount of data with USB DMA enabled
              • +
            • Fix to avoid compiler optimization on count variable used for USB HAL timeout loop check
              • +
            • Add missing registered callbacks check for HAL_HCD_HC_NotifyURBChange_Callback()
              • +
            • Add new API HAL_PCD_SetTestMode() APIs to handle USB device high speed Test modes
              • +
            • Setting SNAK for EPs not required during device reset
              • +
            • Update USB IRQ handler to enable EP OUT disable
              • +
            • Add support of USB IN/OUT Iso incomplete
              • +
            • Fix USB BCD data contact timeout
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • HAL update +
            +
          • HAL EXTI update +
              +
            • Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.
              • +
            • +
          • HAL GPIO update +
              +
            • Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.
              • +
            • +
          • HAL DMA update +
              +
            • Update HAL_DMA_IRQHandler() API to set the DMA state before unlocking access to the DMA handle.
              • +
            • +
          • LL ADC update +
              +
            • Update LL_ADC_DeInit() API to clear missing SQR3 register.
              • +
            • +
          • HAL CAN update +
              +
            • Update HAL_CAN_Init() API to be aligned with reference manual and to avoid timeout error.
              • +
            • +
          • HAL/LL RTC_BKP update +
              +
            • Update __HAL_RTC_…(__HANDLE__, …) macros to access registers through (__HANDLE__)->Instance pointer and avoid “unused variable” warnings.
              • +
            • Correct month management in IS_LL_RTC_MONTH() macro.
              • +
            • +
          • HAL RNG update +
              +
            • Update timeout mechanism to avoid false timeout detection in case of preemption.
              • +
            • +
          • HAL QSPI update +
              +
            • ES0305 workaround disabled for STM32412xx devices.
              • +
            • +
          • HAL I2C update +
              +
            • Update HAL_I2C_Mem_Write_DMA() and HAL_I2C_Mem_Read_DMA() APIs to initialize Devaddress, Memaddress and EventCount parameters.
              • +
            • Update to prevent several calls of Start bit: +
                +
              • Update I2C_MemoryTransmit_TXE_BTF() API to increment EventCount.
                • +
              • +
            • Update to avoid I2C interrupt in endless loop: +
                +
              • Update HAL_I2C_Master_Transmit_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA() and HAL_I2C_Master_Receive_DMA() APIs to unlock the I2C peripheral before generating the start.
                • +
              • +
            • Update to use the right macro to clear I2C ADDR flag inside I2C_Slave_ADDR() API as it’s indicated in the reference manual.
              • +
            • Update I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting register address.
              • +
            • Update HAL_I2C_EV_IRQHandler() and I2C_MasterTransmit_BTF() APIs to correctly manage memory transfers: +
                +
              • Add check on memory mode before calling callbacks procedures.
                • +
              • +
            • +
          • LL USART update +
              +
            • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)
              • +
            • +
          • HAL SMBUS update +
              +
            • Updated HAL_SMBUS_ER_IRQHandler() API to return the correct error code “SMBUS_FLAG_PECERR” in case of packet error occurs.
              • +
            • +
          • HAL/LL SPI update +
              +
            • Updated to fix MISRA-C 2012 Rule-13.2.
              • +
            • Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits.
              • +
            • +
          • HAL UART update +
              +
            • Fix wrong comment related to RX pin configuration within the description section
              • +
            • Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback
              • +
            • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART) +
                +
              • Update CAN Initialization sequence to set “request initialization” bit before exit from sleep mode.
                • +
              • +
            • +
          • HAL USB update +
              +
            • HAL PCD: add fix transfer complete for IN Interrupt transaction in single buffer mode
              • +
            • Race condition in USB PCD control endpoint receive ISR.
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • HAL +
            +
          • HAL/LL USART update +
              +
            • Fix typo in USART_Receive_IT() and USART_TransmitReceive_IT() APIs to avoid possible compilation issues if the UART driver files are not included.
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          • +
        • Added new HAL FMPSMBUS extended driver to support FMPSMBUS fast Mode Plus.
          • +
        • Removed “register” keyword to be compliant with new C++ rules: +
            +
          • The register storage class specifier was deprecated in C++11 and removed in C++17.
            • +
          • +
        • HAL +
            +
          • HAL update
            • +
          • General updates to fix known defects and enhancements implementation.
            • +
          • Added new defines for ARM compiler V6: +
              +
            • __weak
              • +
            • __packed
              • +
            • __NOINLINE
              • +
            • +
          • Updated HAL TimeBase TIM, RTC alarm and RTC WakeUp templates for more robustness +
              +
            • Updated Hal_Init_Tick() API to properly store the priority when using the non-default time base.
              • +
            • +
          • Updated PPP_MODULE_ENABLED for FMPSMBUS.
            • +
          • HAL/LL ADC update +
              +
            • Updated to add include of the LL ADC driver.
              • +
            • Updated the following APIs to set status HAL_ADC_STATE_ERROR_INTERNAL and error code HAL_ADC_ERROR_INTERNAL when error occurs: +
                +
              • HAL_ADC_Start()
                • +
              • HAL_ADC_Start_IT()
                • +
              • HAL_ADC_Start_DMA()
                • +
              • HAL_ADCEx_InjectedStart()
                • +
              • HAL_ADCEx_InjectedStart_IT()
                • +
              • HAL_ADCEx_MultiModeStart_DMA()
                • +
              • +
            • Updated HAL_ADC_Stop_DMA() API to check if DMA state is Busy before calling HAL_DMA_Abort() API to avoid DMA internal error.
              • +
            • Updated IS_ADC_CHANNEL to support temperature sensor for: +
                +
              • STM32F411xE
                • +
              • STM32F413xx
                • +
              • STM32F423xx
                • +
              • +
            • Fixed wrong defined values for: +
                +
              • LL_ADC_MULTI_REG_DMA_LIMIT_3
                • +
              • LL_ADC_MULTI_REG_DMA_UNLMT_3
                • +
              • +
            • Added __LL_ADC_CALC_VREFANALOG_VOLTAGE() macro to evaluate analog reference voltage.
              • +
            • Removed __LL_ADC_CALC_TEMPERATURE() macro for STM32F4x9 devices as the TS_CAL2 is not available.
              • +
            • +
          • HAL/LL DAC update +
              +
            • Added restruction on DAC Channel 2 defines and parameters.
              • +
            • HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID used instead of HAL_DAC_MSP_INIT_CB_ID and HAL_DAC_MSP_DEINIT_CB_ID.
              • +
            • Updated to support dual mode: +
                +
              • Added two new APIs: +
                  +
                • HAL_DACEx_DualStart()
                  • +
                • HAL_DACEx_DualStop()
                  • +
                • +
              • +
            • Added position bit definition to be used instead of __DAC_MASK_SHIFT macro +
                +
              • __DAC_MASK_SHIFT macro has been removed.
                • +
              • +
            • Updated HAL_DAC_Start_DMA() API to return HAL_ERROR when error occurs.
              • +
            • Updated HAL_DAC_Stop_DMA() API to not return HAL_ERROR when DAC is already disabled.
              • +
            • +
          • HAL CEC update +
              +
            • Updated HAL_CEC_IRQHandler() API to avoid appending an extra byte to the end of a message.
              • +
            • +
          • HAL/LL GPIO update +
              +
            • Updated IS_GPIO_AF() to add missing values for STM32F401xC and STM32F401xE devices: +
                +
              • GPIO_AF3_TIM9
                • +
              • GPIO_AF3_TIM10
                • +
              • GPIO_AF3_TIM11
                • +
              • +
            • Updated LL/HAL GPIO_TogglePin() APIs to allow multi Pin’s toggling.
              • +
            • Updated HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.
              • +
            • +
          • HAL/LL RCC update +
              +
            • Updated HAL_RCC_OscConfig() API to add missing checks and to don’t return HAL_ERROR if request repeats the current PLL configuration.
              • +
            • Updated IS_RCC_PLLN_VALUE(VALUE) macro in case of STM32F411xE device in order to be aligned with reference manual.
              • +
            • +
          • HAL SD update +
              +
            • Update function SD_FindSCR() to resolve issue of FIFO blocking when reading.
              • +
            • Update read/write functions in DMA mode in order to force the DMA direction, updated functions: +
                +
              • HAL_SD_ReadBlocks_DMA()
                • +
              • HAL_SD_WriteBlocks_DMA()
                • +
              • +
            • Add the block size settings in the initialization functions and remove it from read/write transactions to avoid repeated and inefficient reconfiguration, updated functions: +
                +
              • HAL_SD_InitCard()
                • +
              • HAL_SD_GetCardStatus()
                • +
              • HAL_SD_ConfigWideBusOperation()
                • +
              • HAL_SD_ReadBlocks()
                • +
              • HAL_SD_WriteBlocks()
                • +
              • HAL_SD_ReadBlocks_IT()
                • +
              • HAL_SD_WriteBlocks_IT()
                • +
              • HAL_SD_ReadBlocks_DMA()
                • +
              • HAL_SD_WriteBlocks_DMA()
                • +
              • +
            • +
          • HAL MMC update +
              +
            • Add the block size settings in the initialization function and remove it from read/write transactions to avoid repeated and inefficient reconfiguration, updated functions: +
                +
              • HAL_MMC_InitCard()
                • +
              • HAL_MMC_ReadBlocks()
                • +
              • HAL_MMC_WriteBlocks()
                • +
              • HAL_MMC_ReadBlocks_IT()
                • +
              • HAL_MMC_WriteBlocks_IT()
                • +
              • HAL_MMC_ReadBlocks_DMA()
                • +
              • HAL_MMC_WriteBlocks_DMA()
                • +
              • +
            • Update read/write functions in DMA mode in order to force the DMA direction, updated functions: +
                +
              • HAL_MMC_ReadBlocks_DMA()
                • +
              • HAL_MMC_WriteBlocks_DMA()
                • +
              • +
            • Deploy new functions MMC_ReadExtCSD() and SDMMC_CmdSendEXTCSD () that read and check the sectors number of the device in order to resolve the issue of wrongly reading big memory size.
              • +
            • +
          • HAL NAND update +
              +
            • Update functions HAL_NAND_Read_SpareArea_16b() and HAL_NAND_Write_SpareArea_16b() to fix column address calculation issue.
              • +
            • +
          • LL SDMMC update +
              +
            • Update the definition of SDMMC_DATATIMEOUT constant in order to allow the user to redefine it in his proper application.
              • +
            • Remove ‘register’ storage class specifier from LL SDMMC driver.
              • +
            • Deploy new functions MMC_ReadExtCSD() and SDMMC_CmdSendEXTCSD () that read and check the sectors number of the device in order to resolve the issue of wrongly reading big memory size.
              • +
            • +
          • HAL SMBUS update +
              +
            • Support for Fast Mode Plus to be SMBUS rev 3 compliant.
              • +
            • Added HAL_FMPSMBUSEx_EnableFastModePlus() and HAL_FMPSMBUSEx_DisableFastModePlus() APIs to manage Fm+.
              • +
            • Updated SMBUS_MasterTransmit_BTF() , SMBUS_MasterTransmit_TXE() and SMBUS_MasterReceive_BTF() APIs to allow stop generation when CurrentXferOptions is different from SMBUS_FIRST_FRAME and SMBUS_NEXT_FRAME.
              • +
            • Updated SMBUS_ITError() API to correct the twice call of HAL_SMBUS_ErrorCallback.
              • +
            • +
          • HAL SPI update +
              +
            • Updated HAL_SPI_Init() API +
                +
              • To avoid setting the BaudRatePrescaler in case of Slave Motorola Mode.
                • +
              • Use the bit-mask for SPI configuration.
                • +
              • +
            • Updated Transmit/Receive processes in half-duplex mode +
                +
              • Disable the SPI instance before setting BDIOE bit.
                • +
              • +
            • Fixed wrong timeout management
              • +
            • Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled.
              • +
            • +
          • HAL SPDIFRX update +
              +
            • Remove ‘register’ storage class specifier from HAL SPDIFRX driver.
              • +
            • +
          • HAL I2S update +
              +
            • Updated I2SEx APIs to correctly support circular transfers +
                +
              • Updated I2SEx_TxRxDMACplt() API to manage DMA circular mode.
                • +
              • +
            • Updated HAL_I2SEx_TransmitReceive_DMA() API to set hdmatx (transfer callback and half) to NULL.
              • +
            • +
          • HAL SAI update +
              +
            • Updated to avoid the incorrect left/right synchronization. +
                +
              • Updated HAL_SAI_Transmit_DMA() API to follow the sequence described in the reference manual for slave transmitter mode.
                • +
              • +
            • Updated HAL_SAI_Init() API to correct the formula in case of SPDIF is wrong.
              • +
            • +
          • HAL CRYP update +
              +
            • Updated HAL_CRYP_SetConfig() and HAL_CRYP_GetConfig() APIs to set/get the continent of KeyIVConfigSkip correctly.
              • +
            • +
          • HAL EXTI update +
              +
            • __EXTI_LINE__ is now used instead of __LINE__ which is a standard C macro.
              • +
            • +
          • HAL DCMI +
              +
            • Support of HAL callback registration feature for DCMI extended driver.
              • +
            • +
          • HAL/LL TIM update +
              +
            • Updated HAL_TIMEx_OnePulseN_Start() and HAL_TIMEx_OnePulseN_Stop() APIs (pooling and IT mode) to take into consideration all OutputChannel parameters.
              • +
            • Corrected reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode.
              • +
            • Updated LL_TIM_GetCounterMode() API to return the correct counter mode.
              • +
            • +
          • HAL/LL SMARTCARD update +
              +
            • Fixed invalid initialization of SMARTCARD configuration by removing FIFO mode configuration as it is not member of SMARTCARD_InitTypeDef Structure.
              • +
            • Fixed typos in SMARTCARD State definition description
              • +
            • +
          • HAL/LL IRDA update +
              +
            • Fixed typos in IRDA State definition description
              • +
            • +
          • LL USART update +
              +
            • Remove useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro.
              • +
            • Update USART polling and interruption processes to fix issues related to accesses out of user specified buffer.
              • +
            • +
          • HAL USB update +
              +
            • Enhanced USB OTG host HAL with USB DMA is enabled: +
                +
              • fixed ping and data toggle issue,
                • +
              • reworked Channel error report management
                • +
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects.
          • +
        • HAL/LL I2C update +
            +
          • Update to fix hardfault issue with HAL_I2C_Mem_Write_DMA() API: +
              +
            • Abort the right ongoing DMA transfer when memory write access request operation failed: fix typo “hdmarx” replaced by “hdmatx”
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          • +
        • HAL/LL I2C update +
            +
          • Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes +
              +
            • Add stop condition generation when NACK occurs.
              • +
            • +
          • Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer). +
              +
            • Add additional check on hi2c->hdmtx and hi2c->hdmarx before resetting DMA Tx/Rx complete callbacks
              • +
            • +
          • Update Sequential transfer APIs to adjust xfermode condition. +
              +
            • Replace hi2c->XferCount < MAX_NBYTE_SIZE by hi2c->XferCount <= MAX_NBYTE_SIZE which corresponds to a case without reload
              • +
            • +
          • +
        • HAL/LL USB update +
            +
          • Bug fix: USB_ReadPMA() and USB_WritePMA() by ensuring 16-bits access to USB PMA memory
            • +
          • Bug fix: correct USB RX count calculation
            • +
          • Fix USB Bulk transfer double buffer mode
            • +
          • Remove register keyword from USB defined macros as no more supported by C++ compiler
            • +
          • Minor rework on USBD_Start() and USBD_Stop() APIs: stopping device will be handled by HAL_PCD_DeInit() API.
            • +
          • Remove non used API for USB device mode.
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add new HAL FMPSMBUS and LL FMPI2C drivers
          • +
        • General updates to fix known defects and enhancements implementation
          • +
        • Update HAL CRYP driver to support block by block decryption without reinitializes the IV and KEY for each call.
          • +
        • Improve code quality by fixing MisraC-2012 violations
          • +
        • HAL/LL USB update +
            +
          • Add handling USB host babble error interrupt
            • +
          • Fix Enabling ULPI interface for platforms that integrates USB HS PHY
            • +
          • Fix Host data toggling for IN Iso transfers
            • +
          • Ensure to disable USB EP during endpoint deactivation
            • +
          • +
        • HAL CRYP update +
            +
          • Update HAL CRYP driver to support block by block decryption without initializing the IV and KEY at each call. +
              +
            • Add new CRYP Handler parameters: “KeyIVConfig” and “SizesSum”
              • +
            • Add new CRYP init parameter: "KeyIVConfigSkip
              • +
            • +
          • +
        • HAL I2S update +
            +
          • Update HAL_I2S_DMAStop() API to be more safe +
              +
            • Add a check on BSY, TXE and RXNE flags before disabling the I2S
              • +
            • +
          • Update HAL_I2S_DMAStop() API to fix multi-call transfer issue(to avoid re-initializing the I2S for the next transfer). +
              +
            • Add __HAL_I2SEXT_FLUSH_RX_DR() and __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside DR registers.
              • +
            • Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          • +
        • HAL Generic update +
            +
          • HAL_SetTickFreq(): update to restore the previous tick frequency when HAL_InitTick() configuration failed.
            • +
          • +
        • HAL/LL GPIO update +
            +
          • Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s
            • +
          • +
        • HAL EXTI update +
            +
          • General update to enhance HAL EXTI driver robustness +
              +
            • Add additional assert check on EXTI config lines
              • +
            • Update to compute EXTI line mask before read/write access to EXTI registers
              • +
            • +
          • Update EXTI callbacks management to be compliant with reference manual: only one PR register for rising and falling interrupts. +
              +
            • Update parameters in EXTI_HandleTypeDef structure: merge HAL EXTI RisingCallback and FallingCallback in only one PendingCallback
              • +
            • Remove HAL_EXTI_RISING_CB_ID and HAL_EXTI_FALLING_CB_ID values from EXTI_CallbackIDTypeDef enumeration.
              • +
            • +
          • Update HAL_EXTI_IRQHandler() API to serve interrupts correctly. +
              +
            • Update to compute EXTI line mask before handle EXTI interrupt.
              • +
            • +
          • Update to support GPIO port interrupts: +
              +
            • Add new “GPIOSel” parameter in EXTI_ConfigTypeDef structure
              • +
            • +
          • +
        • HAL/LL RCC update +
            +
          • Update HAL_RCCEx_PeriphCLKConfig() API to support PLLI2S configuration for STM32F42xxx and STM32F43xxx devices
            • +
          • Update the HAL_RCC_ClockConfig() and HAL_RCC_DeInit() API to don’t overwrite the custom tick priority
            • +
          • Fix LL_RCC_DeInit() failure detected with gcc compiler and high optimization level is selected(-03)
            • +
          • Update HAL_RCC_OscConfig() API to don’t return HAL_ERROR if request repeats the current PLL configuration
            • +
          • +
        • HAL ADC update +
            +
          • Update LL_ADC_REG_Init() to fix wrong ADC CR1 register configuration +
              +
            • The ADC sequencer length is part of ADC SQR1 register not of ADC CR1 register
              • +
            • +
          • +
        • HAL CRYP update +
            +
          • Update HAL_CRYP_Encrypt() and HAL_CRYP_Decrypt() APIs to take into consideration the datatype fed to the DIN register (1-, 8-, 16-, or 32-bit data) when padding the last block of the payload, in case the size of this last block is less than 128 bits.
            • +
          • +
        • HAL RNG update +
            +
          • Update HAL_RNG_IRQHandler() API to fix error code management issue: error code is assigned “HAL_RNG_ERROR_CLOCK” in case of clock error and “HAL_RNG_ERROR_SEED” in case of seed error, not the opposite.
            • +
          • +
        • HAL DFSDM update +
            +
          • Update DFSDM_GetChannelFromInstance() API to remove unreachable check condition
            • +
          • +
        • HAL DMA update +
            +
          • Update HAL_DMA_Start_IT() API to omit the FIFO error
            • +
          • +
        • HAL FLASH update +
            +
          • Update FLASH_Program_DoubleWord() API to fix with EWARM high level optimization issue
            • +
          • +
        • HAL QSPI update +
            +
          • Remove Lock mechanism from HAL_QSPI_Init() and HAL_QSPI_DeInit() APIs
            • +
          • +
        • HAL HASH update +
            +
          • Null pointer on handler “hhash” is now checked before accessing structure member “hhash->Init.DataType” in the following API: +
              +
            • HAL_HASH_Init()
              • +
            • +
          • Following interrupt-based APIs have been added. Interrupt mode could allow the MCU to enter “Sleep” mode while a data block is being processed. Please refer to the “##### How to use this driver #####” section for details about their use. +
              +
            • HAL_HASH_SHA1_Accmlt_IT()
              • +
            • HAL_HASH_MD5_Accmlt_IT()
              • +
            • HAL_HASHEx_SHA224_Accmlt_IT()
              • +
            • HAL_HASHEx_SHA256_Accmlt_IT()
              • +
            • +
          • Following aliases have been added (just for clarity sake) as they shall be used at the end of the computation of a multi-buffers message and not at the start: +
              +
            • HAL_HASH_SHA1_Accmlt_End() to be used instead of HAL_HASH_SHA1_Start()
              • +
            • HAL_HASH_MD5_Accmlt_End() to be used instead of HAL_HASH_MD5_Start()
              • +
            • HAL_HASH_SHA1_Accmlt_End_IT() to be used instead of HAL_HASH_SHA1_Start_IT()
              • +
            • HAL_HASH_MD5_Accmlt_End_IT() to be used instead of HAL_HASH_MD5_Start_IT()
              • +
            • HAL_HASHEx_SHA224_Accmlt_End() to be used instead of HAL_HASHEx_SHA224_Start()
              • +
            • HAL_HASHEx_SHA256_Accmlt_End() to be used instead of HAL_HASHEx_SHA256_Start()
              • +
            • HAL_HASHEx_SHA224_Accmlt_End_IT() to be used instead of HAL_HASHEx_SHA224_Start_IT()
              • +
            • HAL_HASHEx_SHA256_Accmlt_End_IT() to be used instead of HAL_HASHEx_SHA256_Start_IT()
              • +
            • +
          • MISRAC-2012 rule R.5.1 (identifiers shall be distinct in the first 31 characters) constrained the naming of the above listed aliases (e.g. HAL_HASHEx_SHA256_Accmlt_End() could not be named HAL_HASHEx_SHA256_Accumulate_End(). Otherwise the name would have conflicted with HAL_HASHEx_SHA256_Accumulate_End_IT()). In order to have aligned names following APIs have been renamed: +
              +
            • HAL_HASH_MD5_Accumulate() renamed HAL_HASH_MD5_Accmlt()
              • +
            • HAL_HASH_SHA1_Accumulate() renamed HAL_HASH_SHA1_Accmlt()
              • +
            • HAL_HASHEx_SHA224_Accumulate() renamed HAL_HASHEx_SHA224_Accmlt()
              • +
            • HAL_HASHEx_SHA256_Accumulate() renamed HAL_HASHEx_SHA256_Accmlt()
              • +
            • +
          • HASH handler state is no more reset to HAL_HASH_STATE_READY once DMA has been started in the following APIs: +
              +
            • HAL_HASH_MD5_Start_DMA()
              • +
            • HAL_HMAC_MD5_Start_DMA()
              • +
            • HAL_HASH_SHA1_Start_DMA()
              • +
            • HAL_HMAC_SHA1_Start_DMA()
              • +
            • +
          • HASH phase state is now set to HAL_HASH_PHASE_READY once the digest has been read in the following APIs: +
              +
            • HASH_IT()
              • +
            • HMAC_Processing()
              • +
            • HASH_Start()
              • +
            • HASH_Finish()
              • +
            • +
          • Case of a large buffer scattered around in memory each piece of which is not necessarily a multiple of 4 bytes in length. +
              +
            • In section “##### How to use this driver #####”, sub-section "*** Remarks on message length ***" added to provide recommendations to follow in such case.
              • +
            • No modification of the driver as the root-cause is at design-level.
              • +
            • +
          • +
        • HAL CAN update +
            +
          • HAL_CAN_GetRxMessage() update to get the correct value for the RTR (type of frame for the message that will be transmitted) field in the CAN_RxHeaderTypeDef structure.
            • +
          • +
        • HAL DCMI update +
            +
          • Add new HAL_DCMI_ConfigSyncUnmask() API to set embedded synchronization delimiters unmasks.
            • +
          • +
        • HAL RTC update +
            +
          • Following IRQ handlers’ implementation has been aligned with the STM32Cube firmware specification (in case of interrupt lines shared by multiple events, first check the IT enable bit is set then check the IT flag is set too): +
              +
            • HAL_RTC_AlarmIRQHandler()
              • +
            • HAL_RTCEx_WakeUpTimerIRQHandler()
              • +
            • HAL_RTCEx_TamperTimeStampIRQHandler()
              • +
            • +
          • +
        • HAL WWDG update +
            +
          • In “##### WWDG Specific features #####” descriptive comment section: +
              +
            • Maximal prescaler value has been corrected (8 instead of 128).
              • +
            • Maximal APB frequency has been corrected (42MHz instead of 56MHz) and possible timeout values updated.
              • +
            • +
          • +
        • HAL DMA2D update +
            +
          • Add the following API’s to Start DMA2D CLUT Loading. +
              +
            • HAL_DMA2D_CLUTStartLoad() Start DMA2D CLUT Loading.
              • +
            • HAL_DMA2D_CLUTStartLoad_IT() Start DMA2D CLUT Loading with interrupt enabled.
              • +
            • +
          • The following old wrong services will be kept in the HAL DCMI driver for legacy purpose and a specific Note is added: +
              +
            • HAL_DMA2D_CLUTLoad() can be replaced with HAL_DMA2D_CLUTStartLoad()
              • +
            • HAL_DMA2D_CLUTLoad_IT() can be replaced with HAL_DMA2D_CLUTStartLoad_IT()
              • +
            • HAL_DMA2D_ConfigCLUT() can be omitted as the config can be performed using the HAL_DMA2D_CLUTStartLoad() API.
              • +
            • +
          • +
        • HAL SDMMC update +
            +
          • Fix typo in “FileFormatGroup” parameter in the HAL_MMC_CardCSDTypeDef and HAL_SD_CardCSDTypeDef structures
            • +
          • Fix an improve handle state and error management
            • +
          • Rename the defined MMC card capacity type to be more meaningful: +
              +
            • Update MMC_HIGH_VOLTAGE_CARD to MMC LOW_CAPACITY_CARD
              • +
            • Update MMC_DUAL_VOLTAGE_CRAD to MMC_HIGH_CAPACITY_CARD
              • +
            • +
          • Fix management of peripheral flags depending on commands or data transfers +
              +
            • Add new defines “SDIO_STATIC_CMD_FLAGS” and “SDIO_STATIC_DATA_FLAGS”
              • +
            • Updates HAL SD and HAL MMC drivers to manage the new SDIO static flags.
              • +
            • +
          • Due to limitation SDIO hardware flow control indicated in Errata Sheet: +
              +
            • In 4-bits bus wide mode, do not use the HAL_SD_WriteBlocks_IT() or HAL_SD_WriteBlocks() APIs otherwise underrun will occur and it isn’t possible to activate the flow control.
              • +
            • Use DMA mode when using 4-bits bus wide mode or decrease the SDIO_CK frequency.
              • +
            • +
          • +
        • HAL UART update +
            +
          • Update UART polling processes to handle efficiently the Lock mechanism +
              +
            • Move the process unlock at the top of the HAL_UART_Receive() and HAL_UART_Transmit() API.
              • +
            • +
          • Fix baudrate calculation error for clock higher than 172Mhz +
              +
            • Add a forced cast on UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros.
              • +
            • Remove useless parenthesis from UART_DIVFRAQ_SAMPLING8(), UART_DIVFRAQ_SAMPLING16(), UART_BRR_SAMPLING8() and UART_BRR_SAMPLING16() macros to solve some MISRA warnings.
              • +
            • +
          • Update UART interruption handler to manage correctly the overrun interrupt +
              +
            • Add in the HAL_UART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
              • +
            • +
          • Fix baudrate calculation error UART9 and UART10 +
              +
            • In UART_SetConfig() API fix UART9 and UART10 clock source when computing baudrate values by adding a check on these instances and setting clock sourcePCLK2 instead of PCLK1.
              • +
            • +
          • Update UART_SetConfig() API +
              +
            • Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the UART_BRR_SAMPLING8() and UART_BRR_SAMPLING8() macros
              • +
            • +
          • +
        • HAL USART update +
            +
          • Fix baudrate calculation error for clock higher than 172Mhz +
              +
            • Add a forced cast on USART_DIV() macro.
              • +
            • Remove useless parenthesis from USART_DIVFRAQ() macro to solve some MISRA warnings.
              • +
            • +
          • Update USART interruption handler to manage correctly the overrun interrupt +
              +
            • Add in the HAL_USART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
              • +
            • +
          • Fix baudrate calculation error UART9 and UART10 +
              +
            • In USART_SetConfig() API fix UART9 and UART10 clock source when computing baudrate values by adding a check on these instances and setting clock sourcePCLK2 instead of PCLK1.
              • +
            • +
          • Update USART_SetConfig() API +
              +
            • Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the USART_BRR() macro
              • +
            • +
          • +
        • HAL IRDA update +
            +
          • Fix baudrate calculation error for clock higher than 172Mhz +
              +
            • Add a forced cast on IRDA_DIV() macro.
              • +
            • Remove useless parenthesis from IRDA_DIVFRAQ() macro to solve some MISRA warnings.
              • +
            • +
          • Update IRDA interruption handler to manage correctly the overrun interrupt +
              +
            • Add in the HAL_IRDA_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
              • +
            • +
          • Fix baudrate calculation error UART9 and UART10 +
              +
            • In IRDA_SetConfig() API fix UART9 and UART10 clock source when computing baudrate values by adding a check on these instances and setting clock sourcePCLK2 instead of PCLK1.
              • +
            • +
          • Update IRDA_SetConfig() API +
              +
            • Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the IRDA_BRR() macro
              • +
            • +
          • +
        • HAL SMARTCARD update +
            +
          • Fix baudrate calculation error for clock higher than 172Mhz +
              +
            • Add a forced cast on SMARTCARD_DIV() macro.
              • +
            • Remove useless parenthesis from SMARTCARD_DIVFRAQ() macro to solve some MISRA warnings.
              • +
            • +
          • Update SMARTCARD interruption handler to manage correctly the overrun interrupti +
              +
            • Add in the HAL_SMARTCARD_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
              • +
            • +
          • Update SMARTCARD_SetConfig() API +
              +
            • Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the SMARTCARD_BRR() macro
              • +
            • +
          • +
        • HAL TIM update +
            +
          • Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay +
              +
            • __HAL_TIM_ENABLE_OCxFAST() and __HAL_TIM_DISABLE_OCxFAST().
              • +
            • +
          • Update Encoder interface mode to keep TIM_CCER_CCxNP bits low +
              +
            • Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity.
              • +
            • Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity.
              • +
            • Update HAL_TIM_Encoder_Init() API +
                +
              • Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.
                • +
              • +
            • +
          • Update TIM remapping input configuration in HAL_TIMEx_RemapConfig() API +
              +
            • Remove redundant check on LPTIM_OR_TIM5_ITR1_RMP bit and replace it by check on LPTIM_OR_TIM9_ITR1_RMP bit.
              • +
            • +
          • Update HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors and assert fails when using some TIM instances as input trigger. +
              +
            • Replace IS_TIM_SYNCHRO_INSTANCE() macro by IS_TIM_MASTER_INSTANCE() macro.
              • +
            • Add IS_TIM_SLAVE_INSTANCE() macro to check on TIM_SMCR_MSM bit.
              • +
            • +
          • Add lacking TIM input remapping definition +
              +
            • Add LL_TIM_TIM11_TI1_RMP_SPDIFRX and LL_TIM_TIM2_ITR1_RMP_ETH_PTP.
              • +
            • Add lacking definition for linked LPTIM_TIM input trigger remapping +
                +
              • Add following definitions : LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO, LL_TIM_TIM9_ITR1_RMP_LPTIM, LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO, LL_TIM_TIM5_ITR1_RMP_LPTIM, LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO and LL_TIM_TIM1_ITR2_RMP_LPTIM.
                • +
              • Add a new mechanism in LL_TIM_SetRemap() API to remap TIM1, TIM9, and TIM5 input triggers mapped on LPTIM register.
                • +
              • +
            • +
          • +
        • HAL LPTIM update +
            +
          • Add a polling mechanism to check on LPTIM_FLAG_XXOK flags in different API +
              +
            • Add LPTIM_WaitForFlag() API to wait for flag set.
              • +
            • Perform new checks on HAL_LPTIM_STATE_TIMEOUT.
              • +
            • +
          • Add lacking definitions of LPTIM input trigger remapping and its related API +
              +
            • LL_LPTIM_INPUT1_SRC_PAD_AF, LL_LPTIM_INPUT1_SRC_PAD_PA4, LL_LPTIM_INPUT1_SRC_PAD_PB9 and LL_LPTIM_INPUT1_SRC_TIM_DAC.
              • +
            • Add a new API LL_LPTIM_SetInput1Src() to access to the LPTIM_OR register and remap the LPTIM input trigger.
              • +
            • +
          • Perform a new check on indirect EXTI23 line associated to the LPTIM wake up timer +
              +
            • Condition the use of the LPTIM Wake-up Timer associated EXTI line configuration’s macros by EXTI_IMR_MR23 bit in different API : +
                +
              • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE/DDISABLE_FALLING_EDGE()
                • +
              • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()
                • +
              • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()
                • +
              • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()
                • +
              • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
                • +
              • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
                • +
              • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()
                • +
              • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()
                • +
              • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT()
                • +
              • +
            • Update HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_LPTIM_Counter_Start_IT() and HAL_LPTIM_Counter_Stop_IT() API by adding Enable/Disable rising edge trigger on the LPTIM Wake-up Timer Exti line.
              • +
            • Add __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() in the end of the HAL_LPTIM_IRQHandler() API conditioned by EXTI_IMR_MR23 bit.
              • +
            • +
          • +
        • HAL I2C update +
            +
          • Update HAL_I2C_EV_IRQHandler() API to fix I2C send break issue +
              +
            • Add additional check on hi2c->hdmatx, hdmatx->XferCpltCallback, hi2c->hdmarx, hdmarx->XferCpltCallback in I2C_Master_SB() API to avoid enabling DMA request when IT mode is used.
              • +
            • +
          • Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes +
              +
            • Add stop condition generation when NACK occurs.
              • +
            • +
          • Update HAL_I2C_Init() API to force software reset before setting new I2C configuration
            • +
          • Update HAL I2C processes to report ErrorCode when wrong I2C start condition occurs +
              +
            • Add new ErrorCode define: HAL_I2C_WRONG_START
              • +
            • Set ErrorCode parameter in I2C handle to HAL_I2C_WRONG_START
              • +
            • +
          • Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer). +
              +
            • Add additional check on hi2c->hdmtx and hi2c->hdmarx before resetting DMA Tx/Rx complete callbacks
              • +
            • +
          • +
        • HAL FMPI2C update +
            +
          • Fix HAL FMPI2C slave interrupt handling issue with I2C sequential transfers. +
              +
            • Update FMPI2C_Slave_ISR_IT() and FMPI2C_Slave_ISR_DMA() APIs to check on STOP condition and handle it before clearing the ADDR flag
              • +
            • +
          • +
        • HAL NAND update +
            +
          • Update HAL_NAND_Write_Page_8b(), HAL_NAND_Write_Page_16b() and HAL_NAND_Write_SpareArea_16b() to manage correctly the time out condition.
            • +
          • +
        • HAL SAI update +
            +
          • Optimize SAI_DMATxCplt() and SAI_DMARxCplt() APIs to check on “Mode” parameter instead of CIRC bit in the CR register.
            • +
          • Remove unused SAI_FIFO_SIZE define
            • +
          • Update HAL_SAI_Receive_DMA() programming sequence to be inline with reference manual
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          • +
        • HAL I2C update +
            +
          • Fix I2C send break issue in IT processes +
              +
            • Add additional check on hi2c->hdmatx and hi2c->hdmarx to avoid the DMA request enable when IT mode is used.
              • +
            • +
          • +
        • HAL SPI update +
            +
          • Update to implement Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode
            • +
          • +
        • LL LPTIM update +
            +
          • Fix compilation errors with LL_LPTIM_WriteReg() and LL_LPTIM_ReadReg() macros
            • +
          • +
        • HAL SDMMC update +
            +
          • Fix preprocessing compilation issue with SDIO STA STBITERR interrupt
            • +
          • +
        • HAL/LL USB update +
            +
          • Updated USB_WritePacket(), USB_ReadPacket() APIs to prevent compilation warning with GCC GNU v8.2.0
            • +
          • Rework USB_EPStartXfer() API to enable the USB endpoint before unmasking the TX FiFo empty interrupt in case DMA is not used
            • +
          • USB HAL_HCD_Init() and HAL_PCD_Init() APIs updated to avoid enabling USB DMA feature for OTG FS instance, USB DMA feature is available only on OTG HS Instance
            • +
          • Remove duplicated line in hal_hcd.c header file comment section
            • +
          • Rework USB HAL driver to use instance PCD_SPEED_xxx, HCD_SPEED_xx speeds instead of OTG register Core speed definition during the instance initialization
            • +
          • Software Quality improvement with a fix of CodeSonar warning on PCD_Port_IRQHandler() and HCD_Port_IRQHandler() interrupt handlers
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          • +
        • General updates to fix CodeSonar compilation warnings
          • +
        • General updates to fix SW4STM32 compilation errors under Linux
          • +
        • General updates to fix the user manual .chm files
          • +
        • Add support of HAL callback registration feature
          • +
        • Add new HAL EXTI driver
          • +
        • Add new HAL SMBUS driver
          • +
        • The following changes done on the HAL drivers require an update on the application code based on older HAL versions +
            +
          • Rework of HAL CRYP driver (compatibility break) +
              +
            • HAL CRYP driver has been redesigned with new API’s, to bypass limitations on data Encryption/Decryption management present with previous HAL CRYP driver version.
              • +
            • The new HAL CRYP driver is the recommended version. It is located as usual in Drivers/STM32F4xx_HAL_Driver/Src and Drivers/STM32f4xx_HAL_Driver/Inc folders. It can be enabled through switch HAL_CRYP_MODULE_ENABLED in stm32f4xx_hal_conf.h
              • +
            • The legacy HAL CRYP driver is no longer supported.
              • +
            • +
          • Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure to allow the possibilities to enable or disable the TIM Auto Reload Preload.
            • +
          • +
        • HAL/LL Generic update +
            +
          • Add support of HAL callback registration feature +
              +
            • The feature disabled by default is available for the following HAL drivers: +
                +
              • ADC, CAN, CEC, CRYP, DAC, DCMI, DFSDM, DMA2D, DSI, ETH, HASH, HCD, I2C, FMPI2C, SMBUS, UART, USART, IRDA, SMARTCARD, LPTIM, LTDC, MMC, NAND, NOR, PCCARD, PCD, QSPI, RNG, RTC, SAI, SD, SDRAM, SRAM, SPDIFRX, SPI, I2S, TIM, and WWDG
                • +
              • +
            • The feature may be enabled individually per HAL PPP driver by setting the corresponding definition USE_HAL_PPP_REGISTER_CALLBACKS to 1U in stm32f4xx_hal_conf.h project configuration file (template file stm32f4xx_hal_conf_template.h available from Drivers/STM32F4xx_HAL_Driver/Inc)
              • +
            • Once enabled , the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().
              • +
            • +
          • General updates to fix MISRA 2012 compilation errors +
              +
            • Replace HAL_GetUID() API by HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2()
              • +
            • HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() macros implementation update
              • +
            • “stdio.h” include updated with “stddef.h”
              • +
            • +
          • +
        • HAL GPIO update +
            +
          • Add missing define for SPI3 alternate function “GPIO_AF5_SPI3” for STM32F401VE devices
            • +
          • Remove “GPIO_AF9_TIM14” from defined alternate function list for STM32F401xx devices
            • +
          • HAL_GPIO_TogglePin() reentrancy robustness improvement
            • +
          • HAL_GPIO_DeInit() API update to avoid potential pending interrupt after call
            • +
          • Update GPIO_GET_INDEX() API for more compliance with STM32F412Vx/STM32F412Rx/STM32F412Cx devices
            • +
          • Update GPIO_BRR registers with Reference Manual regarding registers and bit definition values
            • +
          • +
        • HAL CRYP update +
            +
          • The CRYP_InitTypeDef is no more supported, changed by CRYP_ConfigTypedef to allow changing parameters using HAL_CRYP_setConfig() API without reinitialize the CRYP IP using the HAL_CRYP_Init() API
            • +
          • New parameters added in the CRYP_ConfigTypeDef structure: B0 and DataWidthUnit
            • +
          • Input data size parameter is added in the CRYP_HandleTypeDef structure
            • +
          • Add new APIs to manage the CRYP configuration: +
              +
            • HAL_CRYP_SetConfig()
              • +
            • HAL_CRYP_GetConfig()
              • +
            • +
          • Add new APIs to manage the Key derivation: +
              +
            • HAL_CRYPEx_EnableAutoKeyDerivation()
              • +
            • HAL_CRYPEx_DisableAutoKeyDerivation()
              • +
            • +
          • Add new APIs to encrypt and decrypt data: +
              +
            • HAL_CRYP_Encypt()
              • +
            • HAL_CRYP_Decypt()
              • +
            • HAL_CRYP_Encypt_IT()
              • +
            • HAL_CRYP_Decypt_IT()
              • +
            • HAL_CRYP_Encypt_DMA()
              • +
            • HAL_CRYP_Decypt_DMA()
              • +
            • +
          • Add new APIs to generate TAG: +
              +
            • HAL_CRYPEx_AES__GCM___GenerateAuthTAG()
              • +
            • HAL_CRYPEx_AES__CCM___Generago teAuthTAG()
              • +
            • +
          • +
        • HAL LPTIM update +
            +
          • Remove useless LPTIM Wakeup EXTI related macros from HAL_LPTIM_TimeOut_Start_IT() API
            • +
          • +
        • HAL I2C update +
            +
          • I2C API changes for MISRA-C 2012 compliance: +
              +
            • Rename HAL_I2C_Master_Sequential_Transmit_IT() to HAL_I2C_Master_Seq_Transmit_IT()
              • +
            • Rename HAL_I2C_Master_Sequentiel_Receive_IT() to HAL_I2C_Master_Seq_Receive_IT()
              • +
            • Rename HAL_I2C_Slave_Sequentiel_Transmit_IT() to HAL_I2C_Slave_Seq_Transmit_IT()
              • +
            • Rename HAL_I2C_Slave_Sequentiel_Receive_DMA() to HAL_I2C_Slave_Seq_Receive_DMA()
              • +
            • +
          • SMBUS defined flags are removed as not used by the HAL I2C driver +
              +
            • I2C_FLAG_SMBALERT
              • +
            • I2C_FLAG_TIMEOUT
              • +
            • I2C_FLAG_PECERR
              • +
            • I2C_FLAG_SMBHOST
              • +
            • I2C_FLAG_SMBDEFAULT
              • +
            • +
          • Add support of I2C repeated start feature in DMA Mode: +
              +
            • With the following new API’s +
                +
              • HAL_I2C_Master_Seq_Transmit_DMA()
                • +
              • HAL_I2C_Master_Seq_Receive_DMA()
                • +
              • HAL_I2C_Slave_Seq_Transmit_DMA()
                • +
              • HAL_I2C_Slave_Seq_Receive_DMA()
                • +
              • +
            • +
          • Add new I2C transfer options to easy manage the sequential transfers +
              +
            • I2C_FIRST_AND_NEXT_FRAME
              • +
            • I2C_LAST_FRAME_NO_STOP
              • +
            • I2C_OTHER_FRAME
              • +
            • I2C_OTHER_AND_LAST_FRAME
              • +
            • +
          • +
        • HAL FMPI2C update +
            +
          • I2C API changes for MISRA-C 2012 compliance: +
              +
            • Rename HAL_FMPI2C_Master_Sequential_Transmit_IT() to HAL_FMPI2C_Master_Seq_Transmit_IT()
              • +
            • Rename HAL_FMPI2C_Master_Sequentiel_Receive_IT() to HAL_FMPI2C_Master_Seq_Receive_IT()
              • +
            • Rename HAL_FMPI2C_Master_Sequentiel_Transmit_DMA() to HAL_FMPI2C_Master_Seq_Transmit_DMA()
              • +
            • Rename HAL_FMPI2C_Master_Sequentiel_Receive_DMA() to HAL_FMPI2C_Master_Seq_Receive_DMA()
              • +
            • +
          • Rename FMPI2C_CR1_DFN to FMPI2C_CR1_DNF for more compliance with Reference Manual regarding registers and bit definition naming
            • +
          • Add support of I2C repeated start feature in DMA Mode: +
              +
            • With the following new API’s +
                +
              • HAL_FMPI2C_Master_Seq_Transmit_DMA()
                • +
              • HAL_FMPI2C_Master_Seq_Receive_DMA()
                • +
              • HAL_FMPI2C_Slave_Seq_Transmit_DMA()
                • +
              • HAL_FMPI2C_Slave_Seq_Receive_DMA()
                • +
              • +
            • +
          • +
        • HAL FLASH update +
            +
          • Update the FLASH_OB_GetRDP() API to return the correct RDP level
            • +
          • +
        • HAL RCC update +
            +
          • Remove GPIOD CLK macros for STM32F412Cx devices (X = D)
            • +
          • Remove GPIOE CLK macros for STM32F412Rx\412Cx devices: (X = E)
            • +
          • Remove GPIOF/G CLK macros for STM32F412Vx\412Rx\412Cx devices (X= F or G) +
              +
            • __HAL_RCC_GPIOX_CLK_ENABLE()
              • +
            • __HAL_RCC_GPIO__X___CLK_DISABLE()
              • +
            • __HAL_RCC_GPIO__X___IS_CLK_ENABLED()
              • +
            • __HAL_RCC_GPIO__X___IS_CLK_DISABLED()
              • +
            • __HAL_RCC_GPIO__X___FORCE_RESET()
              • +
            • +
          • +
        • HAL RNG update +
            +
          • Update to manage RNG error code: +
              +
            • Add ErrorCode parameter in HAL RNG Handler structure
              • +
            • +
          • +
        • LL ADC update +
            +
          • Add __LL_ADC_CALC_TEMPERATURE() helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
            • +
          • Fix ADC channels configuration issues on STM32F413xx/423xx devices +
              +
            • To allow possibility to switch between VBAT and TEMPERATURE channels configurations
              • +
            • HAL_ADC_Start(), HAL_ADC_Start_IT() and HAL_ADC_Start_DMA() update to prevention from starting ADC2 or ADC3 once multimode is enabled
              • +
            • +
          • +
        • HAL DFSDM update +
            +
          • General updates to be compliant with DFSDM bits naming used in CMSIS files.
            • +
          • +
        • HAL CAN update +
            +
          • Update possible values list for FilterActivation parameter in CAN_FilterTypeDef structure +
              +
            • CAN_FILTER_ENABLE instead of ENABLE
              • +
            • CAN_FILTER_DISABLE instead of DISABLE
              • +
            • +
          • +
        • HAL CEC update +
            +
          • Update HAL CEC State management method: +
              +
            • Remove HAL_CEC_StateTypeDef structure parameters
              • +
            • Add new defines for CEC states
              • +
            • +
          • +
        • HAL DMA update +
            +
          • Add clean of callbacks in HAL_DMA_DeInit() API
            • +
          • +
        • HAL DMA2D update +
            +
          • Remove unused DMA2D_ColorTypeDef structure to be compliant with MISRAC 2012 Rule 2.3
            • +
          • General update to use dedicated defines for DMA2D_BACKGROUND_LAYER and DMA2D_FOREGROUND_LAYER instead of numerical values: 0/1.
            • +
          • +
        • HAL DSI update +
            +
          • Fix read multibyte issue: remove extra call to HAL_UNLOCK from DSI_ShortWrite() API.
            • +
          • +
        • HAL/LL RTC update +
            +
          • HAL/ LL drivers optimization +
              +
            • HAL driver: remove unused variables
              • +
            • LL driver: getter APIs optimization
              • +
            • +
          • +
        • HAL PWR update +
            +
          • Remove the following API’s as feature not supported by STM32F469xx/479xx devices +
              +
            • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
              • +
            • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
              • +
            • +
          • +
        • HAL SPI update +
            +
          • Update HAL_SPI_StateTypeDef structure to add new state: HAL_SPI_STATE_ABORT
            • +
          • +
        • HAL/LL TIM update +
            +
          • Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure +
              +
            • Refer to the TIM examples to identify the changes
              • +
            • +
          • Move the following TIM structures from stm32f4xx_hal_tim_ex.h into stm32f4xx_hal_tim.h +
              +
            • TIM_MasterConfigTypeDef
              • +
            • TIM_BreakDeadTimeConfigTypeDef
              • +
            • +
          • Add new TIM Callbacks API’s: +
              +
            • HAL_TIM_PeriodElapsedHalfCpltCallback()
              • +
            • HAL_TIM_IC_CaptureHalfCpltCallback()
              • +
            • HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
              • +
            • HAL_TIM_TriggerHalfCpltCallback()
              • +
            • +
          • TIM API changes for MISRA-C 2012 compliance: +
              +
            • Rename HAL_TIM_SlaveConfigSynchronization to HAL_TIM_SlaveConfigSynchro
              • +
            • Rename HAL_TIM_SlaveConfigSynchronization_IT to HAL_TIM_SlaveConfigSynchro_IT
              • +
            • Rename HAL_TIMEx_ConfigCommutationEvent to HAL_TIMEx_ConfigCommutEvent
              • +
            • Rename HAL_TIMEx_ConfigCommutationEvent_IT to HAL_TIMEx_ConfigCommutEvent_IT
              • +
            • Rename HAL_TIMEx_ConfigCommutationEvent_DMA to HAL_TIMEx_ConfigCommutEvent_DMA
              • +
            • Rename HAL_TIMEx_CommutationCallback to HAL_TIMEx_CommutCallback
              • +
            • Rename HAL_TIMEx_DMACommutationCplt to TIMEx_DMACommutationCplt
              • +
            • +
          • +
        • HAL/LL USB update +
            +
          • Rework USB interrupt handler and improve HS DMA support in Device mode
            • +
          • Fix BCD handling fr OTG instance in device mode
            • +
          • cleanup reference to low speed in device mode
            • +
          • allow writing TX FIFO in case of transfer length is equal to available space in the TX FIFO
            • +
          • Fix Toggle OUT interrupt channel in host mode
            • +
          • Update USB OTG max number of endpoints (6 FS and 9 HS instead of 5 and 8)
            • +
          • Update USB OTG IP to enable internal transceiver when starting USB device after committee BCD negotiation
            • +
          • +
        • LL IWDG update +
            +
          • Update LL inline macros to use IWDGx parameter instead of IWDG instance defined in CMSIS device
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          • +
        • HAL update +
            +
          • Update UNUSED() macro implementation to avoid GCC warning +
              +
            • The warning is detected when the UNUSED() macro is called from C++ file
              • +
            • +
          • Update to make RAMFUNC define as generic type instead of HAL_StatusTypdef type.
            • +
          • +
        • HAL FLASH update +
            +
          • Update the prototypes of the following APIs after change on RAMFUNC defines +
              +
            • HAL_FLASHEx_StopFlashInterfaceClk()
              • +
            • HAL_FLASHEx_StartFlashInterfaceClk()
              • +
            • HAL_FLASHEx_EnableFlashSleepMode()
              • +
            • HAL_FLASHEx_DisableFlashSleepMode()
              • +
            • +
          • +
        • HAL SAI update +
            +
          • Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          • +
        • The following changes done on the HAL drivers require an update on the application code based on older HAL versions +
            +
          • Rework of HAL CAN driver (compatibility break) +
              +
            • A new HAL CAN driver has been redesigned with new APIs, to bypass limitations on CAN Tx/Rx FIFO management present with previous HAL CAN driver version.
              • +
            • The new HAL CAN driver is the recommended version. It is located as usual in Drivers/STM32F4xx_HAL_Driver/Src and Drivers/STM32f4xx_HAL_Driver/Inc folders. It can be enabled through switch HAL_CAN_MODULE_ENABLED in stm32f4xx_hal_conf.h
              • +
            • The legacy HAL CAN driver is also present in the release in Drivers/STM32F4xx_HAL_Driver/Src/Legacy and Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software compatibility reasons. Its usage is not recommended as deprecated. It can however be enabled through switch HAL_CAN_LEGACY_MODULE_ENABLED in stm32f4xx_hal_conf.h
              • +
            • +
          • +
        • HAL update +
            +
          • Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms : +
              +
            • Add the following API’s : +
                +
              • HAL_GetTickPrio(): Returns a tick priority.
                • +
              • HAL_SetTickFreq(): Sets new tick frequency.
                • +
              • HAL_GetTickFreq(): Returns tick frequency.
                • +
              • +
            • Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default).
              • +
            • +
          • +
        • HAL CAN update +
            +
          • Fields of CAN_InitTypeDef structure are reworked: +
              +
            • SJW to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to TransmitFifoPriority
              • +
            • +
          • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API’s
            • +
          • HAL_CAN_Transmit() is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.
            • +
          • HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then HAL_CAN_AddTxMessage() for place Tx request.
            • +
          • HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() to get Rx message.
            • +
          • HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then HAL_CAN_GetRxMessage() in the receivecallback to get Rx message
            • +
          • HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()
            • +
          • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback().
            • +
          • HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback().
            • +
          • More complete “How to use the new driver” is detailed in the driver header section itself.
            • +
          • +
        • HAL FMPI2C update +
            +
          • Add new option FMPI2C_LAST_FRAME_NO_STOP for the sequential transfer management +
              +
            • This option allows to manage a restart condition after several call of the same master sequential interface.
              • +
            • +
          • +
        • HAL RCC update +
            +
          • Add new HAL macros +
              +
            • __HAL_RCC_GET_RTC_SOURCE() allowing to get the RTC clock source
              • +
            • __HAL_RCC_GET_RTC_HSE_PRESCALER() allowing to get the HSE clock divider for RTC peripheral
              • +
            • +
          • Ensure reset of CIR and CSR registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit functions
            • +
          • Update HAL_RCC_OscConfig() to keep backup domain enabled when configuring respectively LSE and RTC clock source
            • +
          • Add new HAL interfaces allowing to control the activation or deactivation of PLLI2S and PLLSAI: +
              +
            • HAL_RCCEx_EnablePLLI2S()
              • +
            • HAL_RCCEx_DisablePLLI2S()
              • +
            • HAL_RCCEx_EnablePLLSAI()
              • +
            • HAL_RCCEx_DisablePLLSAI()
              • +
            • +
          • +
        • LL RCC update +
            +
          • Add new LL RCC macro +
              +
            • LL_RCC_PLL_SetMainSource() allowing to configure PLL main clock source
              • +
            • +
          • +
        • LL FMC / LL FSMC update +
            +
          • Add clear of the PTYP bit to select the PCARD mode in FMC_PCCARD_Init() / FSMC_PCCARD_Init()
            +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          • +
        • Fix compilation warning with GCC compiler
          • +
        • Remove Date and version from header files
          • +
        • Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the POSITION_VAL() macro
          • +
        • HAL Generic update +
            +
          • stm32f4xx_hal_def.h file changes: +
              +
            • Update __weak and __packed defined values for ARM compiler
              • +
            • Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
              • +
            • +
          • stm32f4xx_ll_system.h file: add LL_SYSCFG_REMAP_SDRAM define
            • +
          • +
        • HAL ADC update +
            +
          • Fix wrong definition of ADC channel temperature sensor for STM32F413xx and STM32F423xx devices.
            • +
          • +
        • HAL DMA update +
            +
          • Update values for the following defines: DMA_FLAG_FEIF0_4 and DMA_FLAG_DMEIF0_4
            • +
          • +
        • HAL DSI update +
            +
          • Fix Extra warning with SW4STM32 compiler
            • +
          • Fix DSI display issue when using EWARM w/ high level optimization
            • +
          • Fix MISRAC errors
            • +
          • +
        • HAL FLASH update +
            +
          • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
            • +
          • +
        • HAL FMPI2C update +
            +
          • Update Interface APIs headers to remove confusing message about device address
            • +
          • Update FMPI2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags
            • +
          • Update FMPI2C_TransferConfig() to fix wrong bit management.
            • +
          • Update code comments to use DMA stream instead of DMA channel
            • +
          • +
        • HAL PWR update +
            +
          • HAL_PWR_EnableWakeUpPin() update description to add support of PWR_WAKEUP_PIN2 and PWR_WAKEUP_PIN3
            • +
          • +
        • HAL NOR update +
            +
          • Add the support of STM32F412Rx devices
            • +
          • +
        • HAL I2C update +
            +
          • Update Interface APIs headers to remove confusing message about device address
            • +
          • Update I2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to fix bad Handling of NACK in I2C master receive process.
            • +
          • +
        • HAL RCC update +
            +
          • Update HAL_RCC_GetOscConfig() API to: +
              +
            • set PLLR in the RCC_OscInitStruct
              • +
            • check on null pointer
              • +
            • +
          • Update HAL_RCC_ClockConfig() API to: +
              +
            • check on null pointer
              • +
            • optimize code size by updating the handling method of the SWS bits
              • +
            • update to use __HAL_FLASH_GET_LATENCY() flash macro instead of using direct register access to LATENCY bits in FLASH ACR register.
              • +
            • +
          • Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to +
              +
            • Be able to return HAL/LL status
              • +
            • Add checks for HSI, PLL and PLLI2S ready before modifying RCC CFGR registers
              • +
            • Clear all interrupt flags
              • +
            • Initialize systick interrupt period
              • +
            • +
          • Update HAL_RCC_GetSysClockFreq() to avoid risk of rounding error which may leads to a wrong returned value.
            • +
          • +
        • HAL RNG update +
            +
          • HAL_RNG_Init() remove Lock()/Unlock()
            • +
          • +
        • HAL MMC update +
            +
          • HAL_MMC_Erase() API: add missing () to fix compilation warning detected with SW4STM32 when extra feature is enabled.
            • +
          • +
        • HAL RTC update +
            +
          • HAL_RTC_Init() API: update to force the wait for synchro before setting TAFCR register when BYPSHAD bit in CR register is 0.
            • +
          • +
        • HAL SAI update +
            +
          • Update HAL_SAI_DMAStop() API to flush fifo after disabling SAI
            • +
          • +
        • HAL I2S update +
            +
          • Update I2S DMA fullduplex process to handle I2S Rx and Tx DMA Half transfer complete callback
            • +
          • +
        • HAL TIM update +
            +
          • Update HAL_TIMEx_OCN_xxxx() and HAL_TIMEx_PWMN_xxx() API description to remove support of TIM_CHANNEL_4
            • +
          • +
        • LL DMA update +
            +
          • Update to clear DMA flags using WRITE_REG() instead SET_REG() API to avoid read access to the IFCR register that is write only.
            • +
          • +
        • LL RTC update +
            +
          • Fix warning with static analyzer
            • +
          • +
        • LL USART update +
            +
          • Add assert macros to check USART BaudRate register
            • +
          • +
        • LL I2C update +
            +
          • Rename IS_I2C_CLOCK_SPEED() and IS_I2C_DUTY_CYCLE() respectively to IS_LL_I2C_CLOCK_SPEED() and IS_LL_I2C_DUTY_CYCLE() to avoid incompatible macros redefinition.
            • +
          • +
        • LL TIM update +
            +
          • Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in TIM CR1 register instead of setting it.
            • +
          • Update LL_TIM_DisableUpdateEvent() API to set UDIS bit in TIM CR1 register instead of clearing it.
            • +
          • +
        • LL USART update +
            +
          • Fix MISRA error w/ IS_LL_USART_BRR() macro
            • +
          • Fix wrong check when UART10 instance is used
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Update CHM UserManuals to support LL drivers
          • +
        • General updates to fix known defects and enhancements implementation
          • +
        • HAL CAN update +
            +
          • Add management of overrun error.
            • +
          • Allow possibility to receive messages from the 2 RX FIFOs in parallel via interrupt.
            • +
          • Fix message lost issue with specific sequence of transmit requests.
            • +
          • Handle transmission failure with error callback, when NART is enabled.
            • +
          • Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when timeout is reached
            • +
          • +
        • HAL PWR update +
            +
          • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove check on UDRDY flag
            • +
          • +
        • LL ADC update +
            +
          • Fix wrong ADC group injected sequence configuration +
              +
            • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() API’s update to take in consideration the ADC number of conversions
              • +
            • Update the defined values for ADC group injected seqencer ranks
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add Low Layer drivers allowing performance and footprint optimization +
            +
          • Low Layer drivers APIs provide register level programming: require deep knowledge of peripherals described in STM32F4xx Reference Manuals
            • +
          • Low Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA, DMA2D, EXTI, GPIO, I2C, IWDG, LPTIM, PWR, RCC, RNG, RTC, SPI, TIM, USART, WWDG peripherals and additional Low Level Bus, System and Utilities APIs.
            • +
          • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f4xx_ll_ppp.h file must be included in user code.
            • +
          • +
        • General updates to fix known defects and enhancements implementation
          • +
        • Fix extra warnings with GCC compiler
          • +
        • HAL drivers clean up: remove double casting ‘uint32_t’ and ‘U’
          • +
        • Add new HAL MMC driver
          • +
        • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
          • +
        • HAL SD update +
            +
          • Overall rework of the driver for a more efficient implementation +
              +
            • Modify initialization API and structures
              • +
            • Modify Read / Write sequences: separate transfer process and SD Cards state management
              • +
            • Adding interrupt mode for Read / Write operations
              • +
            • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
              • +
            • +
          • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
            • +
          • +
        • HAL NAND update +
            +
          • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
            • +
          • Add new HAL_NAND_ConfigDevice API
            • +
          • +
        • HAL DFSDM update +
            +
          • Add support of Multichannel Delay feature +
              +
            • Add HAL_DFSDM_ConfigMultiChannelDelay API
              • +
            • The following APIs are moved to internal static functions: HAL_DFSDM_ClockIn_SourceSelection, HAL_DFSDM_ClockOut_SourceSelection, HAL_DFSDM_DataInX_SourceSelection (X=0,2,4,6), HAL_DFSDM_BitStreamClkDistribution_Config
              • +
            • +
          • +
        • HAL I2S update +
            +
          • Add specific callback API to manage I2S full duplex end of transfer process: +
              +
            • HAL_I2S_TxCpltCallback() and HAL_I2S_RxCpltCallback() API’s will be replaced with only HAL_I2SEx_TxRxCpltCallback() API.
              • +
            • +
          • +
        • HAL update +
            +
          • Modify default HAL_Delay implementation to guarantee minimum delay
            • +
          • +
        • HAL Cortex update +
            +
          • Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f4xx_hal_cortex.h to stm32f4xx_hal_cortex.c
            • +
          • Clear the whole MPU control register in HAL_MPU_Disable() API
            • +
          • +
        • HAL FLASH update +
            +
          • IS_FLASH_ADDRESS() macro update to support OTP range
            • +
          • FLASH_Program_DoubleWord(): Replace 64-bit accesses with 2 double-words operations
            • +
          • +
        • LL GPIO update +
            +
          • Update IS_GPIO_PIN() macro implementation to be more safe
            • +
          • +
        • LL RCC update +
            +
          • Update IS_RCC_PLLQ_VALUE() macro implementation: the minimum accepted value is 2 instead of 4
            • +
          • Rename RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1
            • +
          • Fix compilation issue w/ __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() and __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() macros for STM32F401xx devices
            • +
          • Add the following is clock enabled macros for STM32F401xx devices +
              +
            • __HAL_RCC_SDIO_IS_CLK_ENABLED()
              • +
            • __HAL_RCC_SPI4_IS_CLK_ENABLED()
              • +
            • __HAL_RCC_TIM10_IS_CLK_ENABLED()
              • +
            • +
          • Add the following is clock enabled macros for STM32F410xx devices +
              +
            • __HAL_RCC_CRC_IS_CLK_ENABLED()
              • +
            • __HAL_RCC_RNG_IS_CLK_ENABLED()
              • +
            • +
          • Update HAL_RCC_DeInit() to reset the RCC clock configuration to the default reset state.
            • +
          • Remove macros to configure BKPSRAM from STM32F401xx devices
            • +
          • Update to refer to AHBPrescTable[] and APBPrescTable[] tables defined in system_stm32f4xx.c file instead of APBAHBPrescTable[] table.
            • +
          • +
        • HAL FMPI2C update +
            +
          • Add FMPI2C_FIRST_AND_NEXT_FRAME define in Sequential Transfer Options
            • +
          • +
        • HAL ADC update +
            +
          • HAL_ADCEx_InjectedConfigChannel(): update the external trigger injected condition
            • +
          • +
        • HAL DMA update +
            +
          • HAL_DMA_Init(): update to check compatibility between FIFO threshold level and size of the memory burst
            • +
          • +
        • HAL QSPI update +
            +
          • QSPI_HandleTypeDef structure: Update transfer parameters on uint32_t instead of uint16_t
            • +
          • +
        • HAL UART/USART/IrDA/SMARTCARD update +
            +
          • DMA Receive process; the code has been updated to clear the USART OVR flag before enabling DMA receive request.
            • +
          • UART_SetConfig() update to manage correctly USART6 instance that is not available on STM32F410Tx devices
            • +
          • +
        • HAL CAN update +
            +
          • Remove Lock mechanism from HAL_CAN_Transmit_IT() and HAL_CAN_Receive_IT() processes
            • +
          • +
        • HAL TIM update +
            +
          • Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() macro to disable Master output without check on TIM channel state.
            • +
          • Update HAL_TIMEx_ConfigBreakDeadTime() to fix TIM BDTR register corruption.
            • +
          • +
        • HAL I2C update +
            +
          • Update HAL_I2C_Master_Transmit() and HAL_I2C_Slave_Transmit() to avoid sending extra bytes at the end of the transmit processes
            • +
          • Update HAL_I2C_Mem_Read() API to fix wrong check on misused parameter “Size”
            • +
          • Update I2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to enhance Master sequential reception process.
            • +
          • +
        • HAL SPI update +
            +
          • Add transfer abort APIs and associated callbacks in interrupt mode +
              +
            • HAL_SPI_Abort()
              • +
            • HAL_SPI_Abort_IT()
              • +
            • HAL_SPI_AbortCpltCallback()
              • +
            • +
          • +
        • HAL I2S update +
            +
          • Add specific callback API to manage I2S full duplex end of transfer process: +
              +
            • HAL_I2S_TxCpltCallback() and HAL_I2S_RxCpltCallback() API’s will be replaced with only HAL_I2SEx_TxRxCpltCallback() API.
              • +
            • +
          • Update I2S Transmit/Receive polling process to manage Overrun and Underrun errors
            • +
          • Move the I2S clock input frequency calculation to HAL RCC driver.
            • +
          • Update the HAL I2SEx driver to keep only full duplex feature.
            • +
          • HAL_I2S_Init() API updated to +
              +
            • Fix wrong I2S clock calculation when PCM mode is used.
              • +
            • Return state HAL_I2S_ERROR_PRESCALER when the I2S clock is wrongly configured
              • +
            • +
          • +
        • HAL LTDC update +
            +
          • Optimize HAL_LTDC_IRQHandler() function by using direct register read
            • +
          • Rename the following API’s +
              +
            • HAL_LTDC_Relaod() by HAL_LTDC_Reload()
              • +
            • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
              • +
            • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
              • +
            • +
          • Add new defines for LTDC layers (LTDC_LAYER_1 / LTDC_LAYER_2)
            • +
          • Remove unused asserts
            • +
          • +
        • HAL USB PCD update +
            +
          • Flush all TX FIFOs on USB Reset
            • +
          • Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API’s
            • +
          • +
        • LL USB update +
            +
          • Enable DMA Burst mode for USB OTG HS
            • +
          • Fix SD card detection issue
            • +
          • +
        • LL SDMMC update +
            +
          • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F413xx and STM32F423xx devices
          • +
        • General updates to fix known defects and enhancements implementation
          • +
        • HAL CAN update +
            +
          • Update to add the support of 3 CAN management
            • +
          • +
        • HAL CRYP update +
            +
          • Update to add the support of AES features
            • +
          • +
        • HAL DFSDM update +
            +
          • Add definitions for new external trigger filters
            • +
          • Add definition for new Channels 4, 5, 6 and 7
            • +
          • Add functions and API for Filter state configuration and management
            • +
          • Add new functions: +
              +
            • HAL_DFSDM_BitstreamClock_Start()
              • +
            • HAL_DFSDM_BitstreamClock_Stop()
              • +
            • HAL_DFSDM_BitStreamClkDistribution_Config()
              • +
            • +
          • +
        • HAL DMA +
            +
          • Add the support of DMA Channels from 8 to 15
            • +
          • Update HAL_DMA_DeInit() function with the check on DMA stream instance
            • +
          • +
        • HAL DSI update +
            +
          • Update HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid scratch in DSI_CCR register
            • +
          • +
        • HAL FLASH update +
            +
          • Enhance FLASH_WaitForLastOperation() function implementation
            • +
          • Update __HAL_FLASH_GET_FLAG() macro implementation
            • +
          • +
        • HAL GPIO update +
            +
          • Add specific alternate functions definitions
            • +
          • +
        • HAL I2C update +
            +
          • Update I2C_DMAError() function implementation to ignore DMA FIFO error
            • +
          • +
        • HAL I2S update +
            +
          • Enhance HAL_I2S_Init() implementation to test on PCM_SHORT and PCM_LONG standards
            • +
          • +
        • HAL IRDA update +
            +
          • Add new functions and call backs for Transfer Abort +
              +
            • HAL_IRDA_Abort()
              • +
            • HAL_IRDA_AbortTransmit()
              • +
            • HAL_IRDA_AbortReceive()
              • +
            • HAL_IRDA_Abort_IT()
              • +
            • HAL_IRDA_AbortTransmit_IT()
              • +
            • HAL_IRDA_AbortReceive_IT()
              • +
            • HAL_IRDA_AbortCpltCallback()
              • +
            • HAL_IRDA_AbortTransmitCpltCallback()
              • +
            • HAL_IRDA_AbortReceiveCpltCallback()
              • +
            • +
          • +
        • HAL PCD update +
            +
          • Update HAL_PCD_GetRxCount() function implementation
            • +
          • +
        • HAL RCC update +
            +
          • Update __HAL_RCC_HSE_CONFIG() macro implementation
            • +
          • Update __HAL_RCC_LSE_CONFIG() macro implementation
            • +
          • +
        • HAL SMARTCARD update +
            +
          • Add new functions and call backs for Transfer Abort +
              +
            • HAL_ SMARTCARD_Abort()
              • +
            • HAL_ SMARTCARD_AbortTransmit()
              • +
            • HAL_ SMARTCARD_AbortReceive()
              • +
            • HAL_ SMARTCARD_Abort_IT()
              • +
            • HAL_ SMARTCARD_AbortTransmit_IT()
              • +
            • HAL_ SMARTCARD_AbortReceive_IT()
              • +
            • HAL_ SMARTCARD_AbortCpltCallback()
              • +
            • HAL_ SMARTCARD_AbortTransmitCpltCallback()
              • +
            • HAL_ SMARTCARD_AbortReceiveCpltCallback()
              • +
            • +
          • +
        • HAL TIM update +
            +
          • Update HAL_TIMEx_RemapConfig() function to manage TIM internal trigger remap: LPTIM or TIM3_TRGO
            • +
          • +
        • HAL UART update +
            +
          • Add Transfer abort functions and callbacks
            • +
          • +
        • HAL USART update +
            +
          • Add Transfer abort functions and callbacks
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • HAL I2C update +
            +
          • Fix wrong behavior in consecutive transfers in case of single byte transmission (Master/Memory Receive interfaces)
            • +
          • Update HAL_I2C_Master_Transmit_DMA() / HAL_I2C_Master_Receive_DMA()/ HAL_I2C_Slave_Transmit_DMA() and HAL_I2C_Slave_Receive_DMA() to manage addressing phase through interruption instead of polling
            • +
          • Add a check on I2C handle state at start of all I2C API’s to ensure that I2C is ready
            • +
          • Update I2C API’s (Polling, IT and DMA interfaces) to manage I2C XferSize and XferCount handle parameters instead of API size parameter to help user to get information of counter in case of error.
            • +
          • Update Abort functionality to manage DMA use case
            • +
          • +
        • HAL FMPI2C update +
            +
          • Update to disable Own Address before setting the new Own Address configuration: +
              +
            • Update HAL_FMPI2C_Init() to disable FMPI2C_OARx_EN bit before any configuration in OARx registers
              • +
            • +
          • +
        • HAL CAN update +
            +
          • Update CAN receive processes to set CAN RxMsg FIFONumber parameter
            • +
          • +
        • HAL UART update +
            +
          • Update UART handle TxXferCount and RxXferCount parameters as volatile to avoid eventual issue with High Speed optimization
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • HAL GPIO update +
            +
          • HAL_GPIO_Init()/HAL_GPIO_DeInit() API’s: update GPIO_GET_INDEX() macro implementation to support all GPIO’s
            • +
          • +
        • HAL SPI update +
            +
          • Fix regression issue: restore HAL_SPI_DMAPause() and HAL_SPI_DMAResume() API’s
            • +
          • +
        • HAL RCC update +
            +
          • Fix FSMC macros compilation warnings with STM32F412Rx devices
            • +
          • +
        • HAL DMA update +
            +
          • HAL_DMA_PollFortransfer() API clean up
            • +
          • +
        • HAL PPP update(PPP refers to IRDA, UART, USART and SMARTCARD) +
            +
          • Update HAL_PPP_IRQHandler() to add a check on interrupt source before managing the error
            • +
          • +
        • HAL QSPI update +
            +
          • Implement workaround to fix the limitation pronounced in the Errata sheet 2.1.8 section: In some specific cases, DMA2 data corruption occurs when managing AHB and APB2 peripherals in a concurrent way
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F412cx, STM32F412rx, STM32F412vx and STM32F412zx devices
          • +
        • General updates to fix known defects and enhancements implementation
          • +
        • Add new HAL driver for DFSDM peripheral
          • +
        • Enhance HAL delay and time base implementation: +
            +
          • Add new drivers stm32f4xx_hal_timebase_rtc_alarm_template.c and stm32f4xx_hal_timebase_rtc_wakeup_template.c which override the native HAL time base functions (defined as weak) to either use the RTC as time base tick source. For more details about the usage of these drivers, please refer to HAL_TimeBase_RTC examples and FreeRTOS-based applications
            • +
          • +
        • The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.4 +
            +
          • HAL UART, USART, IRDA, SMARTCARD, SPI, I2C,FMPI2C, QSPI (referenced as PPP here below) drivers +
              +
            • Add PPP error management during DMA process. This requires the following updates on user application: +
                +
              • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
                • +
              • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
                • +
              • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
                • +
              • +
            • +
          • HAL I2C, FMPI2C (referenced as PPP here below) drivers: +
              +
            • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the PPP end of transfer interrupt in the DMA transfer process. This requires the following updates on user application: +
                +
              • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
                • +
              • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
                • +
              • +
            • +
          • HAL I2C driver: +
              +
            • I2C transfer processes IT update: NACK during addressing phase is managed through I2C Error interrupt instead of HAL state
              • +
            • +
          • HAL IWDG driver: rework overall driver for better implementation +
              +
            • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
              • +
            • +
          • HAL WWDG driver: rework overall driver for better implementation +
              +
            • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs
              • +
            • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter) function and API by removing the “counter” parameter
              • +
            • +
          • HAL QSPI driver: Enhance the DMA transmit process by using PPP TC interrupt instead of waiting on TC flag under DMA ISR. This requires the following updates on user application: +
              +
            • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
              • +
            • In stm32f4xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function
              • +
            • +
          • HAL CEC driver: Overall driver rework with compatibility break versus previous HAL version +
              +
            • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()
              • +
            • Remove HAL CEC receive interrupt process function HAL_CEC_Receive_IT() and enable the “receive” mode during the Init phase
              • +
            • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize()
              • +
            • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
              • +
            • Remove the ‘InitiatorAddress’ field from the CEC_InitTypeDef structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function
              • +
            • Add new parameter ‘RxFrameSize’ in HAL_CEC_RxCpltCallback() function
              • +
            • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
              • +
            • +
          • +
        • HAL RCC update +
            +
          • Update HAL_RCC_ClockConfig() function to adjust the SystemCoreClock
            • +
          • Rename macros and Literals: +
              +
            • RCC_PERIPHCLK_CK48 by RCC_PERIPHCLK_CLK48
              • +
            • IS_RCC_CK48CLKSOURCE by IS_RCC_CLK48CLKSOURCE
              • +
            • RCC_CK48CLKSOURCE_PLLSAIP by RCC_CLK48CLKSOURCE_PLLSAIP
              • +
            • RCC_SDIOCLKSOURCE_CK48 by RCC_SDIOCLKSOURCE_CLK48
              • +
            • RCC_CK48CLKSOURCE_PLLQ by RCC_CLK48CLKSOURCE_PLLQ
              • +
            • +
          • Update HAL_RCCEx_GetPeriphCLKConfig() and HAL_RCCEx_PeriphCLKConfig() functions to support TIM Prescaler for STM32F411xx devices
            • +
          • HAL_RCCEx_PeriphCLKConfig() API: update to fix the RTC clock configuration issue
            • +
          • +
        • HAL CEC update +
            +
          • Overall driver rework with break of compatibility with HAL V1.4.4 +
              +
            • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
              • +
            • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the “Receive” mode enable within the Init phase
              • +
            • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
              • +
            • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
              • +
            • Remove the ‘InitiatorAddress’ field from the CEC_InitTypeDef structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function
              • +
            • Add new parameter ‘RxFrameSize’ in HAL_CEC_RxCpltCallback() function
              • +
            • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
              • +
            • +
          • Update driver to implement the new CEC state machine: +
              +
            • Add new “rxState” field in CEC_HandleTypeDef structure to provide the CEC state information related to Rx Operations
              • +
            • Rename “state” field in CEC_HandleTypeDef structure to “gstate”: CEC state information related to global Handle management and Tx Operations
              • +
            • Update CEC process to manage the new CEC states.
              • +
            • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)
              • +
            • +
          • +
        • HAL UART, USART, SMARTCARD and IRDA (referenced as PPP here below) update +
            +
          • Update Polling management: +
              +
            • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
              • +
            • +
          • Update DMA process: +
              +
            • Update the management of PPP peripheral errors during DMA process. This requires the following updates in user application: +
                +
              • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
                • +
              • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
                • +
              • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
                • +
              • +
            • +
          • +
        • HAL FMC update +
            +
          • Update FMC_NORSRAM_Init() to remove the Burst access mode configuration
            • +
          • Update FMC_SDRAM_Timing_Init() to fix initialization issue when configuring 2 SDRAM banks
            • +
          • +
        • HAL HCD update +
            +
          • Update HCD_Port_IRQHandler() to unmask disconnect IT only when the port is disabled
            • +
          • +
        • HAL I2C/FMPI2C update +
            +
          • Update Polling management: +
              +
            • The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
              • +
            • +
          • Add the management of Abort service: Abort DMA transfer through interrupt +
              +
            • In the case of Master Abort IT transfer usage: +
                +
              • Add new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process
                • +
              • A new abort state is defined in the HAL_I2C_StateTypeDef structure
                • +
              • +
            • +
          • Add the management of I2C peripheral errors, ACK failure and STOP condition detection during DMA process. This requires the following updates on user application: +
              +
            • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
              • +
            • In stm32f4xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
              • +
            • Add and customize the Error Callback API: HAL_I2C_ErrorCallback()
              • +
            • Refer to the I2C_EEPROM or I2C_TwoBoards_ComDMA project examples usage of the API
              • +
            • +
          • NACK error during addressing phase is returned through interrupt instead of previously through I2C transfer API’s
            • +
          • I2C addressing phase is updated to be managed using interrupt instead of polling (Only for HAL I2C driver) +
              +
            • Add new static functions to manage I2C SB, ADDR and ADD10 flags
              • +
            • +
          • +
        • HAL SPI update +
            +
          • Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency +
              +
            • Polling mode: +
                +
              • Replace the use of SPI_WaitOnFlagUnitTimeout() function by “if” statement to check on RXNE/TXE flags while transferring data
                • +
              • +
            • Interrupt mode: +
                +
              • Minimize access on SPI registers
                • +
              • +
            • All modes: +
                +
              • Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled
                • +
              • Update timeout management to check on global processes
                • +
              • Update error code management in all processes
                • +
              • +
            • Update DMA process: +
                +
              • Add the management of SPI peripheral errors during DMA process. This requires the following updates in the user application:
                • +
              • Configure and enable the SPI IRQ in HAL_SPI_MspInit() function
                • +
              • In stm32f4xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function
                • +
              • Add and customize the Error Callback API: HAL_SPI_ErrorCallback()
                • +
              • Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA
                • +
              • +
            • Fix regression in polling mode: +
                +
              • Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()
                • +
              • Add to manage properly the overrun flag at the end of a HAL_SPI_TransmitReceive()
                • +
              • +
            • Fix regression in interrupt mode: +
                +
              • Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()
                • +
              • Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()
                • +
              • +
            • +
          • +
        • HAL DMA2D update +
            +
          • Update the HAL_DMA2D_DeInit() function to: +
              +
            • Abort transfer in case of ongoing DMA2D transfer
              • +
            • Reset DMA2D control registers
              • +
            • +
          • Update HAL_DMA2D_Abort() to disable DMA2D interrupts after stopping transfer
            • +
          • Optimize HAL_DMA2D_IRQHandler() by reading status registers only once
            • +
          • Update HAL_DMA2D_ProgramLineEvent() function to: +
              +
            • Return HAL error state in case of wrong line value
              • +
            • Enable line interrupt after setting the line watermark configuration
              • +
            • +
          • Add new HAL_DMA2D_CLUTLoad() and HAL_DMA2D_CLUTLoad_IT() functions to start DMA2D CLUT loading +
              +
            • HAL_DMA2D_CLUTLoading_Abort() function to abort the DMA2D CLUT loading
              • +
            • HAL_DMA2D_CLUTLoading_Suspend() function to suspend the DMA2D CLUT loading
              • +
            • HAL_DMA2D_CLUTLoading_Resume() function to resume the DMA2D CLUT loading
              • +
            • +
          • Add new DMA2D dead time management: +
              +
            • HAL_DMA2D_EnableDeadTime() function to enable DMA2D dead time feature
              • +
            • HAL_DMA2D_DisableDeadTime() function to disable DMA2D dead time feature
              • +
            • HAL_DMA2D_ConfigDeadTime() function to configure dead time
              • +
            • +
          • Update the name of DMA2D Input/Output color mode defines to be more clear for user (DMA2D_INPUT_XXX for input layers Colors, DMA2D_OUTPUT_XXX for output framebuffer Colors)
            • +
          • +
        • HAL LTDC update +
            +
          • Update HAL_LTDC_IRQHandler() to manage the case of reload interrupt
            • +
          • Add new callback API HAL_LTDC_ReloadEventCallback()
            • +
          • Add HAL_LTDC_Reload() to configure LTDC reload feature
            • +
          • Add new No Reload LTDC variant APIs +
              +
            • HAL_LTDC_ConfigLayer_NoReload() to configure the LTDC Layer according to the specified without reloading
              • +
            • HAL_LTDC_SetWindowSize_NoReload() to set the LTDC window size without reloading
              • +
            • HAL_LTDC_SetWindowPosition_NoReload() to set the LTDC window position without reloading
              • +
            • HAL_LTDC_SetPixelFormat_NoReload() to reconfigure the pixel format without reloading
              • +
            • HAL_LTDC_SetAlpha_NoReload() to reconfigure the layer alpha value without reloading
              • +
            • HAL_LTDC_SetAddress_NoReload() to reconfigure the frame buffer Address without reloading
              • +
            • HAL_LTDC_SetPitch_NoReload() to reconfigure the pitch for specific cases
              • +
            • HAL_LTDC_ConfigColorKeying_NoReload() to configure the color keying without reloading
              • +
            • HAL_LTDC_EnableColorKeying_NoReload() to enable the color keying without reloading
              • +
            • HAL_LTDC_DisableColorKeying_NoReload() to disable the color keying without reloading
              • +
            • HAL_LTDC_EnableCLUT_NoReload() to enable the color lookup table without reloading
              • +
            • HAL_LTDC_DisableCLUT_NoReload() to disable the color lookup table without reloading
              • +
            • Note: Variant functions with “_NoReload” post fix allows to set the LTDC configuration/settings without immediate reload. This is useful in case when the program requires to modify several LTDC settings (on one or both layers) then applying (reload) these settings in one shot by calling the function “HAL_LTDC_Reload”
              • +
            • +
          • +
        • HAL RTC update +
            +
          • Add new timeout implementation based on cpu cycles for ALRAWF, ALRBWF and WUTWF flags
            • +
          • +
        • HAL SAI update +
            +
          • Update SAI state in case of TIMEOUT error within the HAL_SAI_Transmit() / HAL_SAI_Receive()
            • +
          • Update HAL_SAI_IRQHandler: +
              +
            • Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()
              • +
            • Add error management in case of IT
              • +
            • +
          • Move SAI_BlockSynchroConfig() and SAI_GetInputClock() functions to stm32f4xx_hal_sai.c/.h files (extension files are kept empty for projects compatibility reason)
            • +
          • +
        • HAL DCMI update +
            +
          • Rename DCMI_DMAConvCplt to DCMI_DMAXferCplt
            • +
          • Update HAL_DCMI_Start_DMA() function to Enable the DCMI peripheral
            • +
          • Add new timeout implementation based on cpu cycles for DCMI stop
            • +
          • Add HAL_DCMI_Suspend() function to suspend DCMI capture
            • +
          • Add HAL_DCMI_Resume() function to resume capture after DCMI suspend
            • +
          • Update lock mechanism for DCMI process
            • +
          • Update HAL_DCMI_IRQHandler() function to: +
              +
            • Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()
              • +
            • Optimize code by using direct register read
              • +
            • +
          • +
        • HAL DMA update +
            +
          • Add new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to register/unregister the different callbacks identified by the enum typedef HAL_DMA_CallbackIDTypeDef
            • +
          • Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context +
              +
            • The new registered Abort callback is called when DMA transfer abortion is completed
              • +
            • +
          • Add the check of compatibility between FIFO threshold level and size of the memory burst in the HAL_DMA_Init() API
            • +
          • Add new Error Codes: HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED
            • +
          • Remove all DMA states related to MEM0/MEM1 in HAL_DMA_StateTypeDef
            • +
          • +
        • HAL IWDG update +
            +
          • Overall rework of the driver for a more efficient implementation +
              +
            • Remove the following APIs: +
                +
              • HAL_IWDG_Start()
                • +
              • HAL_IWDG_MspInit()
                • +
              • HAL_IWDG_GetState()
                • +
              • +
            • +
          • Update implementation: +
              +
            • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter
              • +
            • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
              • +
            • +
          • Refer to the following example to identify the changes: IWDG_Example
            • +
          • +
        • HAL LPTIM update +
            +
          • Update HAL_LPTIM_TimeOut_Start_IT() and HAL_LPTIM_Counter_Start_IT( ) APIs to configure WakeUp Timer EXTI interrupt to be able to wakeup MCU from low power mode by pressing the EXTI line.
            • +
          • Update HAL_LPTIM_TimeOut_Stop_IT() and HAL_LPTIM_Counter_Stop_IT( ) APIs to disable WakeUp Timer EXTI interrupt.
            • +
          • +
        • HAL NOR update +
            +
          • Update NOR_ADDR_SHIFT macro implementation
            • +
          • +
        • HAL PCD update +
            +
          • Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value
            • +
          • +
        • HAL QSPI update +
            +
          • Update to manage QSPI error management during DMA process
            • +
          • Improve the DMA transmit process by using QSPI TC interrupt instead of waiting loop on TC flag under DMA ISR
            • +
          • These two improvements require the following updates on user application: +
              +
            • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
              • +
            • In stm32f4xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function
              • +
            • Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()
              • +
            • +
          • Add the management of non-blocking transfer abort service: HAL_QSPI_Abort_IT(). In this case the user must: +
              +
            • Add new callback HAL_QSPI_AbortCpltCallback() to inform user at the end of abort process
              • +
            • A new value of State in the HAL_QSPI_StateTypeDef provides the current state during the abort phase
              • +
            • +
          • Polling management update: +
              +
            • The Timeout value user must be estimated for the overall process duration: the Timeout measurement is cumulative.
              • +
            • +
          • Refer to the following examples, which describe the changes: +
              +
            • QSPI_ReadWrite_DMA
              • +
            • QSPI_MemoryMapped
              • +
            • QSPI_ExecuteInPlace
              • +
            • +
          • Add two new APIs for the QSPI fifo threshold: +
              +
            • HAL_QSPI_SetFifoThreshold(): configure the FIFO threshold of the QSPI
              • +
            • HAL_QSPI_GetFifoThreshold(): give the current FIFO threshold
              • +
            • +
          • Fix wrong data size management in HAL_QSPI_Receive_DMA()
            • +
          • +
        • HAL ADC update +
            +
          • Add new __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() macro for STM32F42x and STM32F43x devices to provide the possibility to convert VrefInt channel when both VrefInt and Vbat channels are selected.
            • +
          • +
        • HAL SPDIFRX update +
            +
          • Overall driver update for wait on flag management optimization
            • +
          • +
        • HAL WWDG update +
            +
          • Overall rework of the driver for more efficient implementation +
              +
            • Remove the following APIs: +
                +
              • HAL_WWDG_Start()
                • +
              • HAL_WWDG_Start_IT()
                • +
              • HAL_WWDG_MspDeInit()
                • +
              • HAL_WWDG_GetState()
                • +
              • +
            • Update implementation: +
                +
              • HAL_WWDG_Init() +
                  +
                • A new parameter in the Init Structure: EWIMode
                  • +
                • +
              • HAL_WWDG_MspInit()
                • +
              • HAL_WWDG_Refresh() +
                  +
                • This function insures the reload of the counter
                  • +
                • The “counter” parameter has been removed
                  • +
                • +
              • HAL_WWDG_IRQHandler()
                • +
              • HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeUpCallback()
                • +
              • +
            • +
          • Refer to the following example to identify the changes: WWDG_Example
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • HAL Generic update +
            +
          • stm32f4xx_hal_conf_template.h +
              +
            • Optimize HSE Startup Timeout value from 5000ms to 100 ms
              • +
            • Add new define LSE_STARTUP_TIMEOUT
              • +
            • Add new define USE_SPI_CRC for code cleanup when the CRC calculation is disabled.
              • +
            • +
          • Update HAL drivers to support MISRA C 2004 rule 10.6
            • +
          • Add new template driver to configure timebase using TIMER : +
              +
            • stm32f4xx_hal_timebase_tim_template.c
              • +
            • +
          • +
        • HAL CAN update +
            +
          • Update HAL_CAN_Transmit() and HAL_CAN_Transmit_IT() functions to unlock process when all Mailboxes are busy
            • +
          • +
        • HAL DSI update +
            +
          • Update HAL_DSI_SetPHYTimings() functions to use the correct mask
            • +
          • +
        • HAL UART update +
            +
          • Several update on HAL UART driver to implement the new UART state machine: +
              +
            • Add new field in UART_HandleTypeDef structure: “rxState”, UART state information related to Rx Operations
              • +
            • Rename “state” field in UART_HandleTypeDef structure by “gstate”: UART state information related to global Handle management and Tx Operations
              • +
            • Update UART process to manage the new UART states.
              • +
            • Update __HAL_UART_RESET_HANDLE_STATE() macro to handle the new UART state parameters (gState, rxState)
              • +
            • +
          • Update UART_BRR_SAMPLING16() and UART_BRR_SAMPLING8() Macros to fix wrong baudrate calculation.
            • +
          • +
        • HAL IRDA update +
            +
          • Several update on HAL IRDA driver to implement the new UART state machine: +
              +
            • Add new field in IRDA_HandleTypeDef structure: “rxState”, IRDA state information related to Rx Operations
              • +
            • Rename “state” field in UART_HandleTypeDef structure by “gstate”: IRDA state information related to global Handle management and Tx Operations
              • +
            • Update IRDA process to manage the new UART states.
              • +
            • Update __HAL_IRDA_RESET_HANDLE_STATE() macro to handle the new IRDA state parameters (gState, rxState)
              • +
            • +
          • Removal of IRDA_TIMEOUT_VALUE define
            • +
          • Update IRDA_BRR() Macro to fix wrong baudrate calculation
            • +
          • +
        • HAL SMARTCARD update +
            +
          • Several update on HAL SMARTCARD driver to implement the new UART state machine: +
              +
            • Add new field in SMARTCARD_HandleTypeDef structure: “rxState”, SMARTCARDstate information related to Rx Operations
              • +
            • Rename “state” field in UART_HandleTypeDef structure by “gstate”: SMARTCARDstate information related to global Handle management and Tx Operations
              • +
            • Update SMARTCARD process to manage the new UART states.
              • +
            • Update __HAL_SMARTCARD_RESET_HANDLE_STATE() macro to handle the new SMARTCARD state parameters (gState, rxState)
              • +
            • +
          • Update SMARTCARD_BRR() macro to fix wrong baudrate calculation
            • +
          • +
        • HAL RCC update +
            +
          • Add new default define value for HSI calibration “RCC_HSICALIBRATION_DEFAULT”
            • +
          • Optimize Internal oscillators and PLL startup timeout
            • +

          • Update to avoid the disable for HSE/LSE oscillators before setting the new RCC HSE/LSE configuration and add the following notes in HAL_RCC_OscConfig() API description:

            +
                               * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+                   *             supported by this API. User should request a transition to LSE Off
+                   *             first and then LSE On or LSE Bypass.
+                   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+                   *             supported by this API. User should request a transition to HSE Off
+                   *             first and then HSE On or HSE Bypass.
            • +
          • Optimize the HAL_RCC_ClockConfig() API implementation.
            • +
          • +
        • HAL DMA2D update +
            +
          • Update HAL_DMA2D_Abort() Function to end current DMA2D transfer properly
            • +
          • Update HAL_DMA2D_PollForTransfer() function to add poll for background CLUT loading (layer 0 and layer 1).
            • +
          • Update HAL_DMA2D_PollForTransfer() to set the corresponding ErrorCode in case of error occurrence
            • +
          • Update HAL_DMA2D_ConfigCLUT() function to fix wrong CLUT size and color mode settings
            • +
          • Removal of useless macro __HAL_DMA2D_DISABLE()
            • +
          • Update HAL_DMA2D_Suspend() to manage correctly the case where no transfer is on going
            • +
          • Update HAL_DMA2D_Resume() to manage correctly the case where no transfer is on going
            • +
          • Update HAL_DMA2D_Start_IT() to enable all required interrupts before enabling the transfer.
            • +
          • Add HAL_DMA2D_CLUTLoad_IT() Function to allow loading a CLUT with interruption model.
            • +

          • Update HAL_DMA2D_IRQHandler() to manage the following cases :

            +
              +
            • CLUT transfer complete
              • +
            • CLUT access error
              • +
            • Transfer watermark reached
              • +
            • +
          • Add new Callback APIs: +
              +
            • HAL_DMA2D_LineEventCallback() to signal a transfer watermark reached event
              • +
            • HAL_DMA2D_CLUTLoadingCpltCallback() to signal a CLUT loading complete event
              • +
            • +
          • Miscellaneous Improvement: +
              +
            • Add “HAL_DMA2D_ERROR_CAE” new define for CLUT Access error management.
              • +
            • Add “assert_param” used for parameters check is now done on the top of the exported functions : before locking the process using __HAL_LOCK
              • +
            • +
          • +
        • HAL I2C update +
            +
          • Add support of I2C repeated start feature: +
              +
            • With the following new API’s +
                +
              • HAL_I2C_Master_Sequential_Transmit_IT()
                • +
              • HAL_I2C_Master_Sequential_Receive_IT()
                • +
              • HAL_I2C_Master_Abort_IT()
                • +
              • HAL_I2C_Slave_Sequential_Transmit_IT()
                • +
              • HAL_I2C_Slave_Sequential_Receive_IT()
                • +
              • HAL_I2C_EnableListen_IT()
                • +
              • HAL_I2C_DisableListen_IT()
                • +
              • +
            • +
          • Add new user callbacks: +
              +
            • HAL_I2C_ListenCpltCallback()
              • +
            • HAL_I2C_AddrCallback()
              • +
            • +
          • Update to generate STOP condition when a acknowledge failure error is detected
            • +
          • Several update on HAL I2C driver to implement the new I2C state machine: +
              +
            • Add new API to get the I2C mode: HAL_I2C_GetMode()
              • +
            • Update I2C process to manage the new I2C states.
              • +
            • +
          • Fix wrong behaviour in single byte transmission
            • +
          • Update I2C_WaitOnFlagUntilTimeout() to manage the NACK feature.
            • +
          • Update I2C transmission process to support the case data size equal 0
            • +
          • +
        • HAL FMPI2C update +
            +
          • Add support of FMPI2C repeated start feature: +
              +
            • With the following new API’s +
                +
              • HAL_FMPI2C_Master_Sequential_Transmit_IT()
                • +
              • HAL_FMPI2C_Master_Sequential_Receive_IT()
                • +
              • HAL_FMPI2C_Master_Abort_IT()
                • +
              • HAL_FMPI2C_Slave_Sequential_Transmit_IT()
                • +
              • HAL_FMPI2C_Slave_Sequential_Receive_IT()
                • +
              • HAL_FMPI2C_EnableListen_IT()
                • +
              • HAL_FMPI2C_DisableListen_IT()
                • +
              • +
            • Add new user callbacks: +
                +
              • HAL_FMPI2C_ListenCpltCallback()
                • +
              • HAL_FMPI2C_AddrCallback()
                • +
              • +
            • Several update on HAL I2C driver to implement the new I2C state machine: +
                +
              • Add new API to get the FMPI2C mode: HAL_FMPI2C_GetMode()
                • +
              • Update FMPI2C process to manage the new FMPI2C states.
                • +
              • +
            • +
          • +
        • HAL SPI update +
            +
          • Major Update to improve performance in polling/interrupt mode to reach max frequency: +
              +
            • Polling mode : +
                +
              • Replace use of SPI_WaitOnFlagUnitTimeout() funnction by “if” statement to check on RXNE/TXE flags while transferring data.
                • +
              • Use API data pointer instead of SPI handle data pointer.
                • +
              • Use a Goto implementation instead of “if..else” statements.
                • +
              • +
            • Interrupt mode +
                +
              • Minimize access on SPI registers.
                • +
              • Split the SPI modes into dedicated static functions to minimize checking statements under HAL_IRQHandler(): +
                  +
                • 1lines/2lines modes
                  • +
                • 8 bit/ 16 bits data formats
                  • +
                • CRC calculation enabled/disabled.
                  • +
                • +
              • Remove waiting loop under ISR when closing the communication.
                • +
              • +
            • All modes: +
                +
              • Adding switch USE_SPI_CRC to minimize number of statements when CRC calculation is disabled.
                • +
              • Update Timeout management to check on global process.
                • +
              • Update Error code management in all processes.
                • +
              • +
            • +
          • Add note to the max frequencies reached in all modes.
            • +
          • Add note about Master Receive mode restrictions : +
              +
            • Master Receive mode restriction: +
              +(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI does not initiate a new transfer the following procedure has to be respected:
              +(##) HAL_SPI_DeInit()
              +(##) HAL_SPI_Init() +
              • +
            • +
          • +
        • HAL SAI update +
            +
          • Update for proper management of the external synchronization input selection +
              +
            • update of HAL_SAI_Init () function
              • +
            • update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups
              • +
            • +
          • Update SAI_SLOTACTIVE_X defines values
            • +
          • Update HAL_SAI_Init() function for proper companding mode management
            • +
          • Update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers
            • +
          • Update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size
            • +
          • Update HAL_SAI_EnableRxMuteMode() function for proper mute management
            • +
          • Update SAI_InitPCM() function to support 24bits configuration
            • +
          • +
        • HAL ETH update +
            +
          • Removal of ETH MAC debug register defines
            • +
          • +
        • HAL FLASH update +
            +
          • Update FLASH_MassErase() function to apply correctly voltage range parameter
            • +
          • +
        • HAL I2S update +
            +
          • Update I2S_DMATxCplt() and I2S_DMARxCplt() to manage properly FullDuplex mode without any risk of missing data.
            • +
          • +
        • LL FMC update +
            +
          • Update the FMC_NORSRAM_Init() function to use BurstAccessMode field properly
            • +
          • +
        • LL FSMC update +
            +
          • Update the FSMC_NORSRAM_Init() function to use BurstAccessMode field properly
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • HAL Generic update +
            +
          • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers by calling the following line: +
              +
            • UNUSED(hppp);
              • +
            • +
          • STM32Fxxx_User_Manual.chm files regenerated for HAL V1.4.3
            • +
          • +
        • HAL ETH update +
            +
          • Update HAL_ETH_Init() function to add timeout on the Software reset management
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          +
          • +
        • One change done on the HAL CRYP requires an update on the application code based on HAL V1.4.1 +
            +
          • Update HAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData parameters
            +
            • +
          • +
        • HAL generic update +
            +
          • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers by calling the following line: +
              +
            • UNUSED(hppp);
              +
              • +
            • +
          • +
        • HAL CORTEX update +
            +
          • Remove duplication for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro
            +
            • +
          • +
        • HAL HASH update +
            +
          • Rename HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef
            • +
          • Rename HAL_HASH_PhaseTypeDef to HAL_HASH_PhaseTypeDef
            • +
          • +
        • HAL RCC update +
            +
          • Add new macros __HAL_RCC_PPP_IS_CLK_ENABLED() to check on Clock enable/disable status
            • +
          • Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable for the SYSCFG
            • +
          • Update HAL_RCC_MCOConfig() API to use new defines for the GPIO Speed
            • +
          • Generic update to improve the PLL VCO min value(100MHz): PLLN, PLLI2S and PLLSAI min value is 50 instead of 192
            • +
          • +
        • HAL FLASH update +
            +
          • __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset ICRST bit in the ACR register after setting it.
            • +
          • Update to support until 15 FLASH wait state (FLASH_LATENCY_15) for STM32F446xx devices
            • +
          • +
        • HAL CRYP update +
            +
          • Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue
            • +
          • +
        • HAL I2S update +
            +
          • Update HAL_I2S_Init() API to call __HAL_RCC_I2S_CONFIG() macro when external I2S clock is selected
            • +
          • +
        • HAL LTDC update +
            +
          • Update HAL_LTDC_SetWindowPosition() API to configure Immediate reload register instead of vertical blanking reload register.
            • +
          • +
        • HAL TIM update +
            +
          • Update HAL_TIM_ConfigClockSource() API to check only the required parameters
            • +
          • +
        • HAL NAND update +
            +
          • Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access
            • +
          • +
        • HAL CAN update +
            +
          • Update to use “=” instead of “|=” to clear flags in the MSR, TSR, RF0R and RF1R registers
            • +
          • +
        • HAL HCD update +
            +
          • Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation
            • +
          • +
        • HAL PCD update +
            +
          • Update HAL_PCD_IRQHandler() API to avoid issue when DMA mode enabled for Status Phase IN stage
            • +
          • +
        • LL FMC update +
            +
          • Update the FMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters
            • +
          • Update the FMC_NORSRAM_Init() API to add a check on the PageSize parameter for STM32F42/43xx devices
            • +
          • +
        • LL FSMC update +
            +
          • Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • HAL DSI update +
            +
          • Update TCCR register assigned value in HAL_DSI_ConfigHostTimeouts() function
            • +
          • Update WPCR register assigned value in HAL_DSI_Init(), HAL_DSI_SetSlewRateAndDelayTuning(), HAL_DSI_SetSlewRateAndDelayTuning(), HAL_DSI_SetLowPowerRXFilter() / HAL_DSI_SetSDD(), HAL_DSI_SetLanePinsConfiguration(), HAL_DSI_SetPHYTimings(), HAL_DSI_ForceTXStopMode(), HAL_DSI_ForceRXLowPower(), HAL_DSI_ForceDataLanesInRX(), HAL_DSI_SetPullDown() and HAL_DSI_SetContentionDetectionOff() functions
            • +
          • Update DSI_HS_PM_ENABLE define value
            • +
          • Implement workaround for the hardware limitation: “The time to activate the clock between HS transmissions is not calculated correctly”
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F469xx, STM32F479xx, STM32F410Cx, STM32F410Rx and STM32F410Tx devices
          • +
        • General updates to fix known defects and enhancements implementation
          • +
        • Add new HAL drivers for DSI and LPTIM peripherals
          • +
        • HAL ADC update +
            +
          • Rename ADC_CLOCKPRESCALER_PCLK_DIV2 define to ADC_CLOCK_SYNC_PCLK_DIV2
            • +
          • Rename ADC_CLOCKPRESCALER_PCLK_DIV4 define to ADC_CLOCK_SYNC_PCLK_DIV4
            • +
          • Rename ADC_CLOCKPRESCALER_PCLK_DIV6 define to ADC_CLOCK_SYNC_PCLK_DIV6
            • +
          • Rename ADC_CLOCKPRESCALER_PCLK_DIV8 define to ADC_CLOCK_SYNC_PCLK_DIV8
            • +
          • +
        • HAL CORTEX update +
            +
          • Add specific API for MPU management +
              +
            • add MPU_Region_InitTypeDef structure
              • +
            • add new function HAL_MPU_ConfigRegion()
              • +
            • +
          • +
        • HAL DMA update +
            +
          • Overall driver update for code optimization +
              +
            • add StreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef structure
              • +
            • add DMA_Base_Registers private structure
              • +
            • add static function DMA_CalcBaseAndBitshift()
              • +
            • update HAL_DMA_Init() function to use the new added static function
              • +
            • update HAL_DMA_DeInit() function to optimize clear flag operations
              • +
            • update HAL_DMA_Start_IT() function to optimize interrupts enable
              • +
            • update HAL_DMA_PollForTransfer() function to optimize check on flags
              • +
            • update HAL_DMA_IRQHandler() function to optimize interrupt flag management
              • +
            • +
          • +
        • HAL FLASH update +
            +
          • update HAL_FLASH_Program_IT() function by removing the pending flag clear
            • +
          • update HAL_FLASH_IRQHandler() function to improve erase operation procedure
            • +
          • update FLASH_WaitForLastOperation() function by checking on end of operation flag
            • +
          • +
        • HAL GPIO update +
            +
          • Rename GPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW
            • +
          • Rename GPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM
            • +
          • Rename GPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH
            • +
          • Rename GPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH
            • +
          • +
        • HAL I2S update +
            +
          • Move I2S_Clock_Source defines to extension file to properly add the support of STM32F410xx devices
            • +
          • +
        • HAL LTDC update +
            +
          • rename HAL_LTDC_LineEvenCallback() function to HAL_LTDC_LineEventCallback()
            • +
          • add new function HAL_LTDC_SetPitch()
            • +
          • add new functions HAL_LTDC_StructInitFromVideoConfig() and HAL_LTDC_StructInitFromAdaptedCommandConfig() applicable only to STM32F469xx and STM32F479xx devices
            • +
          • +
        • HAL PWR update +
            +
          • move __HAL_PWR_VOLTAGESCALING_CONFIG() macro to extension file
            • +
          • move PWR_WAKEUP_PIN2 define to extension file
            • +
          • add PWR_WAKEUP_PIN3 define, applicable only to STM32F10xx devices
            • +
          • add new functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() and HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), applicable only to STM32F469xx and STM32F479xx devices
            • +
          • +
        • HAL RTC update +
            +
          • Update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on the WUTWF flag
            • +
          • +
        • HAL TIM update +
            +
          • add new defines TIM_SYSTEMBREAKINPUT_HARDFAULT, TIM_SYSTEMBREAKINPUT_PVD and TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, applicable only to STM32F410xx devices
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and enhancements implementation
          • +
        • One changes done on the HAL may require an update on the application code based on HAL V1.3.1 +
            +
          • HASH IT process: update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
            • +
          • +
        • HAL RCC update +
            +
          • HAL_RCCEx_PeriphCLKConfig() updates: +
              +
            • Update the LSE check condition after backup domain reset: update to check LSE ready flag when LSE oscillator is already enabled instead of check on LSE oscillator only when LSE is used as RTC clock source
              • +
            • Use the right macro to check the PLLI2SQ parameters
              • +
            • +
          • +
        • HAL RTC update +
            +
          • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro: fix implementation issue
            • +
          • __HAL_RTC_ALARM_GET_IT(), __HAL_RTC_ALARM_CLEAR_FLAG(), __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), __HAL_RTC_TIMESTAMP_CLEAR_FLAG() and __HAL_RTC_TAMPER_CLEAR_FLAG() macros implementation changed: remove unused cast
            • +
          • IS_RTC_TAMPER() macro: update to use literal instead of hardcoded value
            • +
          • Add new parameter SecondFraction in RTC_TimeTypeDef structure
            • +
          • HAL_RTC_GetTime() API update to support the new parameter SecondFraction
            • +
          • +
        • HAL ADC update +
            +
          • Add new literal: ADC_INJECTED_SOFTWARE_START to be used as possible value for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef structure to select the ADC software trigger mode.
            • +
          • +
        • HAL FLASH update +
            +
          • FLASH_OB_GetRDP() API update to return uint8_t instead of FlagStatus
            • +
          • __HAL_FLASH_GET_LATENCY() new macro add to get the flash latency
            • +
          • +
        • HAL SPI update +
            +
          • Fix the wrong definition of HAL_SPI_ERROR_FLAG literal
            • +
          • +
        • HAL I2S update +
            +
          • HAL_I2S_Transmit() API update to check on busy flag only for I2S slave mode
            • +
          • +
        • HAL CRC update +
            +
          • __HAL_CRC_SET_IDR() macro implementation change to use WRITE_REG() instead of MODIFY_REG()
            • +
          • +
        • HAL DMA2D update +
            +
          • HAL_DMA2D_ConfigLayer() API update to use “=” instead of “|=” to erase BGCOLR and FGCOLR registers before setting the new configuration
            • +
          • +
        • HAL HASH update +
            +
          • HAL_HASH_MODE_Start_IT() (MODE stands for MD5, SHA1, SHA224 and SHA36) updates: +
              +
            • Fix processing fail for small input buffers
              • +
            • Update to unlock the process and call return HAL_OK at the end of HASH processing to avoid incorrectly repeating software
              • +
            • Update to properly manage the HashITCounter
              • +
            • Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
              • +
            • +
          • __HAL_HASH_GET_FLAG() update to check the right register when the DINNE flag is selected
            • +
          • HAL_HASH_SHA1_Accumulate() updates: +
              +
            • Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter.
              • +
            • Add the following note in API description +
                +
              • @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
                • +
              • +
            • +
          • +
        • HAL RTC update +
            +
          • Update to define hardware independent literals names: +
              +
            • Rename RTC_TAMPERPIN_PC13 by RTC_TAMPERPIN_DEFAULT
              • +
            • Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1
              • +
            • Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1
              • +
            • Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT
              • +
            • Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1
              • +
            • Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1
              • +
            • +
          • +
        • HAL ETH update +
            +
          • Remove duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros
            • +
          • Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro
            • +
          • Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS)
            • +
          • +
        • HAL PCD update +
            +
          • HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time
            • +
          • +
        • HAL HCD update +
            +
          • Update to use local variable in USB Host channel re-activation
            • +
          • +
        • LL FMC update +
            +
          • FMC_SDRAM_SendCommand() API: remove the following line: return HAL_ERROR;
            • +
          • +
        • LL USB update +
            +
          • USB_FlushTxFifo API: update to flush all Tx FIFO
            • +
          • Update to use local variable in USB Host channel re-activation
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • HAL PWR update +
            +
          • Fix compilation issue with STM32F417xx product: update STM32F17xx by STM32F417xx
            • +
          • +
        • HAL SPI update +
            +
          • Remove unused variable to avoid warning with TrueSTUDIO
            • +
          • +
        • HAL I2C update +
            +
          • I2C Polling/IT/DMA processes: move the wait loop on busy flag at the top of the processes, to ensure that software not perform any write access to I2C_CR1 register before hardware clearing STOP bit and to avoid also the waiting loop on BUSY flag under I2C/DMA ISR.
            • +
          • Update busy flag Timeout value
            • +
          • I2C Master Receive Processes update to disable ACK before generate the STOP
            • +
          • +
        • HAL DAC update +
            +
          • Fix V1.3.0 regression issue with DAC software trigger configuration
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F446xx devices
          • +
        • General updates to fix known defects and enhancements implementation
          • +
        • Add new HAL drivers for CEC, QSPI, FMPI2C and SPDIFRX peripherals
          • +
        • Two changes done on the HAL requires an update on the application code based on HAL V1.2.0 +
            +
          • Overall SAI driver rework to have exhaustive support of the peripheral features: details are provided in HAL SAI update section below –> Compatibility with previous version is impacted
            • +
          • CRYP driver updated to support multi instance,so user must ensure that the new parameter Instance is initialized in his application(CRYPHandle.Instance = CRYP)
            • +
          • +
        • HAL Generic update +
            +
          • stm32f4xx_hal_def.h +
              +
            • Remove NULL definition and add include for stdio.h
              • +
            • +
          • stm32_hal_legacy.h +
              +
            • Update method to manage deference in alias implementation between all STM32 families
              • +
            • +
          • stm32f4xx_hal_ppp.c +
              +
            • HAL_PPP_Init(): update to force the HAL_PPP_STATE_RESET before calling the HAL_PPP_MspInit()
              • +
            • +
          • +
        • HAL RCC update +
            +
          • Add new function HAL_RCCEx_GetPeriphCLKFreq()
            • +
          • Move RCC_PLLInitTypeDef structure to extension file and add the new PLLR field specific to STM32F446xx devices
            • +
          • Move the following functions to extension file and add a __weak attribute in generic driver : this update is related to new system clock source (PLL/PLLR) added and only available for STM32F44xx devices +
              +
            • HAL_RCC_OscConfig()
              • +
            • HAL_RCC_GetSysClockFreq()
              • +
            • HAL_RCC_GetOscConfig()
              • +
            • +
          • Move the following macro to extension file as they have device dependent implementation +
              +
            • __HAL_RCC_PLL_CONFIG()
              • +
            • __HAL_RCC_PLLI2S_CONFIG()
              • +
            • __HAL_RCC_I2S_CONFIG()
              • +
            • +
          • Add new structure RCC_PLLI2SInitTypeDef containing new PLLI2S division factors used only w/ STM32F446xx devices
            • +
          • Add new structure RCC_PLLSAIInitTypeDef containing new PLLSAI division factors used only w/ STM32F446xx devices
            • +
          • Add new RCC_PeriphCLKInitTypeDef to support the peripheral source clock selection for (I2S, SAI, SDIO, FMPI2C, CEC, SPDIFRX and CLK48)
            • +
          • Update the HAL_RCCEx_PeriphCLKConfig() and HAL_RCCEx_GetPeriphCLKConfig() functions to support the new peripherals Clock source selection
            • +
          • Add __HAL_RCC_PLL_CONFIG() macro (the number of parameter and the implementation depend on the device part number)
            • +
          • Add __HAL_RCC_PLLI2S_CONFIG() macro(the number of parameter and the implementation depend on device part number)
            • +
          • Update __HAL_RCC_PLLSAI_CONFIG() macro to support new PLLSAI factors (PLLSAIM and PLLSAIP)
            • +
          • Add new macros for clock enable/Disable for the following peripherals (CEC, SPDIFRX, SAI2, QUADSPI)
            • +
          • Add the following new macros for clock source selection : +
              +
            • __HAL_RCC_SAI1_CONFIG() / __HAL_RCC_GET_SAI1_SOURCE()
              • +
            • __HAL_RCC_SAI2_CONFIG() / __HAL_RCC_GET_SAI2_SOURCE()
              • +
            • __HAL_RCC_I2S1_CONFIG() / __HAL_RCC_GET_I2S1_SOURCE()
              • +
            • __HAL_RCC_I2S2_CONFIG() / __HAL_RCC_GET_I2S2_SOURCE()
              • +
            • __HAL_RCC_CEC_CONFIG() / __HAL_RCC__GET_CEC_SOURCE()
              • +
            • __HAL_RCC_FMPI2C1_CONFIG() / __HAL_RCC_GET_FMPI2C1_SOURCE()
              • +
            • __HAL_RCC_SDIO_CONFIG() / __HAL_RCC_GET_SDIO_SOURCE()
              • +
            • __HAL_RCC_CLK48_CONFIG() / __HAL_RCC_GET_CLK48_SOURCE()
              • +
            • __HAL_RCC_SPDIFRXCLK_CONFIG() / __HAL_RCC_GET_SPDIFRX_SOURCE()
              • +
            • +
          • __HAL_RCC_PPP_CLK_ENABLE(): Implement workaround to cover RCC limitation regarding peripheral enable delay
            • +
          • HAL_RCC_OscConfig() fix issues: +
              +
            • Add a check on LSERDY flag when LSE_BYPASS is selected as new state for LSE oscillator.
              • +
            • +
          • Add new possible value RCC_PERIPHCLK_PLLI2S to be selected as PeriphClockSelection parameter in the RCC_PeriphCLKInitTypeDef structure to allow the possibility to output the PLLI2S on MCO without activating the I2S or the SAI.
            • +

          • __HAL_RCC_HSE_CONFIG() macro: add the comment below:
            +* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
            +* User should request a transition to HSE Off first and then HSE On or HSE Bypass.

            • +

          • __HAL_RCC_LSE_CONFIG() macro: add the comment below:
            +* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
            +* User should request a transition to LSE Off first and then LSE On or LSE Bypass.

            • +
          • Add the following new macros for PLL source and PLLM selection : +
              +
            • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
              • +
            • __HAL_RCC_PLL_PLLM_CONFIG()
              • +
            • +
          • Macros rename: +
              +
            • HAL_RCC_OTGHS_FORCE_RESET() by HAL_RCC_USB_OTG_HS_FORCE_RESET()
              • +
            • HAL_RCC_OTGHS_RELEASE_RESET() by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
              • +
            • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
              • +
            • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
              • +
            • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
              • +
            • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
              • +
            • +
          • Add __HAL_RCC_SYSCLK_CONFIG() new macro to configure the system clock source (SYSCLK)
            • +
          • __HAL_RCC_GET_SYSCLK_SOURCE() updates: +
              +
            • Add new RCC Literals: +
                +
              • RCC_SYSCLKSOURCE_STATUS_HSI
                • +
              • RCC_SYSCLKSOURCE_STATUS_HSE
                • +
              • RCC_SYSCLKSOURCE_STATUS_PLLCLK
                • +
              • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
                • +
              • +
            • Update macro description to refer to the literals above
              • +
            • +
          • +
        • HAL PWR update +
            +
          • Add new define PWR_WAKEUP_PIN2
            • +
          • Add new API to Control/Get VOS bits of CR register +
              +
            • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
              • +
            • HAL_PWREx_GetVoltageRange()
              • +
            • +
          • __HAL_PWR_ VOLTAGESCALING_CONFIG(): Implement workaround to cover VOS limitation delay when PLL is enabled after setting the VOS configuration
            • +
          • +
        • HAL GPIO update +
            +
          • Add the new Alternate functions literals related to remap for SPI, USART, I2C, SPDIFRX, CEC and QSPI
            • +
          • HAL_GPIO_DeInit(): Update to check if GPIO Pin x is already used in EXTI mode on another GPIO Port before De-Initialize the EXTI registers
            • +
          • +
        • HAL FLASH update +
            +
          • __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset ICRST bit in the ACR register after setting it.
            • +
          • __HAL_FLASH_DATA_CACHE_RESET() macro: update to reset DCRST bit in the ACR register after setting it.
            • +
          • +
        • HAL ADC update +
            +
          • Add new literal: ADC_SOFTWARE_START to be used as possible value for the ExternalTrigConv parameter in the ADC_InitTypeDef structure to select the ADC software trigger mode.
            • +
          • IS_ADC_CHANNEL() macro update to don’t assert stop the ADC_CHANNEL_TEMPSENSOR value
            • +
          • HAL_ADC_PollForConversion(): update to manage particular case when ADC configured in DMA mode and ADC sequencer with several ranks and polling for end of each conversion
            • +
          • HAL_ADC_Start()/HAL_ADC_Start_IT() /HAL_ADC_Start_DMA() update: +
              +
            • unlock the process before starting the ADC software conversion.
              • +
            • Optimize the ADC stabilization delays
              • +
            • +
          • __HAL_ADC_GET_IT_SOURCE() update macro implementation
            • +
          • Add more details in ‘How to use this driver’ section
            • +
          • +
        • HAL DAC update +
            +
          • Add new macro to check if the specified DAC interrupt source is enabled or disabled +
              +
            • __HAL_DAC_GET_IT_SOURCE()
              • +
            • +
          • HAL_DACEx_TriangleWaveGeneration() update to use DAC CR bit mask definition
            • +
          • HAL_DACEx_NoiseWaveGeneration() update to use DAC CR bit mask definition
            • +
          • +
        • HAL CAN update +
            +
          • CanTxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8]
            • +
          • CanRxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8]
            • +
          • +
        • HAL RTC update +
            +
          • Update to use CMSIS mask definition instead of hardcoded values (EXTI_IMR_IM17, EXTI_IMR_IM19..)
            • +
          • +
        • HAL LTDC update +
            +
          • LTDC_SetConfig() update to allow the drawing of partial bitmap in active layer.
            • +
          • +
        • HAL USART update +
            +
          • HAL_USART_Init() fix USART baud rate configuration issue: USART baud rate is twice Higher than expected
            • +
          • +
        • HAL SMARTCARD update +
            +
          • HAL_SMARTCARD_Transmit_IT() update to force the disable for the ERR interrupt to avoid the OVR interrupt
            • +
          • HAL_SMARTCARD_IRQHandler() update check condition for transmission end
            • +
          • Clean up: remove the following literals that aren’t used in smartcard mode +
              +
            • SMARTCARD_PARITY_NONE
              • +
            • SMARTCARD_WORDLENGTH_8B
              • +
            • SMARTCARD_STOPBITS_1
              • +
            • SMARTCADR_STOPBITS_2
              • +
            • +
          • +
        • HAL SPI update +
            +
          • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TarnsmitReceive_DMA() update to unlock the process before enabling the SPI peripheral
            • +
          • HAL_SPI_Transmit_DMA() update to manage correctly the DMA RX stream in SPI Full duplex mode
            • +
          • Section SPI_Exported_Functions_Group2 update to remove duplication in *.chm UM
            • +
          • +
        • HAL CRYP update +
            +
          • Update to manage multi instance: +
              +
            • Add new parameter Instance in the CRYP_HandleTypeDef Handle structure.
              • +
            • Add new parameter in all HAL CRYP macros +
                +
              • example: __HAL_CRYP_ENABLE() updated by __HAL_CRYP_ENABLE(__HANDLE__)
                • +
              • +
            • +
          • +
        • HAL DCMI update +
            +
          • Add an extension driver stm32f4xx_hal_dcmi_ex.c/h to manage the support of new Black and White feature
            • +
          • Add __weak attribute for HAL_DCMI_Init() function and add a new implementation in the extension driver to manage the black and white configuration only available in the STM32F446xx devices.
            • +
          • Move DCMI_InitTypeDef structure to extension driver and add the following new fields related to black and white feature: ByteSelectMode, ByteSelectStart, LineSelectMode and LineSelectStart
            • +
          • +
        • HAL PCD update +
            +
          • Add the support of LPM feature +
              +
            • add PCD_LPM_StateTypeDef enum
              • +
            • update PCD_HandleTypeDef structure to support the LPM feature
              • +
            • add new functions HAL_PCDEx_ActivateLPM(), HAL_PCDEx_DeActivateLPM() and HAL_PCDEx_LPM_Callback() in the stm32f4xx_hal_pcd_ex.h/.c files
              • +
            • +
          • +
        • HAL TIM update +
            +
          • Add TIM_TIM11_SPDIFRX define
            • +
          • +
        • HAL SAI update +
            +
          • Add stm32f4xx_hal_sai_ex.h/.c files for the SAI_BlockSynchroConfig() and the SAI_GetInputClock() management
            • +
          • Add new defines HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_CNREADY, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code group
            • +
          • Add new defines SAI_SYNCEXT_DISABLE, SAI_SYNCEXT_IN_ENABLE, SAI_SYNCEXT_OUTBLOCKA_ENABLE, SAI_SYNCEXT_OUTBLOCKB_ENABLE for the SAI External synchronization
            • +
          • Add new defines SAI_I2S_STANDARD, SAI_I2S_MSBJUSTIFIED, SAI_I2S_LSBJUSTIFIED, SAI_PCM_LONG and SAI_PCM_SHORT for the SAI Supported protocol
            • +
          • Add new defines SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT and SAI_PROTOCOL_DATASIZE_32BIT for SAI protocol data size
            • +
          • Add SAI Callback prototype definition
            • +
          • Update SAI_InitTypeDef structure by adding new fields: SynchroExt, Mckdiv, MonoStereoMode, CompandingMode, TriState
            • +
          • Update SAI_HandleTypeDef structure: +
              +
            • remove uint16_t pTxBuffPtr, pRxBuffPtr, TxXferSize, RxXferSize, TxXferCount and RxXferCount and replace them respectively by uint8_t *pBuffPtr, uint16_t XferSize and uint16_t XferCount
              • +
            • add mutecallback field
              • +
            • add struct __SAI_HandleTypeDef *hsai field
              • +
            • +
          • Remove SAI_CLKSOURCE_PLLR and SAI_CLOCK_PLLSRC defines
            • +
          • Add SAI_CLKSOURCE_NA define
            • +
          • Add SAI_AUDIO_FREQUENCY_MCKDIV define
            • +
          • Add SAI_SPDIF_PROTOCOL define
            • +
          • Add SAI_SYNCHRONOUS_EXT define
            • +
          • Add new functions HAL_SAI_InitProtocol(), HAL_SAI_Abort(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_DisableRxMuteMode()
            • +
          • Update HAL_SAI_Transmit(), HAL_SAI_Receive(), HAL_SAI_Transmit_IT(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Receive_DMA() functions to use uint8_t pData instead of uint16_t pData –> This update is mainly impacting the compatibility with previous driver version.
            • +
          • +
        • HAL I2S update +
            +
          • Split the following functions between Generic and Extended API based on full duplex management and add the attribute __weak in the Generic API +
              +
            • HAL_I2S_Init(), HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle()
              • +
            • +
          • Move the following static functions from generic to extension driver +
              +
            • I2S_DMARxCplt() and I2S_DMATxCplt()
              • +
            • +
          • Remove static attribute from I2S_Transmit_IT() and I2S_Receive_IT() functions
            • +
          • Move I2SxEXT() macro to extension file
            • +
          • Add I2S_CLOCK_PLLR and I2S_CLOCK_PLLSRC defines for I2S clock source
            • +
          • Add new function I2S_GetInputClock()
            • +
          • +
        • HAL LL FMC update +
            +
          • Add WriteFifo and PageSize fields in the FMC_NORSRAM_InitTypeDef structure
            • +
          • Add FMC_PAGE_SIZE_NONE, FMC_PAGE_SIZE_128, FMC_PAGE_SIZE_256, FMC_PAGE_SIZE_1024, FMC_WRITE_FIFO_DISABLE, FMC_WRITE_FIFO_ENABLE defines
            • +
          • Update FMC_NORSRAM_Init(), FMC_NORSRAM_DeInit() and FMC_NORSRAM_Extended_Timing_Init() functions
            • +
          • +
        • HAL LL USB update +
            +
          • Update USB_OTG_CfgTypeDef structure to support LPM, lpm_enable field added
            • +
          • Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Maintenance release to fix known defects and enhancements implementation
          • +
        • Macros and literals renaming to ensure compatibles across STM32 series, backward compatibility maintained thanks to new added file stm32_hal_legacy.h under /Inc/Legacy
          • +
        • Add *.chm UM for all drivers, a UM is provided for each superset RPN
          • +
        • Update drivers to be C++ compliant
          • +
        • Several update on source code formatting, for better UM generation (i.e. Doxygen tags updated)
          • +
        • Two changes done on the HAL requires an update on the application code based on HAL V1.1.0 +
            +
          • LSI_VALUE constant has been corrected in stm32f4xx_hal_conf.h file, its value changed from 40 KHz to 32 KHz
            • +
          • UART, USART, IRDA and SMARTCARD (referenced as PPP here below) drivers: in DMA transmit process, the code has been updated to avoid waiting on TC flag under DMA ISR, PPP TC interrupt is used instead. Below the update to be done on user application: +
              +
            • Configure and enable the USART IRQ in HAL_PPP_MspInit() function
              • +
            • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
              • +
            • +
          • +
        • HAL generic update +
            +
          • stm32f4xx_hal_def.h +
              +
            • Update NULL definition to fix C++ compilation issue
              • +
            • Add UNUSED() macro
              • +
            • Add a new define __NOINLINE to be used for the no inline code independent from tool chain
              • +
            • +
          • stm32f4xx_hal_conf_template.h +
              +
            • LSI_VALUE constant has been corrected, its value changed from 40 KHz to 32 KHz
              • +
            • +
          • Update all macros and literals naming to be uper case
            • +
          • ErrorCode parameter in PPP_HandleTypeDef structure updated to uint32_t instead of enum HAL_PPP_ErrorTypeDef
            • +
          • Remove the unused FLAG and IT assert macros
            • +
          • +
        • HAL ADC update +
            +
          • Fix temperature sensor channel configuration issue for STM32F427/437xx and STM32F429/439xx devices
            • +
          • +
        • HAL DAC update +
            +
          • HAL_DAC_ConfigChannel(): update the access to the DAC peripheral registers via the hdac handle instance
            • +
          • HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and DAC_FLAG_DMAUDR2
            • +
          • HAL_DACEx_NoiseWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration
            • +
          • HAL_DACEx_TriangleWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration
            • +
          • +
        • HAL CAN update +
            +
          • Unlock the CAN process when communication error occurred
            • +
          • +
        • HAL CORTEX update +
            +
          • Add new macro IS_NVIC_DEVICE_IRQ() to check on negative values of IRQn parameter
            • +
          • +

        • HAL CRYP update

          +
            +
          • HAL_CRYP_DESECB_Decrypt_DMA(): fix the inverted pPlainData and pCypherData parameters issue
            • +
          • CRYPEx_GCMCCM_SetInitVector(): remove the IVSize parameter as the key length 192bits and 256bits are not supported by this version
            • +
          • Add restriction for the CCM Encrypt/Decrypt API’s that only DataType equal to 8bits is supported
            • +
          • HAL_CRYPEx_AESGCM_Finish(): +
              +
            • Add restriction that the implementation is limited to 32bits inputs data length (Plain/Ciphertext, Header) compared with GCM stadards specifications (800-38D)
              • +
            • Update Size parameter on 32bits instead of 16bits
              • +
            • Fix issue with 16-bit Data Type: update to use intrinsic __ROR() instead of __REV16()
              • +
            • +
          • +

        • HAL DCMI update

          +
            +
          • HAL_DCMI_ConfigCROP(): Invert assert macros to check Y0 and Ysize parameters
            • +
          • +

        • HAL DMA update

          +
            +
          • HAL_DMA_Init(): Update to clear the DBM bit in the SxCR register before setting the new configuration
            • +
          • DMA_SetConfig(): add to clear the DBM bit in the SxCR register
            • +
          • +

        • HAL FLASH update

          +
            +
          • Add “HAL_” prefix in the defined values for the FLASH error code +
              +
            • Example: FLASH_ERROR_PGP renamed by HAL_FLASH_ERROR_PGP
              • +
            • +
          • Clear the Flash ErrorCode in the FLASH_WaitForLastOperation() function
            • +
          • Update FLASH_SetErrorCode() function to use “|=” operant to update the Flash ErrorCode parameter in the FLASH handle
            • +
          • IS_FLASH_ADDRESS(): Update the macro check using ‘<=’ condition instead of ‘<’
            • +
          • IS_OPTIONBYTE(): Update the macro check using ‘<=’ condition instead of ‘<’
            • +
          • Add “FLASH_” prefix in the defined values of FLASH Type Program parameter +
              +
            • Example: TYPEPROGRAM_BYTE renamed by FLASH_TYPEPROGRAM_BYTE
              • +
            • +
          • Add “FLASH_” prefix in the defined values of FLASH Type Erase parameter +
              +
            • Example: TYPEERASE_SECTORS renamed by FLASH_TYPEERASE_SECTORS
              • +
            • +
          • Add “FLASH_” prefix in the defined values of FLASH Voltage Range parameter +
              +
            • Example: VOLTAGE_RANGE_1 renamed by FLASH_VOLTAGE_RANGE_1
              • +
            • +
          • Add “OB_” prefix in the defined values of FLASH WRP State parameter +
              +
            • Example: WRPSTATE_ENABLE renamed by OB_WRPSTATE_ENABLE
              • +
            • +
          • Add “OB_” prefix in the defined values of the FLASH PCROP State parameter +
              +
            • PCROPSTATE_DISABLE updated by OB_PCROP_STATE_DISABLE
              • +
            • PCROPSTATE_ENABLE updated by OB_PCROP_STATE_ENABLE
              • +
            • +
          • Change “OBEX” prefix by “OPTIONBYTE” prefix in these defines: +
              +
            • OBEX_PCROP by OPTIONBYTE_PCROP
              • +
            • OBEX_BOOTCONFIG by OPTIONBYTE_BOOTCONFIG
              • +
            • +
          • +
        • HAL ETH update +
            +
          • Fix macros naming typo +
              +
            • Update __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() by __HAL_ETH_EXTI_SET_RISING_EDGE_TRIGGER()
              • +
            • Update __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() by __HAL_ETH_EXTI_SET_FALLING_EDGE_TRIGGER()
              • +
            • +
          • +
        • HAL PWR update +
            +
          • Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register +
              +
            • HAL_PWR_DisableSleepOnExit()
              • +
            • HAL_PWR_EnableSleepOnExit()
              • +
            • HAL_PWR_EnableSEVOnPend()
              • +
            • HAL_PWR_DisableSEVOnPend()
              • +
            • +
          • HAL_PWR_EnterSTOPMode() +
              +
            • Update to clear the CORTEX SLEEPDEEP bit of SCR register before entering in sleep mode
              • +
            • Update usage of __WFE() in low power entry function: if there is a pending event, calling __WFE() will not enter the CortexM4 core to sleep mode. The solution is to made the call below; the first __WFE() is always ignored and clears the event if one was already pending, the second is always applied
              +__SEV()
              +__WFE()
              +__WFE()
              • +
            • +
          • Add new PVD configuration modes +
              +
            • PWR_PVD_MODE_NORMAL
              • +
            • PWR_PVD_MODE_EVENT_RISING
              • +
            • PWR_PVD_MODE_EVENT_FALLING
              • +
            • PWR_PVD_MODE_EVENT_RISING_FALLING
              • +
            • +
          • Add new macros to manage PVD Trigger +
              +
            • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()
              • +
            • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(
              • +
            • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()
              • +
            • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
              • +
            • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
              • +
            • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
              • +
            • +
          • PVD macros: +
              +
            • Remove the __EXTILINE__ parameter
              • +
            • Update to use prefix "__HAL_PWR_PVD_" instead of prefix "__HAL_PVD"
              • +
            • +
          • Rename HAL_PWR_PVDConfig() by HAL_PWR_ConfigPVD()
            • +
          • Rename HAL_PWREx_ActivateOverDrive() by HAL_PWREx_EnableOverDrive()
            • +
          • Rename HAL_PWREx_DeactivateOverDrive() by HAL_PWREx_DisableOverDrive()
            • +
          • +
        • HAL GPIO update +
            +
          • HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call to the CMSIS assert macro to check GPIO instance: IS_GPIO_ALL_INSTANCE()
            • +
          • HAL_GPIO_WritePin(): update to write in BSRR register
            • +
          • Rename GPIO_GET_SOURCE() by GET_GPIO_INDEX() and move this later to file stm32f4xx_hal_gpio_ex.h
            • +
          • Add new define for alternate function GPIO_AF5_SPI3 for STM32F429xx/439xx and STM32F427xx/437xx devices
            • +
          • +
        • HAL HASH update +
            +
          • HAL_HASH_MD5_Start_IT(): fix input address management issue
            +
            • +
          • +
        • HAL RCC update +
            +
          • Rename the following Macros +
              +
            • __PPP_CLK_ENABLE() by __HAL_RCC_PPP_CLK_ENABLE()
              • +
            • __PPP_CLK_DISABLE() by __HAL_RCC_PPP_CLK_DISABLE()
              • +
            • __PPP_FORCE_RESET() by __HAL_RCC_PPP_FORCE_RESET()
              • +
            • __PPP_RELEASE_RESET() by __HAL_RCC_PPP_RELEASE_RESET()
              • +
            • __PPP_CLK_SLEEP_ENABLE() by __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
              • +
            • __PPP_CLK_SLEEP_DISABLE() by __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
              • +
            • +
          • IS_RCC_PLLSAIN_VALUE() macro: update the check condition
            • +
          • Add description of RCC known Limitations
            • +
          • Rename HAL_RCC_CCSCallback() by HAL_RCC_CSSCallback()
            • +
          • HAL_RCC_OscConfig() fix issues: +
              +
            • Remove the disable of HSE oscillator when HSE_BYPASS is used as system clock source or as PPL clock source
              • +
            • Add a check on HSERDY flag when HSE_BYPASS is selected as new state for HSE oscillator.
              • +
            • +
          • Rename __HAL_RCC_I2SCLK() by __HAL_RCC_I2S_Config()
            • +
          • +

        • HAL I2S update

          +
            +
          • HAL_I2S_Init(): add check on I2S instance using CMSIS macro IS_I2S_ALL_INSTANCE()
            • +
          • HAL_I2S_IRQHandler() update for compliance w/ C++
            • +
          • Add use of tmpreg variable in __HAL_I2S_CLEAR_OVRFLAG() and __HAL_I2S_CLEAR_UDRFLAG() macro for compliance with C++
            • +
          • HAL_I2S_GetError(): update to return uint32_t instead of HAL_I2S_ErrorTypeDef enumeration
            • +
          • +

        • HAL I2C update

          +
            +
          • Update to clear the POS bit in the CR1 register at the end of HAL_I2C_Master_Read_IT() and HAL_I2C_Mem_Read_IT() process
            • +
          • Rename HAL_I2CEx_DigitalFilter_Config() by HAL_I2CEx_ConfigDigitalFilter()
            • +
          • Rename HAL_I2CEx_AnalogFilter_Config() by HAL_I2CEx_ConfigAnalogFilter()
            • +
          • Add use of tmpreg variable in __HAL_I2C_CLEAR_ADDRFLAG() and __HAL_I2C_CLEAR_STOPFLAG() macro for compliance with C++
            • +
          • +
        • HAL IrDA update +
            +
          • DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, IrDA TC interrupt is used instead. Below the update to be done on user application: +
              +
            • Configure and enable the USART IRQ in HAL_IRDA_MspInit() function
              • +
            • In stm32f4xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_IRDA_IRQHandler() function
              • +
            • +
          • IT transmit process; the code has been updated to avoid waiting on TC flag under IRDA ISR, IrDA TC interrupt is used instead. No impact on user application
            • +
          • Rename Macros: add prefix "__HAL" +
              +
            • __IRDA_ENABLE() by __HAL_IRDA_ENABLE()
              • +
            • __IRDA_DISABLE() by __HAL_IRDA_DISABLE()
              • +
            • +
          • +
        • Add new user macros to manage the sample method feature +
            +
          • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
            • +
          • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
            • +
          • +
        • HAL_IRDA_Transmit_IT(): update to remove the enable of the parity error interrupt
          • +
        • Add use of tmpreg variable in __HAL_IRDA_CLEAR_PEFLAG() macro for compliance with C++
          • +
        • HAL_IRDA_Transmit_DMA() update to follow the right procedure “Transmission using DMA” in the reference manual +
            +
          • Add clear the TC flag in the SR register before enabling the DMA transmit request
            • +
          • +
        • HAL IWDG update +
            +
          • Rename the defined IWDG keys: +
              +
            • KR_KEY_RELOAD by IWDG_KEY_RELOAD
              • +
            • KR_KEY_ENABLE by IWDG_KEY_ENABLE
              • +
            • KR_KEY_EWA by IWDG_KEY_WRITE_ACCESS_ENABLE
              • +
            • KR_KEY_DWA by IWDG_KEY_WRITE_ACCESS_DISABLE
              • +
            • +
          • Add new macros __HAL_IWDG_RESET_HANDLE_STATE() and __HAL_IWDG_CLEAR_FLAG()
            • +
          • Update __HAL_IWDG_ENABLE_WRITE_ACCESS() and __HAL_IWDG_DISABLE_WRITE_ACCESS() as private macro
            • +
          • +

        • HAL SPI update

          +
            +
          • HAL_SPI_TransmitReceive_DMA() update to remove the DMA Tx Error Callback initialization when SPI RxOnly mode is selected
            • +
          • Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix “Unused variable” warning with TrueSTUDIO.
            • +
          • Rename Literals: remove “D” from “DISABLED” and “ENABLED” +
              +
            • SPI_TIMODE_DISABLED by SPI_TIMODE_DISABLE
              • +
            • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
              • +
            • SPI_CRCCALCULATION_DISABLED by SPI_CRCCALCULATION_DISABLE
              • +
            • SPI_CRCCALCULATION_ENABLED by SPI_CRCCALCULATION_ENABLE
              • +
            • +
          • Add use of tmpreg variable in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_FREFLAG() and __HAL_SPI_CLEAR_OVRFLAG() macros for compliance with C++
            +
            • +
          • +

        • HAL SDMMC update

          +
            +
          • IS_SDIO_ALL_INSTANCE() macro moved to CMSIS files
            • +
          • +
        • HAL LTDC update +
            +
          • HAL_LTDC_ConfigCLUT: optimize the function when pixel format is LTDC_PIXEL_FORMAT_AL44 +
              +
            • Update the size of color look up table to 16 instead of 256 when the pixel format is LTDC_PIXEL_FORMAT_AL44
              • +
            • +
          • +
        • HAL NAND update +
            +
          • Rename NAND Address structure to NAND_AddressTypeDef instead of NAND_AddressTypedef
            • +
          • Update the used algorithm of these functions +
              +
            • HAL_NAND_Read_Page()
              • +
            • HAL_NAND_Write_Page()
              • +
            • HAL_NAND_Read_SpareArea()
              • +
            • HAL_NAND_Write_SpareArea()
              • +
            • +
          • HAL_NAND_Write_Page(): move initialization of tickstart before while loop
            • +
          • HAL_NAND_Erase_Block(): add whait until NAND status is ready before exiting this function
            • +
          • +
        • HAL NOR update +
            +
          • Rename NOR Address structure to NOR_AddressTypeDef instead of NOR_AddressTypedef
            • +
          • NOR Status literals renamed +
              +
            • NOR_SUCCESS by HAL_NOR_STATUS_SUCCESS
              • +
            • NOR_ONGOING by HAL_NOR_STATUS_ONGOING
              • +
            • NOR_ERROR by HAL_NOR_STATUS_ERROR
              • +
            • NOR_TIMEOUT by HAL_NOR_STATUS_TIMEOUT
              • +
            • +
          • HAL_NOR_GetStatus() update to fix Timeout issue and exit from waiting loop when timeout occurred
            • +
          • +
        • HAL PCCARD update +
            +
          • Rename PCCARD Address structure to HAL_PCCARD_StatusTypeDef instead of CF_StatusTypedef
            • +
          • PCCARD Status literals renamed +
              +
            • CF_SUCCESS by HAL_PCCARD_STATUS_SUCCESS
              • +
            • CF_ONGOING by HAL_PCCARD_STATUS_ONGOING
              • +
            • CF_ERROR by HAL_PCCARD_STATUS_ERROR
              • +
            • CF_TIMEOUT by HAL_PCCARD_STATUS_TIMEOUT
              • +
            • +
          • Update “CF” by “PCCARD” in functions, literals and macros
            • +
          • +
        • HAL PCD update +
            +
          • Rename functions +
              +
            • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
              • +
            • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
              • +
            • +
          • Rename literals +
              +
            • USB_FS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
              • +
            • USB_FS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
              • +
            • USB_FS_EXTI_TRIGGER_BOTH_EDGE() by USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
              • +
            • USB_HS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
              • +
            • USB_HS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
              • +
            • USB_HS_EXTI_TRIGGER_BOTH_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
              • +
            • USB_HS_EXTI_LINE_WAKEUP by USB_OTG_HS_EXTI_LINE_WAKEUP
              • +
            • USB_FS_EXTI_LINE_WAKEUP by USB_OTG_FS_EXTI_LINE_WAKEUP
              • +
            • +
          • +
        • Rename USB EXTI macros (FS, HS referenced as SUBBLOCK here below) +
            +
          • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()
            +
            • +
          • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
            • +
          • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG()
            • +
          • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
            • +
          • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
            • +
          • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
            • +
          • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
            • +
          • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT()
            +
            • +
          • +
        • HAL RNG update +
            +
          • Add new functions +
              +
            • HAL_RNG_GenerateRandomNumber(): to generate a 32-bits random number, return random value in argument and return HAL status.
              • +
            • HAL_RNG_GenerateRandomNumber_IT(): to start generation of the 32-bits random number, user should call the HAL_RNG_ReadLastRandomNumber() function under the HAL_RNG_ReadyCallback() to get the generated random value.
              • +
            • HAL_RNG_ReadLastRandomNumber(): to return the last random value stored in the RNG handle
              • +
            • +
          • HAL_RNG_GetRandomNumber(): return value update (obsolete), replaced by HAL_RNG_GenerateRandomNumber()
            • +
          • HAL_RNG_GetRandomNumber_IT(): wrong implementation (obsolete), replaced by HAL_RNG_GenerateRandomNumber_IT()
            • +
          • __HAL_RNG_CLEAR_FLAG() macro (obsolete), replaced by new __HAL_RNG_CLEAR_IT() macro
            • +
          • Add new define for RNG ready interrupt: RNG_IT_DRDY
            • +
          • +
        • HAL RTC update +
            +

          • HAL_RTC_GetTime() and HAL_RTC_GetDate(): add the comment below
            +* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
            +* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
            +* Reading RTC current time locks the values in calendar shadow registers until Current date is read.

            • +
          • Rename literals: add prefix "__HAL" +
              +
            • FORMAT_BIN by HAL_FORMAT_BIN
              • +
            • FORMAT_BCD by HAL_FORMAT_BCD
              • +
            • +
          • Rename macros (ALARM, WAKEUPTIMER and TIMESTAMP referenced as SUBBLOCK here below) +
              +
            • __HAL_RTC_EXTI_ENABLE_IT() by __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
              • +
            • __HAL_RTC_EXTI_DISABLE_IT() by __HAL_RTC__SUBBLOCK_EXTI_DISABLE_IT()
              • +
            • __HAL_RTC_EXTI_CLEAR_FLAG() by __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()
              • +
            • __HAL_RTC_EXTI_GENERATE_SWIT() by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
              • +
            • +
          • Add new macros (ALARM, WAKEUPTIMER and TAMPER_TIMESTAMP referenced as SUBBLOCK here below) +
              +
            • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE()
              • +
            • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
              • +
            • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
              • +
            • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
              • +
            • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
              • +
            • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
              • +
            • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
              • +
            • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
              • +
            • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
              • +
            • __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
              • +
            • +
          • +
        • HAL SAI update +
            +
          • Update SAI_STREOMODE by SAI_STEREOMODE
            • +
          • Update FIFO status Level defines in upper case
            • +
          • Rename literals: remove “D” from “DISABLED” and “ENABLED” +
              +
            • SAI_OUTPUTDRIVE_DISABLED by SAI_OUTPUTDRIVE_DISABLE
              • +
            • SAI_OUTPUTDRIVE_ENABLED by SAI_OUTPUTDRIVE_ENABLE
              • +
            • SAI_MASTERDIVIDER_ENABLED by SAI_MASTERDIVIDER_ENABLE
              • +
            • SAI_MASTERDIVIDER_DISABLED by SAI_MASTERDIVIDER_DISABLE
              • +
            • +
          • +
        • HAL SD update +
            +
          • Rename SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
            • +
          • SD_PowerON() updated to add 1ms required power up waiting time before starting the SD initialization sequence
            • +
          • SD_DMA_RxCplt()/SD_DMA_TxCplt(): add a call to HAL_DMA_Abort()
            • +
          • HAL_SD_ReadBlocks() update to set the defined DATA_BLOCK_SIZE as SDIO DataBlockSize parameter
            • +
          • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() update to call the HAL_DMA_Start_IT() function with DMA Datalength set to BlockSize/4 as the DMA is configured in word
            • +
          • +
        • HAL SMARTCARD update +
            +
          • DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, SMARTCARD TC interrupt is used instead. Below the update to be done on user application: +
              +
            • Configure and enable the USART IRQ in HAL_SAMRTCARD_MspInit() function
              • +
            • In stm32f4xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_SMARTCARD_IRQHandler() function
              • +
            • +
          • IT transmit process; the code has been updated to avoid waiting on TC flag under SMARTCARD ISR, SMARTCARD TC interrupt is used instead. No impact on user application
            • +
          • Rename macros: add prefix "__HAL" +
              +
            • __SMARTCARD_ENABLE() by __HAL_SMARTCARD_ENABLE()
              • +
            • __SMARTCARD_DISABLE() by __HAL_SMARTCARD_DISABLE()
              • +
            • __SMARTCARD_ENABLE_IT() by __HAL_SMARTCARD_ENABLE_IT()
              • +
            • __SMARTCARD_DISABLE_IT() by __HAL_SMARTCARD_DISABLE_IT()
              • +
            • __SMARTCARD_DMA_REQUEST_ENABLE() by __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
              • +
            • __SMARTCARD_DMA_REQUEST_DISABLE() by __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
              • +
            • +
          • Rename literals: remove “D” from “DISABLED” and “ENABLED” +
              +
            • SMARTCARD_NACK_ENABLED by SMARTCARD_NACK_ENABLE
              • +
            • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
              • +
            • +
          • Add new user macros to manage the sample method feature +
              +
            • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
              • +
            • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
              • +
            • +
          • Add use of tmpreg variable in __HAL_SMARTCARD_CLEAR_PEFLAG() macro for compliance with C++
            • +
          • HAL_SMARTCARD_Transmit_DMA() update to follow the right procedure “Transmission using DMA” in the reference manual +
              +
            • Add clear the TC flag in the SR register before enabling the DMA transmit request
              • +
            • +
          • +
        • HAL TIM update +
            +
          • Add TIM_CHANNEL_ALL as possible value for all Encoder Start/Stop APIs Description
            • +
          • HAL_TIM_OC_ConfigChannel() remove call to IS_TIM_FAST_STATE() assert macro
            • +
          • HAL_TIM_PWM_ConfigChannel() add a call to IS_TIM_FAST_STATE() assert macro to check the OCFastMode parameter
            • +
          • HAL_TIM_DMADelayPulseCplt() Update to set the TIM Channel before to call HAL_TIM_PWM_PulseFinishedCallback()
            • +
          • HAL_TIM_DMACaptureCplt() update to set the TIM Channel before to call HAL_TIM_IC_CaptureCallback()
            • +
          • TIM_ICx_ConfigChannel() update to fix Timer CCMR1 register corruption when setting ICFilter parameter
            • +
          • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() update to abort the DMA transfer for the specific TIM channel
            • +
          • Add new function for TIM Slave configuration in IT mode: HAL_TIM_SlaveConfigSynchronization_IT()
            • +
          • HAL_TIMEx_ConfigBreakDeadTime() add an assert check on Break & DeadTime parameters values
            • +
          • HAL_TIMEx_OCN_Start_IT() add the enable of Break Interrupt for all output modes
            • +
          • Add new macros to ENABLE/DISABLE URS bit in TIM CR1 register: +
              +
            • __HAL_TIM_URS_ENABLE()
              • +
            • __HAL_TIM_URS_DISABLE()
              • +
            • +
          • Add new macro for TIM Edge modification: __HAL_TIM_SET_CAPTUREPOLARITY()
            • +
          • +
        • HAL UART update +
            +
          • Add IS_LIN_WORD_LENGTH() and IS_LIN_OVERSAMPLING() macros: to check respectively WordLength and OverSampling parameters in LIN mode
            • +
          • DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, UART TC interrupt is used instead. Below the update to be done on user application: +
              +
            • Configure and enable the USART IRQ in HAL_UART_MspInit() function
              • +
            • In stm32f4xx_it.c file, USARTx_IRQHandler() function: add a call to HAL_UART_IRQHandler() function
              • +
            • +
          • IT transmit process; the code has been updated to avoid waiting on TC flag under UART ISR, UART TC interrupt is used instead. No impact on user application
            • +
          • Rename macros: +
              +
            • __HAL_UART_ONEBIT_ENABLE() by __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
              • +
            • __HAL_UART_ONEBIT_DISABLE() by __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
              • +
            • +
          • Rename literals: +
              +
            • UART_WAKEUPMETHODE_IDLELINE by UART_WAKEUPMETHOD_IDLELINE
              • +
            • UART_WAKEUPMETHODE_ADDRESSMARK by UART_WAKEUPMETHOD_ADDRESSMARK
              • +
            • +
          • Add use of tmpreg variable in __HAL_UART_CLEAR_PEFLAG() macro for compliance with C++
            • +
          • HAL_UART_Transmit_DMA() update to follow the right procedure “Transmission using DMA” in the reference manual +
              +
            • Add clear the TC flag in the SR register before enabling the DMA transmit request
              • +
            • +
          • +
        • HAL USART update +
            +
          • DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, USART TC interrupt is used instead. Below the update to be done on user application: +
              +
            • Configure and enable the USART IRQ in HAL_USART_MspInit() function
              • +
            • In stm32f4xx_it.c file, USARTx_IRQHandler() function: add a call to HAL_USART_IRQHandler() function
              • +
            • +
          • IT transmit process; the code has been updated to avoid waiting on TC flag under USART ISR, USART TC interrupt is used instead. No impact on user application
            • +
          • HAL_USART_Init() update to enable the USART oversampling by 8 by default in order to reach max USART frequencies
            • +
          • USART_DMAReceiveCplt() update to set the new USART state after checking on the old state
            • +
          • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() update to follow the right procedure “Transmission using DMA” in the reference manual +
              +
            • Add clear the TC flag in the SR register before enabling the DMA transmit request
              • +
            • +
          • Rename macros: +
              +
            • __USART_ENABLE() by __HAL_USART_ENABLE()
              • +
            • __USART_DISABLE() by __HAL_USART_DISABLE()
              • +
            • __USART_ENABLE_IT() by __HAL_USART_ENABLE_IT()
              • +
            • __USART_DISABLE_IT() by __HAL_USART_DISABLE_IT()
              • +
            • +
          • Rename literals: remove “D” from “DISABLED” and “ENABLED” +
              +
            • USART_CLOCK_DISABLED by USART_CLOCK_DISABLE
              • +
            • USART_CLOCK_ENABLED by USART_CLOCK_ENABLE
              • +
            • USARTNACK_ENABLED by USART_NACK_ENABLE
              • +
            • USARTNACK_DISABLED by USART_NACK_DISABLE
              • +
            • +
          • Add new user macros to manage the sample method feature +
              +
            • __HAL_USART_ONE_BIT_SAMPLE_ENABLE()
              • +
            • __HAL_USART_ONE_BIT_SAMPLE_DISABLE()
              • +
            • +
          • Add use of tmpreg variable in __HAL_USART_CLEAR_PEFLAG() macro for compliance with C++
            • +
          • +
        • HAL WWDG update +
            +
          • Add new parameter in __HAL_WWDG_ENABLE_IT() macro
            • +
          • Add new macros to manage WWDG IT & correction: +
              +
            • __HAL_WWDG_DISABLE()
              • +
            • __HAL_WWDG_DISABLE_IT()
              • +
            • __HAL_WWDG_GET_IT()
              • +
            • __HAL_WWDG_GET_IT_SOURCE()
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F411xE devices
          • +
        • HAL generic update +
            +
          • Enhance HAL delay and time base implementation +
              +
            • Systick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source)
              • +
            • Functions affecting time base configurations are declared as __Weak to make override possible in case of other implementations in user file, for more details please refer to HAL_TimeBase example
              • +
            • +
          • Fix flag clear procedure: use atomic write operation “=” instead of ready-modify-write operation “|=” or “&=”
            • +
          • Fix on Timeout management, Timeout value set to 0 passed to API automatically exits the function after checking the flag without any wait
            • +
          • Common update for the following communication peripherals: SPI, UART, USART and IRDA +
              +
            • Add DMA circular mode support
              • +
            • Remove lock from recursive process
              • +
            • +
          • Add new macro __HAL_RESET_HANDLE_STATE to reset a given handle state
            • +
          • Add a new attribute for functions executed from internal SRAM and depending from Compiler implementation
            • +
          • When USE_RTOS == 1 (in stm32l0xx_hal_conf.h), the __HAL_LOCK() is not defined instead of being defined empty
            • +
          • Miscellaneous comments and formatting update
            • +
          • stm32f4xx_hal_conf_template.h +
              +
            • Add a new define for LSI default value LSI_VALUE
              • +
            • Add a new define for LSE default value LSE_VALUE
              • +
            • Add a new define for Tick interrupt priority TICK_INT_PRIORITY (needed for the enhanced time base implementation)
              • +
            • Important Note: aliases has been added for any API naming change, to keep compatibility with previous version
              • +
            • +
          • +
        • HAL GPIO update +
            +
          • Add a new macro __HAL_GPIO_EXTI_GENERATE_SWIT() to manage the generation of software interrupt on selected EXTI line
            • +
          • HAL_GPIO_Init(): use temporary variable when modifying the registers, to avoid unexpected transition in the GPIO pin configuration
            • +
          • Remove IS_GET_GPIO_PIN macro
            • +
          • Add a new function HAL_GPIO_LockPin()
            • +
          • Private Macro __HAL_GET_GPIO_SOURCE renamed into GET_GPIO_SOURCE
            • +
          • Add the support of STM32F411xx devices : add the new Alternate functions values related to new remap added for SPI, USART, I2C
            • +
          • Update the following HAL GPIO macros description: rename EXTI_Linex by GPIO_PIN_x +
              +
            • __HAL_GPIO_EXTI_CLEAR_IT()
              • +
            • __HAL_GPIO_EXTI_GET_IT()
              • +
            • __HAL_GPIO_EXTI_CLEAR_FLAG()
              • +
            • __HAL_GPIO_EXTI_GET_FLAG()
              • +
            • +
          • +

        • HAL DMA update

          +
            +
          • Fix in HAL_DMA_PollForTransfer() to: +
              +
            • set DMA error code in case of HAL_ERROR status
              • +
            • set HAL Unlock before DMA state update
              • +
            • +
          • +

        • HAL DMA2D update

          +
            +
          • Add configuration of source address in case of A8 or A4 M2M_PFC DMA2D mode
            • +
          • +
        • HAL FLASH update +
            +
          • Functions reorganization update, depending on the features supported by each STM32F4 device
            • +
          • Add new driver (stm32f4xx_hal_flash_ramfunc.h/.c) to manage function executed from RAM, these functions are available only for STM32F411xx Devices +
              +
            • FLASH_StopFlashInterfaceClk() : Stop the flash interface while System Run
              • +
            • FLASH_StartFlashInterfaceClk() : Stop the flash interface while System Run
              • +
            • FLASH_EnableFlashSleepMode() : Enable the flash sleep while System Run
              • +
            • FLASH_DisableFlashSleepMode() : Disable the flash sleep while System Run
              • +
            • +
          • +
        • HAL PWR update +
            +
          • HAL_PWR_PVDConfig(): add clear of the EXTI trigger before new configuration
            • +
          • Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function
            • +
          • HAL_PWR_EnterSLEEPMode() +
              +
            • Remove disable and enable of SysTick Timer
              • +
            • Update usage of __WFE() in low power entry function: if there is a pending event, calling __WFE() will not enter the CortexM4 core to sleep mode. The solution is to made the call below; the first __WFE() is always ignored and clears the event if one was already pending, the second is always applied
              +__SEV()
              +__WFE()
              +__WFE()
              • +
            • +
          • Add new macro for software event generation __HAL_PVD_EXTI_GENERATE_SWIT()
            • +
          • Remove the following defines form Generic driver and add them under extension driver because they are only used within extension functions. +
              +
            • CR_FPDS_BB: used within HAL_PWREx_EnableFlashPowerDown() function
              • +
            • CSR_BRE_BB: used within HAL_PWREx_EnableBkUpReg() function
              • +
            • +
          • Add the support of STM32F411xx devices add the define STM32F411xE +
              +
            • For STM32F401xC, STM32F401xE and STM32F411xE devices add the following functions used to enable or disable the low voltage mode for regulators +
                +
              • HAL_PWREx_EnableMainRegulatorLowVoltage()
                • +
              • HAL_PWREx_DisableMainRegulatorLowVoltage()
                • +
              • HAL_PWREx_EnableLowRegulatorLowVoltage()
                • +
              • HAL_PWREx_DisableLowRegulatorLowVoltage()
                • +
              • +
            • For STM32F42xxx/43xxx devices, add a new function for Under Driver management as the macro already added for this mode is not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()
              • +
            • +
          • +
        • HAL RCC update +
            +
          • In HAL_RCC_ClockConfig() function: update the AHB clock divider before clock switch to new source
            • +
          • Allow to calibrate the HSI when it is used as system clock source
            • +
          • Rename the following macros +
              +
            • __OTGFS_FORCE_RESET () by __USB_OTG_FS_FORCE_RESET()
              • +
            • __OTGFS_RELEASE_RESET () by __USB_OTG_FS_RELEASE_RESET()
              • +
            • __OTGFS_CLK_SLEEP_ENABLE () by __USB_OTG_FS_CLK_SLEEP_ENABLE()
              • +
            • __OTGFS_CLK_SLEEP_DISABLE () by __USB_OTG_FS_CLK_SLEEP_DISABLE()
              • +
            • +
          • Add new field PLLI2SM in RCC_PLLI2SInitTypeDef structure, this division factor is added for PLLI2S VCO input clock only STM32F411xE devices => the FW compatibility is broken vs. STM32F401xx devices
            • +
          • Update HAL_RCCEx_PeriphCLKConfig() and HAL_RCCEx_GetPeriphCLKConfig() functions to support the new PLLI2SM
            • +
          • Add new function to manage the new LSE mode : HAL_RCCEx_SelectLSEMode()
            • +
          • Reorganize the macros depending from Part number used and make them more clear
            • +
          • +

        • HAL UART update

          +
            +
          • Add new macros to control CTS and RTS
            • +
          • Add specific macros to manage the flags cleared only by a software sequence +
              +
            • __HAL_UART_CLEAR_PEFLAG()
              • +
            • __HAL_UART_CLEAR_FEFLAG()
              • +
            • __HAL_UART_CLEAR_NEFLAG()
              • +
            • __HAL_UART_CLEAR_OREFLAG()
              • +
            • __HAL_UART_CLEAR_IDLEFLAG()
              • +
            • +
          • Add several enhancements without affecting the driver functionalities +
              +
            • Remove the check on RXNE set after reading the Data in the DR register
              • +
            • Update the transmit processes to use TXE instead of TC
              • +
            • Update HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC
              • +
            • +
          • +

        • HAL USART update

          +
            +
          • Add specific macros to manage the flags cleared only by a software sequence +
              +
            • __HAL_USART_CLEAR_PEFLAG()
              • +
            • __HAL_USART_CLEAR_FEFLAG()
              • +
            • __HAL_USART_CLEAR_NEFLAG()
              • +
            • __HAL_USART_CLEAR_OREFLAG()
              • +
            • __HAL_USART_CLEAR_IDLEFLAG()
              • +
            • +
          • Update HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC
            • +
          • +

        • HAL IRDA update

          +
            +
          • Add specific macros to manage the flags cleared only by a software sequence __HAL_IRDA_CLEAR_PEFLAG() __HAL_ IRDA _CLEAR_FEFLAG() __HAL_ IRDA _CLEAR_NEFLAG() __HAL_ IRDA _CLEAR_OREFLAG() __HAL_ IRDA _CLEAR_IDLEFLAG()
            • +
          • Add several enhancements without affecting the driver functionalities +
              +
            • Remove the check on RXNE set after reading the Data in the DR register
              • +
            • Update HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC
              • +
            • +
          • Add the following APIs used within DMA process +
              +
            • HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
              • +
            • HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
              • +
            • HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
              • +
            • void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
              • +
            • void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
              • +
            • +
          • +

        • HAL SMARTCARD update

          +
            +
          • Add specific macros to manage the flags cleared only by a software sequence +
              +
            • __HAL_SMARTCARD_CLEAR_PEFLAG()
              • +
            • __HAL_SMARTCARD_CLEAR_FEFLAG()
              • +
            • __HAL_SMARTCARD_CLEAR_NEFLAG()
              • +
            • __HAL_SMARTCARD_CLEAR_OREFLAG()
              • +
            • __HAL_SMARTCARD_CLEAR_IDLEFLAG()
              • +
            • +
          • Add several enhancements without affecting the driver functionalities +
              +
            • Add a new state HAL_SMARTCARD_STATE_BUSY_TX_RX and all processes has been updated accordingly
              • +
            • Update HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC
              • +
            • +
          • +
        • HAL SPI update +
            +
          • Bugs fix +
              +
            • SPI interface is used in synchronous polling mode: at high clock rates like SPI prescaler 2 and 4, calling HAL_SPI_TransmitReceive() returns with error HAL_TIMEOUT
              • +
            • HAL_SPI_TransmitReceive_DMA() does not clean up the TX DMA, so any subsequent SPI calls return the DMA error
              • +
            • HAL_SPI_Transmit_DMA() is failing when data size is equal to 1 byte
              • +
            • +
          • Add the following APIs used within the DMA process +
              +
            • HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
              • +
            • HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
              • +
            • HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
              • +
            • void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
              • +
            • void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
              • +
            • void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
              • +
            • +
          • +
        • HAL RNG update +
            +
          • Add a conditional define to make this driver visible for all STM32F4xx devices except STM32F401xx and STM32F411xx Devices.
            • +
          • +
        • HAL CRC update +
            +
          • These macros are added to read/write the CRC IDR register: __HAL_CRC_SET_IDR() and __HAL_CRC_GET_IDR()
            • +
          • +
        • HAL DAC update +
            +
          • Enhance the DMA channel configuration when used with DAC
            • +
          • +
        • HAL TIM update +
            +
          • HAL_TIM_IRQHandler(): update to check the input capture channel 3 and 4 in CCMR2 instead of CCMR1
            • +
          • __HAL_TIM_PRESCALER() updated to use ‘=’ instead of ‘|=’
            • +
          • Add the following macro in TIM HAL driver +
              +
            • __HAL_TIM_GetCompare()
              • +
            • __HAL_TIM_GetCounter()
              • +
            • __HAL_TIM_GetAutoreload()
              • +
            • __HAL_TIM_GetClockDivision()
              • +
            • __HAL_TIM_GetICPrescaler()
              • +
            • +
          • +
        • HAL SDMMC update +
            +
          • Use of CMSIS constants instead of magic values
            • +
          • Miscellaneous update in functions internal coding
            • +
          • +
        • HAL NAND update +
            +
          • Fix issue of macros returning wrong address for NAND blocks
            • +
          • Fix issue for read/write NAND page/spare area
            • +
          • +
        • HAL NOR update +
            +
          • Add the NOR address bank macro used within the API
            • +
          • Update NOR API implementation to avoid the use of NOR address bank hard coded
            • +
          • +
        • HAL HCD update +
            +
          • HCD_StateTypeDef structure members renamed
            • +
          • These macro are renamed +
              +
            • __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
              • +
            • __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)
              • +
            • __HAL_IS_INVALID_INTERRUPT(__HANDLE__) by __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)
              • +
            • +
          • +
        • HAL PCD update +
            +
          • HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() renamed into HAL_PCDEx_SetTxFiFo() and HAL_PCDEx_SetRxFiFo() and moved to the extension files stm32f4xx_hal_pcd_ex.h/.c
            • +
          • PCD_StateTypeDef structure members renamed
            • +
          • Fix incorrect masking of TxFIFOEmpty
            • +
          • stm32f4xx_ll_usb.c: fix issue in HS mode
            • +
          • New macros added +
              +
            • __HAL_PCD_IS_PHY_SUSPENDED()
              • +
            • __HAL_USB_HS_EXTI_GENERATE_SWIT()
              • +
            • __HAL_USB_FS_EXTI_GENERATE_SWIT()
              • +
            • +
          • These macro are renamed +
              +
            • __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
              • +
            • __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)
              • +
            • __HAL_IS_INVALID_INTERRUPT(__HANDLE__) by __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)
              • +
            • __HAL_PCD_UNGATE_CLOCK(__HANDLE__) by __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
              • +
            • __HAL_PCD_GATE_CLOCK(__HANDLE___) by __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)
              • +
            • +
          • +
        • HAL ETH update +
            +
          • Update HAL_ETH_GetReceivedFrame_IT() function to return HAL_ERROR if the received packet is not complete
            • +
          • Use HAL_Delay() instead of counting loop
            • +
          • __HAL_ETH_MAC_CLEAR_FLAG() macro is removed: the MACSR register is read only
            • +
          • Add the following macros used to Wake up the device from STOP mode by Ethernet event : +
              +
            • __HAL_ETH_EXTI_ENABLE_IT()
              • +
            • __HAL_ETH_EXTI_DISABLE_IT()
              • +
            • __HAL_ETH_EXTI_GET_FLAG()
              • +
            • __HAL_ETH_EXTI_CLEAR_FLAG()
              • +
            • __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()
              • +
            • __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()
              • +
            • __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()
              • +
            • +
          • +
        • HAL WWDG update +
            +
          • Update macro parameters to use underscore: __XXX__
            • +
          • Use of CMSIS constants instead of magic values
            • +
          • Use MODIFY_REG macro in HAL_WWDG_Init()
            • +
          • Add IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() and HAL_WWDG_DeInit()
            • +
          • +
        • HAL IWDG update +
            +
          • Use WRITE_REG instead of SET_BIT for all IWDG macros
            • +
          • __HAL_IWDG_CLEAR_FLAG removed: no IWDG flag cleared by access to SR register
            • +
          • Use MODIFY_REG macro in HAL_IWDG_Init()
            • +
          • Add IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()Add the following macros used to Wake
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • First official release
          • +
        +
        +
        +
        +
        +
        +

        For complete documentation on STM32F4xx, visit: [www.st.com/stm32f4]

        +

        This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.

        +
        + + diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index fb7811dde4..de14a0e331 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.8.1 + * @brief STM32F4xx HAL Driver version number V1.8.2 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ @@ -368,7 +368,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) /** * @brief Return tick frequency. - * @retval tick period in Hz + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. */ HAL_TickFreqTypeDef HAL_GetTickFreq(void) { diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c index 128b23608a..9ad943d8d0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c @@ -266,7 +266,7 @@ * @{ */ /* Private function prototypes -----------------------------------------------*/ -static void ADC_Init(ADC_HandleTypeDef* hadc); +static void ADC_Init(ADC_HandleTypeDef *hadc); static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); static void ADC_DMAError(DMA_HandleTypeDef *hdma); static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); @@ -308,12 +308,12 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } @@ -331,12 +331,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); } - if(hadc->State == HAL_ADC_STATE_RESET) + if (hadc->State == HAL_ADC_STATE_RESET) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ @@ -402,12 +402,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } @@ -424,19 +424,19 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } - /* DeInit the low level hardware: RCC clock, NVIC */ - hadc->MspDeInitCallback(hadc); + /* DeInit the low level hardware: RCC clock, NVIC */ + hadc->MspDeInitCallback(hadc); #else - /* DeInit the low level hardware: RCC clock, NVIC */ - HAL_ADC_MspDeInit(hadc); + /* DeInit the low level hardware: RCC clock, NVIC */ + HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ @@ -659,7 +659,7 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -674,7 +674,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -713,7 +713,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -728,7 +728,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -736,14 +736,14 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -786,15 +786,15 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { #if defined(ADC2) && defined(ADC3) - if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ - || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) { #endif /* ADC2 || ADC3 */ /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -806,10 +806,10 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } } @@ -836,7 +836,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) * * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -849,7 +849,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, @@ -879,7 +879,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart = 0U; @@ -890,7 +890,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and polling for end of each conversion. */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && - HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -905,15 +905,15 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti tickstart = HAL_GetTick(); /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + while (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + if (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -939,10 +939,10 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); @@ -968,7 +968,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart = 0U; @@ -980,15 +980,15 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy tickstart = HAL_GetTick(); /* Check selected event flag */ - while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + while (!(__HAL_ADC_GET_FLAG(hadc, EventType))) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + if (!(__HAL_ADC_GET_FLAG(hadc, EventType))) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1003,7 +1003,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy } /* Analog watchdog (level out of window) event */ - if(EventType == ADC_AWD_EVENT) + if (EventType == ADC_AWD_EVENT) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -1034,7 +1034,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy * the configuration information for the specified ADC. * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -1049,7 +1049,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -1057,14 +1057,14 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -1110,15 +1110,15 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { #if defined(ADC2) && defined(ADC3) - if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ - || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) { #endif /* ADC2 || ADC3 */ /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -1130,10 +1130,10 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } } @@ -1159,7 +1159,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1172,9 +1172,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { - /* Disable ADC end of conversion interrupt for regular group */ + /* Disable ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); /* Set ADC state */ @@ -1196,7 +1196,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { uint32_t tmp1 = 0U, tmp2 = 0U; @@ -1211,7 +1211,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmp1 = tmp_sr & ADC_FLAG_EOC; tmp2 = tmp_cr1 & ADC_IT_EOC; /* Check End of conversion flag for regular channels */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) @@ -1226,10 +1226,10 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ @@ -1260,7 +1260,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmp1 = tmp_sr & ADC_FLAG_JEOC; tmp2 = tmp_cr1 & ADC_IT_JEOC; /* Check End of conversion flag for injected channels */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) @@ -1273,12 +1273,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* by external trigger, scan sequence on going or by automatic injected */ /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Disable ADC end of single conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); @@ -1295,9 +1295,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Conversion complete callback */ /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->InjectedConvCpltCallback(hadc); + hadc->InjectedConvCpltCallback(hadc); #else - HAL_ADCEx_InjectedConvCpltCallback(hadc); + HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ @@ -1307,9 +1307,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmp1 = tmp_sr & ADC_FLAG_AWD; tmp2 = tmp_cr1 & ADC_IT_AWD; /* Check Analog watchdog flag */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -1329,7 +1329,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmp1 = tmp_sr & ADC_FLAG_OVR; tmp2 = tmp_cr1 & ADC_IT_OVR; /* Check Overrun flag */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Note: On STM32F4, ADC overrun can be set through other parameters */ /* refer to description of parameter "EOCSelection" for more */ @@ -1343,9 +1343,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); + hadc->ErrorCallback(hadc); #else - HAL_ADC_ErrorCallback(hadc); + HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the Overrun flag */ @@ -1361,7 +1361,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -1376,7 +1376,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -1384,7 +1384,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } @@ -1392,13 +1392,13 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Check ADC DMA Mode */ /* - disable the DMA Mode if it is already enabled */ - if((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA) + if ((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA) { CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -1463,15 +1463,15 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { #if defined(ADC2) && defined(ADC3) - if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ - || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) { #endif /* ADC2 || ADC3 */ /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -1483,10 +1483,10 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } } @@ -1509,7 +1509,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; @@ -1524,7 +1524,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Disable the selected ADC DMA mode */ hadc->Instance->CR2 &= ~ADC_CR2_DMA; @@ -1565,7 +1565,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval Converted value */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) { /* Return the selected ADC converted value */ return hadc->Instance->DR; @@ -1577,7 +1577,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -1592,7 +1592,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -1607,7 +1607,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -1642,7 +1642,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -1658,15 +1658,15 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * @{ */ - /** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param sConfig ADC configuration structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +/** +* @brief Configures for the selected ADC regular channel its corresponding +* rank in the sequencer and its sample time. +* @param hadc pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param sConfig ADC configuration structure. +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -1725,10 +1725,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); } - /* Pointer to the common control register to which is belonging hadc */ - /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ - /* control register) */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) @@ -1754,12 +1754,12 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Enable the Temperature sensor and VREFINT channel*/ tmpADC_Common->CCR |= ADC_CCR_TSVREFE; - if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } @@ -1789,7 +1789,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * that contains the configuration information of ADC analog watchdog. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { #ifdef USE_FULL_ASSERT uint32_t tmp = 0U; @@ -1809,7 +1809,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* Process locked */ __HAL_LOCK(hadc); - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { /* Enable the ADC Analog watchdog interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); @@ -1871,7 +1871,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * the configuration information for the specified ADC. * @retval HAL state */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) { /* Return ADC state */ return hadc->State; @@ -1903,7 +1903,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * the configuration information for the specified ADC. * @retval None */ -static void ADC_Init(ADC_HandleTypeDef* hadc) +static void ADC_Init(ADC_HandleTypeDef *hadc) { ADC_Common_TypeDef *tmpADC_Common; @@ -1934,7 +1934,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); @@ -1955,7 +1955,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) hadc->Instance->CR2 &= ~(ADC_CR2_CONT); hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); - if(hadc->Init.DiscontinuousConvMode != DISABLE) + if (hadc->Init.DiscontinuousConvMode != DISABLE) { assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); @@ -1994,7 +1994,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) @@ -2008,10 +2008,10 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ @@ -2046,8 +2046,8 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - else - { + else + { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } @@ -2062,8 +2062,8 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) */ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Half conversion callback */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else @@ -2079,11 +2079,11 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hadc->State = HAL_ADC_STATE_ERROR_DMA; /* Set ADC error code to DMA error */ hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - /* Error callback */ + /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c index cff0760cdc..7db1993715 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c @@ -143,7 +143,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; uint32_t tmp1 = 0U, tmp2 = 0U; @@ -156,7 +156,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -164,14 +164,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ @@ -205,11 +205,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -219,7 +219,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) + if ((hadc->Instance == ADC1) && tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -246,7 +246,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) * * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; uint32_t tmp1 = 0U, tmp2 = 0U; @@ -259,7 +259,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -267,14 +267,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ @@ -311,11 +311,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -325,7 +325,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) + if ((hadc->Instance == ADC1) && tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -357,7 +357,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; @@ -373,15 +373,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, @@ -411,7 +411,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart = 0U; @@ -419,17 +419,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u tickstart = HAL_GetTick(); /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + while (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + if (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) { - hadc->State= HAL_ADC_STATE_TIMEOUT; + hadc->State = HAL_ADC_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; @@ -450,12 +450,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); @@ -482,7 +482,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u * @param hadc ADC handle * @retval None */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; @@ -498,15 +498,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); @@ -544,7 +544,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected * @retval None */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { __IO uint32_t tmp = 0U; @@ -556,7 +556,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Return the selected ADC converted value */ - switch(InjectedRank) + switch (InjectedRank) { case ADC_INJECTED_RANK_4: { @@ -579,7 +579,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa } break; default: - break; + break; } return tmp; } @@ -595,7 +595,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -610,7 +610,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -618,14 +618,14 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -697,7 +697,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -722,7 +722,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; @@ -743,7 +743,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Disable the selected ADC DMA mode for multimode */ tmpADC_Common->CCR &= ~ADC_CCR_DDS; @@ -775,7 +775,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval The converted data value. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) { ADC_Common_TypeDef *tmpADC_Common; @@ -794,7 +794,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -811,7 +811,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) * @param sConfigInjected ADC configuration structure for injected channel. * @retval None */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) { #ifdef USE_FULL_ASSERT @@ -835,7 +835,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); #endif /* USE_FULL_ASSERT */ - if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); } @@ -868,17 +868,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Rank configuration */ /* Clear the old SQx bits for the selected rank */ - hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion); /* Set the SQx bits for the selected rank */ - hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion); /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ - if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); @@ -917,7 +917,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); } - switch(sConfigInjected->InjectedRank) + switch (sConfigInjected->InjectedRank) { case 1U: /* Set injected channel 1 offset */ @@ -944,7 +944,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ /* control register) */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* if ADC1 Channel_18 is selected enable VBAT Channel */ if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) @@ -975,7 +975,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I * the configuration information for multimode. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { ADC_Common_TypeDef *tmpADC_Common; @@ -1025,7 +1025,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) @@ -1039,10 +1039,10 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ @@ -1077,9 +1077,9 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) */ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); } /** @@ -1090,11 +1090,11 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) */ static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - HAL_ADC_ErrorCallback(hadc); + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hadc->State = HAL_ADC_STATE_ERROR_DMA; + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + HAL_ADC_ErrorCallback(hadc); } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c index 4abdc60a9a..f99111633b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c @@ -33,7 +33,7 @@ (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() (++) Configure CAN pins (+++) Enable the clock for the CAN GPIOs - (+++) Configure CAN pins as alternate function open-drain + (+++) Configure CAN pins as alternate function (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) (+++) Configure the CAN interrupt priority using HAL_NVIC_SetPriority() @@ -226,8 +226,8 @@ #ifdef HAL_CAN_MODULE_ENABLED #ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" -#endif +#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -235,6 +235,7 @@ * @{ */ #define CAN_TIMEOUT_VALUE 10U +#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U /** * @} */ @@ -248,8 +249,8 @@ */ /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); @@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) #else /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Reset the CAN peripheral */ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); @@ -555,7 +556,8 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)) +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)) { HAL_StatusTypeDef status = HAL_OK; @@ -813,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca */ /** @defgroup CAN_Exported_Functions_Group2 Configuration functions - * @brief Configuration functions. - * + * @brief Configuration functions. + * @verbatim ============================================================================== ##### Configuration functions ##### @@ -835,7 +837,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca * contains the filter configuration information. * @retval None */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; @@ -886,7 +888,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); -#endif +#endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); @@ -905,7 +907,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); -#endif +#endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); @@ -997,8 +999,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe */ /** @defgroup CAN_Exported_Functions_Group3 Control functions - * @brief Control functions - * + * @brief Control functions + * @verbatim ============================================================================== ##### Control functions ##### @@ -1170,7 +1172,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) { __IO uint32_t count = 0; - uint32_t timeout = 1000000U; HAL_CAN_StateTypeDef state = hcan->State; if ((state == HAL_CAN_STATE_READY) || @@ -1186,15 +1187,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) count++; /* Check if timeout is reached */ - if (count > timeout) + if (count > CAN_WAKEUP_TIMEOUT_COUNTER) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; return HAL_ERROR; } - } - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); /* Return function status */ return HAL_OK; @@ -1216,7 +1216,7 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) * - 0 : Sleep mode is not active. * - 1 : Sleep mode is active. */ -uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) { uint32_t status = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1247,7 +1247,8 @@ uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox) { uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; @@ -1278,15 +1279,6 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; - /* Check transmit mailbox value */ - if (transmitmailbox > 2U) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; - - return HAL_ERROR; - } - /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; @@ -1404,7 +1396,7 @@ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMai * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { uint32_t freelevel = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1447,7 +1439,7 @@ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) * - 1 : Pending transmission request on at least one of the selected * Tx Mailbox. */ -uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) { uint32_t status = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1479,7 +1471,7 @@ uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxe * This parameter can be one value of @arg CAN_Tx_Mailboxes. * @retval Timestamp of message sent from Tx Mailbox. */ -uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox) { uint32_t timestamp = 0U; uint32_t transmitmailbox; @@ -1513,7 +1505,8 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { HAL_CAN_StateTypeDef state = hcan->State; @@ -1554,10 +1547,19 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, } else { - pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); - pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) + { + /* Truncate DLC to 8 if received field is over range */ + pHeader->DLC = 8U; + } + else + { + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; @@ -1603,7 +1605,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, * This parameter can be a value of @arg CAN_receive_FIFO_number. * @retval Number of messages available in Rx FIFO. */ -uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo) { uint32_t filllevel = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1633,8 +1635,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) */ /** @defgroup CAN_Exported_Functions_Group4 Interrupts management - * @brief Interrupts management - * + * @brief Interrupts management + * @verbatim ============================================================================== ##### Interrupts management ##### @@ -2099,8 +2101,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) */ /** @defgroup CAN_Exported_Functions_Group5 Callback functions - * @brief CAN Callback functions - * + * @brief CAN Callback functions + * @verbatim ============================================================================== ##### Callback functions ##### @@ -2349,8 +2351,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) */ /** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * + * @brief CAN Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2371,7 +2373,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) { HAL_CAN_StateTypeDef state = hcan->State; @@ -2406,7 +2408,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) * the configuration information for the specified CAN. * @retval CAN Error Code */ -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) { /* Return CAN error code */ return hcan->ErrorCode; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c index 56e6e8489f..6a39d16ac6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c @@ -233,7 +233,8 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) /* Write to CEC Control Register */ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \ - hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \ + hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \ + hcec->Init.BroadcastMsgNoErrorBitGen | \ hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \ hcec->Init.ListenMode; @@ -412,10 +413,10 @@ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) * @param hcec CEC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID - * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID + * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID + * @arg HAL_CEC_ERROR_CB_ID Error callback ID + * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -501,10 +502,10 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call * @param hcec uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID - * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID + * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID + * @arg HAL_CEC_ERROR_CB_ID Error callback ID + * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID * @retval status */ HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID) @@ -694,7 +695,7 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - uint8_t *pData, uint32_t Size) + const uint8_t *pData, uint32_t Size) { /* if the peripheral isn't already busy and if there is no previous transmission already pending due to arbitration lost */ @@ -749,7 +750,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator * @param hcec CEC handle * @retval Frame size */ -uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec) { return hcec->RxXferSize; } @@ -775,13 +776,13 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) { /* save interrupts register for further error or interrupts handling purposes */ - uint32_t reg; - reg = hcec->Instance->ISR; + uint32_t itflag; + itflag = hcec->Instance->ISR; /* ----------------------------Arbitration Lost Management----------------------------------*/ /* CEC TX arbitration error interrupt occurred --------------------------------------*/ - if ((reg & CEC_FLAG_ARBLST) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST)) { hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); @@ -789,7 +790,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* ----------------------------Rx Management----------------------------------*/ /* CEC RX byte received interrupt ---------------------------------------------------*/ - if ((reg & CEC_FLAG_RXBR) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR)) { /* reception is starting */ hcec->RxState = HAL_CEC_STATE_BUSY_RX; @@ -801,7 +802,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) } /* CEC RX end received interrupt ---------------------------------------------------*/ - if ((reg & CEC_FLAG_RXEND) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND)) { /* clear IT */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); @@ -820,7 +821,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* ----------------------------Tx Management----------------------------------*/ /* CEC TX byte request interrupt ------------------------------------------------*/ - if ((reg & CEC_FLAG_TXBR) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR)) { --hcec->TxXferCount; if (hcec->TxXferCount == 0U) @@ -829,14 +830,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) __HAL_CEC_LAST_BYTE_TX_SET(hcec); } /* In all cases transmit the byte */ - hcec->Instance->TXDR = *hcec->pTxBuffPtr; + hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr; hcec->pTxBuffPtr++; /* clear Tx-Byte request flag */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); } /* CEC TX end interrupt ------------------------------------------------*/ - if ((reg & CEC_FLAG_TXEND) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); @@ -854,21 +855,21 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) } /* ----------------------------Rx/Tx Error Management----------------------------------*/ - if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR | - CEC_ISR_TXACKE)) != 0U) + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | + CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U) { - hcec->ErrorCode = reg; + hcec->ErrorCode = itflag; __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE | HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE); - if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) { hcec->Init.RxBuffer -= hcec->RxXferSize; hcec->RxXferSize = 0U; hcec->RxState = HAL_CEC_STATE_READY; } - else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) + else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) { /* Set the CEC state ready to be able to start again the process */ hcec->gState = HAL_CEC_STATE_READY; @@ -957,9 +958,10 @@ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) * the configuration information for the specified CEC module. * @retval HAL state */ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec) { - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = hcec->gState; temp2 = hcec->RxState; @@ -972,7 +974,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) * the configuration information for the specified CEC. * @retval CEC Error Code */ -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec) { return hcec->ErrorCode; } @@ -993,4 +995,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) /** * @} */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c index 54d44b49ec..3de962f8f8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -335,6 +335,16 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) } #endif /* __MPU_PRESENT */ +/** + * @brief Clear pending events. + * @retval None + */ +void HAL_CORTEX_ClearEvent(void) +{ + __SEV(); + __WFE(); +} + /** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c index 2e86b2b6a2..9bd354ab10 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c @@ -147,7 +147,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + __HAL_CRC_SET_IDR(hcrc, 0); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); @@ -303,7 +303,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t * @param hcrc CRC handle * @retval HAL state */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) { /* Return CRC handle state */ return hcrc->State; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c index 65ad59dfcd..bb41673b2d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c @@ -1011,7 +1011,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; - /* Statrt DES/TDES encryption process */ + /* Start DES/TDES encryption process */ status = CRYP_TDES_Process(hcryp, Timeout); break; @@ -2533,15 +2533,17 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); #else /* CRYP */ @@ -2780,7 +2782,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2822,7 +2825,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); /* Turn back to ALGOMODE of the configuration */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); @@ -2867,15 +2871,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); #else /* CRYP */ @@ -2961,7 +2967,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3005,7 +3012,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); /* Turn back to ALGOMODE of the configuration */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); @@ -3943,7 +3951,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ @@ -3980,7 +3989,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4218,7 +4228,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ @@ -4255,7 +4266,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4855,7 +4867,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); /* Select header phase */ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); @@ -5016,7 +5029,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ @@ -5062,7 +5076,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5107,7 +5122,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } @@ -5144,7 +5160,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } @@ -5178,7 +5195,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } @@ -5247,7 +5265,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5320,7 +5339,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) } /** - * @brief Sets the payload phase in iterrupt mode + * @brief Sets the payload phase in interrupt mode * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval state @@ -5545,16 +5564,16 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) - { - /* Call Input transfer complete callback */ + { + /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } + } } else /* Last block of payload < 128bit*/ { @@ -5966,7 +5985,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } } else @@ -6001,7 +6021,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Last block optionally pad the data with zeros*/ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) @@ -6051,7 +6072,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Wait until the complete message has been processed */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; @@ -6071,7 +6093,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); #else /* AES */ @@ -6119,7 +6142,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -6158,13 +6182,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes /4U) % 4U)); loopcounter++) + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -6211,7 +6236,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -6329,10 +6355,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -6463,10 +6489,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c index f6883eea39..8953638e5d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c @@ -168,7 +168,7 @@ and a pointer to the user callback function. Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. @@ -183,9 +183,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + reset to the legacy weak (overridden) functions in the HAL_DAC_Init and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -200,7 +200,7 @@ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** DAC HAL driver macros list *** ============================================= @@ -270,7 +270,7 @@ */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -331,7 +331,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -434,6 +434,12 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -489,6 +495,12 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -519,11 +531,17 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment) { - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpreg = 0U; + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tmpreg; + + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -560,12 +578,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; - default: - break; } } #if defined(DAC_CHANNEL2_SUPPORT) @@ -594,17 +610,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Get DHR12L2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L2; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R2; break; - default: - break; } } #endif /* DAC_CHANNEL2_SUPPORT */ - - /* Enable the DMA Stream */ if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ @@ -653,6 +665,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -701,10 +719,13 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + uint32_t itsource = hdac->Instance->CR; + uint32_t itflag = hdac->Instance->SR; + + if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) { /* Check underrun flag of DAC channel 1 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -716,7 +737,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); /* Disable the selected DAC channel1 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -728,10 +749,10 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) } #if defined(DAC_CHANNEL2_SUPPORT) - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) + if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) { /* Check underrun flag of DAC channel 2 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -743,7 +764,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); /* Disable the selected DAC channel2 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -776,6 +797,12 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui { __IO uint32_t tmp = 0UL; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); @@ -893,10 +920,13 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) { uint32_t result = 0; + /* Check the DAC peripheral handle */ + assert_param(hdac != NULL); + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -925,11 +955,19 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpreg1; uint32_t tmpreg2; + /* Check the DAC peripheral handle and channel configuration struct */ + if ((hdac == NULL) || (sConfig == NULL)) + { + return HAL_ERROR; + } + /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); @@ -944,7 +982,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL)); + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) + << (Channel & 0x10UL)); /* Configure for the selected DAC channel: buffer output, trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ @@ -963,7 +1002,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf __HAL_UNLOCK(hdac); /* Return function status */ - return HAL_OK; + return status; } /** @@ -992,7 +1031,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * the configuration information for the specified DAC. * @retval HAL state */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac) { /* Return DAC handle state */ return hdac->State; @@ -1005,7 +1044,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) * the configuration information for the specified DAC. * @retval DAC Error Code */ -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac) { return hdac->ErrorCode; } @@ -1028,7 +1067,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief Register a User DAC Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback + * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -1052,6 +1093,12 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call { HAL_StatusTypeDef status = HAL_OK; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + if (pCallback == NULL) { /* Update the error code */ @@ -1059,9 +1106,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdac); - if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) @@ -1132,14 +1176,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } /** * @brief Unregister a User DAC Callback - * DAC Callback is redirected to the weak (surcharged) predefined callback + * DAC Callback is redirected to the weak (overridden) predefined callback + * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1160,8 +1204,11 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hdac); + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } if (hdac->State == HAL_DAC_STATE_READY) { @@ -1247,8 +1294,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ @@ -1334,8 +1379,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) #endif /* DAC */ #endif /* HAL_DAC_MODULE_ENABLED */ - /** * @} */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c index 343dd98682..6e5ab5121d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c @@ -23,15 +23,6 @@ ##### How to use this driver ##### ============================================================================== [..] - - *** Dual mode IO operation *** - ============================== - [..] - (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : - Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in - Channel 1 and Channel 2. - *** Signal generation operation *** =================================== [..] @@ -61,6 +52,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -100,6 +92,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) { uint32_t tmp_swtrig = 0UL; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Process locked */ __HAL_LOCK(hdac); @@ -141,6 +139,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); @@ -180,6 +184,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -230,6 +240,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 */ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -275,6 +291,12 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Align uint32_t data; uint32_t tmp; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); @@ -391,7 +413,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac) { uint32_t tmp = 0UL; @@ -492,4 +514,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) /** * @} */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c index 5279edf0a8..63126be305 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c @@ -324,7 +324,7 @@ DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NUL * @{ */ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels); -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance); +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance); static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); @@ -960,7 +960,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; @@ -1329,7 +1329,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; @@ -1596,7 +1596,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd * @param hdfsdm_channel DFSDM channel handle. * @retval Channel analog watchdog value. */ -int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { return (int16_t) hdfsdm_channel->Instance->CHWDATAR; } @@ -1655,7 +1655,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf * @param hdfsdm_channel DFSDM channel handle. * @retval DFSDM channel state. */ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { /* Return DFSDM channel handle state */ return hdfsdm_channel->State; @@ -2637,7 +2637,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd * @param Channel Corresponding channel of regular conversion. * @retval Regular conversion value */ -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; @@ -3051,7 +3051,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; @@ -3079,7 +3079,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef *awdParam) + const DFSDM_Filter_AwdParamTypeDef *awdParam) { HAL_StatusTypeDef status = HAL_OK; @@ -3236,7 +3236,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil * @retval Extreme detector maximum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; @@ -3264,7 +3264,7 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter * @retval Extreme detector minimum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; @@ -3291,7 +3291,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter * @retval Conversion time value * @note To get time in second, this value has to be divided by DFSDM clock frequency. */ -uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { uint32_t reg = 0U; uint32_t value = 0U; @@ -3676,7 +3676,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter state. */ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Return DFSDM filter handle state */ return hdfsdm_filter->State; @@ -3687,7 +3687,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter error code. */ -uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { return hdfsdm_filter->ErrorCode; } @@ -4183,7 +4183,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) * @param Instance DFSDM channel instance. * @retval Channel number. */ -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance) { uint32_t channel; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c index 4cfac40613..76f2b4673e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c @@ -118,7 +118,7 @@ and a pointer to the user callback function. (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -130,16 +130,16 @@ (+) MspDeInitCallback : DMA2D MspDeInit. (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak (overridden) functions: examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init + reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Exception as well for Transfer Completion and Transfer Error callbacks that are not defined - as weak (surcharged) functions. They must be defined by the user to be resorted to. + as weak (overridden) functions. They must be defined by the user to be resorted to. Callbacks can be registered/unregistered in READY state only. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered @@ -151,7 +151,7 @@ When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. [..] (@) You can refer to the DMA2D HAL driver header file for more useful macros @@ -422,7 +422,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) /** * @brief Register a User DMA2D Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hdma2d DMA2D handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -521,7 +521,7 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM /** * @brief Unregister a DMA2D Callback - * DMA2D Callback is redirected to the weak (surcharged) predefined callback + * DMA2D Callback is redirected to the weak (overridden) predefined callback * @param hdma2d DMA2D handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -562,11 +562,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ break; case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ break; case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ break; default : @@ -582,11 +582,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ switch (CallbackID) { case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ break; case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ break; default : diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c index bde68610e0..b193c24e69 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c @@ -1835,6 +1835,95 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Verify that there are no ULPS exit or request on data lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + /* ULPS Request on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_URDL; @@ -1898,6 +1987,58 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Exit ULPS on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_UEDL; @@ -1947,6 +2088,61 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /* De-assert the ULPM requests and the ULPM exit bits */ hdsi->Instance->PUCR = 0U; + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -1967,6 +2163,96 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Verify that there are no ULPS exit or request on both data and clock lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + /* Clock lane configuration: no more HS request */ hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; @@ -1979,7 +2265,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /* Get tick */ tickstart = HAL_GetTick(); - /* Wait until all active lanes exit ULPM */ + /* Wait until all active lanes enter ULPM */ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) @@ -2039,9 +2325,44 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \ + DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \ + DSI_PSR_PSS1 | DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + /* Turn on the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + /* Get tick */ tickstart = HAL_GetTick(); @@ -2114,6 +2435,62 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* Restore clock lane configuration to HS */ hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c index 634da3fd8d..ff0cfec156 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c @@ -501,7 +501,6 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call { /* Update the error code */ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - return HAL_ERROR; } @@ -579,7 +578,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call /** * @brief Unregister an ETH Callback - * ETH callabck is redirected to the weak predefined callback + * ETH callback is redirected to the weak predefined callback * @param heth eth handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -702,7 +701,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) { heth->gState = HAL_ETH_STATE_BUSY; - /* Set nombre of descriptors to build */ + /* Set number of descriptors to build */ heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; /* Build all descriptors */ @@ -772,7 +771,7 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \ ETH_MMCTIMR_TGFSCM); - /* Set nombre of descriptors to build */ + /* Set number of descriptors to build */ heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; /* Build all descriptors */ @@ -836,6 +835,7 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) { /* Set the ETH peripheral state to BUSY */ heth->gState = HAL_ETH_STATE_BUSY; + /* Disable the DMA transmission */ CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); @@ -903,6 +903,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) /* Disable the MAC reception */ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1085,7 +1086,6 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) uint32_t bufflength; uint8_t rxdataready = 0U; - if (pAppBuff == NULL) { heth->ErrorCode |= HAL_ETH_ERROR_PARAM; @@ -1108,9 +1108,9 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) { /* Get timestamp high */ - heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC6; + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC7; /* Get timestamp low */ - heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC7; + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC6; } if ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) { @@ -1193,6 +1193,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) */ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) { + uint32_t tailidx; uint32_t descidx; uint32_t desccount; ETH_DMADescTypeDef *dmarxdesc; @@ -1238,12 +1239,6 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) WRITE_REG(dmarxdesc->DESC1, ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH); } - /* Before transferring the ownership to DMA, make sure that the RX descriptors bits writing - is fully performed. - The __DMB() instruction is added to avoid any potential compiler optimization that - may lead to abnormal behavior. */ - __DMB(); - SET_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN); /* Increment current rx descriptor index */ @@ -1256,8 +1251,14 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (heth->RxDescList.RxBuildDescCnt != desccount) { + /* Set the tail pointer index */ + tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + + /* DMB instruction to avoid race condition */ + __DMB(); + /* Set the Tail pointer address */ - WRITE_REG(heth->Instance->DMARPDR, 0); + WRITE_REG(heth->Instance->DMARPDR, ((uint32_t)(heth->Init.RxDesc + (tailidx)))); heth->RxDescList.RxBuildDescIdx = descidx; heth->RxDescList.RxBuildDescCnt = desccount; @@ -1317,7 +1318,7 @@ __weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) /** * @brief Rx Link callback. * @param pStart: pointer to packet start - * @param pStart: pointer to packet end + * @param pEnd: pointer to packet end * @param buff: pointer to received data * @param Length: received data length * @retval None @@ -1904,14 +1905,12 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) } } - /* ETH DMA Error */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_AIS)) { if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_AISE)) { heth->ErrorCode |= HAL_ETH_ERROR_DMA; - /* if fatal bus error occurred */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_FBES)) { @@ -2116,7 +2115,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA * @param RegValue: the value to write * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue) { uint32_t tmpreg1; @@ -2254,6 +2253,7 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp ETH_DMAOMR_FUGF) >> 6) > 0U) ? ENABLE : DISABLE; dmaconf->ReceiveThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RTC); dmaconf->SecondFrameOperate = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_OSF) >> 2) > 0U) ? ENABLE : DISABLE; + return HAL_OK; } @@ -2369,7 +2369,7 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) * the configuration of the ETH MAC filters. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig) { uint32_t filterconfig; uint32_t tmpreg1; @@ -2447,7 +2447,8 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil * @param pMACAddr: Pointer to MAC address buffer data (6 bytes) * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr) +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, + const uint8_t *pMACAddr) { uint32_t macaddrlr; uint32_t macaddrhr; @@ -2546,7 +2547,7 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBit * that contains the Power Down configuration * @retval None. */ -void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig) +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig) { uint32_t powerdownconfig; @@ -2650,7 +2651,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi * the configuration information for ETHERNET module * @retval HAL state */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) +HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth) { return heth->gState; } @@ -2661,7 +2662,7 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) * the configuration information for ETHERNET module * @retval ETH Error Code */ -uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth) +uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth) { return heth->ErrorCode; } @@ -2672,7 +2673,7 @@ uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth) * the configuration information for ETHERNET module * @retval ETH DMA Error Code */ -uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth) +uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth) { return heth->DMAErrorCode; } @@ -2683,7 +2684,7 @@ uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth) * the configuration information for ETHERNET module * @retval ETH MAC Error Code */ -uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth) +uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth) { return heth->MACErrorCode; } @@ -2694,7 +2695,7 @@ uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth) * the configuration information for ETHERNET module * @retval ETH MAC WakeUp event source */ -uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth) +uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth) { return heth->MACWakeUpEvent; } @@ -2941,10 +2942,10 @@ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) { dmatxdesc = heth->Init.TxDesc + i; - WRITE_REG(dmatxdesc->DESC0, 0x0); - WRITE_REG(dmatxdesc->DESC1, 0x0); - WRITE_REG(dmatxdesc->DESC2, 0x0); - WRITE_REG(dmatxdesc->DESC3, 0x0); + WRITE_REG(dmatxdesc->DESC0, 0x0U); + WRITE_REG(dmatxdesc->DESC1, 0x0U); + WRITE_REG(dmatxdesc->DESC2, 0x0U); + WRITE_REG(dmatxdesc->DESC3, 0x0U); WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); @@ -2986,12 +2987,12 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) { dmarxdesc = heth->Init.RxDesc + i; - WRITE_REG(dmarxdesc->DESC0, 0x0); - WRITE_REG(dmarxdesc->DESC1, 0x0); - WRITE_REG(dmarxdesc->DESC2, 0x0); - WRITE_REG(dmarxdesc->DESC3, 0x0); - WRITE_REG(dmarxdesc->BackupAddr0, 0x0); - WRITE_REG(dmarxdesc->BackupAddr1, 0x0); + WRITE_REG(dmarxdesc->DESC0, 0x0U); + WRITE_REG(dmarxdesc->DESC1, 0x0U); + WRITE_REG(dmarxdesc->DESC2, 0x0U); + WRITE_REG(dmarxdesc->DESC3, 0x0U); + WRITE_REG(dmarxdesc->BackupAddr0, 0x0U); + WRITE_REG(dmarxdesc->BackupAddr1, 0x0U); /* Set Own bit of the Rx descriptor Status */ dmarxdesc->DESC0 = ETH_DMARXDESC_OWN; @@ -3015,11 +3016,11 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) } } - WRITE_REG(heth->RxDescList.RxDescIdx, 0); - WRITE_REG(heth->RxDescList.RxDescCnt, 0); - WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0); - WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0); - WRITE_REG(heth->RxDescList.ItMode, 0); + WRITE_REG(heth->RxDescList.RxDescIdx, 0U); + WRITE_REG(heth->RxDescList.RxDescCnt, 0U); + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U); + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U); + WRITE_REG(heth->RxDescList.ItMode, 0U); /* Set Receive Descriptor List Address */ WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc); @@ -3170,7 +3171,6 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; dmatxdesclist->CurTxDesc = descidx; - /* disable the interrupt */ __disable_irq(); @@ -3217,4 +3217,3 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) /** * @} */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c index 04b5215fdd..89166e2650 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c @@ -64,7 +64,7 @@ (++) Provide exiting handle as parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). (++) Provide exiting handle as parameter. (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). @@ -75,7 +75,7 @@ (#) Get interrupt pending bit using HAL_EXTI_GetPending(). - (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @@ -300,8 +300,8 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { assert_param(IS_EXTI_GPIO_PIN(linepos)); - regval = (SYSCFG->EXTICR[linepos >> 2u] << 16u ); - pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 28u); + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; } } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c index d079dd07e7..a84b29d35e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c @@ -357,28 +357,28 @@ /* Private define for @ref PreviousState usage */ #define FMPI2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_FMPI2C_STATE_BUSY_TX | \ - (uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & \ - (uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY)))) + (uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ #define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */ #define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_MASTER)) + (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_MASTER)) + (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_SLAVE)) + (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_SLAVE)) + (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_MEM)) + (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_MEM)) + (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ @@ -401,7 +401,16 @@ * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup FMPI2C_Private_Macro + * @{ + */ +/* Macro to get remaining data to transfer on DMA side */ +#define FMPI2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -416,6 +425,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma); static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma); + /* Private functions to handle IT transfer */ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); static void FMPI2C_ITMasterSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c); @@ -427,33 +437,37 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for FMPI2C transfer IRQ handler */ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Mem_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources); + uint32_t ITSources); static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Mem_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources); + uint32_t ITSources); /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t Tickstart); + uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); @@ -467,7 +481,7 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c); /* Private function to handle start, restart or stop a transfer */ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); + uint32_t Request); /* Private function to Convert Specific options */ static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c); @@ -595,7 +609,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) /* Configure FMPI2Cx: Addressing Master mode */ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) { - hfmpi2c->Instance->CR2 = (FMPI2C_CR2_ADD10); + SET_BIT(hfmpi2c->Instance->CR2, FMPI2C_CR2_ADD10); + } + else + { + /* Clear the FMPI2C ADD10 bit */ + CLEAR_BIT(hfmpi2c->Instance->CR2, FMPI2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hfmpi2c->Instance->CR2 |= (FMPI2C_CR2_AUTOEND | FMPI2C_CR2_NACK); @@ -606,7 +625,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) /* Configure FMPI2Cx: Dual mode and Own Address2 */ hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | \ - (hfmpi2c->Init.OwnAddress2Masks << 8)); + (hfmpi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/ /* Configure FMPI2Cx: Generalcall and NoStretch mode */ @@ -705,6 +724,8 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c) /** * @brief Register a User FMPI2C Callback * To be used instead of the weak predefined callback + * @note The HAL_FMPI2C_RegisterCallback() may be called before HAL_FMPI2C_Init() in HAL_FMPI2C_STATE_RESET + * to register callbacks for HAL_FMPI2C_MSPINIT_CB_ID and HAL_FMPI2C_MSPDEINIT_CB_ID. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param CallbackID ID of the callback to be registered @@ -724,7 +745,7 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c) * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, - pFMPI2C_CallbackTypeDef pCallback) + pFMPI2C_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -735,8 +756,6 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hfmpi2c); if (HAL_FMPI2C_STATE_READY == hfmpi2c->State) { @@ -825,14 +844,14 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpi2c); return status; } /** * @brief Unregister an FMPI2C Callback * FMPI2C callback is redirected to the weak predefined callback + * @note The HAL_FMPI2C_UnRegisterCallback() may be called before HAL_FMPI2C_Init() in HAL_FMPI2C_STATE_RESET + * to un-register callbacks for HAL_FMPI2C_MSPINIT_CB_ID and HAL_FMPI2C_MSPDEINIT_CB_ID. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param CallbackID ID of the callback to be unregistered @@ -855,9 +874,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, H { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hfmpi2c); - if (HAL_FMPI2C_STATE_READY == hfmpi2c->State) { switch (CallbackID) @@ -945,8 +961,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, H status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpi2c); return status; } @@ -969,8 +983,6 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hfmpi2c); if (HAL_FMPI2C_STATE_READY == hfmpi2c->State) { @@ -985,8 +997,6 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpi2c); return status; } @@ -1001,9 +1011,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hfmpi2c); - if (HAL_FMPI2C_STATE_READY == hfmpi2c->State) { hfmpi2c->AddrCallback = HAL_FMPI2C_AddrCallback; /* Legacy weak AddrCallback */ @@ -1017,8 +1024,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpi2c); return status; } @@ -1113,9 +1118,10 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t xfermode; if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { @@ -1139,19 +1145,40 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint hfmpi2c->XferCount = Size; hfmpi2c->XferISR = NULL; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_GENERATE_START_WRITE); + xfermode = FMPI2C_RELOAD_MODE; } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_WRITE); + xfermode = FMPI2C_AUTOEND_MODE; + } + + if (hfmpi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), xfermode, + FMPI2C_GENERATE_START_WRITE); + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, + FMPI2C_GENERATE_START_WRITE); } while (hfmpi2c->XferCount > 0U) @@ -1182,13 +1209,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } } @@ -1232,7 +1259,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1262,15 +1289,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } while (hfmpi2c->XferCount > 0U) @@ -1302,13 +1329,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } } @@ -1350,9 +1377,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { @@ -1387,6 +1416,19 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 return HAL_ERROR; } + /* Preload TX data if no stretch enable */ + if (hfmpi2c->Init.NoStretchMode == FMPI2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + } + /* Clear ADDR flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); @@ -1432,26 +1474,48 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 hfmpi2c->XferCount--; } - /* Wait until STOP flag is set */ - if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + /* Wait until AF flag is set */ + error = FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; + /* Check that FMPI2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ - if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + tmpXferCount = hfmpi2c->XferCount; + if ((hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) && (tmpXferCount == 0U)) { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ + /* Reset ErrorCode to NONE */ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; } else { + /* Disable Address Acknowledge */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; return HAL_ERROR; } } + else + { + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); - /* Clear STOP flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + /* Clear AF flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + } /* Wait until BUSY flag is reset */ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) @@ -1488,7 +1552,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; @@ -1512,6 +1576,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ /* Prepare transfer parameters */ hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; + hfmpi2c->XferSize = hfmpi2c->XferCount; hfmpi2c->XferISR = NULL; /* Enable Address Acknowledge */ @@ -1554,6 +1619,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ hfmpi2c->pBuffPtr++; hfmpi2c->XferCount--; + hfmpi2c->XferSize--; } return HAL_ERROR; @@ -1566,6 +1632,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ hfmpi2c->pBuffPtr++; hfmpi2c->XferCount--; + hfmpi2c->XferSize--; } /* Wait until STOP flag is set */ @@ -1615,7 +1682,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) + uint16_t Size) { uint32_t xfermode; @@ -1652,7 +1719,26 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE); + if (hfmpi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), xfermode, + FMPI2C_GENERATE_START_WRITE); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, + FMPI2C_GENERATE_START_WRITE); + } /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1686,7 +1772,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) + uint16_t Size) { uint32_t xfermode; @@ -1712,7 +1798,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; xfermode = FMPI2C_RELOAD_MODE; } else @@ -1775,6 +1861,20 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; + /* Preload TX data if no stretch enable */ + if (hfmpi2c->Init.NoStretchMode == FMPI2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1857,10 +1957,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { @@ -1893,6 +1994,20 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, xfermode = FMPI2C_AUTOEND_MODE; } + if (hfmpi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + sizetoxfer = hfmpi2c->XferSize; + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + if (hfmpi2c->XferSize > 0U) { if (hfmpi2c->hdmatx != NULL) @@ -1908,8 +2023,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, - hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, + (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); } else { @@ -1930,7 +2045,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, { /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), + xfermode, FMPI2C_GENERATE_START_WRITE); /* Update XferCount value */ hfmpi2c->XferCount -= hfmpi2c->XferSize; @@ -1969,8 +2085,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2004,7 +2120,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -2031,7 +2147,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; xfermode = FMPI2C_RELOAD_MODE; } else @@ -2117,7 +2233,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2125,11 +2241,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); } return HAL_OK; @@ -2173,67 +2289,99 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Slave_ISR_DMA; - if (hfmpi2c->hdmatx != NULL) + /* Preload TX data if no stretch enable */ + if (hfmpi2c->Init.NoStretchMode == FMPI2C_NOSTRETCH_ENABLE) { - /* Set the FMPI2C DMA transfer complete callback */ - hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError; + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; - /* Set the unused DMA callbacks to NULL */ - hfmpi2c->hdmatx->XferHalfCpltCallback = NULL; - hfmpi2c->hdmatx->XferAbortCallback = NULL; + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, - hfmpi2c->XferSize); + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; } - else + + if (hfmpi2c->XferCount != 0U) { - /* Update FMPI2C state */ - hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if (hfmpi2c->hdmatx != NULL) + { + /* Set the FMPI2C DMA transfer complete callback */ + hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt; - /* Update FMPI2C error code */ - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM; + /* Set the DMA error callback */ + hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Set the unused DMA callbacks to NULL */ + hfmpi2c->hdmatx->XferHalfCpltCallback = NULL; + hfmpi2c->hdmatx->XferAbortCallback = NULL; - return HAL_ERROR; - } + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, + (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); + } + else + { + /* Update FMPI2C state */ + hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK; + /* Update FMPI2C error code */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - /* Note : The FMPI2C interrupts must be enabled after unlocking current process - to avoid the risk of FMPI2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + /* Note : The FMPI2C interrupts must be enabled after unlocking current process + to avoid the risk of FMPI2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + } + else + { + /* Update FMPI2C state */ + hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + + /* Update FMPI2C error code */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + return HAL_ERROR; + } } else { - /* Update FMPI2C state */ - hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - - /* Update FMPI2C error code */ - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA; + /* Enable Address Acknowledge */ + hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Note : The FMPI2C interrupts must be enabled after unlocking current process + to avoid the risk of FMPI2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); } return HAL_OK; @@ -2347,6 +2495,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui return HAL_BUSY; } } + /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains @@ -2361,7 +2510,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2445,13 +2594,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } @@ -2498,7 +2647,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2545,15 +2694,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } do @@ -2583,15 +2732,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t) hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } } while (hfmpi2c->XferCount > 0U); @@ -2635,11 +2784,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); @@ -2659,41 +2805,38 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; /* Prepare transfer parameters */ + hfmpi2c->XferSize = 0U; hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_IT; + hfmpi2c->Devaddress = DevAddress; - if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); + } /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; - } - - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2729,11 +2872,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); @@ -2753,9 +2893,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2764,29 +2901,29 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_IT; + hfmpi2c->Devaddress = DevAddress; - if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2795,11 +2932,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); return HAL_OK; } @@ -2808,6 +2945,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t return HAL_BUSY; } } + /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains @@ -2821,10 +2959,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2846,9 +2982,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2857,28 +2990,36 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_DMA; + hfmpi2c->Devaddress = DevAddress; if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); + } if (hfmpi2c->hdmatx != NULL) { @@ -2913,12 +3054,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 if (dmaxferstatus == HAL_OK) { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP); - - /* Update XferCount value */ - hfmpi2c->XferCount -= hfmpi2c->XferSize; + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2926,11 +3063,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } else { @@ -2968,10 +3105,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2993,9 +3128,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -3004,25 +3136,35 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_DMA; + hfmpi2c->Devaddress = DevAddress; if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); } if (hfmpi2c->hdmarx != NULL) @@ -3058,11 +3200,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ if (dmaxferstatus == HAL_OK) { - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); - - /* Update XferCount value */ - hfmpi2c->XferCount -= hfmpi2c->XferSize; + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3070,11 +3209,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } else { @@ -3111,7 +3250,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; @@ -3203,22 +3342,6 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (FMPI2C_Trials == Trials) - { - /* Generate Stop */ - hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); - } - /* Increment Trials */ FMPI2C_Trials++; } while (FMPI2C_Trials < Trials); @@ -3253,10 +3376,11 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3288,6 +3412,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 xfermode = hfmpi2c->XferOptions; } + if ((hfmpi2c->XferSize > 0U) && ((XferOptions == FMPI2C_FIRST_FRAME) || \ + (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + sizetoxfer = hfmpi2c->XferSize; + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3309,7 +3448,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 } /* Send Slave Address and set NBYTES to write */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)) + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3317,6 +3463,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); return HAL_OK; @@ -3340,11 +3490,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3376,6 +3527,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi xfermode = hfmpi2c->XferOptions; } + if ((hfmpi2c->XferSize > 0U) && ((XferOptions == FMPI2C_FIRST_FRAME) || \ + (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + sizetoxfer = hfmpi2c->XferSize; + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3411,8 +3577,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, - hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, + (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); } else { @@ -3432,7 +3598,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi if (dmaxferstatus == HAL_OK) { /* Send Slave Address and set NBYTES to write */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)) + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + } /* Update XferCount value */ hfmpi2c->XferCount -= hfmpi2c->XferSize; @@ -3471,8 +3644,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_WRITE); + if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)) + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3508,7 +3687,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_READ; @@ -3595,7 +3774,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_READ; @@ -3727,7 +3906,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3735,11 +3914,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); } return HAL_OK; @@ -3761,8 +3940,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3822,7 +4004,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c hfmpi2c->XferOptions = XferOptions; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -3857,8 +4040,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3893,7 +4078,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; /* Set the FMPI2C DMA Abort callback : - will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort; /* Abort DMA RX */ @@ -3915,7 +4100,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 if (hfmpi2c->hdmatx != NULL) { /* Set the FMPI2C DMA Abort callback : - will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort; /* Abort DMA TX */ @@ -4000,7 +4185,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 return HAL_ERROR; } - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4010,15 +4196,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); + /* Enable DMA Request */ + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; - return HAL_OK; } else @@ -4038,8 +4224,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4099,7 +4288,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, hfmpi2c->XferOptions = XferOptions; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4134,8 +4324,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4277,7 +4469,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c return HAL_ERROR; } - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4287,15 +4480,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); + /* Enable DMA Request */ + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; - return HAL_OK; } else @@ -4429,7 +4622,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint * the configuration information for the specified FMPI2C. * @retval None */ -void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) +void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) /* Derogation MISRAC2012-Rule-8.13 */ { /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hfmpi2c->Instance->ISR); @@ -4682,7 +4875,7 @@ __weak void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c) * the configuration information for the specified FMPI2C. * @retval HAL state */ -HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c) +HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(const FMPI2C_HandleTypeDef *hfmpi2c) { /* Return FMPI2C handle state */ return hfmpi2c->State; @@ -4694,7 +4887,7 @@ HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c) * the configuration information for FMPI2C module * @retval HAL mode */ -HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c) +HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(const FMPI2C_HandleTypeDef *hfmpi2c) { return hfmpi2c->Mode; } @@ -4705,7 +4898,7 @@ HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c) * the configuration information for the specified FMPI2C. * @retval FMPI2C Error Code */ -uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c) +uint32_t HAL_FMPI2C_GetError(const FMPI2C_HandleTypeDef *hfmpi2c) { return hfmpi2c->ErrorCode; } @@ -4731,7 +4924,7 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c) * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -4768,17 +4961,22 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm hfmpi2c->XferSize--; hfmpi2c->XferCount--; } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) == RESET) && \ + ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET))) { /* Write data to TXDR */ - hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + if (hfmpi2c->XferCount != 0U) + { + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; - /* Increment Buffer pointer */ - hfmpi2c->pBuffPtr++; + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; - hfmpi2c->XferSize--; - hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + hfmpi2c->XferCount--; + } } else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && \ (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) @@ -4789,7 +4987,15 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); } else @@ -4798,12 +5004,12 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) { FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, - hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); + hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); } else { FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, - FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); } } } @@ -4869,50 +5075,208 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm } /** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param ITFlags Interrupt flags to handle. * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Mem_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { - uint32_t tmpoptions = hfmpi2c->XferOptions; + uint32_t direction = FMPI2C_GENERATE_START_WRITE; uint32_t tmpITFlags = ITFlags; - /* Process locked */ + /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Check if STOPF is set */ - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { - /* Call FMPI2C Slave complete process */ - FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags); + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~FMPI2C_FLAG_RXNE; - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + /* Read data from RXDR */ + *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferSize--; + hfmpi2c->XferCount--; + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) { - /* Check that FMPI2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hfmpi2c->XferCount == 0U) + if (hfmpi2c->Memaddress == 0xFFFFFFFFU) { - if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) - /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for - Warning[Pa134]: left and right operands are identical */ - { - /* Call FMPI2C Listen complete process */ - FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags); - } - else if ((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != FMPI2C_NO_OPTION_FRAME)) - { - /* Clear NACK Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferSize--; + hfmpi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hfmpi2c->Instance->TXDR = hfmpi2c->Memaddress; + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U)) + { + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE); + } + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); + + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + direction = FMPI2C_GENERATE_START_READ; + } + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } + + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, direction); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + { + /* Call FMPI2C Master complete process */ + FMPI2C_ITMasterCplt(hfmpi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains + * the configuration information for the specified FMPI2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hfmpi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hfmpi2c); + + /* Check if STOPF is set */ + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + { + /* Call FMPI2C Slave complete process */ + FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags); + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + { + /* Check that FMPI2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hfmpi2c->XferCount == 0U) + { + if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call FMPI2C Listen complete process */ + FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags); + } + else if ((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != FMPI2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); @@ -5018,7 +5382,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -5057,7 +5421,15 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf /* Prepare the new XferSize to transfer */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } xfermode = FMPI2C_RELOAD_MODE; } else @@ -5149,6 +5521,170 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains + * the configuration information for the specified FMPI2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef FMPI2C_Mem_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = FMPI2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hfmpi2c); + + if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Set corresponding Error Code */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT); + + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hfmpi2c->Instance->TXDR = hfmpi2c->Memaddress; + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); + + if (hfmpi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hfmpi2c->XferCount -= hfmpi2c->XferSize; + + /* Enable DMA Request */ + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + } + else + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE); + } + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); + + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + direction = FMPI2C_GENERATE_START_READ; + } + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } + + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, direction); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hfmpi2c->XferCount -= hfmpi2c->XferSize; + + /* Enable DMA Request */ + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + } + else + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + } + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + { + /* Call FMPI2C Master complete process */ + FMPI2C_ITMasterCplt(hfmpi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains @@ -5158,7 +5694,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint32_t tmpoptions = hfmpi2c->XferOptions; uint32_t treatdmanack = 0U; @@ -5174,9 +5710,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags); } - - if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5190,7 +5725,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm { if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_RXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) { treatdmanack = 1U; } @@ -5202,7 +5737,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm { if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_TXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx) == 0U) { treatdmanack = 1U; } @@ -5303,8 +5838,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); @@ -5358,8 +5893,8 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); @@ -5775,6 +6310,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hfmpi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hfmpi2c->XferOptions; HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State; /* Clear STOP Flag */ @@ -5791,6 +6327,11 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT); hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_FMPI2C_STATE_LISTEN) + { + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT); + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; + } else { /* Do nothing */ @@ -5813,7 +6354,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) if (hfmpi2c->hdmatx != NULL) { - hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx); + hfmpi2c->XferCount = (uint16_t)FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx); } } else if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_RXDMAEN) != RESET) @@ -5823,7 +6364,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) if (hfmpi2c->hdmarx != NULL) { - hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx); + hfmpi2c->XferCount = (uint16_t)FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx); } } else @@ -5857,6 +6398,57 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; } + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_IT_NACKI) != RESET)) + { + /* Check that FMPI2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hfmpi2c->XferCount == 0U) + { + if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call FMPI2C Listen complete process */ + FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags); + } + else if ((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != FMPI2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); + + /* Last Byte is Transmitted */ + /* Call FMPI2C Slave Sequential complete process */ + FMPI2C_ITSlaveSeqCplt(hfmpi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + + if ((tmpoptions == FMPI2C_FIRST_FRAME) || (tmpoptions == FMPI2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode); + } + } + } + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; hfmpi2c->XferISR = NULL; @@ -5984,6 +6576,7 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) { HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ @@ -6011,20 +6604,38 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) /* Disable all interrupts */ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT); + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hfmpi2c->State != HAL_FMPI2C_STATE_ABORT) { /* Set HAL_FMPI2C_STATE_READY */ hfmpi2c->State = HAL_FMPI2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) + { + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) + { + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + } + } hfmpi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ tmppreviousstate = hfmpi2c->PreviousState; + if ((hfmpi2c->hdmatx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_TX) || \ - (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX))) + (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX))) { if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) { @@ -6054,7 +6665,7 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) } /* Abort DMA RX transfer if any */ else if ((hfmpi2c->hdmarx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_RX) || \ - (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX))) + (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX))) { if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN) { @@ -6197,6 +6808,7 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C slave transmit process complete callback. * @param hdma DMA handle @@ -6225,6 +6837,7 @@ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C master receive process complete callback. * @param hdma DMA handle @@ -6253,7 +6866,15 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /* Set the XferSize to transfer */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } } else { @@ -6275,6 +6896,7 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C slave receive process complete callback. * @param hdma DMA handle @@ -6286,7 +6908,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hfmpi2c->XferOptions; - if ((__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) && \ + if ((FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) && \ (tmpoptions != FMPI2C_NO_OPTION_FRAME)) { /* Disable DMA Request */ @@ -6303,6 +6925,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C communication error callback. * @param hdma DMA handle @@ -6316,7 +6939,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) if (hfmpi2c->hdmatx != NULL) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx) == 0U) { treatdmaerror = 1U; } @@ -6324,7 +6947,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) if (hfmpi2c->hdmarx != NULL) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) { treatdmaerror = 1U; } @@ -6341,6 +6964,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C communication abort callback * (To be called at end of DMA Abort procedure). @@ -6365,6 +6989,7 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) FMPI2C_TreatErrorCallback(hfmpi2c); } + /** * @brief This function handles FMPI2C Communication Timeout. It waits * until a flag is no longer in the specified status. @@ -6377,22 +7002,31 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t Tickstart) + uint32_t Timeout, uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status) { + /* Check if an error is detected */ + if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + return HAL_ERROR; + } } } } @@ -6408,7 +7042,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart) + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET) { @@ -6423,14 +7057,17 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -6446,7 +7083,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart) + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) { @@ -6459,14 +7096,17 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6481,18 +7121,20 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart) + uint32_t Tickstart) { - while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -6500,40 +7142,51 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) { + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF; + /* Clear STOP Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); /* Clear Configuration Register 2 */ FMPI2C_RESET_CR2(hfmpi2c); - hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + status = HAL_ERROR; + } } } - return HAL_OK; + return status; } /** @@ -6549,15 +7202,14 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u HAL_StatusTypeDef status = HAL_OK; uint32_t itflag = hfmpi2c->Instance->ISR; uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_FMPI2C_ModeTypeDef tmp2; if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_AF)) { - /* In case of Soft End condition, generate the STOP condition */ - if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE) - { - /* Generate Stop */ - hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; - } + /* Clear NACKF Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ @@ -6566,11 +7218,35 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - error_code |= HAL_FMPI2C_ERROR_TIMEOUT; + tmp1 = (uint32_t)(hfmpi2c->Instance->CR2 & FMPI2C_CR2_STOP); + tmp2 = hfmpi2c->Mode; - status = HAL_ERROR; + /* In case of FMPI2C still busy, try to regenerate a STOP manually */ + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) != RESET) && \ + (tmp1 != FMPI2C_CR2_STOP) && \ + (tmp2 != HAL_FMPI2C_MODE_SLAVE)) + { + /* Generate Stop */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > FMPI2C_TIMEOUT_STOPF) + { + error_code |= HAL_FMPI2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } } } } @@ -6582,9 +7258,6 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); } - /* Clear NACKF Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); - error_code |= HAL_FMPI2C_ERROR_AF; status = HAL_ERROR; @@ -6666,7 +7339,7 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u * @retval None */ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request) + uint32_t Request) { /* Check the parameters */ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance)); @@ -6675,14 +7348,14 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAdd /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \ - (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hfmpi2c->Instance->CR2, \ ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \ (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | \ - FMPI2C_CR2_START | FMPI2C_CR2_STOP)), tmp); + FMPI2C_CR2_START | FMPI2C_CR2_STOP)), tmp); } /** @@ -6696,8 +7369,9 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR { uint32_t tmpisr = 0U; - if ((hfmpi2c->XferISR == FMPI2C_Master_ISR_DMA) || \ - (hfmpi2c->XferISR == FMPI2C_Slave_ISR_DMA)) + if ((hfmpi2c->XferISR != FMPI2C_Master_ISR_DMA) && \ + (hfmpi2c->XferISR != FMPI2C_Slave_ISR_DMA) && \ + (hfmpi2c->XferISR != FMPI2C_Mem_ISR_DMA)) { if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) { @@ -6705,6 +7379,18 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } + if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI; + } + + if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI; + } + if (InterruptRequest == FMPI2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ @@ -6714,39 +7400,46 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR if (InterruptRequest == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= (FMPI2C_IT_STOPI | FMPI2C_IT_TCI); - } - - if (InterruptRequest == FMPI2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= FMPI2C_IT_TCI; + tmpisr |= FMPI2C_IT_STOPI; } } + else { if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ + /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI; } if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI; } + if (InterruptRequest == FMPI2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI; + } + if (InterruptRequest == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= FMPI2C_IT_STOPI; + tmpisr |= (FMPI2C_IT_STOPI | FMPI2C_IT_TCI); + } + + if (InterruptRequest == FMPI2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= FMPI2C_IT_TCI; } } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c index 700f25af05..4c913c6283 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c @@ -209,20 +209,28 @@ /** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions * @{ */ +/* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, - FlagStatus Status, uint32_t Timeout); + FlagStatus Status, uint32_t Timeout); -static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); -static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +/* Private functions for FMPSMBUS transfer IRQ handler */ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); +static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); -static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/* Private functions to centralize the enable/disable of Interrupts */ +static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); -static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/* Private function to flush TXDR register */ +static void FMPSMBUS_Flush_TXDR(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/* Private function to handle start, restart or stop a transfer */ static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, - uint32_t Mode, uint32_t Request); + uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus); /** * @} */ @@ -371,13 +379,13 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus) /*---------------------------- FMPSMBUSx OAR2 Configuration -----------------------*/ /* Configure FMPSMBUSx: Dual mode and Own Address2 */ hfmpsmbus->Instance->OAR2 = (hfmpsmbus->Init.DualAddressMode | hfmpsmbus->Init.OwnAddress2 | \ - (hfmpsmbus->Init.OwnAddress2Masks << 8U)); + (hfmpsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- FMPSMBUSx CR1 Configuration ------------------------*/ /* Configure FMPSMBUSx: Generalcall and NoStretch mode */ hfmpsmbus->Instance->CR1 = (hfmpsmbus->Init.GeneralCallMode | hfmpsmbus->Init.NoStretchMode | \ - hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | \ - hfmpsmbus->Init.AnalogFilter); + hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | \ + hfmpsmbus->Init.AnalogFilter); /* Enable Slave Byte Control only in case of Packet Error Check is enabled and FMPSMBUS Peripheral is set in Slave mode */ @@ -577,6 +585,9 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps /** * @brief Register a User FMPSMBUS Callback * To be used instead of the weak predefined callback + * @note The HAL_FMPSMBUS_RegisterCallback() may be called before HAL_FMPSMBUS_Init() in + * HAL_FMPSMBUS_STATE_RESET to register callbacks for HAL_FMPSMBUS_MSPINIT_CB_ID and + * HAL_FMPSMBUS_MSPDEINIT_CB_ID. * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains * the configuration information for the specified FMPSMBUS. * @param CallbackID ID of the callback to be registered @@ -593,8 +604,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, - pFMPSMBUS_CallbackTypeDef pCallback) + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, + pFMPSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -606,9 +617,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hfmpsmbus); - if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) { switch (CallbackID) @@ -684,14 +692,15 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpsmbus); return status; } /** * @brief Unregister an FMPSMBUS Callback * FMPSMBUS callback is redirected to the weak predefined callback + * @note The HAL_FMPSMBUS_UnRegisterCallback() may be called before HAL_FMPSMBUS_Init() in + * HAL_FMPSMBUS_STATE_RESET to un-register callbacks for HAL_FMPSMBUS_MSPINIT_CB_ID and + * HAL_FMPSMBUS_MSPDEINIT_CB_ID * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains * the configuration information for the specified FMPSMBUS. * @param CallbackID ID of the callback to be unregistered @@ -708,13 +717,10 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hfmpsmbus); - if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) { switch (CallbackID) @@ -790,8 +796,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsm status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpsmbus); return status; } @@ -804,7 +808,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsm * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - pFMPSMBUS_AddrCallbackTypeDef pCallback) + pFMPSMBUS_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -815,8 +819,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmp return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hfmpsmbus); if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) { @@ -831,8 +833,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmp status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpsmbus); return status; } @@ -847,9 +847,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hfmpsmbus); - if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) { hfmpsmbus->AddrCallback = HAL_FMPSMBUS_AddrCallback; /* Legacy weak AddrCallback */ @@ -863,8 +860,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpsmbus); return status; } @@ -929,9 +924,10 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions) + uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; + uint32_t sizetoxfer; /* Check the parameters */ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -964,13 +960,37 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm hfmpsmbus->XferSize = Size; } + sizetoxfer = hfmpsmbus->XferSize; + if ((sizetoxfer > 0U) && ((XferOptions == FMPSMBUS_FIRST_FRAME) || + (XferOptions == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || + (XferOptions == FMPSMBUS_FIRST_FRAME_WITH_PEC) || + (XferOptions == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) + { + if (hfmpsmbus->pBuffPtr != NULL) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpsmbus->Instance->TXDR = *hfmpsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpsmbus->pBuffPtr++; + + hfmpsmbus->XferCount--; + hfmpsmbus->XferSize--; + } + else + { + return HAL_ERROR; + } + } + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) + if ((sizetoxfer < hfmpsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE)) { - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), - FMPSMBUS_GENERATE_START_WRITE); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_GENERATE_START_WRITE); } else { @@ -983,8 +1003,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) && \ (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -993,17 +1013,24 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); /* Handle Transfer */ - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - hfmpsmbus->XferOptions, - FMPSMBUS_GENERATE_START_WRITE); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, + hfmpsmbus->XferOptions, + FMPSMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) { - hfmpsmbus->XferSize--; - hfmpsmbus->XferCount--; + if (hfmpsmbus->XferSize > 0U) + { + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } } } @@ -1035,7 +1062,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -1076,8 +1103,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), - FMPSMBUS_GENERATE_START_READ); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_GENERATE_START_READ); } else { @@ -1091,7 +1118,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1101,8 +1128,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb /* Handle Transfer */ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - hfmpsmbus->XferOptions, - FMPSMBUS_GENERATE_START_READ); + hfmpsmbus->XferOptions, + FMPSMBUS_GENERATE_START_READ); } } @@ -1197,7 +1224,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1246,14 +1273,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) { FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -1295,7 +1322,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1340,7 +1367,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbu if (((FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) && (hfmpsmbus->XferSize == 2U)) || (hfmpsmbus->XferSize == 1U)) { FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); } else { @@ -1455,7 +1482,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; @@ -1604,7 +1631,7 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) /* FMPSMBUS in mode Transmitter ---------------------------------------------------*/ if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | - FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1629,7 +1656,7 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) /* FMPSMBUS in mode Receiver ----------------------------------------------------*/ if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | - FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1750,7 +1777,7 @@ __weak void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @retval None */ __weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, - uint16_t AddrMatchCode) + uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfmpsmbus); @@ -1819,7 +1846,7 @@ __weak void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) * the configuration information for the specified FMPSMBUS. * @retval HAL state */ -uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus) +uint32_t HAL_FMPSMBUS_GetState(const FMPSMBUS_HandleTypeDef *hfmpsmbus) { /* Return FMPSMBUS handle state */ return hfmpsmbus->State; @@ -1831,7 +1858,7 @@ uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus) * the configuration information for the specified FMPSMBUS. * @retval FMPSMBUS Error Code */ -uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus) +uint32_t HAL_FMPSMBUS_GetError(const FMPSMBUS_HandleTypeDef *hfmpsmbus) { return hfmpsmbus->ErrorCode; } @@ -1872,6 +1899,9 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, /* No need to generate STOP, it is automatically done */ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF; + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hfmpsmbus); @@ -1997,15 +2027,15 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, MAX_NBYTE_SIZE, - (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), - FMPSMBUS_NO_STARTSTOP); + (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), + FMPSMBUS_NO_STARTSTOP); hfmpsmbus->XferSize = MAX_NBYTE_SIZE; } else { hfmpsmbus->XferSize = hfmpsmbus->XferCount; FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2162,6 +2192,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u /* Clear NACK Flag */ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF); + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hfmpsmbus); } @@ -2183,6 +2216,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u /* Set ErrorCode corresponding to a Non-Acknowledge */ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF; + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hfmpsmbus); @@ -2258,8 +2294,8 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u { /* Set Reload for next Bytes */ FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK; @@ -2272,15 +2308,15 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) { FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, - (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), - FMPSMBUS_NO_STARTSTOP); + (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), + FMPSMBUS_NO_STARTSTOP); hfmpsmbus->XferSize = MAX_NBYTE_SIZE; } else { hfmpsmbus->XferSize = hfmpsmbus->XferCount; FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2584,7 +2620,13 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_PECERR); } - /* Store current volatile hfmpsmbus->State, misra rule */ + if (hfmpsmbus->ErrorCode != HAL_FMPSMBUS_ERROR_NONE) + { + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + } + + /* Store current volatile hfmpsmbus->ErrorCode, misra rule */ tmperror = hfmpsmbus->ErrorCode; /* Call the Error Callback in case of Error detected */ @@ -2625,7 +2667,7 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @retval HAL status */ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, - FlagStatus Status, uint32_t Timeout) + FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2654,6 +2696,27 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef return HAL_OK; } +/** + * @brief FMPSMBUS Tx data register flush process. + * @param hfmpsmbus FMPSMBUS handle. + * @retval None + */ +static void FMPSMBUS_Flush_TXDR(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXIS) != RESET) + { + hfmpsmbus->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXE) == RESET) + { + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXE); + } +} + /** * @brief Handle FMPSMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hfmpsmbus FMPSMBUS handle. @@ -2675,7 +2738,7 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef * @retval None */ static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, - uint32_t Mode, uint32_t Request) + uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c index f3aafe0a57..5fc5cc9d95 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c @@ -1657,7 +1657,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; uint32_t inputaddr; uint32_t buffersize; - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; if (hhash->State != HAL_HASH_STATE_SUSPENDED) { diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c index c7c5b70b90..7ab1222726 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c @@ -109,7 +109,9 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx; +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ /* Check the HCD handle allocation */ if (hhcd == NULL) @@ -120,7 +122,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); +#if defined (USB_OTG_FS) USBx = hhcd->Instance; +#endif /* defined (USB_OTG_FS) */ if (hhcd->State == HAL_HCD_STATE_RESET) { @@ -150,23 +154,37 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) hhcd->State = HAL_HCD_STATE_BUSY; +#if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 8)) == 0U) + if (USBx == USB_OTG_FS) { hhcd->Init.dma_enable = 0U; } +#endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_HCD_DISABLE(hhcd); /* Init the Core (common init.) */ - (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } - /* Force Host Mode*/ - (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + /* Force Host Mode */ + if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } /* Init Host */ - (void)USB_HostInit(hhcd->Instance, hhcd->Init); + if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } hhcd->State = HAL_HCD_STATE_READY; @@ -197,24 +215,22 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 0 to32K * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) { HAL_StatusTypeDef status; + uint32_t HostCoreSpeed; + uint32_t HCcharMps = mps; __HAL_LOCK(hhcd); hhcd->hc[ch_num].do_ping = 0U; hhcd->hc[ch_num].dev_addr = dev_address; - hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ep_type = ep_type; hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num); + if ((epnum & 0x80U) == 0x80U) { hhcd->hc[ch_num].ep_is_in = 1U; @@ -224,15 +240,27 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].ep_is_in = 0U; } + HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + if (ep_type == EP_TYPE_ISOC) + { + /* FS device plugged to HS HUB */ + if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + if (HCcharMps > ISO_SPLT_MPS) + { + /* ISO Max Packet Size for Split mode */ + HCcharMps = ISO_SPLT_MPS; + } + } + } + hhcd->hc[ch_num].speed = speed; + hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps; + + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, + dev_address, speed, ep_type, (uint16_t)HCcharMps); - status = USB_HC_Init(hhcd->Instance, - ch_num, - epnum, - dev_address, - speed, - ep_type, - mps); __HAL_UNLOCK(hhcd); return status; @@ -250,7 +278,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) HAL_StatusTypeDef status = HAL_OK; __HAL_LOCK(hhcd); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + (void)USB_HC_Halt(hhcd->Instance, ch_num); __HAL_UNLOCK(hhcd); return status; @@ -389,24 +417,41 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, switch (ep_type) { case EP_TYPE_CTRL: - if ((token == 1U) && (direction == 0U)) /*send data */ + if (token == 1U) /* send data */ { - if (length == 0U) + if (direction == 0U) { - /* For Status OUT stage, Length==0, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1U; - } + if (length == 0U) + { + /* For Status OUT stage, Length == 0U, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } - /* Set the Data Toggle bit as per the Flag */ - if (hhcd->hc[ch_num].toggle_out == 0U) - { - /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } else { - /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + if (hhcd->hc[ch_num].do_ssplit == 1U) + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } } } break; @@ -541,8 +586,11 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) (void)USB_FlushTxFifo(USBx, 0x10U); (void)USB_FlushRxFifo(USBx); - /* Restore FS Clock */ - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) @@ -571,16 +619,6 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); } - /* Handle Rx Queue Level Interrupts */ - if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) - { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - HCD_RXQLVL_IRQHandler(hhcd); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - /* Handle Host channel Interrupt */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { @@ -601,6 +639,16 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } } } @@ -1084,7 +1132,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) * @param hhcd HCD handle * @retval HAL state */ -HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd) { return hhcd->State; } @@ -1103,7 +1151,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) * URB_ERROR/ * URB_STALL */ -HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) { return hhcd->hc[chnum].urb_state; } @@ -1116,7 +1164,7 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu * This parameter can be a value from 1 to 15 * @retval last transfer size in byte */ -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum) { return hhcd->hc[chnum].xfer_count; } @@ -1138,7 +1186,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) * HC_BBLERR/ * HC_DATATGLERR */ -HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) { return hhcd->hc[chnum].state; } @@ -1163,6 +1211,54 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) return (USB_GetHostSpeed(hhcd->Instance)); } +/** + * @brief Set host channel Hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr) +{ + uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + /* LS/FS device plugged to HS HUB */ + if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + hhcd->hc[ch_num].do_ssplit = 1U; + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U)) + { + hhcd->hc[ch_num].toggle_in = 1U; + } + } + + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + + return HAL_OK; +} + + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + hhcd->hc[ch_num].do_ssplit = 0U; + hhcd->hc[ch_num].do_csplit = 0U; + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + + return HAL_OK; +} /** * @} */ @@ -1183,84 +1279,86 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)chnum; - uint32_t tmpreg; - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); - hhcd->hc[ch_num].state = HC_BBLERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); + hhcd->hc[chnum].state = HC_BBLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - hhcd->hc[ch_num].state = HC_STALL; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); - hhcd->hc[ch_num].state = HC_DATATGLERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) - { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } else { /* ... */ } - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) { - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) { + /* Clear any pending ACK IT */ + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + if (hhcd->Init.dma_enable != 0U) { - hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \ - (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); } - hhcd->hc[ch_num].state = HC_XFRC; - hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + hhcd->hc[chnum].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } - else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)) + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || + (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[ch_num].urb_state = URB_DONE; + USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[chnum].urb_state = URB_DONE; #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else @@ -1270,96 +1368,220 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 1U) { - if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U) + if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) { - hhcd->hc[ch_num].toggle_in ^= 1U; + hhcd->hc[chnum].toggle_in ^= 1U; } } else { - hhcd->hc[ch_num].toggle_in ^= 1U; + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 1U; + hhcd->hc[chnum].state = HC_ACK; + + (void)USB_HC_Halt(hhcd->Instance, chnum); } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) { - if (hhcd->hc[ch_num].state == HC_XFRC) + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; } - else if (hhcd->hc[ch_num].state == HC_STALL) + else if (hhcd->hc[chnum].state == HC_STALL) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; } - else if ((hhcd->hc[ch_num].state == HC_XACTERR) || - (hhcd->hc[ch_num].state == HC_DATATGLERR)) + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } } } - else if (hhcd->hc[ch_num].state == HC_NAK) + else if (hhcd->hc[chnum].state == HC_NYET) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + if (hhcd->hc[chnum].do_csplit == 1U) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].NyetErrCnt++; + if (hhcd->hc[chnum].NyetErrCnt > 2U) + { + hhcd->hc[chnum].NyetErrCnt = 0U; + hhcd->hc[chnum].do_csplit = 0U; + + if (hhcd->hc[chnum].ErrCnt < 3U) + { + hhcd->hc[chnum].ep_ss_schedule = 1U; + } + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Set Complete split and re-activate the channel */ + USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } } - else if (hhcd->hc[ch_num].state == HC_BBLERR) + else if (hhcd->hc[chnum].state == HC_BBLERR) { - hhcd->hc[ch_num].ErrCnt++; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - /* ... */ + if (hhcd->hc[chnum].state == HC_HALTED) + { + return; + } } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].ErrCnt = 0U; + } + + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) { - if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) { - hhcd->hc[ch_num].ErrCnt = 0U; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt = 0U; - if (hhcd->Init.dma_enable == 0U) + if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) { - hhcd->hc[ch_num].state = HC_NAK; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); } } else { /* ... */ } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + __HAL_HCD_UNMASK_ACK_HC_INT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } else { @@ -1376,184 +1598,231 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)chnum; uint32_t tmpreg; uint32_t num_packets; - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ping == 1U) + { + hhcd->hc[chnum].do_ping = 0U; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } - if (hhcd->hc[ch_num].do_ping == 1U) + if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) { - hhcd->hc[ch_num].do_ping = 0U; - hhcd->hc[ch_num].urb_state = URB_NOTREADY; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) + { + hhcd->hc[chnum].do_csplit = 1U; + } + + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + + /* reset error_count */ + hhcd->hc[chnum].ErrCnt = 0U; } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) { - hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt = 0U; /* transaction completed with NYET state, update do ping state */ - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) { - hhcd->hc[ch_num].do_ping = 1U; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); - hhcd->hc[ch_num].state = HC_XFRC; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + + if (hhcd->hc[chnum].do_csplit != 0U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) { - hhcd->hc[ch_num].state = HC_NYET; - hhcd->hc[ch_num].do_ping = 1U; - hhcd->hc[ch_num].ErrCnt = 0U; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].do_ping = 1U; + } + + hhcd->hc[chnum].ErrCnt = 0U; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - hhcd->hc[ch_num].state = HC_STALL; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].state = HC_NAK; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; - if (hhcd->hc[ch_num].do_ping == 0U) + if (hhcd->hc[chnum].do_ping == 0U) { - if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH) + if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) { - hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[chnum].do_ping = 1U; } } - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) { if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } else { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; } } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) { - hhcd->hc[ch_num].state = HC_DATATGLERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) { - if (hhcd->hc[ch_num].state == HC_XFRC) + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) { if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[ch_num].toggle_out ^= 1U; + hhcd->hc[chnum].toggle_out ^= 1U; } - if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U)) + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) { - num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; + num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; if ((num_packets & 1U) != 0U) { - hhcd->hc[ch_num].toggle_out ^= 1U; + hhcd->hc[chnum].toggle_out ^= 1U; } } } } - else if (hhcd->hc[ch_num].state == HC_NAK) + else if (hhcd->hc[chnum].state == HC_ACK) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } } - else if (hhcd->hc[ch_num].state == HC_NYET) + else if (hhcd->hc[chnum].state == HC_NAK) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } } - else if (hhcd->hc[ch_num].state == HC_STALL) + else if (hhcd->hc[chnum].state == HC_NYET) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; } - else if ((hhcd->hc[ch_num].state == HC_XACTERR) || - (hhcd->hc[ch_num].state == HC_DATATGLERR)) + else if (hhcd->hc[chnum].state == HC_STALL) { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; } } else { - /* ... */ + return; } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); - #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { - /* ... */ + return; } } @@ -1564,17 +1833,17 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t pktsts; uint32_t pktcnt; uint32_t GrxstspReg; uint32_t xferSizePktCnt; uint32_t tmpreg; - uint32_t ch_num; + uint32_t chnum; GrxstspReg = hhcd->Instance->GRXSTSP; - ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; @@ -1582,33 +1851,33 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { case GRXSTS_PKTSTS_IN: /* Read the data into the host buffer. */ - if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) + if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) { - if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len) + if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) { (void)USB_ReadPacket(hhcd->Instance, - hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); /* manage multiple Xfer */ - hhcd->hc[ch_num].xfer_buff += pktcnt; - hhcd->hc[ch_num].xfer_count += pktcnt; + hhcd->hc[chnum].xfer_buff += pktcnt; + hhcd->hc[chnum].xfer_count += pktcnt; /* get transfer size packet count */ - xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; - if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) { /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - hhcd->hc[ch_num].toggle_in ^= 1U; + USBx_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].toggle_in ^= 1U; } } else { - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].urb_state = URB_ERROR; } } break; @@ -1630,7 +1899,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0; __IO uint32_t hprt0_dup; @@ -1663,7 +1932,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) { - if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { @@ -1678,7 +1947,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { if (hhcd->Init.speed == HCD_SPEED_FULL) { - USBx_HOST->HFIR = 60000U; + USBx_HOST->HFIR = HFIR_60_MHZ; } } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c index c2a8eb7543..f2884b69f6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -89,7 +89,7 @@ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() @@ -139,7 +139,7 @@ or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() @@ -193,7 +193,7 @@ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() @@ -313,7 +313,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @addtogroup I2C_Private_Define +/** @defgroup I2C_Private_Define I2C Private Define * @{ */ #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ @@ -334,6 +334,14 @@ */ /* Private macro -------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macros + * @{ + */ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -383,6 +391,9 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + +/* Private function to flush DR register */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c); /** * @} */ @@ -940,6 +951,20 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @brief I2C data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c) +{ + /* Write a dummy data in DR to clear TXE flag */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET) + { + hi2c->Instance->DR = 0x00U; + } +} + /** * @} */ @@ -1357,6 +1382,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) { + + if (hi2c->XferSize == 3U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; @@ -1662,10 +1694,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -1742,10 +1771,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -1952,10 +1978,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -2110,10 +2133,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -2811,6 +2831,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) { + if (hi2c->XferSize == 3U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; @@ -2871,10 +2896,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -2959,10 +2981,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3057,10 +3076,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3241,10 +3257,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3577,10 +3590,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3676,10 +3686,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3859,10 +3866,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3984,10 +3988,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -4712,7 +4713,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4728,7 +4729,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA UNUSED(DevAddress); /* Abort Master transfer during Receive or Transmit process */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER)) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) || + (CurrentMode == HAL_I2C_MODE_MEM))) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -5504,7 +5506,8 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) } else { - /* Do nothing */ + /* Clear TXE and BTF flags */ + I2C_Flush_DR(hi2c); } } @@ -5519,7 +5522,9 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { uint32_t tmp; + uint32_t CurrentXferOptions; + CurrentXferOptions = hi2c->XferOptions; tmp = hi2c->XferCount; if (tmp > 3U) { @@ -5575,7 +5580,14 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) else { hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterRxCpltCallback(hi2c); @@ -5723,7 +5735,14 @@ static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) else { hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterRxCpltCallback(hi2c); #else @@ -6170,7 +6189,7 @@ static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) { if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) { - hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx)); + hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx)); if (hi2c->XferCount != 0U) { @@ -6198,7 +6217,7 @@ static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) } else { - hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx)); + hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx)); if (hi2c->XferCount != 0U) { @@ -6367,6 +6386,9 @@ static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Clear TXE flag */ + I2C_Flush_DR(hi2c); + #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else @@ -7028,7 +7050,14 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) else { hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterRxCpltCallback(hi2c); @@ -7203,15 +7232,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7255,15 +7287,18 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7293,15 +7328,18 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7331,15 +7369,18 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7367,15 +7408,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -7441,15 +7485,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c index 47b44ffdb1..0072dc19f2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c @@ -439,6 +439,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) /** * @brief Register a User IRDA Callback * To be used instead of the weak predefined callback + * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -466,8 +468,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hirda); if (hirda->gState == HAL_IRDA_STATE_READY) { @@ -552,15 +552,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } /** * @brief Unregister an IRDA callback * IRDA callback is redirected to the weak predefined callback + * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -580,9 +579,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hirda); - if (HAL_IRDA_STATE_READY == hirda->gState) { switch (CallbackID) @@ -666,9 +662,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ @@ -2030,7 +2023,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA. * @retval HAL state */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) { uint32_t temp1 = 0x00U, temp2 = 0x00U; temp1 = hirda->gState; @@ -2045,7 +2038,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA. * @retval IRDA Error Code */ -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) { return hirda->ErrorCode; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c index 7b569513ce..05fa66da80 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c @@ -185,7 +185,7 @@ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag); /* Exported functions --------------------------------------------------------*/ @@ -1753,7 +1753,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Counter value. */ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1766,7 +1766,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Autoreload value. */ -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1779,7 +1779,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Compare value. */ -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -2077,9 +2077,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2150,9 +2147,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } @@ -2178,9 +2172,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2262,9 +2253,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -2292,7 +2280,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti * @param hlptim LPTIM handle * @retval HAL state */ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim) { /* Return LPTIM handle state */ return hlptim->State; @@ -2339,7 +2327,7 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) * @param flag The lptim flag * @retval HAL status */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag) { HAL_StatusTypeDef result = HAL_OK; uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c index fcc5fa1611..f5f814820d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c @@ -178,7 +178,13 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Define LTDC Private Define + * @{ + */ #define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -549,7 +555,7 @@ HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTD break; case HAL_LTDC_MSPINIT_CB_ID : - hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ break; case HAL_LTDC_MSPDEINIT_CB_ID : diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c index 2ee7795bf3..ab2ca72ec4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c @@ -74,16 +74,18 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc /* The following polarity is inverted: LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ +#if !defined(POLARITIES_INVERSION_UPDATED) /* Note 1 : Code in line w/ Current LTDC specification */ hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \ DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; - +#else /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ - /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; - hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; - hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ + hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; +#endif /* POLARITIES_INVERSION_UPDATED */ /* Retrieve vertical timing parameters from DSI */ hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; @@ -115,17 +117,18 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ +#if !defined(POLARITIES_INVERSION_UPDATED) /* Note 1 : Code in line w/ Current LTDC specification */ hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \ DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; - +#else /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ - /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; - hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; - hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ - + hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; +#endif /* POLARITIES_INVERSION_UPDATED */ return HAL_OK; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c index a0b89e621c..5cd4ab2dae 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c @@ -77,15 +77,15 @@ and a pointer to the user callback function. Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_NAND_Init + reset to the legacy weak (overridden) functions in the HAL_NAND_Init and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -100,7 +100,7 @@ When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -199,7 +199,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank); #else __FMC_NAND_ENABLE(hnand->Instance); -#endif +#endif /* (FMC_Bank2_3) || (FSMC_Bank2_3) */ /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -428,7 +428,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Send Read ID command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; @@ -441,7 +441,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) #else /* FMC_PCR2_PWID is defined */ if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) -#endif +#endif /* FSMC_PCR2_PWID */ { data = *(__IO uint32_t *)deviceaddress; @@ -512,7 +512,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Send NAND reset command */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; @@ -561,8 +561,8 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; @@ -597,7 +597,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -730,8 +730,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; @@ -766,7 +766,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -860,9 +860,9 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address /* Calculate PageSize */ #if defined(FSMC_PCR2_PWID) - if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) #else - if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) #endif /* FSMC_PCR2_PWID */ { hnand->Config.PageSize = hnand->Config.PageSize / 2U; @@ -913,8 +913,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; @@ -922,7 +922,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; - uint8_t *buff = pBuffer; + const uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -949,7 +949,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1077,8 +1077,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; @@ -1086,7 +1086,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; - uint16_t *buff = pBuffer; + const uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1113,7 +1113,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1181,9 +1181,9 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres /* Calculate PageSize */ #if defined(FSMC_PCR2_PWID) - if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) #else - if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) #endif /* FSMC_PCR2_PWID */ { hnand->Config.PageSize = hnand->Config.PageSize / 2U; @@ -1256,8 +1256,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumSpareAreaToRead) +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; @@ -1293,7 +1293,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1432,7 +1432,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; @@ -1469,7 +1469,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1608,8 +1608,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; @@ -1618,7 +1618,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; - uint8_t *buff = pBuffer; + const uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1645,7 +1645,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Page address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1782,8 +1782,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; @@ -1792,7 +1792,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; - uint16_t *buff = pBuffer; + const uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1819,7 +1819,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1954,7 +1954,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A * @param pAddress pointer to NAND address structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress) { uint32_t deviceaddress; @@ -1983,7 +1983,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Send Erase block command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; @@ -2021,7 +2021,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address */ -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { uint32_t status = NAND_VALID_ADDRESS; @@ -2052,7 +2052,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /** * @brief Register a User NAND Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hnand : NAND handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -2072,9 +2072,6 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hnand); - if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) @@ -2116,14 +2113,12 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnand); return status; } /** * @brief Unregister a User NAND Callback - * NAND Callback is redirected to the weak (surcharged) predefined callback + * NAND Callback is redirected to the weak predefined callback * @param hnand : NAND handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -2136,9 +2131,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hnand); - if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) @@ -2180,8 +2172,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnand); return status; } #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ @@ -2332,7 +2322,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, * the configuration information for NAND module. * @retval HAL state */ -HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand) { return hnand->State; } @@ -2343,7 +2333,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) * the configuration information for NAND module. * @retval NAND status */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand) { uint32_t data; uint32_t deviceaddress; @@ -2361,7 +2351,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Send Read status operation command */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c index 0a82044866..22366b4005 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c @@ -74,15 +74,15 @@ and a pointer to the user callback function. Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_NOR_Init + reset to the legacy weak (overridden) functions in the HAL_NOR_Init and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -97,7 +97,7 @@ When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -106,7 +106,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" -#if defined(FMC_Bank1) || defined(FSMC_Bank1) +#if defined(FMC_Bank1) || defined(FSMC_Bank1) /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -127,6 +127,11 @@ */ /* Constants to define address to set to write a command */ +#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA +#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA +#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA + #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA @@ -264,7 +269,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); /* Initialize NOR extended mode timing Interface */ - (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); + (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, + hnor->Init.NSBank, hnor->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); @@ -310,7 +316,16 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe else { /* Get the value of the command set */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); status = HAL_NOR_ReturnToReadMode(hnor); @@ -472,9 +487,22 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /* Send read ID command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_AUTO_SELECT); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_AUTO_SELECT); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -641,9 +669,22 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -722,9 +763,21 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /* Send program data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_PROGRAM); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -814,9 +867,22 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -909,10 +975,20 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + } + else + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + } /* Write Buffer Load Command */ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); @@ -1012,14 +1088,26 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Send block erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + } NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) @@ -1097,15 +1185,28 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /* Send NOR chip erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), + NOR_CMD_DATA_CHIP_ERASE); + } } else { @@ -1176,8 +1277,15 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR } /* Send read CFI query command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } /* read the NOR CFI information */ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); @@ -1201,7 +1309,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /** * @brief Register a User NOR Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hnor : NOR handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1221,9 +1329,6 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hnor); - state = hnor->State; if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { @@ -1247,14 +1352,12 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnor); return status; } /** * @brief Unregister a User NOR Callback - * NOR Callback is redirected to the weak (surcharged) predefined callback + * NOR Callback is redirected to the weak predefined callback * @param hnor : NOR handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1267,9 +1370,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hnor); - state = hnor->State; if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { @@ -1293,8 +1393,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnor); return status; } #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ @@ -1411,7 +1509,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) * the configuration information for NOR module. * @retval NOR controller state */ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor) { return hnor->State; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c index 7e46592b31..fa50ea1863 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -122,7 +122,9 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx; +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ @@ -134,7 +136,9 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); +#if defined (USB_OTG_FS) USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) { @@ -171,11 +175,13 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; +#if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 8)) == 0U) + if (USBx == USB_OTG_FS) { hpcd->Init.dma_enable = 0U; } +#endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); @@ -187,8 +193,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) return HAL_ERROR; } - /* Force Device Mode*/ - (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) @@ -224,13 +234,17 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->USB_Address = 0U; hpcd->State = HAL_PCD_STATE_READY; -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) { (void)HAL_PCDEx_ActivateLPM(hpcd); } -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); return HAL_OK; @@ -318,7 +332,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function @@ -432,7 +446,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status @@ -1004,8 +1018,8 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; @@ -1033,8 +1047,8 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -1306,7 +1320,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) { @@ -1332,7 +1348,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { @@ -1513,16 +1531,17 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) */ void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) USB_OTG_GlobalTypeDef *USBx; - USBx = hpcd->Instance; - if ((USBx->CID & (0x1U << 8)) == 0U) + if (USBx == USB_OTG_FS) { /* Clear EXTI pending Bit */ __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); } else +#endif /* defined (USB_OTG_FS) */ { /* Clear EXTI pending Bit */ __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG(); @@ -1733,8 +1752,8 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; @@ -1757,8 +1776,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -1818,6 +1837,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; } + /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) { @@ -1851,7 +1871,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; ep->is_in = 0U; } - ep->num = ep_addr & EP_ADDR_MSK; + ep->num = ep_addr & EP_ADDR_MSK; __HAL_LOCK(hpcd); (void)USB_DeactivateEndpoint(hpcd->Instance, ep); @@ -1886,14 +1906,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); return HAL_OK; } @@ -1904,7 +1917,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u * @param ep_addr endpoint address * @retval Data Size */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) { return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; } @@ -1934,14 +1947,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); return HAL_OK; } @@ -2119,20 +2125,21 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval HAL state */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) { return hpcd->State; } +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Set the USB Device high speed test mode. * @param hpcd PCD handle * @param testmode USB Device high speed test mode * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; switch (testmode) @@ -2151,6 +2158,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) return HAL_OK; } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -2233,9 +2241,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { USB_OTG_EPTypeDef *ep; - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if (hpcd->Init.dma_enable == 1U) @@ -2344,9 +2352,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if ((gSNPSiD > USB_OTG_CORE_ID_300A) && diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c index 292faf13bc..b66be6ac35 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c @@ -115,7 +115,9 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) return HAL_OK; } -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -148,8 +150,11 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \ + || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Handle BatteryCharging Process. * @param hpcd PCD handle @@ -178,9 +183,9 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; HAL_Delay(50U); if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U) @@ -196,9 +201,9 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { /* start secondary detection to check connection to Charging Downstream Port or Dedicated Charging Port */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN; + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; HAL_Delay(50U); if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET) @@ -285,7 +290,8 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) return HAL_OK; } -#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c index b9f7cc20cb..6b29888126 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @@ -179,10 +179,12 @@ void HAL_PWR_DisableBkUpAccess(void) ================== [..] (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry) functions with (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and + no clear of pending event before. -@@- The Regulator parameter is not used for the STM32F4 family and is kept as parameter just to maintain compatibility with the @@ -204,10 +206,17 @@ void HAL_PWR_DisableBkUpAccess(void) the HAL_PWREx_DisableFlashPowerDown() function. (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry) function with: - (++) Main regulator ON. - (++) Low Power regulator ON. + (++) Regulator: + (+++) Main regulator ON. + (+++) Low Power regulator ON. + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + clear of pending events before. + (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + no clear of pending event before. (+) Exit: Any EXTI Line (Internal or External) configured in Interrupt/Event mode. @@ -372,12 +381,18 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * just to maintain compatibility with the lower power families. * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and + * no clear of pending event before. * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); @@ -393,9 +408,14 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) } else { + if(SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + /* Request Wait For Event */ - __SEV(); - __WFE(); __WFE(); } } @@ -415,8 +435,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @arg PWR_STOPENTRY_WFI : Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE : Enter Stop mode with WFE instruction and + * clear of pending events before. + * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + * no clear of pending event before. * @retval None */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) @@ -439,9 +462,13 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) } else { + if(STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } /* Request Wait For Event */ - __SEV(); - __WFE(); __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c index 74ffe1647c..508f0b6d85 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c @@ -162,7 +162,7 @@ and a pointer to the user callback function. Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. (+) FifoThresholdCallback : callback when the fifo threshold is reached. @@ -178,9 +178,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + reset to the legacy weak (overridden) functions in the HAL_QSPI_Init and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -195,7 +195,7 @@ When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** Workarounds linked to Silicon Limitation *** ==================================================== @@ -2075,7 +2075,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) /** * @brief Register a User QSPI Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hqspi QSPI handle * @param CallbackId ID of the callback to be registered * This parameter can be one of the following values: @@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI /** * @brief Unregister a User QSPI Callback - * QSPI Callback is redirected to the weak (surcharged) predefined callback + * QSPI Callback is redirected to the weak predefined callback * @param hqspi QSPI handle * @param CallbackId ID of the callback to be unregistered * This parameter can be one of the following values: diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c index f187348743..8e494e630e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -479,7 +479,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -517,7 +517,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c index 114e09e058..0250aa722d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -843,6 +843,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -1253,6 +1257,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -1910,6 +1918,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -2140,6 +2152,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -2491,6 +2507,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -2745,6 +2765,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c index bd50438df1..885ce69aa9 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c @@ -52,7 +52,7 @@ [..] Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -66,10 +66,10 @@ [..] By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak (overridden) functions: example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -86,7 +86,7 @@ [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -307,8 +307,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -362,8 +360,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -382,8 +378,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -437,8 +431,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -697,15 +689,16 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; /* RNG clock error interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } - else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; @@ -736,7 +729,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) } /* Check RNG data ready interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) { /* Generate random number once, so disable the IT */ __HAL_RNG_DISABLE_IT(hrng); @@ -768,7 +761,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval random value */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) { return (hrng->RandomNumber); } @@ -830,7 +823,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval HAL state */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) { return hrng->State; } @@ -840,7 +833,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code */ -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ return hrng->ErrorCode; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c index 2d2be66ddc..0365accf00 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -306,38 +306,50 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + if (status == HAL_OK) + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL; + hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; } if (status == HAL_OK) { - hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL; - hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); - hrtc->State = HAL_RTC_STATE_READY; } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - return status; } @@ -522,7 +534,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call /** * @brief Unregisters an RTC Callback - * RTC callabck is redirected to the weak predefined callback + * RTC callback is redirected to the weak predefined callback * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param CallbackID ID of the callback to be unregistered @@ -1293,7 +1305,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ do { - if (count-- == 0U) + count = count - 1U; + if (count == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1329,7 +1342,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ do { - if (count-- == 0U) + count = count - 1U; + if (count == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1529,21 +1543,24 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) { + /* Clear the EXTI's line Flag for RTC Alarm */ + __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); + /* Get the Alarm A interrupt source enable status */ if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U) { /* Get the pending status of the Alarm A Interrupt */ if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U) { + /* Clear the Alarm A interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + /* Alarm A callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmAEventCallback(hrtc); #else HAL_RTC_AlarmAEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Alarm A interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); } } @@ -1553,21 +1570,18 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the pending status of the Alarm B Interrupt */ if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U) { + /* Clear the Alarm B interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + /* Alarm B callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmBEventCallback(hrtc); #else HAL_RTCEx_AlarmBEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Alarm B interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); } } - /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } @@ -1663,8 +1677,8 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { uint32_t tickstart = 0U; - /* Clear RSF flag */ - hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; + /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ + hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK)); /* Get tick */ tickstart = HAL_GetTick(); @@ -1859,7 +1873,7 @@ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) */ uint8_t RTC_ByteToBcd2(uint8_t number) { - uint8_t bcdhigh = 0U; + uint32_t bcdhigh = 0U; while (number >= 10U) { @@ -1877,9 +1891,9 @@ uint8_t RTC_ByteToBcd2(uint8_t number) */ uint8_t RTC_Bcd2ToByte(uint8_t number) { - uint8_t tmp = 0U; - tmp = ((uint8_t)(number & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (number & (uint8_t)0x0F)); + uint32_t tens = 0U; + tens = (((uint32_t)number & 0xF0U) >> 4U) * 10U; + return (uint8_t)(tens + ((uint32_t)number & 0x0FU)); } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c index eb5708fa0d..f6aec5ea18 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -605,6 +605,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { + /* Clear the EXTI's Flag for RTC Timestamp and Tamper */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); + /* Get the Timestamp interrupt source enable status */ if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U) { @@ -618,7 +621,8 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_TimeStampEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the Timestamp interrupt pending bit */ + /* Clear the Timestamp interrupt pending bit after returning from callback + as RTC_TSTR and RTC_TSDR registers are cleared when TSF bit is reset */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); } } @@ -629,15 +633,15 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the pending status of the Tamper 1 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) { + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->Tamper1EventCallback(hrtc); #else HAL_RTCEx_Tamper1EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); } } @@ -648,22 +652,19 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the pending status of the Tamper 2 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) { + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->Tamper2EventCallback(hrtc); #else HAL_RTCEx_Tamper2EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); } } #endif /* RTC_TAMPER2_SUPPORT */ - /* Clear the EXTI's Flag for RTC Timestamp and Tamper */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } @@ -979,7 +980,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ do { - if (count-- == 0U) + count = count - 1U; + if (count == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1006,7 +1008,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ do { - if (count-- == 0U) + count = count - 1U; + if (count == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1130,23 +1133,23 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { + /* Clear the EXTI's line Flag for RTC WakeUpTimer */ + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); + /* Get the pending status of the Wakeup timer Interrupt */ if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) { + /* Clear the Wakeup timer interrupt pending bit */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + /* Wakeup timer callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->WakeUpTimerEventCallback(hrtc); #else HAL_RTCEx_WakeUpTimerEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Wakeup timer interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); } - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c index 19e3748285..e881d252ac 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c @@ -172,7 +172,7 @@ [..] Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. [..] @@ -187,10 +187,10 @@ [..] By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + reset to the legacy weak functions in the HAL_SAI_Init and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -207,7 +207,7 @@ [..] When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim */ @@ -260,7 +260,7 @@ typedef enum * @{ */ static void SAI_FillFifo(SAI_HandleTypeDef *hsai); -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode); +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode); static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); @@ -1243,6 +1243,9 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + SAI_Disable(hsai); + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -1274,9 +1277,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) } } - /* Disable SAI peripheral */ - SAI_Disable(hsai); - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1302,6 +1302,9 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + SAI_Disable(hsai); + /* Check SAI DMA is enabled or not */ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { @@ -1341,9 +1344,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) hsai->Instance->IMR = 0U; hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Disable SAI peripheral */ - SAI_Disable(hsai); - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1909,7 +1909,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval HAL state */ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai) { return hsai->State; } @@ -1920,7 +1920,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) * the configuration information for the specified SAI Block. * @retval SAI Error Code */ -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai) { return hsai->ErrorCode; } @@ -2138,7 +2138,7 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable */ -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode) { uint32_t tmpIT = SAI_IT_OVRUDR; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c index 78a73f8089..2d5e8c4d67 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c @@ -95,7 +95,7 @@ * the configuration information for SAI module. * @retval SAI Clock Input */ -void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) +void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai) { uint32_t tmpregisterGCR; @@ -158,7 +158,7 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval SAI Clock Input */ -uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) +uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai) { /* This variable used to store the SAI_CK_x (value in Hz) */ uint32_t saiclocksource = 0U; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c index 32e54ea152..ebafec7025 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c @@ -696,7 +696,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 } /* Get error state */ +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); @@ -911,7 +915,11 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint } /* Get error state */ +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); @@ -2921,13 +2929,17 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ { return HAL_SD_ERROR_DATA_TIMEOUT; } @@ -2949,7 +2961,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) *pData = SDIO_ReadFIFO(hsd->Instance); pData++; - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3141,13 +3153,17 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) break; } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ { __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c index 31633a2b4e..eb31bdeef8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c @@ -82,15 +82,15 @@ and a pointer to the user callback function. Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : SDRAM MspInit. (+) MspDeInitCallback : SDRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init + reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -105,7 +105,7 @@ When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -132,9 +132,15 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma); static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma); static void SDRAM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions @@ -785,7 +791,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) /** * @brief Register a User SDRAM Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -806,9 +812,6 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsdram); - state = hsdram->State; if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { @@ -851,14 +854,12 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsdram); return status; } /** * @brief Unregister a User SDRAM Callback - * SDRAM Callback is redirected to the weak (surcharged) predefined callback + * SDRAM Callback is redirected to the weak predefined callback * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -874,9 +875,6 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_ HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hsdram); - state = hsdram->State; if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { @@ -925,14 +923,12 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsdram); return status; } /** * @brief Register a User SDRAM Callback for DMA transfers - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1229,6 +1225,9 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) * @} */ +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ /** * @brief DMA SDRAM process complete callback. * @param hdma : DMA handle @@ -1295,6 +1294,9 @@ static void SDRAM_DMAError(DMA_HandleTypeDef *hdma) #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } +/** + * @} + */ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c index e721d80cd6..2295e7ecfd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c @@ -449,6 +449,9 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) /** * @brief Register a User SMARTCARD Callback * To be used instead of the weak predefined callback + * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsc smartcard handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -474,8 +477,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, H return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsc); if (hsc->gState == HAL_SMARTCARD_STATE_READY) { @@ -554,15 +555,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, H status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsc); - return status; } /** * @brief Unregister an SMARTCARD callback * SMARTCARD callback is redirected to the weak predefined callback + * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsc smartcard handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -580,9 +581,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsc); - if (HAL_SMARTCARD_STATE_READY == hsc->gState) { switch (CallbackID) @@ -659,9 +657,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsc); - return status; } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -1780,7 +1775,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc * the configuration information for SMARTCARD module. * @retval HAL state */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc) { uint32_t temp1= 0x00U, temp2 = 0x00U; temp1 = hsc->gState; @@ -1795,7 +1790,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) * the configuration information for the specified SMARTCARD. * @retval SMARTCARD Error Code */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc) { return hsc->ErrorCode; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c index 25c72fda52..f8dbf31f6a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c @@ -181,7 +181,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @addtogroup SMBUS_Private_Define +/** @defgroup SMBUS_Private_Define SMBUS Private Define * @{ */ #define SMBUS_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ @@ -213,6 +213,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); static void SMBUS_ITError(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_Flush_DR(SMBUS_HandleTypeDef *hsmbus); /* Private functions for SMBUS transfer IRQ handler */ static HAL_StatusTypeDef SMBUS_MasterTransmit_TXE(SMBUS_HandleTypeDef *hsmbus); @@ -845,6 +846,17 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +/** + * @brief SMBUS data register flush process. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_Flush_DR(SMBUS_HandleTypeDef *hsmbus) +{ + /* Write a dummy data in DR to clear it */ + hsmbus->Instance->DR = 0x00U; +} + /** * @} */ @@ -1680,6 +1692,12 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) /* Clear AF flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Disable EVT, BUF and ERR interrupts */ + __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR); + + /* Flush data register */ + SMBUS_Flush_DR(hsmbus); } } @@ -2036,7 +2054,7 @@ static HAL_StatusTypeDef SMBUS_MasterTransmit_BTF(SMBUS_HandleTypeDef *hsmbus) /* Generate Stop */ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP); - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->PreviousState = SMBUS_STATE_NONE; hsmbus->State = HAL_SMBUS_STATE_READY; hsmbus->Mode = HAL_SMBUS_MODE_NONE; #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c index da7c302189..3b0ab1fa4d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c @@ -33,10 +33,12 @@ (##) SPDIFRX pins configuration: (+++) Enable the clock for the SPDIFRX GPIOs. (+++) Configure these SPDIFRX pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's). + (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and + HAL_SPDIFRX_ReceiveDataFlow_IT() API's). (+++) Configure the SPDIFRX interrupt priority. (+++) Enable the NVIC SPDIFRX IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's). + (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and + HAL_SPDIFRX_ReceiveControlFlow_DMA() API's). (+++) Declare a DMA handle structure for the reception of the Data Flow channel. (+++) Declare a DMA handle structure for the reception of the Control Flow channel. (+++) Enable the DMAx interface clock. @@ -46,8 +48,8 @@ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA CtrlRx/DataRx channel. - (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits - using HAL_SPDIFRX_Init() function. + (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, + stereo mode and masking of user bits using HAL_SPDIFRX_Init() function. -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process. @@ -90,7 +92,7 @@ ============================================= [..] Below the list of most used macros in SPDIFRX HAL driver. - (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State) + (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDLE State) (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State) (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts @@ -173,8 +175,13 @@ #if defined(STM32F446xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define SPDIFRX_TIMEOUT_VALUE 0xFFFFU - +/** @defgroup SPDIFRX_Private_Defines SPDIFRX Private Defines + * @{ + */ +#define SPDIFRX_TIMEOUT_VALUE 10U +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -888,7 +895,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, { if (count == 0U) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -973,7 +981,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi { if (count == 0U) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -1047,7 +1056,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != + HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1074,7 +1084,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, { if (count == 0U) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -1148,7 +1159,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != + HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1175,7 +1187,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd { if (count == 0U) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -1224,8 +1237,14 @@ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); /* Disable the SPDIFRX DMA channel */ - __HAL_DMA_DISABLE(hspdif->hdmaDrRx); - __HAL_DMA_DISABLE(hspdif->hdmaCsRx); + if (hspdif->hdmaDrRx != NULL) + { + __HAL_DMA_DISABLE(hspdif->hdmaDrRx); + } + if (hspdif->hdmaCsRx != NULL) + { + __HAL_DMA_DISABLE(hspdif->hdmaCsRx); + } /* Disable SPDIFRX peripheral */ __HAL_SPDIFRX_IDLE(hspdif); @@ -1578,8 +1597,8 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) * @param tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t tickstart) +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, + FlagStatus Status, uint32_t Timeout, uint32_t tickstart) { /* Wait until flag is set */ while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) @@ -1589,7 +1608,8 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c index 62d5d65870..341b7ab591 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -856,6 +856,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -885,6 +886,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -914,9 +916,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error: - hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); return errorcode; @@ -939,6 +944,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -952,12 +963,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1023,6 +1028,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1046,6 +1052,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1112,9 +1119,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1213,6 +1223,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { @@ -1246,6 +1265,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1258,6 +1278,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { @@ -1291,6 +1319,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1339,8 +1368,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD __HAL_SPI_CLEAR_OVRFLAG(hspi); } + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + else + { + hspi->State = HAL_SPI_STATE_READY; + } + error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1360,8 +1397,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); if ((pData == NULL) || (Size == 0U)) { @@ -1375,6 +1410,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1414,10 +1452,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1425,8 +1459,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } -error : + /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1442,6 +1480,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1449,14 +1494,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); } - /* Process Locked */ - __HAL_LOCK(hspi); - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -1464,6 +1501,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1503,9 +1543,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current process unlock */ @@ -1517,9 +1554,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1541,9 +1581,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; @@ -1561,6 +1598,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p goto error; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1596,8 +1636,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p } #endif /* USE_SPI_CRC */ - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1606,9 +1644,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1695,7 +1736,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1735,6 +1775,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1749,12 +1795,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1810,7 +1850,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1932,7 +1971,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1954,7 +1992,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -3595,6 +3632,13 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + /* Timeout in µs */ __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c index ef2eaf092e..178843732e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c @@ -83,15 +83,15 @@ and a pointer to the user callback function. Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init + reset to the legacy weak (overridden) functions in the HAL_SRAM_Init and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -106,7 +106,7 @@ When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -133,9 +133,15 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); static void SRAM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ @@ -731,7 +737,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /** * @brief Register a User SRAM Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -751,9 +757,6 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsram); - state = hsram->State; if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) { @@ -777,14 +780,12 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsram); return status; } /** * @brief Unregister a User SRAM Callback - * SRAM Callback is redirected to the weak (surcharged) predefined callback + * SRAM Callback is redirected to the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -799,9 +800,6 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hsram); - state = hsram->State; if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { @@ -847,14 +845,12 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsram); return status; } /** * @brief Register a User SRAM Callback for DMA transfers - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1018,7 +1014,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) * the configuration information for SRAM module. * @retval HAL state */ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) { return hsram->State; } @@ -1031,6 +1027,10 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) * @} */ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ + /** * @brief DMA SRAM process complete callback. * @param hdma : DMA handle @@ -1097,6 +1097,10 @@ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } +/** + * @} + */ + /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c index 1ca1781e9f..d5978cca3e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c @@ -204,9 +204,9 @@ all interrupt callbacks are set to the corresponding weak functions: /** @addtogroup TIM_Private_Functions * @{ */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); @@ -222,7 +222,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); + const TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ @@ -275,6 +275,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -522,7 +523,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; @@ -536,7 +537,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else if (htim->State == HAL_TIM_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -658,6 +659,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1043,7 +1045,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1058,7 +1061,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1321,6 +1324,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1706,7 +1710,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1721,7 +1726,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1983,6 +1988,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -2376,7 +2382,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -2632,6 +2638,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -3009,7 +3016,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; @@ -3035,6 +3042,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) { @@ -3544,7 +3552,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData1 == NULL) && (Length > 0U)) + if ((pData1 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3569,7 +3577,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData2 == NULL) && (Length > 0U)) + if ((pData2 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3598,7 +3606,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) { return HAL_ERROR; } @@ -3814,13 +3822,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3848,11 +3859,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3878,11 +3889,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3908,11 +3919,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3938,11 +3949,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3951,11 +3962,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else @@ -3964,11 +3975,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -3977,11 +3988,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM commutation event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else @@ -4028,7 +4039,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4106,7 +4117,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4206,7 +4217,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4468,7 +4479,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status; @@ -4520,7 +4532,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; @@ -5160,7 +5172,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -5289,7 +5301,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -5475,7 +5487,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5516,7 +5528,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5558,7 +5570,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; @@ -5832,8 +5844,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call { return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { @@ -6025,9 +6035,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } @@ -6070,9 +6077,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(htim); - if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) @@ -6304,9 +6308,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -6335,7 +6336,7 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @param htim TIM Base handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6345,7 +6346,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Output Compare handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6355,7 +6356,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6365,7 +6366,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) * @param htim TIM IC handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6375,7 +6376,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM OPM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6385,7 +6386,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Encoder Interface handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6395,7 +6396,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval Active channel */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) { return htim->Channel; } @@ -6413,7 +6414,7 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -6430,7 +6431,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, ui * @param htim TIM handle * @retval DMA burst state */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -6773,7 +6774,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) * @param Structure TIM Base configuration structure * @retval None */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; @@ -6813,6 +6814,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } } /** @@ -6821,17 +6829,18 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -6896,17 +6905,18 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -6935,7 +6945,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -6972,17 +6981,18 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7046,17 +7056,18 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7107,7 +7118,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -7247,9 +7258,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) @@ -7337,9 +7348,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; @@ -7376,9 +7387,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; @@ -7420,9 +7431,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; @@ -7468,9 +7479,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c index 092175f562..889f8fb9a7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c @@ -135,7 +135,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; @@ -151,6 +151,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -501,7 +502,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -834,7 +835,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -866,7 +867,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -881,7 +883,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1079,17 +1081,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1315,7 +1306,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1347,7 +1338,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1362,7 +1354,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1960,7 +1952,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) + const TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -2021,7 +2013,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; @@ -2098,7 +2090,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { - /* Check parameters */ assert_param(IS_TIM_REMAP(htim->Instance, Remap)); @@ -2149,7 +2140,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2163,7 +2154,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2178,7 +2169,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2215,7 +2206,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) * @param htim TIM Hall Sensor handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -2230,7 +2221,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_3: TIM Channel 3 * @retval TIM Complementary channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -2329,15 +2320,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } else { /* nothing to do */ @@ -2406,13 +2388,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha { uint32_t tmp; - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ } /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c index e7f0ace40a..e45f04c7af 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c @@ -6,7 +6,7 @@ * * This file override the native HAL time base functions (defined as weak) * to use the RTC ALARM for time base generation: - * + Intializes the RTC peripheral to increment the seconds registers each 1ms + * + Initializes the RTC peripheral to increment the seconds registers each 1ms * + The alarm is configured to assert an interrupt when the RTC reaches 1ms * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00 * + HSE (default), LSE or LSI can be selected as RTC clock source @@ -102,19 +102,19 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) HAL_StatusTypeDef status; #ifdef RTC_CLOCK_SOURCE_LSE - /* Configue LSE as RTC clock soucre */ + /* Configure LSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; #elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configue LSI as RTC clock soucre */ + /* Configure LSI as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSIState = RCC_LSI_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; #elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configue HSE as RTC clock soucre */ + /* Configure HSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c index a9cff87d24..897db4e612 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c @@ -6,7 +6,7 @@ * * This file overrides the native HAL time base functions (defined as weak) * to use the RTC WAKEUP for the time base generation: - * + Intializes the RTC peripheral and configures the wakeup timer to be + * + Initializes the RTC peripheral and configures the wakeup timer to be * incremented each 1ms * + The wakeup feature is configured to assert an interrupt each 1ms * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback @@ -109,19 +109,19 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) HAL_StatusTypeDef status; #ifdef RTC_CLOCK_SOURCE_LSE - /* Configue LSE as RTC clock soucre */ + /* Configure LSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; #elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configue LSI as RTC clock soucre */ + /* Configure LSI as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSIState = RCC_LSI_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; #elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configue HSE as RTC clock soucre */ + /* Configure HSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c index 8e18d9744c..098acf9364 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c @@ -6,7 +6,7 @@ * * This file overrides the native HAL time base functions (defined as weak) * the TIM time base: - * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms + * + Initializes the TIM peripheral generate a Period elapsed Event each 1ms * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms * ****************************************************************************** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c index 36b7317a61..33a5f002c8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -420,6 +420,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -489,6 +490,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -569,6 +571,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -652,6 +655,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -694,6 +698,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Process Unlock */ __HAL_UNLOCK(huart); @@ -735,6 +740,8 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Register a User UART Callback * To be used instead of the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), + * HAL_MultiProcessor_Init() to register callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -763,8 +770,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_READY) { @@ -849,15 +854,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } /** * @brief Unregister an UART Callback * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() to un-register callbacks for HAL_UART_MSPINIT_CB_ID + * and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -877,9 +882,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - if (HAL_UART_STATE_READY == huart->gState) { switch (CallbackID) @@ -963,9 +965,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -1147,9 +1146,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; @@ -1171,13 +1167,12 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD pdata16bits = NULL; } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1195,6 +1190,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } @@ -1235,9 +1232,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1260,14 +1254,13 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Check the remain data to be received */ while (huart->RxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { + huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1322,9 +1315,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1332,9 +1322,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); @@ -1367,9 +1354,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1404,9 +1388,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1433,9 +1414,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -1470,9 +1448,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1494,9 +1469,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { uint32_t dmarequest = 0x00U; - /* Process Locked */ - __HAL_LOCK(huart); - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) { @@ -1515,9 +1487,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1529,8 +1498,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - /* Process Locked */ - __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_BUSY_TX) { @@ -1554,9 +1521,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1636,11 +1600,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -1660,8 +1623,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* Initialize output number of received elements */ *RxLen = 0U; @@ -1678,6 +1639,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p /* If Set, and data has already been received, this means Idle Event is valid : End reception */ if (*RxLen > 0U) { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; huart->RxState = HAL_UART_STATE_READY; return HAL_OK; @@ -1760,10 +1722,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_IT(huart, pData, Size); @@ -1821,10 +1782,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_DMA(huart, pData, Size); @@ -1854,6 +1814,36 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ } } +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (returned value will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return(huart->RxEventType); +} + /** * @brief Abort ongoing transfers (blocking mode). * @param huart UART handle. @@ -2526,6 +2516,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); @@ -2556,6 +2551,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); @@ -2791,6 +2791,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -2818,6 +2819,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -2923,7 +2925,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) * the configuration information for the specified UART module. * @retval HAL state */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { uint32_t temp1 = 0x00U, temp2 = 0x00U; temp1 = huart->gState; @@ -2938,7 +2940,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval UART Error Code */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { return huart->ErrorCode; } @@ -3040,6 +3042,7 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) { @@ -3063,6 +3066,10 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } } + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3098,6 +3105,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3180,19 +3191,31 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; + } - /* Process Unlocked */ - __HAL_UNLOCK(huart); + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_OREFLAG(huart); - return HAL_TIMEOUT; + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } } } } @@ -3219,9 +3242,6 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - if (huart->Init.Parity != UART_PARITY_NONE) { /* Enable the UART Parity Error Interrupt */ @@ -3277,9 +3297,6 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); - /* Process Unlocked */ - __HAL_UNLOCK(huart); - if (huart->Init.Parity != UART_PARITY_NONE) { /* Enable the UART Parity Error Interrupt */ @@ -3619,6 +3636,9 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c index 945a646959..50c1b817dc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c @@ -427,6 +427,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) /** * @brief Register a User USART Callback * To be used instead of the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -454,8 +456,6 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(husart); if (husart->State == HAL_USART_STATE_READY) { @@ -536,15 +536,14 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } /** * @brief Unregister an USART Callback * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -563,9 +562,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(husart); - if (husart->State == HAL_USART_STATE_READY) { switch (CallbackID) @@ -645,9 +641,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -2075,7 +2068,7 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) * the configuration information for the specified USART module. * @retval HAL state */ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) { return husart->State; } @@ -2086,11 +2079,14 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART Error Code */ -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) { return husart->ErrorCode; } +/** + * @} + */ /** * @} */ @@ -2819,10 +2815,6 @@ static void USART_SetConfig(USART_HandleTypeDef *husart) } } -/** - * @} - */ - /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c index 2d6e082864..cdb750fe6f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c @@ -22,9 +22,9 @@ #include "stm32f4xx_ll_bus.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32F4xx_LL_Driver @@ -326,7 +326,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni #if defined(ADC_MULTIMODE_SUPPORT) assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); @@ -338,7 +338,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ - if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ @@ -350,16 +350,16 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* - Set ADC multimode DMA transfer */ /* - Set ADC multimode: delay between 2 sampling phases */ #if defined(ADC_MULTIMODE_SUPPORT) - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_ADCPRE + ADC_CCR_ADCPRE | ADC_CCR_MULTI | ADC_CCR_DMA | ADC_CCR_DDS | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | ADC_CommonInitStruct->Multimode | ADC_CommonInitStruct->MultiDMATransfer | ADC_CommonInitStruct->MultiTwoSamplingDelay @@ -368,13 +368,13 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni else { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_ADCPRE + ADC_CCR_ADCPRE | ADC_CCR_MULTI | ADC_CCR_DMA | ADC_CCR_DDS | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } @@ -408,7 +408,7 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) #if defined(ADC_MULTIMODE_SUPPORT) /* Set fields of ADC multimode */ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; - ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; + ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; #endif /* ADC_MULTIMODE_SUPPORT */ } @@ -431,7 +431,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) assert_param(IS_ADC_ALL_INSTANCE(ADCx)); /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1UL) + if (LL_ADC_IsEnabled(ADCx) == 1UL) { /* Set ADC group regular trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ @@ -449,48 +449,48 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Check whether ADC state is compliant with expected state */ /* (hardware requirements of bits state to reset registers below) */ - if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) + if (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) { /* ========== Reset ADC registers ========== */ /* Reset register SR */ CLEAR_BIT(ADCx->SR, - ( LL_ADC_FLAG_STRT + (LL_ADC_FLAG_STRT | LL_ADC_FLAG_JSTRT | LL_ADC_FLAG_EOCS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_JEOS - | LL_ADC_FLAG_AWD1 ) + | LL_ADC_FLAG_AWD1) ); /* Reset register CR1 */ CLEAR_BIT(ADCx->CR1, - ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN + (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE - | ADC_CR1_AWDCH ) + | ADC_CR1_AWDCH) ); /* Reset register CR2 */ CLEAR_BIT(ADCx->CR2, - ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL + (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DMA - | ADC_CR2_CONT | ADC_CR2_ADON ) + | ADC_CR2_CONT | ADC_CR2_ADON) ); /* Reset register SMPR1 */ CLEAR_BIT(ADCx->SMPR1, - ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 + (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) ); /* Reset register SMPR2 */ CLEAR_BIT(ADCx->SMPR2, - ( ADC_SMPR2_SMP9 + (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) @@ -512,28 +512,28 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register SQR1 */ CLEAR_BIT(ADCx->SQR1, - ( ADC_SQR1_L + (ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) ); /* Reset register SQR2 */ CLEAR_BIT(ADCx->SQR2, - ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 + (ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) ); /* Reset register SQR3 */ CLEAR_BIT(ADCx->SQR3, - ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 + (ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) ); /* Reset register JSQR */ CLEAR_BIT(ADCx->JSQR, - ( ADC_JSQR_JL + (ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 - | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) ); /* Reset register DR */ @@ -595,24 +595,24 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC instance */ /* - Set ADC data resolution */ /* - Set ADC conversion data alignment */ MODIFY_REG(ADCx->CR1, - ADC_CR1_RES + ADC_CR1_RES | ADC_CR1_SCAN - , - ADC_InitStruct->Resolution + , + ADC_InitStruct->Resolution | ADC_InitStruct->SequencersScanMode ); MODIFY_REG(ADCx->CR2, - ADC_CR2_ALIGN - , - ADC_InitStruct->DataAlignment + ADC_CR2_ALIGN + , + ADC_InitStruct->DataAlignment ); } @@ -685,7 +685,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); } @@ -699,7 +699,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group regular */ @@ -712,33 +712,33 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* Note: On this STM32 series, ADC trigger edge is set when starting */ /* ADC conversion. */ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CR1, - ADC_CR1_DISCEN + ADC_CR1_DISCEN | ADC_CR1_DISCNUM - , - ADC_REG_InitStruct->SequencerDiscont + , + ADC_REG_InitStruct->SequencerDiscont ); } else { MODIFY_REG(ADCx->CR1, - ADC_CR1_DISCEN + ADC_CR1_DISCEN | ADC_CR1_DISCNUM - , - LL_ADC_REG_SEQ_DISCONT_DISABLE + , + LL_ADC_REG_SEQ_DISCONT_DISABLE ); } MODIFY_REG(ADCx->CR2, - ADC_CR2_EXTSEL + ADC_CR2_EXTSEL | ADC_CR2_EXTEN | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS - , - (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) + , + (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DMATransfer ); @@ -820,7 +820,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); } @@ -828,7 +828,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group injected */ @@ -840,32 +840,32 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* Note: On this STM32 series, ADC trigger edge is set when starting */ /* ADC conversion. */ /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CR1, - ADC_CR1_JDISCEN + ADC_CR1_JDISCEN | ADC_CR1_JAUTO - , - ADC_INJ_InitStruct->SequencerDiscont + , + ADC_INJ_InitStruct->SequencerDiscont | ADC_INJ_InitStruct->TrigAuto ); } else { MODIFY_REG(ADCx->CR1, - ADC_CR1_JDISCEN + ADC_CR1_JDISCEN | ADC_CR1_JAUTO - , - LL_ADC_REG_SEQ_DISCONT_DISABLE + , + LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_INJ_InitStruct->TrigAuto ); } MODIFY_REG(ADCx->CR2, - ADC_CR2_JEXTSEL + ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN - , - (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) + , + (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) ); /* Note: Hardware constraint (refer to description of this function): */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c index 113879301f..b64b4761ba 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c @@ -59,7 +59,7 @@ * - SUCCESS: CRC registers are de-initialized * - ERROR: CRC registers are not de-initialized */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c index 4514d9186f..77ce3587c7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c @@ -47,19 +47,16 @@ */ #if defined(DAC_CHANNEL2_SUPPORT) #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ - ( \ - ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ ) #else #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ - ( \ - ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ - ) + (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)) #endif /* DAC_CHANNEL2_SUPPORT */ #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ - ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ @@ -70,45 +67,45 @@ ) #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ - ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ ) \ ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ - ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) /** @@ -135,7 +132,7 @@ * - SUCCESS: DAC registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) +ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx) { /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); @@ -170,14 +167,14 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: DAC registers are initialized * - ERROR: DAC registers are not initialized */ -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; @@ -277,4 +274,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c index 1bdf9dea7a..2431213940 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c @@ -61,7 +61,8 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ -#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) +#if defined(HAL_NOR_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -1449,7 +1450,7 @@ HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or * FMC_SDRAM_POWER_DOWN_MODE. */ -uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank) { uint32_t tmpreg; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c index 04966ea018..94718b7b24 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c @@ -46,22 +46,22 @@ */ #define IS_LL_FMPI2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_FMPI2C_MODE_I2C) || \ - ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_HOST) || \ - ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE) || \ - ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE_ARP)) + ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_HOST) || \ + ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE) || \ + ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE_ARP)) #define IS_LL_FMPI2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_FMPI2C_ANALOGFILTER_ENABLE) || \ - ((__VALUE__) == LL_FMPI2C_ANALOGFILTER_DISABLE)) + ((__VALUE__) == LL_FMPI2C_ANALOGFILTER_DISABLE)) #define IS_LL_FMPI2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) #define IS_LL_FMPI2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) #define IS_LL_FMPI2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_FMPI2C_ACK) || \ - ((__VALUE__) == LL_FMPI2C_NACK)) + ((__VALUE__) == LL_FMPI2C_NACK)) #define IS_LL_FMPI2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_FMPI2C_OWNADDRESS1_7BIT) || \ - ((__VALUE__) == LL_FMPI2C_OWNADDRESS1_10BIT)) + ((__VALUE__) == LL_FMPI2C_OWNADDRESS1_10BIT)) /** * @} */ @@ -84,7 +84,7 @@ * - SUCCESS: FMPI2C registers are de-initialized * - ERROR: FMPI2C registers are not de-initialized */ -ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx) +ErrorStatus LL_FMPI2C_DeInit(const FMPI2C_TypeDef *FMPI2Cx) { ErrorStatus status = SUCCESS; @@ -115,7 +115,7 @@ ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx) * - SUCCESS: FMPI2C registers are initialized * - ERROR: Not applicable */ -ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct) +ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, const LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct) { /* Check the FMPI2C Instance FMPI2Cx */ assert_param(IS_FMPI2C_ALL_INSTANCE(FMPI2Cx)); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c index 8172871fa6..ff79111818 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c @@ -59,7 +59,8 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ -#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \ + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FSMC_LL FSMC Low Layer * @brief FSMC driver modules diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c index 9336b5ca82..bb75125d06 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c @@ -92,7 +92,7 @@ * - SUCCESS: LPTIMx registers are de-initialized * - ERROR: invalid LPTIMx instance */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx) +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx) { ErrorStatus result = SUCCESS; @@ -137,7 +137,7 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) * - SUCCESS: LPTIMx instance has been initialized * - ERROR: LPTIMx instance hasn't been initialized */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { ErrorStatus result = SUCCESS; /* Check the parameters */ @@ -259,8 +259,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c index 333d63ca45..fc1ea50baa 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c @@ -59,7 +59,7 @@ * - SUCCESS: RNG registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) { ErrorStatus status = SUCCESS; @@ -77,7 +77,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) /* Enable RNG reset state */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); - /* Release RNG from reset state */ + /* Release RNG from reset state */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); #endif /* !RCC_AHB2_SUPPORT */ } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c index f3ee3ce016..4d106da398 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c index b272b62d95..49217db9fd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c @@ -137,14 +137,14 @@ /** @defgroup TIM_LL_Private_Functions TIM Private Functions * @{ */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); /** * @} */ @@ -165,7 +165,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: invalid TIMx instance */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) { ErrorStatus result = SUCCESS; @@ -301,7 +301,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) { uint32_t tmpcr1; @@ -380,7 +380,7 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) { ErrorStatus result = ERROR; @@ -435,7 +435,7 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) { ErrorStatus result = ERROR; @@ -489,7 +489,7 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -582,7 +582,7 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { uint32_t tmpcr2; uint32_t tmpccmr1; @@ -687,7 +687,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; @@ -711,7 +711,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); /* Set TIMx_BDTR */ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); @@ -738,7 +737,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -749,8 +748,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -778,8 +775,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -817,7 +816,7 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -828,8 +827,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -857,8 +854,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -896,7 +895,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -907,8 +906,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -936,8 +933,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -975,7 +974,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -986,8 +985,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1015,7 +1012,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the Output Idle state */ @@ -1037,7 +1033,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni return SUCCESS; } - /** * @brief Configure the TIMx input channel 1. * @param TIMx Timer Instance @@ -1046,7 +1041,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); @@ -1079,7 +1074,7 @@ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); @@ -1112,7 +1107,7 @@ static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); @@ -1145,7 +1140,7 @@ static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); @@ -1162,7 +1157,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c index 3cf68e363c..5b1ffa838e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c @@ -121,7 +121,7 @@ * - SUCCESS: USART registers are de-initialized * - ERROR: USART registers are not de-initialized */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) { ErrorStatus status = SUCCESS; @@ -245,7 +245,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * - SUCCESS: USART registers are initialized according to USART_InitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; @@ -409,7 +409,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c index 1df5fcf1b6..2570d422b8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -27,7 +27,7 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. (#) Call USB_CoreInit() API to initialize the USB Core peripheral. @@ -258,9 +258,9 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy do { - HAL_Delay(1U); - ms++; - } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); } else if (mode == USB_DEVICE_MODE) { @@ -268,16 +268,16 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy do { - HAL_Delay(1U); - ms++; - } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); } else { return HAL_ERROR; } - if (ms == 50U) + if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) { return HAL_ERROR; } @@ -304,7 +304,9 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf USBx->DIEPTXF[i] = 0U; } -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) { @@ -341,14 +343,13 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; } -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; - /* Device mode configuration */ - USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - if (cfg.phy_itface == USB_OTG_ULPI_PHY) { if (cfg.speed == USBD_HS_SPEED) @@ -478,7 +479,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -492,7 +493,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -515,7 +516,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -529,7 +530,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -549,7 +550,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -565,7 +566,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t speed; @@ -594,7 +595,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -632,7 +633,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -671,7 +672,7 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -718,7 +719,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -785,8 +786,21 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); @@ -856,18 +870,34 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - if (ep->xfer_len == 0U) + if (epnum == 0U) { - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); } else { - pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); - ep->xfer_size = ep->maxpacket * pktcnt; + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } } if (dma == 1U) @@ -896,106 +926,6 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef return HAL_OK; } -/** - * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - /* IN endpoint */ - if (ep->is_in == 1U) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - } - - if (dma == 1U) - { - if ((uint32_t)ep->dma_addr != 0U) - { - USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - } - else - { - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0U) - { - USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); - } - } - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len > 0U) - { - ep->xfer_len = ep->maxpacket; - } - - /* Store transfer size, for EP0 this is equal to endpoint max packet size */ - ep->xfer_size = ep->maxpacket; - - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); - - if (dma == 1U) - { - if ((uint32_t)ep->xfer_buff != 0U) - { - USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); - } - } - - /* EP enable */ - USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - - return HAL_OK; -} - /** * @brief USB_EPStoptXfer Stop transfer on an EP @@ -1003,7 +933,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { __IO uint32_t count = 0U; HAL_StatusTypeDef ret = HAL_OK; @@ -1067,7 +997,7 @@ HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * 1 : DMA feature used * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1098,7 +1028,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, * @param len Number of bytes to read * @retval pointer to destination buffer */ -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t *pDest = dest; @@ -1140,7 +1070,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -1171,7 +1101,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -1241,7 +1171,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1256,7 +1186,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t addres * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1273,7 +1203,7 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1288,9 +1218,9 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Global Interrupt status */ -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { uint32_t tmpreg; @@ -1300,12 +1230,29 @@ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) return tmpreg; } +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + /** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Device OUT EP interrupt status */ -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1319,9 +1266,9 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Device IN EP interrupt status */ -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1339,7 +1286,7 @@ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1357,7 +1304,7 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1380,7 +1327,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) */ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) { - USBx->GINTSTS |= interrupt; + USBx->GINTSTS &= interrupt; } /** @@ -1391,7 +1338,7 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * 0 : Host * 1 : Device */ -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { return ((USBx->GINTSTS) & 0x1U); } @@ -1401,7 +1348,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1423,10 +1370,10 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) * @param psetup pointer to setup packet * @retval HAL status */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); if (gSNPSiD > USB_OTG_CORE_ID_300A) { @@ -1465,7 +1412,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1479,7 +1426,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1505,7 +1452,9 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /* Disable HW VBUS sensing */ USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); #else @@ -1516,13 +1465,17 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \ + || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /* Disable Battery chargin detector */ USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); -#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ - if ((USBx->CID & (0x1U << 8)) != 0U) + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) { if (cfg.speed == USBH_FSLS_SPEED) { @@ -1555,7 +1508,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Clear all pending HC Interrupts */ for (i = 0U; i < cfg.Host_channels; i++) { - USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; USBx_HC(i)->HCINTMSK = 0U; } @@ -1563,9 +1516,9 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GINTMSK = 0U; /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFFU; - - if ((USBx->CID & (0x1U << 8)) != 0U) + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) { /* set Rx FIFO size */ USBx->GRXFSIZ = 0x200U; @@ -1573,6 +1526,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); } else +#endif /* defined (USB_OTG_HS) */ { /* set Rx FIFO size */ USBx->GRXFSIZ = 0x80U; @@ -1604,7 +1558,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1613,15 +1567,15 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) if (freq == HCFG_48_MHZ) { - USBx_HOST->HFIR = 48000U; + USBx_HOST->HFIR = HFIR_48_MHZ; } else if (freq == HCFG_6_MHZ) { - USBx_HOST->HFIR = 6000U; + USBx_HOST->HFIR = HFIR_6_MHZ; } else { - /* ... */ + return HAL_ERROR; } return HAL_OK; @@ -1634,7 +1588,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) * @note (1)The application must wait at least 10 ms * before clearing the reset bit. */ -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1661,7 +1615,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) * 1 : Activate VBUS * @retval HAL status */ -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) { uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0 = 0U; @@ -1691,7 +1645,7 @@ HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) * @arg HCD_SPEED_FULL: Full speed mode * @arg HCD_SPEED_LOW: Low speed mode */ -uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0 = 0U; @@ -1705,7 +1659,7 @@ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval current frame number */ -uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1747,7 +1701,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint32_t HostCoreSpeed; /* Clear old interrupt conditions for this host channel. */ - USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; /* Enable channel interrupts required for this transfer. */ switch (ep_type) @@ -1767,11 +1721,13 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, } else { - if ((USBx->CID & (0x1U << 8)) != 0U) +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) { USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM; } +#endif /* defined (USB_OTG_HS) */ } break; @@ -1808,6 +1764,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, break; } + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + /* Enable host channel Halt interrupt */ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; @@ -1842,7 +1801,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | - ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) { @@ -1870,53 +1830,118 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe uint8_t is_oddframe; uint16_t len_words; uint16_t num_packets; - uint16_t max_hc_pkt_count = 256U; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; - if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) { - /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ - if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK))) + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if (dma == 1U) { - USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | - USB_OTG_HCINTMSK_ACKM | - USB_OTG_HCINTMSK_NAKM); - } + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) + { - if ((dma == 0U) && (hc->do_ping == 1U)) + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + } + else { - (void)USB_DoPing(USBx, hc->ch_num); - return HAL_OK; + if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) + { + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } } - } +#endif /* defined (USB_OTG_HS) */ - /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0U) + if (hc->do_ssplit == 1U) { - num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + /* Set number of packet to 1 for Split transaction */ + num_packets = 1U; - if (num_packets > max_hc_pkt_count) + if (hc->ep_is_in != 0U) { - num_packets = max_hc_pkt_count; hc->XferSize = (uint32_t)num_packets * hc->max_packet; } - } - else - { - num_packets = 1U; - } + else + { + if (hc->ep_type == EP_TYPE_ISOC) + { + if (hc->xfer_len > ISO_SPLT_MPS) + { + /* Isochrone Max Packet Size for Split mode */ + hc->XferSize = hc->max_packet; + hc->xfer_len = hc->XferSize; - /* - * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of - * max_packet size. - */ - if (hc->ep_is_in != 0U) - { - hc->XferSize = (uint32_t)num_packets * hc->max_packet; + if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_MIDDLE; + } + else + { + hc->iso_splt_xactPos = HCSPLT_BEGIN; + } + } + else + { + hc->XferSize = hc->xfer_len; + + if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_FULL; + } + else + { + hc->iso_splt_xactPos = HCSPLT_END; + } + } + } + else + { + if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + } } else { - hc->XferSize = hc->xfer_len; + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } } /* Initialize the HCTSIZn register */ @@ -1934,6 +1959,65 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + if (hc->do_ssplit == 1U) + { + /* Set Hub start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | + (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; + + /* unmask ack & nyet for IN/OUT transactions */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NYET); + + if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + } + + if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && + (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + } + + /* Position management for iso out transaction on split mode */ + if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) + { + /* Set data payload position */ + switch (hc->iso_splt_xactPos) + { + case HCSPLT_BEGIN: + /* First data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; + break; + + case HCSPLT_MIDDLE: + /* Middle data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; + break; + + case HCSPLT_END: + /* End data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; + break; + + case HCSPLT_FULL: + /* Entire data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; + break; + + default: + break; + } + } + } + else + { + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + } + /* Set host channel enable */ tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; @@ -1955,7 +2039,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe return HAL_OK; } - if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) { switch (hc->ep_type) { @@ -2001,7 +2085,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe * @param USBx Selected device * @retval HAL state */ -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2015,16 +2099,21 @@ uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t hcnum = (uint32_t)hc_num; __IO uint32_t count = 0U; uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; + + /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. + At the end of the next uframe/frame (in the worst case), the core generates a channel halted + and disables the channel automatically. */ - if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && - (ChannelEna == 0U)) + if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && + ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) { return HAL_OK; } @@ -2055,6 +2144,10 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } } else { @@ -2090,7 +2183,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t chnum = (uint32_t)ch_num; @@ -2166,8 +2259,8 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFFU; - USBx->GINTSTS = 0xFFFFFFFFU; + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; (void)USB_EnableGlobalInt(USBx); @@ -2179,7 +2272,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2197,7 +2290,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2208,7 +2301,6 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) } #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - /** * @} */ diff --git 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system/Drivers/STM32F4xx_HAL_Driver/_htmresc/mini-st.css rename to system/Drivers/STM32F4xx_HAL_Driver/_htmresc/mini-st_2020.css index 3caf11c32e..db8b406aa4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/_htmresc/mini-st.css +++ b/system/Drivers/STM32F4xx_HAL_Driver/_htmresc/mini-st_2020.css @@ -1,39 +1,39 @@ @charset "UTF-8"; /* - Flavor name: Default (mini-default) - Author: Angelos Chalaris (chalarangelo@gmail.com) - Maintainers: Angelos Chalaris - mini.css version: v3.0.0-alpha.3 + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 */ /* Browsers resets and base typography. */ /* Core module CSS variable definitions */ :root { - --fore-color: #111; - --secondary-fore-color: #444; - --back-color: #f8f8f8; - --secondary-back-color: #f0f0f0; - --blockquote-color: #f57c00; - --pre-color: #1565c0; - --border-color: #aaa; - --secondary-border-color: #ddd; - --heading-ratio: 1.19; + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; --universal-margin: 0.5rem; - --universal-padding: 0.125rem; - --universal-border-radius: 0.125rem; - --a-link-color: #0277bd; - --a-visited-color: #01579b; } + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } html { - font-size: 14px; } + font-size: 13.5px; } a, b, del, em, i, ins, q, span, strong, u { font-size: 1em; } html, * { - font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; - line-height: 1.4; + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; -webkit-text-size-adjust: 100%; } * { @@ -42,7 +42,10 @@ html, * { body { margin: 0; color: var(--fore-color); - background: var(--back-color); } + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } details { display: block; } @@ -62,9 +65,9 @@ img { height: auto; } h1, h2, h3, h4, h5, h6 { - line-height: 1.2; + line-height: 1.25; margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 500; } + font-weight: 400; } h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { color: var(--secondary-fore-color); display: block; @@ -74,21 +77,15 @@ h1 { font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); - background: var(--mark-back-color); - font-weight: 600; - padding: 0.1em 0.5em 0.2em 0.5em; - color: var(--mark-fore-color); } - + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } h3 { - font-size: calc(1rem * var(--heading-ratio)); - padding-left: calc(2 * var(--universal-margin)); - /* background: var(--border-color); */ - } + font-size: calc(1rem * var(--heading-ratio) ); } h4 { - font-size: 1rem;); - padding-left: calc(4 * var(--universal-margin)); } + font-size: calc(1rem * var(--heading-ratio)); } h5 { font-size: 1rem; } @@ -101,7 +98,7 @@ p { ol, ul { margin: var(--universal-margin); - padding-left: calc(6 * var(--universal-margin)); } + padding-left: calc(3 * var(--universal-margin)); } b, strong { font-weight: 700; } @@ -111,7 +108,7 @@ hr { border: 0; line-height: 1.25em; margin: var(--universal-margin); - height: 0.0625rem; + height: 0.0714285714rem; background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } blockquote { @@ -121,16 +118,16 @@ blockquote { color: var(--secondary-fore-color); margin: var(--universal-margin); padding: calc(3 * var(--universal-padding)); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.375rem solid var(--blockquote-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } blockquote:before { position: absolute; top: calc(0rem - var(--universal-padding)); left: 0; font-family: sans-serif; - font-size: 3rem; - font-weight: 700; + font-size: 2rem; + font-weight: 800; content: "\201c"; color: var(--blockquote-color); } blockquote[cite]:after { @@ -160,8 +157,8 @@ pre { background: var(--secondary-back-color); padding: calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.25rem solid var(--pre-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } sup, sub, code, kbd { @@ -204,7 +201,8 @@ a { box-sizing: border-box; display: flex; flex: 0 1 auto; - flex-flow: row wrap; } + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } .col-sm, [class^='col-sm-'], @@ -565,9 +563,9 @@ a { order: 999; } } /* Card component CSS variable definitions */ :root { - --card-back-color: #f8f8f8; - --card-fore-color: #111; - --card-border-color: #ddd; } + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } .card { display: flex; @@ -578,7 +576,7 @@ a { width: 100%; background: var(--card-back-color); color: var(--card-fore-color); - border: 0.0625rem solid var(--card-border-color); + border: 0.0714285714rem solid var(--card-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); overflow: hidden; } @@ -592,7 +590,7 @@ a { margin: 0; border: 0; border-radius: 0; - border-bottom: 0.0625rem solid var(--card-border-color); + border-bottom: 0.0714285714rem solid var(--card-border-color); padding: var(--universal-padding); width: 100%; } .card > .sectione.media { @@ -617,17 +615,18 @@ a { width: auto; } .card.warning { -/* --card-back-color: #ffca28; */ --card-back-color: #e5b8b7; - --card-border-color: #e8b825; } + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } .card.error { - --card-back-color: #b71c1c; - --card-fore-color: #f8f8f8; - --card-border-color: #a71a1a; } + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } .card > .sectione.dark { - --card-back-color: #e0e0e0; } + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } .card > .sectione.double-padded { padding: calc(1.5 * var(--universal-padding)); } @@ -637,12 +636,12 @@ a { */ /* Input_control module CSS variable definitions */ :root { - --form-back-color: #f0f0f0; - --form-fore-color: #111; - --form-border-color: #ddd; - --input-back-color: #f8f8f8; - --input-fore-color: #111; - --input-border-color: #ddd; + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; --input-focus-color: #0288d1; --input-invalid-color: #d32f2f; --button-back-color: #e2e2e2; @@ -655,13 +654,13 @@ a { form { background: var(--form-back-color); color: var(--form-fore-color); - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); padding: calc(2 * var(--universal-padding)) var(--universal-padding); } fieldset { - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 4); padding: var(--universal-padding); } @@ -671,7 +670,7 @@ legend { display: table; max-width: 100%; white-space: normal; - font-weight: 700; + font-weight: 500; padding: calc(var(--universal-padding) / 2); } label { @@ -716,7 +715,7 @@ input:not([type]), [type="text"], [type="email"], [type="number"], [type="search box-sizing: border-box; background: var(--input-back-color); color: var(--input-fore-color); - border: 0.0625rem solid var(--input-border-color); + border: 0.0714285714rem solid var(--input-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 2); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } @@ -763,8 +762,8 @@ option { [type="radio"]:checked:before { border-radius: 100%; content: ''; - top: calc(0.0625rem + var(--universal-padding) / 2); - left: calc(0.0625rem + var(--universal-padding) / 2); + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); background: var(--input-fore-color); width: 0.5rem; height: 0.5rem; } @@ -793,7 +792,7 @@ a[role="button"], label[role="button"], [role="button"] { display: inline-block; background: var(--button-back-color); color: var(--button-fore-color); - border: 0.0625rem solid var(--button-border-color); + border: 0.0714285714rem solid var(--button-border-color); border-radius: var(--universal-border-radius); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); @@ -814,7 +813,7 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d .button-group { display: flex; - border: 0.0625rem solid var(--button-group-border-color); + border: 0.0714285714rem solid var(--button-group-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { @@ -826,13 +825,13 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d border-radius: 0; box-shadow: none; } .button-group > :not(:first-child) { - border-left: 0.0625rem solid var(--button-group-border-color); } + border-left: 0.0714285714rem solid var(--button-group-border-color); } @media screen and (max-width: 499px) { .button-group { flex-direction: column; } .button-group > :not(:first-child) { border: 0; - border-top: 0.0625rem solid var(--button-group-border-color); } } + border-top: 0.0714285714rem solid var(--button-group-border-color); } } /* Custom elements for forms and input elements. @@ -874,29 +873,29 @@ button.large, [type="button"].large, [type="submit"].large, [type="reset"].large */ /* Navigation module CSS variable definitions */ :root { - --header-back-color: #f8f8f8; - --header-hover-back-color: #f0f0f0; - --header-fore-color: #444; - --header-border-color: #ddd; - --nav-back-color: #f8f8f8; - --nav-hover-back-color: #f0f0f0; - --nav-fore-color: #444; - --nav-border-color: #ddd; - --nav-link-color: #0277bd; - --footer-fore-color: #444; - --footer-back-color: #f8f8f8; - --footer-border-color: #ddd; - --footer-link-color: #0277bd; - --drawer-back-color: #f8f8f8; - --drawer-hover-back-color: #f0f0f0; - --drawer-border-color: #ddd; - --drawer-close-color: #444; } + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } header { - height: 3.1875rem; + height: 2.75rem; background: var(--header-back-color); color: var(--header-fore-color); - border-bottom: 0.0625rem solid var(--header-border-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); padding: calc(var(--universal-padding) / 4) 0; white-space: nowrap; overflow-x: auto; @@ -927,7 +926,7 @@ header { nav { background: var(--nav-back-color); color: var(--nav-fore-color); - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } nav * { @@ -946,10 +945,10 @@ nav { nav .sublink-1:before { position: absolute; left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } nav .sublink-2 { position: relative; @@ -957,16 +956,16 @@ nav { nav .sublink-2:before { position: absolute; left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } footer { background: var(--footer-back-color); color: var(--footer-fore-color); - border-top: 0.0625rem solid var(--footer-border-color); + border-top: 0.0714285714rem solid var(--footer-border-color); padding: calc(2 * var(--universal-padding)) var(--universal-padding); font-size: 0.875rem; } footer a, footer a:visited { @@ -1013,7 +1012,7 @@ footer.sticky { height: 100vh; overflow-y: auto; background: var(--drawer-back-color); - border: 0.0625rem solid var(--drawer-border-color); + border: 0.0714285714rem solid var(--drawer-border-color); border-radius: 0; margin: 0; z-index: 1110; @@ -1060,38 +1059,36 @@ footer.sticky { */ /* Table module CSS variable definitions. */ :root { - --table-border-color: #aaa; - --table-border-separator-color: #666; - --table-head-back-color: #e6e6e6; - --table-head-fore-color: #111; - --table-body-back-color: #f8f8f8; - --table-body-fore-color: #111; - --table-body-alt-back-color: #eee; } + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } table { border-collapse: separate; border-spacing: 0; - : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + margin: 0; display: flex; flex: 0 1 auto; flex-flow: row wrap; padding: var(--universal-padding); - padding-top: 0; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + padding-top: 0; } table caption { - font-size: 1.25 * rem; + font-size: 1rem; margin: calc(2 * var(--universal-margin)) 0; max-width: 100%; - flex: 0 0 100%; - text-align: left;} + flex: 0 0 100%; } table thead, table tbody { display: flex; flex-flow: row wrap; - border: 0.0625rem solid var(--table-border-color); } + border: 0.0714285714rem solid var(--table-border-color); } table thead { z-index: 999; border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0625rem solid var(--table-border-separator-color); } + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } table tbody { border-top: 0; margin-top: calc(0 - var(--universal-margin)); @@ -1109,11 +1106,11 @@ table { table td { background: var(--table-body-back-color); color: var(--table-body-fore-color); - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table:not(.horizontal) { overflow: auto; - max-height: 850px; } + max-height: 100%; } table:not(.horizontal) thead, table:not(.horizontal) tbody { max-width: 100%; flex: 0 0 100%; } @@ -1134,32 +1131,33 @@ table.horizontal { border: 0; } table.horizontal thead, table.horizontal tbody { border: 0; + flex: .2 0 0; flex-flow: row nowrap; } table.horizontal tbody { overflow: auto; justify-content: space-between; - flex: 1 0 0; - margin-left: calc( 4 * var(--universal-margin)); + flex: .8 0 0; + margin-left: 0; padding-bottom: calc(var(--universal-padding) / 4); } table.horizontal tr { flex-direction: column; flex: 1 0 auto; } table.horizontal th, table.horizontal td { - width: 100%; + width: auto; border: 0; - border-bottom: 0.0625rem solid var(--table-border-color); } + border-bottom: 0.0714285714rem solid var(--table-border-color); } table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { border-top: 0; } table.horizontal th { text-align: right; - border-left: 0.0625rem solid var(--table-border-color); - border-right: 0.0625rem solid var(--table-border-separator-color); } + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } table.horizontal thead tr:first-child { padding-left: 0; } table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td { - border-right: 0.0625rem solid var(--table-border-color); } + border-right: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td:first-child { border-top-right-radius: 0.25rem; } table.horizontal tbody tr:last-child td:last-child { @@ -1191,12 +1189,12 @@ table.horizontal { display: table-row-group; } table tr, table.horizontal tr { display: block; - border: 0.0625rem solid var(--table-border-color); + border: 0.0714285714rem solid var(--table-border-color); border-radius: var(--universal-border-radius); - background: #fafafa; + background: #ffffff; padding: var(--universal-padding); margin: var(--universal-margin); - margin-bottom: calc(2 * var(--universal-margin)); } + margin-bottom: calc(1 * var(--universal-margin)); } table th, table td, table.horizontal th, table.horizontal td { width: auto; } table td, table.horizontal td { @@ -1211,9 +1209,6 @@ table.horizontal { border-top: 0; } table tbody tr:last-child td, table.horizontal tbody tr:last-child td { border-right: 0; } } -:root { - --table-body-alt-back-color: #eee; } - table tr:nth-of-type(2n) > td { background: var(--table-body-alt-back-color); } @@ -1234,8 +1229,8 @@ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focu */ /* Contextual module CSS variable definitions */ :root { - --mark-back-color: #0277bd; - --mark-fore-color: #fafafa; } + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } mark { background: var(--mark-back-color); @@ -1243,11 +1238,11 @@ mark { font-size: 0.95em; line-height: 1em; border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } mark.inline-block { display: inline-block; font-size: 1em; - line-height: 1.5; + line-height: 1.4; padding: calc(var(--universal-padding) / 2) var(--universal-padding); } :root { @@ -1314,8 +1309,8 @@ mark { :root { --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #444; - --modal-close-hover-color: #f0f0f0; } + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } [type="checkbox"].modal { height: 1px; @@ -1368,13 +1363,14 @@ mark { z-index: 1211; } :root { - --collapse-label-back-color: #e8e8e8; - --collapse-label-fore-color: #212121; - --collapse-label-hover-back-color: #f0f0f0; - --collapse-selected-label-back-color: #ececec; - --collapse-border-color: #ddd; - --collapse-content-back-color: #fafafa; - --collapse-selected-label-border-color: #0277bd; } + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } .collapse { width: calc(100% - 2 * var(--universal-margin)); @@ -1395,13 +1391,13 @@ mark { .collapse > label { flex-grow: 1; display: inline-block; - height: 1.5rem; + height: 1.25rem; cursor: pointer; - transition: background 0.3s; + transition: background 0.2s; color: var(--collapse-label-fore-color); background: var(--collapse-label-back-color); - border: 0.0625rem solid var(--collapse-border-color); - padding: calc(1.5 * var(--universal-padding)); } + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } .collapse > label:hover, .collapse > label:focus { background: var(--collapse-label-hover-back-color); } .collapse > label + div { @@ -1418,7 +1414,7 @@ mark { max-height: 1px; } .collapse > :checked + label { background: var(--collapse-selected-label-back-color); - border-bottom-color: var(--collapse-selected-label-border-color); } + border-color: var(--collapse-selected-label-border-color); } .collapse > :checked + label + div { box-sizing: border-box; position: relative; @@ -1427,13 +1423,13 @@ mark { overflow: auto; margin: 0; background: var(--collapse-content-back-color); - border: 0.0625rem solid var(--collapse-border-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); border-top: 0; padding: var(--universal-padding); clip: auto; -webkit-clip-path: inset(0%); clip-path: inset(0%); - max-height: 850px; } + max-height: 100%; } .collapse > label:not(:first-of-type) { border-top: 0; } .collapse > label:first-of-type { @@ -1450,11 +1446,8 @@ mark { /* Custom elements for contextual background elements, toasts and tooltips. */ -mark.secondary { - --mark-back-color: #d32f2f; } - mark.tertiary { - --mark-back-color: #308732; } + --mark-back-color: #3cb4e6; } mark.tag { padding: calc(var(--universal-padding)/2) var(--universal-padding); @@ -1463,9 +1456,9 @@ mark.tag { /* Definitions for progress elements and spinners. */ -/* Progess module CSS variable definitions */ +/* Progress module CSS variable definitions */ :root { - --progress-back-color: #ddd; + --progress-back-color: #3cb4e6; --progress-fore-color: #555; } progress { @@ -1558,45 +1551,53 @@ span[class^='icon-'] { filter: invert(100%); } span.icon-alert { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } span.icon-bookmark { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-calendar { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-credit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-edit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } span.icon-link { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } span.icon-help { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } span.icon-home { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-info { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } span.icon-lock { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } span.icon-mail { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-location { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' 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16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-search { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } span.icon-settings { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-share { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } span.icon-cart { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } span.icon-upload { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } /* Definitions for utilities and helper classes. @@ -1604,7 +1605,7 @@ span.icon-user { /* Utility module CSS variable definitions */ :root { --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } .hidden { display: none !important; } @@ -1622,7 +1623,7 @@ span.icon-user { overflow: hidden !important; } .bordered { - border: 0.0625rem solid var(--generic-border-color) !important; } + border: 0.0714285714rem solid var(--generic-border-color) !important; } .rounded { border-radius: var(--universal-border-radius) !important; } @@ -1697,4 +1698,14 @@ span.icon-user { clip-path: inset(100%) !important; overflow: hidden !important; } } -/*# sourceMappingURL=mini-default.css.map */ +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git 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zw7ER9v~DyrC*R$do9aEw5r@B)YzHOLB^-c9Eu9D!sFmI8^VljVKE89{zY_8PTSF+J b^}%0^qYmp2WD(pA|JtZ4>nPPKybJpu3@X?! literal 0 HcmV?d00001 diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 5abbc1daf2..4476fdd94e 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -5,7 +5,7 @@ * STM32F1: 1.1.9 * STM32F2: 1.2.8 * STM32F3: 1.5.7 - * STM32F4: 1.8.0 + * STM32F4: 1.8.2 * STM32F7: 1.3.0 * STM32G0: 1.4.4 * STM32G4: 1.2.2 From f79dbe152717a557b9b8d812e3ac6d29e8ce1c04 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 29 Nov 2023 09:41:02 +0100 Subject: [PATCH 56/83] system(F4): update STM32F4xx CMSIS Drivers to v2.6.9 Included in STM32CubeF4 FW v1.28.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32F4xx/Include/stm32f401xc.h | 24 +- .../Device/ST/STM32F4xx/Include/stm32f401xe.h | 24 +- .../Device/ST/STM32F4xx/Include/stm32f405xx.h | 32 +- .../Device/ST/STM32F4xx/Include/stm32f407xx.h | 37 +- .../Device/ST/STM32F4xx/Include/stm32f410cx.h | 34 +- .../Device/ST/STM32F4xx/Include/stm32f410rx.h | 34 +- .../Device/ST/STM32F4xx/Include/stm32f410tx.h | 32 +- .../Device/ST/STM32F4xx/Include/stm32f411xe.h | 26 +- .../Device/ST/STM32F4xx/Include/stm32f412cx.h | 34 +- .../Device/ST/STM32F4xx/Include/stm32f412rx.h | 40 +- .../Device/ST/STM32F4xx/Include/stm32f412vx.h | 40 +- .../Device/ST/STM32F4xx/Include/stm32f412zx.h | 40 +- .../Device/ST/STM32F4xx/Include/stm32f413xx.h | 62 +- .../Device/ST/STM32F4xx/Include/stm32f415xx.h | 36 +- .../Device/ST/STM32F4xx/Include/stm32f417xx.h | 41 +- .../Device/ST/STM32F4xx/Include/stm32f423xx.h | 62 +- .../Device/ST/STM32F4xx/Include/stm32f427xx.h | 53 +- .../Device/ST/STM32F4xx/Include/stm32f429xx.h | 57 +- .../Device/ST/STM32F4xx/Include/stm32f437xx.h | 57 +- .../Device/ST/STM32F4xx/Include/stm32f439xx.h | 61 +- .../Device/ST/STM32F4xx/Include/stm32f446xx.h | 56 +- .../Device/ST/STM32F4xx/Include/stm32f469xx.h | 61 +- .../Device/ST/STM32F4xx/Include/stm32f479xx.h | 65 +- .../Device/ST/STM32F4xx/Include/stm32f4xx.h | 116 +- .../ST/STM32F4xx/Include/system_stm32f4xx.h | 18 +- .../ST/STM32F4xx/{License.md => LICENSE.md} | 0 .../CMSIS/Device/ST/STM32F4xx/README.md | 11 +- .../Device/ST/STM32F4xx/Release_Notes.html | 2818 +++++------------ .../Templates/gcc/startup_stm32f401xc.s | 9 +- .../Templates/gcc/startup_stm32f401xe.s | 9 +- .../Templates/gcc/startup_stm32f405xx.s | 9 +- .../Templates/gcc/startup_stm32f407xx.s | 9 +- .../Templates/gcc/startup_stm32f410cx.s | 9 +- .../Templates/gcc/startup_stm32f410rx.s | 9 +- .../Templates/gcc/startup_stm32f410tx.s | 9 +- .../Templates/gcc/startup_stm32f411xe.s | 9 +- .../Templates/gcc/startup_stm32f412cx.s | 9 +- .../Templates/gcc/startup_stm32f412rx.s | 9 +- .../Templates/gcc/startup_stm32f412vx.s | 9 +- .../Templates/gcc/startup_stm32f412zx.s | 9 +- .../Templates/gcc/startup_stm32f413xx.s | 9 +- .../Templates/gcc/startup_stm32f415xx.s | 9 +- .../Templates/gcc/startup_stm32f417xx.s | 9 +- .../Templates/gcc/startup_stm32f423xx.s | 9 +- .../Templates/gcc/startup_stm32f427xx.s | 9 +- .../Templates/gcc/startup_stm32f429xx.s | 9 +- .../Templates/gcc/startup_stm32f437xx.s | 10 +- .../Templates/gcc/startup_stm32f439xx.s | 9 +- .../Templates/gcc/startup_stm32f446xx.s | 9 +- .../Templates/gcc/startup_stm32f469xx.s | 9 +- .../Templates/gcc/startup_stm32f479xx.s | 9 +- .../Device/ST/STM32F4xx/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../{mini-st.css => mini-st_2020.css} | 363 ++- .../Device/ST/STM32F4xx/_htmresc/st_logo.png | Bin 18616 -> 0 bytes .../ST/STM32F4xx/_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 56 files changed, 1731 insertions(+), 2813 deletions(-) rename system/Drivers/CMSIS/Device/ST/STM32F4xx/{License.md => LICENSE.md} (100%) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/favicon.png rename system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/{mini-st.css => mini-st_2020.css} (77%) delete mode 100644 system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/st_logo.png create mode 100644 system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/st_logo_2020.png diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h index f37c761409..bf0ee64bbc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention @@ -34,7 +34,7 @@ #define __STM32F401xC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS @@ -64,7 +64,7 @@ */ typedef enum { -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ @@ -73,7 +73,7 @@ typedef enum DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ + /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ @@ -129,7 +129,7 @@ typedef enum I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ - SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ } IRQn_Type; /** @@ -203,7 +203,7 @@ typedef struct __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; +} DBGMCU_TypeDef; /** @@ -822,9 +822,9 @@ typedef struct * @} */ - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ @@ -1400,7 +1400,7 @@ typedef struct /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) -#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ @@ -3915,7 +3915,7 @@ typedef struct #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */ @@ -4291,7 +4291,7 @@ typedef struct #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk /******************** Bit definition for RCC_AHB2ENR register ***************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h index fdb6a532cb..de30bcc23d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention @@ -34,7 +34,7 @@ #define __STM32F401xE_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS @@ -64,7 +64,7 @@ */ typedef enum { -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ @@ -73,7 +73,7 @@ typedef enum DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ + /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ @@ -129,7 +129,7 @@ typedef enum I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ - SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ } IRQn_Type; /** @@ -203,7 +203,7 @@ typedef struct __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; +} DBGMCU_TypeDef; /** @@ -822,9 +822,9 @@ typedef struct * @} */ - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ @@ -1400,7 +1400,7 @@ typedef struct /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) -#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ @@ -3915,7 +3915,7 @@ typedef struct #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */ @@ -4291,7 +4291,7 @@ typedef struct #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk /******************** Bit definition for RCC_AHB2ENR register ***************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h index febecd7ca9..246c80051d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention @@ -34,7 +34,7 @@ #define __STM32F405xx_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS @@ -64,7 +64,7 @@ */ typedef enum { -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ @@ -73,7 +73,7 @@ typedef enum DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ + /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ @@ -314,7 +314,7 @@ typedef struct __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; +} DBGMCU_TypeDef; /** @@ -1052,9 +1052,9 @@ typedef struct * @} */ - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ @@ -1066,7 +1066,7 @@ typedef struct /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define ADC_MULTIMODE_SUPPORT /*! - - - - - - - Release Notes for STM32F4xx CMSIS - - - - - -
        -


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        Back - - - to Release page
        -

        Release - Notes for STM32F4xx CMSIS

        -

        Copyright - 2017 STMicroelectronics

        -

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        - - - - - - - - - -
        -

        Update History

        - -

        V2.6.8 / 11-February-2022

        - -     -   Main - - - Changes
        -         - - -
          - -
        • All source files: update disclaimer to add reference to the new license agreement.
          • - -
        • Correct ETH bits definitions to be in line with naming used in the STM32F4 reference manual documents.
          • -
        -

        V2.6.7 / 16-July-2021

        - -     -   Main - - - Changes
        -         - -
          -
        • Add missing definition - FLASH_CR_ERRIE to the CMSIS header file.
          • - -
        • Remove unsupported �GPIOF_BASE� - and �GPIOG_BASE� defines from STM32F412Vx - device.
          • - -
        • Add new atomic register access - macros in stm32f4xx.h file.
          • - -
        • Add LSI maximum startup time - datasheet value: LSI_STARTUP_TIME.
          • - -
        • Fix a typo in CMSIS STM32F4xx - version macro (__STM32F4xx_CMSIS_VERSION).
          -
          • -
        -

        V2.6.6 / 12-February-2021

        -     -   Main - - - Changes
        -         - -
          -
        • system_stm32f4xx.c:
          • -
            -
          • Protect -Vector - - - table modification following SRAM or - FLASH preprocessor directive by a - generic preprocessor directive : - USER_VECT_TAB_ADDRESS
            • -
          • Update - - - SystemInit_ExtMemCtl() API to initialize - the tmpreg variable before each time out - loop condition.
            -
            • -
          -
        • Add License.md and - Readme.md files required for GitHub - publication
          • -
        • Improve GCC startup - files robustness.
          • -
        • Fix wrong value for - GPIO_MODER_MODE8_Msk and - GPIO_MODER_MODE2_Pos.
          • -
        • Update max number of - host channels in FS for STM32F446:
          • -
            -
          • Update - - - USB_OTG_FS_HOST_MAX_CHANNEL_NBR value - from 8 to 12.
            • -
          -
        • Add SMBDEN and SMBHEN - bit definition for STM32F410Tx device.
          -
          • -
        -

        V2.6.5 / 10-February-2020

        -     -   Main - - - Changes
        -         - -
          -
        • All header files
          • -
            -
          • Update - - - to use new BSD License format
            -
            • -
          -
        • MDK-ARM startup files
          • -
            -
          • Update - - - to fix invalid config wizard annotations
            • -
          -
        -

        V2.6.4 / 06-December-2019

        -     -   Main - - - Changes
        -         - -
          -
        • stm32f446xx.h file
          • -
            -
          • Update - - - to support HW flow control on UART4 and - UART5 instances
            • -
          -
        • stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files
          • -
            -
          • Remove - - - unused IS_USB_ALL_INSTANCE() assert macro
            • -
          -
        • All header files
          • -
            -
          • Remove - - - unused IS_TIM_SYNCHRO_INSTANCE() assert - macro
            • -
          -
        • system_stm32f4xx.c file
          • -
            -
          • Update - - - SystemInit() API to don't reset RCC - registers to its reset values
            -
            • -
          -
        -

        V2.6.3 / 08-February-2019

        -     -   Main - - - Changes
        -         - -
          -
        • CRYP:
          • -
            -
          • Update CMSIS - devices with correct CRYP data input - register name: DIN instead of DR
            • -
          • Add Bits - definition for CRYP CR ALGOMODE AES - GCM/CCM
            • -
          -
        • HASH:
          • -
            -
          • Update - HASH_DIGEST_TypeDef structure: resize - the HR register
            -
            • -
          • Remove MDMAT Bits - definition
            • -
          -
        • TIM:
          • -
            -
          • Add requires TIM - assert macros:
            • -
              -
            • IS_TIM_SYNCHRO_INSTANCE()
              • -
            • IS_TIM_CLOCKSOURCE_TIX_INSTANCE()
              • -
            • IS_TIM_CLOCKSOURCE_ITRX_INSTANCE()
              • -
            -
          -
        • RCC
          • -
            -
          • Add - - - RCC_CSR_BORRSTF bits definition
            • -
          -
        • GPIO
          -
          • -
            -
          • Fix - - - GPIO BRR bits definition
            • -
          • Adjust - - - the GPIO present on STM32F412 devices
            -
            • -
          -
        • SAI
          • -
            -
          • Fix - - - frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits - description
            -
            • -
          -
        • USB:
          • -
            -
          • Add - - - missing Bits Definitions in - USB_OTG_DOEPMSK register
            • -
          -
            -
              -
            • USB_OTG_DOEPMSK_AHBERRM
              • -
            • USB_OTG_DOEPMSK_OTEPSPRM
              • -
            • USB_OTG_DOEPMSK_BERRM
              • -
            • USB_OTG_DOEPMSK_NAKM
              • -
            • USB_OTG_DOEPMSK_NYETM
              • -
            -
          -
            -
          • Add - - - missing Bits Definitions in - USB_OTG_DIEPINT register
            • -
          -
            -
              -
            • USB_OTG_DIEPINT_INEPNM
              • -
            • USB_OTG_DIEPINT_AHBERR
              • -
            • USB_OTG_DOEPINT_OUTPKTERR
              • -
            •  USB_OTG_DOEPINT_NAK
              • -
            • USB_OTG_DOEPINT_STPKTRX
              • -
            -
          • Add - - - missing Bits Definitions in USB_OTG_DCFG - register
            • -
              -
            • USB_OTG_DCFG_XCVRDLY
              • -
            • USB_OTG_DCFG_ERRATIM
              • -
            -
          -
            -
          • Update - - - USB OTG max number of endpoints (6 FS - and 9 HS instead of 5 and 8)
            • -
          -
        • I2C/FMPI2C
          • -
            -
          • Align - - - Bit naming for FMPI2C_CR1 register: - FMPI2C_CR1_DFN--> FMPI2C_CR1_DNF
            • -
          • Add - - - IS_SMBUS_ALL_INSTANCE() - - - define
            • -
          -
        • DFSDM
          • -
            -
          • Align - - - Bit naming for DFSDM_FLTICR register: - DFSDM_FLTICR_CLRSCSDF--> - DFSDM_FLTICR_CLRSCDF
            • -
          -
        • PWR
          • -
            -
          • Remove PWR_CSR_WUPP - define: feature not available on - STM32F469xx/479xx devices
            • -
          -
        -

        V2.6.2 / 06-October-2017

        -     -   Main - - - Changes
        -         - -
          -
            -
          • Remove Date and - Version from all header files
            • -
          • USB_OTG - - - register clean up: remove - duplicated bits definitions
            • -
          • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
            • -
              -
            • Remove - - - BKPSRAM_BASE define: feature not - available
              • -
            -
          • stm32f405xx.h, stm32f407xx.h files
            • -
              -
            • Rename - - - HASH_RNG_IRQn to RNG_IRQn: HASH - instance not available 
              • -
            -
          • stm32f410xx.h, stm32f412xx.h, stm32f413xx.h,  stm32f423xx.h files
            • -
              -
            • Add - - - missing wake-up pins defines
              • -
            -
          • stm32f412cx.h files
            • -
              -
            •  Add - support of USART3 instance
              • -
            -
          -
        -

        V2.6.1 / 14-February-2017

        -     -   Main - - - Changes
        -         - -
          -
        • General updates in - header files to support LL drivers
          • -
            -
          • Align - - - Bit naming for RCC_CSR - register (ex: RCC_CSR_PADRSTF - --> RCC_CSR_PINRSTF)
            • -
          • Add - - - new defines for RCC features support:
            • -
              -
            • RCC - - - PLLI2S and RCC PLLSAI support
              • -
            • RCC - - - PLLR I2S clock source and RCC PLLR - system clock support
              • -
            • RCC - - - SAI1A PLL source and RCC SAI1B PLL - source support
              • -
            • RCC - - - AHB2 support
              -
              • -
            -
          • Add - - - RCC_DCKCFGR_PLLI2SDIVQ_X - and  RCC_DCKCFGR_PLLSAIDIVQ_X - bits definition
            • -
          • Add new defines for - RCC_PLLI2SCFGR_RST_VALUE, - RCC_PLLSAICFGR_RST_VALUE and - RCC_PLLCFGR_RST_VALUE
            • -
          • Add - - - new defines for RTC features support:
            • -
              -
            • RTC - - - Tamper 2 support
              • -
            • RTC - - - AF2 mapping support
              -
              • -
            -
          • Align - - - Bit naming for RTC_CR and RTC_TAFCR - registers (ex: RTC_CR_BCK --> RTC_CR_BKP)
            • -
          • Add - - - new define to manage RTC backup register - number: RTC_BKP_NUMBER
            • -
          • Rename - - - IS_UART_INSTANCE() macro to - IS_UART_HALFDUPLEX_INSTANCE()
            • -
          • Add new defines to check - LIN instance: IS_UART_LIN_INSTANCE
            • -
          • Remove - - - USART6 instance from STM32F410Tx header - file
            • -
          • Rename - IS_I2S_ALL_INSTANCE_EXT() macro to - IS_I2S_EXT_ALL_INSTANCEE()
            • -
          • Add - - - IS_I2S_APB1_INSTANCE() macro to check if - I2S instance mapping: API1 or APB2
            -
            • -
          • Remove - - - SPI_I2S_SUPPORT define for SPI I2S - features support: I2S feature is - available on all STM32F4xx devices
            • -
          • Add - - - SPI_I2S_FULLDUPLEX_SUPPORT define for - STM32F413xx/423xx devices
            • -
          • Align - - - SPI_I2SCFGR bit - naming: SPI_I2SCFGR_ASTRTEN bit is - missing for STM32F412xx devices
            • -
          • Add - - - new I2S_APB1_APB2_FEATURE - - - define - - - for STM32F4xx devices where I2S IP's are - splited between RCC APB1 and APB2 - interfaces
            -
            • -
          • Add new FLASH_SR_RDERR define in FLASH_SR register
            • -
          • Add FLASH_OTP_BASE and  FLASH_OTP_END defnes - to manage FLASH OPT area
            -
            • -
          • Add - - - bit definitions for ETH_MACDBGR - register
            • -
          • Add - - - new defines ADC1_COMMON_BASE and - ADC123_COMMON_BASE to replace ADC_BASE - define
            • -
          • Add - - - new defines ADC1_COMMON and - ADC123_COMMON to replace ADC define
            • -
          • Add - - - new ADC macros: IS_ADC_COMMON_INSTANCE() -and IS_ADC_MULTIMODE_MASTER_INSTANCE()
            -
            • -
          • Add - - - new defines for ADC multi mode features - support
            • -
          • Add - - - new ADC aliases ADC_CDR_RDATA_MST and - ADC_CDR_RDATA_SLV for compatibilities - with all STM32 Families
            • -
          • Update - - - TIM CNT and ARR register mask on 32-bits
            • -
          • Add new TIM_OR_TI1_RMP define in TIM_OR register
            • -
          • Add - - - new TIM macros to check TIM feature - instance support:
            • -
              -
            • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
              • -
            • IS_TIM_CLOCK_DIVISION_INSTANCE()
              • -
            • IS_TIM_COMMUTATION_EVENT_INSTANCE()
              • -
            • IS_TIM_OCXREF_CLEAR_INSTANCE()
              • -
            • IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
              • -
            • IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
              • -
            • IS_TIM_REPETITION_COUNTER_INSTANCE()
              • -
            • IS_TIM_ENCODER_INTERFACE_INSTANCE()
              • -
            • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
              • -
            • IS_TIM_BREAK_INSTANCE()
              • -
            -
          • CAN_IER - - - register clean up: remove duplicated bit - definitions
            • -
          • USB_OTG - - - register: fix the wrong defined values - for USB_OTG_GAHBCFG bits
            • -
          -
        -

        V2.6.0 / 04-November-2016

        -     -   Main - - - Changes
        -         - -
          -
        • Add support of STM32F413xx and STM32F423xx devices 
          • -
            -
          • Add - - - "stm32f413xx.h" and "stm32f423xx.h" - - - files
            • -
          -
            -
          • -

            Add - - - startup files  "startup_stm32f413xx.s" - - - and "startup_stm32f423xx.s" - - - for EWARM, MDK-ARM and SW4STM32 - toolchains

            -
            • -
          • Add - - - Linker files "stm32f413xx_flash.icf", - - - "stm32f413xx_sram.icf", - - - "stm32f423xx_flash.icf" - - - and "stm32f423xx_sram.icf" - - - used - - - within EWARM Workspaces
            • -
          -
        • All header files
          • -
            -
          • Use - - - _Pos and _Mask macro for all Bit - Definitions
            • -
          • Update - - - LPTIM_OR Bit Definition
            • -
          • Update - - - the defined frequencies by scale for USB - exported constants
            • -
          • Add - - - UID_BASE, FLASHSIZE_BASE and - PACKAGE_BASE defines
            • -
          • Add - - - new define DAC_CHANNEL2_SUPPORT to - manage DAC channel2 support
            • -
          • Use - - - new DAC1 naming
            • -
          • Rename - - - PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY - in PWR_CSR register
            • -
          • Align - - - Bit naming for EXTI_IMR and EXTI_EMR - registers (ex: EXTI_IMR_MR0 --> - EXTI_IMR_IM0)
            -
            • -
          • Add - - - new EXTI_IMR_IM define in EXTI_IMR - register
            • -
          • Add - - - missing DMA registers definition
            • -
          • Add - - - macro to check SMBUS instance support
            -
            • -
          -
        • stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files
          • -
            -
          • Add missing SYSCFG - register: CFGR2
            • -
          -
        • stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files
          • -
            -
          • Remove - - - HASH_RNG_IRQn in IRQn_Type enumeration
            • -
          -
        • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
          • -
            -
          • Remove - - - I2C FLTR register as not supported
            -
            • -
          -
        • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
          • -
            -
          • Add - - - missing Bit Definition of ETH_MACDBGR - register
            • -
          -
        • system_stm32f4xx.c file
          • -
            -
          • Add - - - APBPrescTable declaration
            • -
          -
        -

        V2.5.1 / 28-June-2016

        -     -   Main - - - Changes
        -         - -
          -
        • stm32f412rx.h, - stm32f412vx.h and - - - stm32f412zx.h files:
          • -
            -
          • -

            Add QSPI1_V2_1L - define to manage the QSPI DMA2 - limitation
            -

            -
            • -
          -
        -

        V2.5.0 / 22-April-2016

        -     -   Main - - - Changes
        -         - -
          -
        • Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices
          • -
            -
          • -

            Add - "stm32f412Cx.h", "stm32f412Rx.h", "stm32f412Vx.h" and "stm32f412Zx.h" files

            -
            • -
          • -

            Add startup - files  "startup_stm32f412cx.s", "startup_stm32f412rx.s", "startup_stm32f412vx.s" and - - - "startup_stm32f412zx.s" - - - for EWARM, MDK-ARM and SW4STM32 - toolchains

            -
            • -
          • Add Linker files "stm32f412cx_flash.icf", "stm32f412cx_sram.icf", "stm32f412rx_flash.icf", "stm32f412rx_sram.icf", "stm32f412vx_flash.icf", "stm32f412vx_sram.icf", "stm32f412zx_flash.icf" and "stm32f412zx_sram.icf" used within EWARM - Workspaces
            • -
          -
        • Header files for all - STM32 devices
          • -
            -
          • Remove uint32_t cast - and keep only Misra Cast (U) to avoid - two types cast duplication
            • -
          • Correct some bits - definition to be in line with naming - used in the Reference Manual
            • -
              -
            • WWDG_CR_Tx changed - - - to WWDG_CR_T_x
              • -
            • WWDG_CFR_Wx changed - - - to WWDG_CFR_W_x
              • -
            • WWDG_CFR_WDGTBx changed - - - to WWDG_CFR_WDGTB_x
              • -
            -
          -
        • stm32f407xx.h, - stm32f417xx.h, stm32f427xx.h, - - - stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
          • -
            -
          • Correct some bits - definition to be in line with naming - used in the Reference Manual
            • -
          -
            -
              -
            • DCMI_RISR_x changed - - - to DCMI_RIS_x
              • -
            • DCMI_RISR_OVF_RIS - - - changed to DCMI_RIS_OVR_RIS
              • -
            • DCMI_IER_OVF_IE - - - changed to DCMI_IER_OVR_IE
              • -
            -
          -
        • stm32f427xx.h, - stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
          • -
            -
          • Correct some bits - definition to be in line with naming - used in the Reference Manual
            • -
              -
            • SAI_xFRCR_FSPO changed - - - to SAI_xFRCR_FSPOL
              • -
            -
          • Rename - IS_SAI_BLOCK_PERIPH to - IS_SAI_ALL_INSTANCE
            -
            • -
          -
        • stm32f410cx.h, - stm32f410rx.h, stm32f410tx.h files - - - and stm32f446xx.h
          • -
            -
          • Remove - FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN - Bit definition for I2C_CR1 register
            • -
          -
        • stm32f407xx.h, - stm32f417xx.h, stm32f427xx.h, - stm32f437xx.h, stm32f439xx.h, - stm32f469xx.h, stm32f479xx.h files
          • -
            -
          • Add missing bits - definitions for DMA2D_CR, - DMA2D_FGPFCCR, DMA2D_BGPFCCR, - DMA2D_OPFCCR registers
            • -
          -
        • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
          • -
            -
          • Add missing RCC_DCKCFGR register - - - in RCC_TypeDef structure
            -
            • -
          • Add - missing Bit definition for RCC_DCKCFGR - register
            • -
          -
        • system_stm32f4xx.c
          -
          • -
            -
          • Update - SystemInit_ExtMemCtl() API to fix delay - optimization problem with GCC compiler: index variable is - declared as volatile 
            • -
          -
        • stm32f4xx.h
          • -
            -
          • Rename - __STM32F4xx_CMSIS_DEVICE_VERSION_xx - defines to - __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
            • -
          -
        - -

        V2.4.3 / 29-January-2016

        -     -   Main - - - Changes
        -
        -         -
          -
        • -

          Header file for all STM32 devices -

          -
          • -
            -
          • Rename -ADC - - - overrun flags definitions : - ADC_CSR_DOVR1, ADC_CSR_DOVR2 and - ADC_CSR_DOVR3 are replaced respectively - by ADC_CSR_OVR1, ADC_CSR_OVR2 and - ADC_CSR_OVR3 to be aligned with - reference manuals
            • -
          • Add - - - missing bits definitions for DAC : - DAC_CR_DMAUDRIE1 and DAC_CR_DMAUDRIE2
            • -
          • Update - - - CMSIS driver to be compliant with MISRA - C 2004 rule 10.6
            • -
          • Remove - - - the double definition of - USB_OTG_HS_MAX_IN_ENDPOINTS and add a - new one for  - USB_OTG_HS_MAX_OUT_ENDPOINTS
            • -
          -
        • stm32f446xx.h, - - - stm32f469xx.h, stm32f479xx.h files 
          • -
            -
          • Change - - - the bit definition value of - QUADSPI_CR_FTHRES
            • -
          -
        • - stm32f446xx.h, stm32f469xx.h, - stm32f479xx.h, stm32f429xx.h, - stm32f439xx.h files
          • -
            -
          • Rename - - - the LTDC_GCR_DTEN to LTDC_GCR_DEN in - order to be aligned with the reference - manual
            • -
          • Rename - - - DCMI_MISR bit definitions to DCMI_MIS
            • -
          • Rename - - - DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
            • -
          • Add - - - missing bits definitions for DCMI_ESCR, - DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, - DCMI_DR registers
            • -
          -
        • - stm32f407xx.h, stm32f417xx.h, - stm32f427xx.h, stm32f437xx.h files
          • -
            -
          • Rename - - - DCMI_MISR bit definitions to DCMI_MIS
            • -
          • Rename - - - DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
            • -
          • Add - - - missing bits definitions for DCMI_ESCR, - DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, - DCMI_DR registers
            • -
          -
        • - stm32f410cx.h, stm32f410rx.h, - stm32f410tx.h files
          • -
            -
          • Update - - - the - - - LPTIM SNGSTRT defined value
            • -
          -
        • stm32f427xx.h, - stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f469xx.h, stm32f479xx.h - - - files
          • -
            -
          • Rename - - - the DMA2D_IFSR bit definitions to - DMA2D_IFCR
            • -
          -
        • stm32f427xx.h, - stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h - - - files 
          • -
            -
          • Correct - - - a wrong value of SAI_xCR2_CPL definition - bit 
            -
            • -
          -
        -

        V2.4.2 / 13-November-2015

        -

        Main Changes

        -
          -
        • -

          system_stm32f4xx.c file -

          -
          • -
            -
          • update -SystemInit_ExtMemCtl() - - - function implementation to allow the - possibility of simultaneous use of - DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM
            • -
          -
        • stm32f4xx.h - - - file
          • -
            -
          • add - - - symbols for STM32F411xC devices
            -
            • -
          -
        • stm32f405xx.h, - - - stm32f407xx.h, stm32f415xx.h, - stm32f417xx.h files
          • -
            -
          • add - - - FSMC_BCRx_CPSIZE bits definitions
            • -
          • remove - - - FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT - bits definitions
            • -
          -
        • stm32f429xx.h, - - - stm32f427xx.h, stm32f437xx.h files
          • -
            -
          • add - - - FMC_BCRx_CPSIZE bits definitions
            • -
          • remove - - - FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT - bits definitions
            • -
          -
        • stm32f446xx.h, - - - stm32f469xx.h and stm32f479xx.h
          • -
            -
          • update - - - USB_OTG_GlobalTypeDef registers - structure to remove ADP control - registers
            • -
          • add - - - USB_OTG_DOEPMSK_OTEPSPRM and - USB_OTG_DOEPINT_OTEPSPR bits definitions
            • -
          • Remove - - - ADP related bits definitions
            • -
          • add - - - IS_PCD_ALL_INSTANCE() and - IS_HCD_ALL_INSTANCE() macros
            -
            • -
          -
        -

        V2.4.1 / 09-October-2015

        -

        Main Changes

        -
          -
        • "stm32f469xx.h", - - - "stm32f479xx.h" -
            -
          • Update bits definition for - DSI_WPCR and DSI_TCCR registers
            -
            • -
          -
          • -
        -

        V2.4.0 / 14-August-2015

        -

        Main Changes

        -
          -
        • -

          Add - - - support of STM32F469xx - and STM32F479xx devices
          -

          -
          • -
            -
          • -

            Add - - - "stm32f469xx.h" and "stm32f479xx.h" - - - files

            -
            • -
          -
            -
          • -

            Add - - - startup files  "startup_stm32f469xx.s" - - - and "startup_stm32f479xx.s" - - - for EWARM, MDK-ARM and SW4STM32 - toolchains

            -
            • -
          • Add - - - Linker files "stm32f469xx_flash.icf", - - - "stm32f469xx_sram.icf", - - - "stm32f479xx_flash.icf" - - - and "stm32f479xx_sram.icf" - - - used - - - within EWARM Workspaces
            • -
          -
        • -

          Add - - - support of STM32F410xx - devices
          -

          -
          • -
            -
          • -

            Add - - - "stm32f410cx.h", "stm32f410tx.h" - and "stm32f410rx.h" - - - files

            -
            • -
          -
            -
          • -

            Add - - - startup files  "startup_stm32f410cx.s", - - - "startup_stm32f410rx.s" and "startup_stm32f410tx.s" - - - for EWARM, MDK-ARM and SW4STM32 - toolchains

            -
            • -
          • Add - - - Linker files "stm32f410cx_flash.icf", - - - "stm32f410cx_sram.icf", - - - "stm32f410rx_flash.icf", "stm32f410tx_sram.icf", - - - "stm32f410tx_flash.icf",  - and "stm32f410rx_sram.icf" - - - used - - - within EWARM Workspaces
            • -
          -
        -

        V2.3.2 / 26-June-2015

        -

        Main Changes

        -
          -
        • "stm32f405xx.h", - - - "stm32f407xx.h", "stm32f415xx.h" and - "stm32f417xx.h" -
            -
          • Update FSMC_BTRx_DATAST - - - and FSMC_BWTRx_DATAST (where x can - be 1, 2, 3 and 4) mask on 8bits - instead of 4bits
            • -
          -
          • -
        • "stm32f427xx.h", - - - "stm32f437xx.h", "stm32f429xx.h" and - "stm32f439xx.h"
          -
            -
          • Update the defined mask value - for SAI_xSR_FLVL_2
            • -
          -
          • -
        • "stm32f415xx.h", - - - "stm32f417xx.h", "stm32f437xx.h" and - "stm32f439xx.h"
          • -
            -
          • HASH alignement with bits namming - used in documentation -
              -
                -
              • Rename HASH_IMR_DINIM to - HASH_IMR_DINIE
                • -
              -
                -
              • Rename HASH_IMR_DCIM to - HASH_IMR_DCIE
                • -
              -
                -
              • Rename HASH_STR_NBW to - HASH_STR_NBW
                • -
              -
            -
            • -
          -
        • system_stm32f4xx.c
          • -
            -
          • Remove __IO on constant table - declaration
            • -
          -
            -
          • Implement workaround to cover - RCC limitation regarding peripheral - enable delay
            • -
          -
            -
          • SystemInit_ExtMemCtl() - - - update GPIO configuration when external - SDRAM is used 
            • -
          -
        - -

        V2.3.1 / 03-April-2015

        - Main Changes -
          -
        • -

          Header file for all STM32 devices

          -
            -
          • Update SRAM2, SRAM3 and - BKPSRAM Bit-Banding base address - defined values
            • -
          • Keep reference to - SRAM3 only for STM32F42xx and - STM32F43xx devices
            • -
          • Remove CCMDATARAM_BB_BASE: the - CCM Data RAM region is not accessible - via Bit-Banding
            -
            • -
          • Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of - 0x00001FFF
            -
            • -
          -
          • -
        -

        V2.3.0 / 02-March-2015

        -

        Main Changes

        - -
          -
        • -

          Add - - - support of STM32F446xx - devices
          -

          -
          • -
            -
          • -

            Add - - - "stm32f446xx.h" file

            -
            • -
          -
            -
          • -

            Add - - - startup file "startup_stm32f446xx.s" - for EWARM, MDK-ARM and TrueSTUDIO - toolchains

            -
            • -
          • Add - - - Linker files "stm32f446xx_flash.icf" and - "stm32f446xx_sram.icf" used within EWARM - Workspaces
            • -
          -
        • -

          Header file for all STM32 devices

          -
            -
          • Add missing bits - definition in the EXTI IMR, EMR, RTSR, - FTSR, SWIER and PR registers
            • -
          • Update - RCC_AHB1RSTR_OTGHRST bit definition
            • -
          • Update PWR_CR_VOS - bits definition for STM32F40xx - - - and STM32F41xx - - - devices
            • -
          • -

            update SAI_xCR1_MCKDIV bit - definition
            -

            -
            • -
          -
          • -
        -

        V2.2.0 / 15-December-2014

        -

        Main Changes

        - -
          -
        • -

          stm32f4xx.h

          -
            -
          • -

            Add new constant definition STM32F4 -
            -

            -
            • -
          -
          • -
        • -

          system_stm32f4xx.c
          -

          -
            -
          • -

            Fix SDRAM configuration in - SystemInit_ExtMemCtl(): change RowBitsNumber - from 11 to 12 (for MT48LC4M32B2 - available on STM324x9I_EVAL board)
            -

            -
            • -
          -
          • -
        • -

          Header file for all STM32 devices

          -
            -
          • -

            Add missing bits definition - for CAN, FMC and USB peripherals

            -
            • -
          • -

            GPIO_TypeDef: change the BSRR - register definition, the two 16-bits - definition BSRRH and BSRRL are - merged in a single 32-bits - definition BSRR

            -
            • -
          -
          • -
        -

        V2.1.0 / 19-June-2014

        -

        Main Changes

        - - - -
          -
        • -

          Add - - - support of STM32F411xExx - devices
          -

          -
          • -
            -
          • -

            Add - - - "stm32f411xe.h" file

            -
            • -
          -
            -
          • -

            Add - - - startup file "startup_stm32f411xx.s" - for EWARM, MDK-ARM and TrueSTUDIO - toolchains

            -
            • -
          -
        • -

          All - - - header files

          -
          • -
            -
          • -

            Add - - - missing defines for GPIO LCKR Register

            -
            • -
          • -

            Add defines for - memories base and end addresses: - FLASH, SRAM, BKPSRAM and CCMRAM.

            -
            • -
          • -

            Add -the - - - following aliases for IRQ number and - handler definition to ensure - compatibility across the product lines - of STM32F4 Series;
            -

            -
            • -
              -
            • -

              example for STM32F405xx.h

              -
              • -
            -
          -
        -
        #define - - - FMC_IRQn              - - - FSMC_IRQn
        - #define - - - FMC_IRQHandler     - FSMC_IRQHandler
        -
          -
            -
              -
            • -

              and for STM32F427xx.h

              -
              • -
            -
          -
        -
        #define - - - FSMC_IRQn            - - - FMC_IRQn
        - #define - - - FSMC_IRQHandler   FMC_IRQHandler
        -
          -
        • "stm32f401xc.h" - - - and "stm32f401xe.h": update to be in line - with latest version of the Reference - - - manual
          • -
            -
          • Remove - - - RNG registers structures and the - corresponding bit definitions
            • -
          • Remove - - - any occurrence to RNG (clock enable, - clock reset,�)
            • -
          • Add - - - the following bit definition for PWR CR - register
            • -
              -
            • #define  PWR_CR_ADCDC1      - - - ((uint32_t)0x00002000)
              • -
            -
              -
            • #define  PWR_CR_LPLVDS       - - - ((uint32_t)0x00000400)     
              • -
            -
              -
            • #define  - - - PWR_CR_MRLVDS   -    ((uint32_t)0x00000800)     
              • -
            -
          -
        • "stm32f427xx.h", - - - "stm32f437xx.h", "stm32f429xx.h" and - "stm32f439xx.h"
          • -
            -
          • Add - - - a new legacy bit definition for PWR to - be in line with latest version of the - Reference manual
            • -
              -
            • #define  PWR_CR_LPUDS        PWR_CR_LPLVDS
              • -
            -
              -
            • #define  -PWR_CR_MRUDS      - - - PWR_CR_MRLVDS
              • -
            -
          -
        • -

          Update startup - files for EWARM toolchain to cope with - compiler enhancement of the V7.10 - version

          -
          • -
        • -

          system_stm32f4xx.c

          -
          • -
            -
          • Remove - - - dependency vs. the HAL, to allow using - this file without the need to have the - HAL drivers
            -
            • -
              -
            • Include - - - stm32f4xx.h - - - instead of stm32f4xx_hal.h
              • -
            • Add -definition - - - of HSE_VALUE and HSI_VALUE, if they - are not yet defined in the compilation - scope (these values are defined in - stm32f4xx_hal_conf).
              -
              • -
            -
          • -

            Use �__IO const� - instead of �__I�, to avoid any - compilation issue when __cplusplus - switch is defined

            -
            • -
          -
        -

        V2.0.0 / 18-February-2014

        -

        Main Changes

        - - - -
          -
        • Update based on STM32Cube - specification
          -
          • -
        • This version and later has to be - used only with STM32CubeF4 based development
          • -
        -

        V1.3.0 / - 08-November-2013

        -

        Main Changes

        -
          -
        • -

          Add -support - - - of STM32F401xExx - devices

          -
          • -
        • Update startup files "startup_stm32f401xx.s" for EWARM, MDK-ARM, TrueSTUDIO and - Ride toolchains: Add SPI4 interrupt - handler entry in the vector table
          • -
        -

        V1.2.1 / - 19-September-2013

        -

        Main Changes

        -
          -
        • -

          system_stm32f4xx.c : Update FMC SDRAM - configuration (RBURST mode activation)
          -

          -
          • -
        • Update startup files "startup_stm32f427_437xx.s" and "startup_stm32f429_439xx.s"  for - TrueSTUDIO and Ride toolchains and - maintain the old name of startup files for - legacy purpose
          • -
        -

        V1.2.0 / - 11-September-2013

        -

        Main Changes

        -
          -
        • -

          Add -support - - - of STM32F429/439xx - and STM32F401xCxx - devices

          -
          • -
        • Update - - - definition of STM32F427/437xx devices : - extension -of - - - the features to include system clock up to - 180MHz, dual bank Flash, reduced STOP Mode - current, SAI, PCROP, SDRAM and DMA2D
          • -
        • stm32f4xx.h
          -           -
            -
          • Add the - following device defines :
            • -
              -
            • "#define - STM32F40_41xxx" for all STM32405/415/407/417xx devices
              • -
            • "#define - STM32F427_437xx" for all STM32F427/437xx devices
              • -
            • "#define - STM32F429_439xx" for all STM32F429/439xx devices
              • -
            • "#define - STM32F401xx" for all STM32F401xx devices
              • -
            -
          • Maintain the - old device define for legacy purpose
            • -
          • Update IRQ - handler enumeration structure to - support all STM32F4xx Family devices. -  
            • -
          -
          • -
        • Add new startup files "startup_stm32f40_41xxx.s","startup_stm32f427_437xx.s", "startup_stm32f429_439xx.s" and "startup_stm32f401xx.s" for all toolchains and maintain - the old name for startup files for legacy - purpose
          • -
        • system_stm32f4xx.c -
            -
          • Update - the system configuration to - support all STM32F4xx Family devices. -  
            • -
          -
          • -
        -

        V1.1.0 / - 11-January-2013

        -

        Main Changes

        -
          -
        • Official release for STM32F427x/437x - devices.
          • -
        • stm32f4xx.h
          -           -
            -
          • Update product - define: replace "#define STM32F4XX" by - "#define STM32F40XX" for STM32F40x/41x - devices
            • -
          •  Add new - product define: "#define STM32F427X" - for STM32F427x/437x devices.
            • -
          -
          • -
        • Add new startup files "startup_stm32f427x.s" for all - toolchains
          • -
        • rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s" for all - toolchains
          • -
        • system_stm32f4xx.c -
            -
          • Prefetch Buffer - enabled
            • -
          • Add reference - to STM32F427x/437x devices and - STM324x7I_EVAL board
            • -
          • SystemInit_ExtMemCtl() - - - function
            -             -
              -
            • Add - configuration of missing FSMC - address and data lines
              -
              • -
            -
              -
            • Change - memory type to SRAM instead of - PSRAM (PSRAM is available only on - STM324xG-EVAL RevA) and update - timing values
              • -
            -
            • -
          -
          • -
        - -

        V1.0.2 / 05-March-2012

        -

        Main Changes

        -
          -
        • All source files: license - disclaimer text update and add link to the - License file on ST Internet.
          • -
        -

        V1.0.1 / 28-December-2011

        -

        Main Changes

        -
          -
        • All source files: update - disclaimer to add reference to - the new license agreement
          • -
        • stm32f4xx.h
          • -
            -
          • Correct bit - - - definition: RCC_AHB2RSTR_HSAHRST changed - - - to RCC_AHB2RSTR_HASHRST
            • -
          -
        -

        V1.0.0 / 30-September-2011

        -

        Main Changes

        -
          -
        • First official release for STM32F40x/41x - devices
          • -
        • Add startup file for TASKING - toolchain
          • -
        • system_stm32f4xx.c: - driver's comments update
          • -
        -

        V1.0.0RC2 / 26-September-2011

        -

        Main Changes

        -
          -
        • Official version (V1.0.0) - Release Candidate2 for STM32F40x/41x - devices
          • -
        • stm32f4xx.h
          • -
            -
          • Add define for Cortex-M4 - revision __CM4_REV
            • -
          • Correct RCC_CFGR_PPRE2_DIV16 - bit (in RCC_CFGR register) value - to 0x0000E000
            • -
          • Correct some bits - definition to be in line with naming - used in the Reference Manual (RM0090)
            • -
              -
            • GPIO_OTYPER_IDR_x - changed to GPIO_IDR_IDR_x
              • -
            • GPIO_OTYPER_ODR_x - changed to GPIO_ODR_ODR_x
              • -
            • SYSCFG_PMC_MII_RMII - changed to SYSCFG_PMC_MII_RMII_SEL
              • -
            • RCC_APB2RSTR_SPI1 - changed to RCC_APB2RSTR_SPI1RST
              • -
            • DBGMCU_APB1_FZ_DBG_IWDEG_STOP - changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
              • -
            • PWR_CR_PMODE - changed to PWR_CR_VOS
              • -
            • PWR_CSR_REGRDY - changed to PWR_CSR_VOSRDY
              • -
            • Add new define - RCC_AHB1ENR_CCMDATARAMEN
              • -
            • Add new - defines SRAM2_BASE, CCMDATARAM_BASE - and BKPSRAM_BASE
              • -
            -
          • GPIO_TypeDef structure: in the - comment change AFR[2] address - mapping to 0x20-0x24 - instead of 0x24-0x28
            • -
          -
        • system_stm32f4xx.c
          • -
            -
          • SystemInit(): add code - to enable the FPU
            • -
          • SetSysClock(): change - PWR_CR_PMODE - by PWR_CR_VOS
            • -
          • SystemInit_ExtMemCtl(): - remove commented values
            • -
          -
        • startup (for all compilers)
          • -
            -
          • Delete code used to enable the - FPU (moved to system_stm32f4xx.c file)
            • -
          • File�s header updated
            • -
          -
        -

        V1.0.0RC1 / 25-August-2011

        -

        Main Changes

        -
          -
        • Official version (V1.0.0) - Release Candidate1 for STM32F4xx devices
          • -
        - -
          -
        -
        -
        -

        For - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

        -

        -
        -

        -
        -
        -

         

        -
        - \ No newline at end of file + + + + + + + Release Notes for STM32F4xx CMSIS + + + + + + +
        +
        +
        +

        Release Notes for

        +

        STM32F4xx CMSIS

        +

        Copyright © 2017 STMicroelectronics
        +

        + +
        +

        Purpose

        +

        This driver provides the CMSIS device for the stm32f4xx products.

        +
        +
        +

        Update History

        +
        + +
        +

        Main Changes

        +
          +
        • Added new atomic register access macros in stm32f4xx.h file.
          • +
        • Update FLASH_SCALE2_LATENCY4_FREQ value to 120MHz instead of 12MHz.
          • +
        • Update the GCC startup file to be aligned to IAR/Keil IDE.
          • +
        • STM32F410/412/413/423: +
            +
          • Fix wrong defined value for wake-up pin 3 (PWR_CSR_EWUP3).
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • All source files: update disclaimer to add reference to the new license agreement.
          • +
        • Correct ETH bits definitions to be in line with naming used in the STM32F4 reference manual documents.
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add missing definition FLASH_CR_ERRIE to the CMSIS header file.
          • +
        • Remove unsupported “GPIOF_BASE” and “GPIOG_BASE” defines from STM32F412Vx device.
          • +
        • Add new atomic register access macros in stm32f4xx.h file.
          • +
        • Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.
          • +
        • Fix a typo in CMSIS STM32F4xx version macro (__STM32F4xx_CMSIS_VERSION).
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • system_stm32f4xx.c: +
            +
          • Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS
            • +
          • Update SystemInit_ExtMemCtl() API to initialize the tmpreg variable before each time out loop condition.
            • +
          • +
        • Add License.md and Readme.md files required for GitHub publication
          • +
        • Improve GCC startup files robustness.
          • +
        • Fix wrong value for GPIO_MODER_MODE8_Msk and GPIO_MODER_MODE2_Pos.
          • +
        • Update max number of host channels in FS for STM32F446: +
            +
          • Update USB_OTG_FS_HOST_MAX_CHANNEL_NBR value from 8 to 12.
            • +
          • +
        • Add SMBDEN and SMBHEN bit definition for STM32F410Tx device.
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • All header files +
            +
          • Update to use new BSD License format
            • +
          • +
        • MDK-ARM startup files +
            +
          • Update to fix invalid config wizard annotations
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • stm32f446xx.h file +
            +
          • Update to support HW flow control on UART4 and UART5 instances
            • +
          • +
        • stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files +
            +
          • Remove unused IS_USB_ALL_INSTANCE() assert macro
            • +
          • +
        • All header files +
            +
          • Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro
            • +
          • +
        • system_stm32f4xx.c file +
            +
          • Update SystemInit() API to don’t reset RCC registers to its reset values
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • CRYP: +
            +
          • Update CMSIS devices with correct CRYP data input register name: DIN instead of DR
            • +
          • Add Bits definition for CRYP CR ALGOMODE AES GCM/CCM
            • +
          • +
        • HASH: +
            +
          • Update HASH_DIGEST_TypeDef structure: resize the HR register
            • +
          • Remove MDMAT Bits definition
            • +
          • +
        • TIM: +
            +
          • Add requires TIM assert macros:
            • +
          • IS_TIM_SYNCHRO_INSTANCE()
            • +
          • IS_TIM_CLOCKSOURCE_TIX_INSTANCE()
            • +
          • IS_TIM_CLOCKSOURCE_ITRX_INSTANCE()
            • +
          • +
        • RCC +
            +
          • Add RCC_CSR_BORRSTF bits definition
            • +
          • +
        • GPIO +
            +
          • Fix GPIO BRR bits definition
            • +
          • Adjust the GPIO present on STM32F412 devices
            • +
          • +
        • SAI +
            +
          • Fix frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits description
            • +
          • +
        • USB: +
            +
          • Add missing Bits Definitions in USB_OTG_DOEPMSK register
            • +
          • USB_OTG_DOEPMSK_AHBERRM
            • +
          • USB_OTG_DOEPMSK_OTEPSPRM
            • +
          • USB_OTG_DOEPMSK_BERRM
            • +
          • USB_OTG_DOEPMSK_NAKM
            • +
          • USB_OTG_DOEPMSK_NYETM
            • +
          • Add missing Bits Definitions in USB_OTG_DIEPINT register
            • +
          • USB_OTG_DIEPINT_INEPNM
            • +
          • USB_OTG_DIEPINT_AHBERR
            • +
          • USB_OTG_DOEPINT_OUTPKTERR
            • +
          • USB_OTG_DOEPINT_NAK
            • +
          • USB_OTG_DOEPINT_STPKTRX
            • +
          • Add missing Bits Definitions in USB_OTG_DCFG register
            • +
          • USB_OTG_DCFG_XCVRDLY
            • +
          • USB_OTG_DCFG_ERRATIM
            • +
          • Update USB OTG max number of endpoints (6 FS and 9 HS instead of 5 and 8)
            • +
          • +
        • I2C/FMPI2C +
            +
          • Align Bit naming for FMPI2C_CR1 register: FMPI2C_CR1_DFN–> FMPI2C_CR1_DNF
            • +
          • Add IS_SMBUS_ALL_INSTANCE() define
            • +
          • +
        • DFSDM +
            +
          • Align Bit naming for DFSDM_FLTICR register: DFSDM_FLTICR_CLRSCSDF–> DFSDM_FLTICR_CLRSCDF
            • +
          • +
        • PWR +
            +
          • Remove PWR_CSR_WUPP define: feature not available on STM32F469xx/479xx devices
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Remove Date and Version from all header files
          • +
        • USB_OTG register clean up: remove duplicated bits definitions
          • +
        • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files +
            +
          • Remove BKPSRAM_BASE define: feature not available
            • +
          • +
        • stm32f405xx.h, stm32f407xx.h files +
            +
          • Rename HASH_RNG_IRQn to RNG_IRQn: HASH instance not available
            • +
          • +
        • stm32f410xx.h, stm32f412xx.h, stm32f413xx.h, stm32f423xx.h files +
            +
          • Add missing wake-up pins defines
            • +
          • +
        • stm32f412cx.h files +
            +
          • Add support of USART3 instance
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates in header files to support LL drivers +
            +
          • Align Bit naming for RCC_CSR register (ex: RCC_CSR_PADRSTF –> RCC_CSR_PINRSTF)
            • +
          • Add new defines for RCC features support:
            • +
          • RCC PLLI2S and RCC PLLSAI support
            • +
          • RCC PLLR I2S clock source and RCC PLLR system clock support
            • +
          • RCC SAI1A PLL source and RCC SAI1B PLL source support
            • +
          • RCC AHB2 support
            • +
          • Add RCC_DCKCFGR_PLLI2SDIVQ_X and RCC_DCKCFGR_PLLSAIDIVQ_X bits definition
            • +
          • Add new defines for RCC_PLLI2SCFGR_RST_VALUE, RCC_PLLSAICFGR_RST_VALUE and RCC_PLLCFGR_RST_VALUE
            • +
          • Add new defines for RTC features support:
            • +
          • RTC Tamper 2 support
            • +
          • RTC AF2 mapping support
            • +
          • Align Bit naming for RTC_CR and RTC_TAFCR registers (ex: RTC_CR_BCK –> RTC_CR_BKP)
            • +
          • Add new define to manage RTC backup register number: RTC_BKP_NUMBER
            • +
          • Rename IS_UART_INSTANCE() macro to IS_UART_HALFDUPLEX_INSTANCE()
            • +
          • Add new defines to check LIN instance: IS_UART_LIN_INSTANCE
            • +
          • Remove USART6 instance from STM32F410Tx header file
            • +
          • Rename IS_I2S_ALL_INSTANCE_EXT() macro to IS_I2S_EXT_ALL_INSTANCEE()
            • +
          • Add IS_I2S_APB1_INSTANCE() macro to check if I2S instance mapping: API1 or APB2
            • +
          • Remove SPI_I2S_SUPPORT define for SPI I2S features support: I2S feature is available on all STM32F4xx devices
            • +
          • Add SPI_I2S_FULLDUPLEX_SUPPORT define for STM32F413xx/423xx devices
            • +
          • Align SPI_I2SCFGR bit naming: SPI_I2SCFGR_ASTRTEN bit is missing for STM32F412xx devices
            • +
          • Add new I2S_APB1_APB2_FEATURE define for STM32F4xx devices where I2S IP’s are splited between RCC APB1 and APB2 interfaces
            • +
          • Add new FLASH_SR_RDERR define in FLASH_SR register
            • +
          • Add FLASH_OTP_BASE and FLASH_OTP_END defnes to manage FLASH OPT area
            • +
          • Add bit definitions for ETH_MACDBGR register
            • +
          • Add new defines ADC1_COMMON_BASE and ADC123_COMMON_BASE to replace ADC_BASE define
            • +
          • Add new defines ADC1_COMMON and ADC123_COMMON to replace ADC define
            • +
          • Add new ADC macros: IS_ADC_COMMON_INSTANCE() and IS_ADC_MULTIMODE_MASTER_INSTANCE()
            • +
          • Add new defines for ADC multi mode features support
            • +
          • Add new ADC aliases ADC_CDR_RDATA_MST and ADC_CDR_RDATA_SLV for compatibilities with all STM32 Families
            • +
          • Update TIM CNT and ARR register mask on 32-bits
            • +
          • Add new TIM_OR_TI1_RMP define in TIM_OR register
            • +
          • Add new TIM macros to check TIM feature instance support:
            • +
          • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
            • +
          • IS_TIM_CLOCK_DIVISION_INSTANCE()
            • +
          • IS_TIM_COMMUTATION_EVENT_INSTANCE()
            • +
          • IS_TIM_OCXREF_CLEAR_INSTANCE()
            • +
          • IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
            • +
          • IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
            • +
          • IS_TIM_REPETITION_COUNTER_INSTANCE()
            • +
          • IS_TIM_ENCODER_INTERFACE_INSTANCE()
            • +
          • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
            • +
          • IS_TIM_BREAK_INSTANCE()
            • +
          • +
        • CAN_IER register clean up: remove duplicated bit definitions
          • +
        • USB_OTG register: fix the wrong defined values for USB_OTG_GAHBCFG bits
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F413xx and STM32F423xx devices +
            +
          • Add “stm32f413xx.h” and “stm32f423xx.h” files
            • +
          • Add startup files “startup_stm32f413xx.s” and “startup_stm32f423xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains
            • +
          • Add Linker files “stm32f413xx_flash.icf”, “stm32f413xx_sram.icf”, “stm32f423xx_flash.icf” and “stm32f423xx_sram.icf” used within EWARM Workspaces
            • +
          • +
        • All header files +
            +
          • Use _Pos and _Mask macro for all Bit Definitions
            • +
          • Update LPTIM_OR Bit Definition
            • +
          • Update the defined frequencies by scale for USB exported constants
            • +
          • Add UID_BASE, FLASHSIZE_BASE and PACKAGE_BASE defines
            • +
          • Add new define DAC_CHANNEL2_SUPPORT to manage DAC channel2 support
            • +
          • Use new DAC1 naming
            • +
          • Rename PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY in PWR_CSR register
            • +
          • Align Bit naming for EXTI_IMR and EXTI_EMR registers (ex: EXTI_IMR_MR0 –> EXTI_IMR_IM0)
            • +
          • Add new EXTI_IMR_IM define in EXTI_IMR register
            • +
          • Add missing DMA registers definition
            • +
          • Add macro to check SMBUS instance support
            • +
          • +
        • stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files +
            +
          • Add missing SYSCFG register: CFGR2
            • +
          • +
        • stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files +
            +
          • Remove HASH_RNG_IRQn in IRQn_Type enumeration
            • +
          • +
        • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files +
            +
          • Remove I2C FLTR register as not supported
            • +
          • +
        • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files +
            +
          • Add missing Bit Definition of ETH_MACDBGR register
            • +
          • +
        • system_stm32f4xx.c file +
            +
          • Add APBPrescTable declaration
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • stm32f412rx.h, stm32f412vx.h and stm32f412zx.h files: +
            +
          • Add QSPI1_V2_1L define to manage the QSPI DMA2 limitation
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices +
            +
          • Add “stm32f412Cx.h”, “stm32f412Rx.h”, “stm32f412Vx.h” and “stm32f412Zx.h” files
            • +
          • Add startup files “startup_stm32f412cx.s”, “startup_stm32f412rx.s”, “startup_stm32f412vx.s” and “startup_stm32f412zx.s” for EWARM, MDK-ARM and SW4STM32 toolchains
            • +
          • Add Linker files “stm32f412cx_flash.icf”, “stm32f412cx_sram.icf”, “stm32f412rx_flash.icf”, “stm32f412rx_sram.icf”, “stm32f412vx_flash.icf”, “stm32f412vx_sram.icf”, “stm32f412zx_flash.icf” and “stm32f412zx_sram.icf” used within EWARM Workspaces
            • +
          • +
        • Header files for all STM32 devices +
            +
          • Remove uint32_t cast and keep only Misra Cast (U) to avoid two types cast duplication
            • +
          • Correct some bits definition to be in line with naming used in the Reference Manual
            • +
          • WWDG_CR_Tx changed to WWDG_CR_T_x
            • +
          • WWDG_CFR_Wx changed to WWDG_CFR_W_x
            • +
          • WWDG_CFR_WDGTBx changed to WWDG_CFR_WDGTB_x
            • +
          • +
        • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files +
            +
          • Correct some bits definition to be in line with naming used in the Reference Manual
            • +
          • DCMI_RISR_x changed to DCMI_RIS_x
            • +
          • DCMI_RISR_OVF_RIS changed to DCMI_RIS_OVR_RIS
            • +
          • DCMI_IER_OVF_IE changed to DCMI_IER_OVR_IE
            • +
          • +
        • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files +
            +
          • Correct some bits definition to be in line with naming used in the Reference Manual
            • +
          • SAI_xFRCR_FSPO changed to SAI_xFRCR_FSPOL
            • +
          • Rename IS_SAI_BLOCK_PERIPH to IS_SAI_ALL_INSTANCE
            • +
          • +
        • stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files and stm32f446xx.h +
            +
          • Remove FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN Bit definition for I2C_CR1 register
            • +
          • +
        • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files +
            +
          • Add missing bits definitions for DMA2D_CR, DMA2D_FGPFCCR, DMA2D_BGPFCCR, DMA2D_OPFCCR registers
            • +
          • +
        • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files +
            +
          • Add missing RCC_DCKCFGR register in RCC_TypeDef structure
            • +
          • Add missing Bit definition for RCC_DCKCFGR register
            • +
          • +
        • system_stm32f4xx.c +
            +
          • Update SystemInit_ExtMemCtl() API to fix delay optimization problem with GCC compiler: index variable is declared as volatile
            • +
          • +
        • stm32f4xx.h +
            +
          • Rename __STM32F4xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Header file for all STM32 devices +
            +
          • Rename ADC overrun flags definitions : ADC_CSR_DOVR1, ADC_CSR_DOVR2 and ADC_CSR_DOVR3 are replaced respectively by ADC_CSR_OVR1, ADC_CSR_OVR2 and ADC_CSR_OVR3 to be aligned with reference manuals
            • +
          • Add missing bits definitions for DAC : DAC_CR_DMAUDRIE1 and DAC_CR_DMAUDRIE2
            • +
          • Update CMSIS driver to be compliant with MISRA C 2004 rule 10.6
            • +
          • Remove the double definition of USB_OTG_HS_MAX_IN_ENDPOINTS and add a new one for USB_OTG_HS_MAX_OUT_ENDPOINTS
            • +
          • +
        • stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files +
            +
          • Change the bit definition value of QUADSPI_CR_FTHRES
            • +
          • +
        • stm32f446xx.h, stm32f469xx.h, stm32f479xx.h, stm32f429xx.h, stm32f439xx.h files +
            +
          • Rename the LTDC_GCR_DTEN to LTDC_GCR_DEN in order to be aligned with the reference manual
            • +
          • Rename DCMI_MISR bit definitions to DCMI_MIS
            • +
          • Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
            • +
          • Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
            • +
          • +
        • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h files +
            +
          • Rename DCMI_MISR bit definitions to DCMI_MIS
            • +
          • Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
            • +
          • Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
            • +
          • +
        • stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files +
            +
          • Update the LPTIM SNGSTRT defined value
            • +
          • +
        • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files +
            +
          • Rename the DMA2D_IFSR bit definitions to DMA2D_IFCR
            • +
          • +
        • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files +
            +
          • Correct a wrong value of SAI_xCR2_CPL definition bit
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • system_stm32f4xx.c file +
            +
          • update SystemInit_ExtMemCtl() function implementation to allow the possibility of simultaneous use of DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM
            • +
          • +
        • stm32f4xx.h file +
            +
          • add symbols for STM32F411xC devices
            • +
          • +
        • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files +
            +
          • add FSMC_BCRx_CPSIZE bits definitions
            • +
          • remove FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT bits definitions
            • +
          • +
        • stm32f429xx.h, stm32f427xx.h, stm32f437xx.h files +
            +
          • add FMC_BCRx_CPSIZE bits definitions
            • +
          • remove FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT bits definitions
            • +
          • +
        • stm32f446xx.h, stm32f469xx.h and stm32f479xx.h +
            +
          • update USB_OTG_GlobalTypeDef registers structure to remove ADP control registers
            • +
          • add USB_OTG_DOEPMSK_OTEPSPRM and USB_OTG_DOEPINT_OTEPSPR bits definitions
            • +
          • Remove ADP related bits definitions
            • +
          • add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() macros
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • “stm32f469xx.h”, “stm32f479xx.h” +
            +
          • Update bits definition for DSI_WPCR and DSI_TCCR registers
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F469xx and STM32F479xx devices +
            +
          • Add “stm32f469xx.h” and “stm32f479xx.h” files
            • +
          • Add startup files “startup_stm32f469xx.s” and “startup_stm32f479xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains
            • +
          • Add Linker files “stm32f469xx_flash.icf”, “stm32f469xx_sram.icf”, “stm32f479xx_flash.icf” and “stm32f479xx_sram.icf” used within EWARM Workspaces
            • +
          • +
        • Add support of STM32F410xx devices +
            +
          • Add “stm32f410cx.h”, “stm32f410tx.h” and “stm32f410rx.h” files
            • +
          • Add startup files “startup_stm32f410cx.s”, “startup_stm32f410rx.s” and “startup_stm32f410tx.s” for EWARM, MDK-ARM and SW4STM32 toolchains
            • +
          • Add Linker files “stm32f410cx_flash.icf”, “stm32f410cx_sram.icf”, “stm32f410rx_flash.icf”, “stm32f410tx_sram.icf”, “stm32f410tx_flash.icf”, and “stm32f410rx_sram.icf” used within EWARM Workspaces
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • “stm32f405xx.h”, “stm32f407xx.h”, “stm32f415xx.h” and “stm32f417xx.h” +
            +
          • Update FSMC_BTRx_DATAST and FSMC_BWTRx_DATAST (where x can be 1, 2, 3 and 4) mask on 8bits instead of 4bits
            • +
          • +
        • “stm32f427xx.h”, “stm32f437xx.h”, “stm32f429xx.h” and “stm32f439xx.h” +
            +
          • Update the defined mask value for SAI_xSR_FLVL_2
            • +
          • +
        • “stm32f415xx.h”, “stm32f417xx.h”, “stm32f437xx.h” and “stm32f439xx.h” +
            +
          • HASH alignement with bits namming used in documentation
            • +
          • Rename HASH_IMR_DINIM to HASH_IMR_DINIE
            • +
          • Rename HASH_IMR_DCIM to HASH_IMR_DCIE
            • +
          • Rename HASH_STR_NBW to HASH_STR_NBW
            • +
          • +
        • system_stm32f4xx.c +
            +
          • Remove __IO on constant table declaration
            • +
          • Implement workaround to cover RCC limitation regarding peripheral enable delay
            • +
          • SystemInit_ExtMemCtl() update GPIO configuration when external SDRAM is used
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Header file for all STM32 devices +
            +
          • Update SRAM2, SRAM3 and BKPSRAM Bit-Banding base address defined values
            • +
          • Keep reference to SRAM3 only for STM32F42xx and STM32F43xx devices
            • +
          • Remove CCMDATARAM_BB_BASE: the CCM Data RAM region is not accessible via Bit-Banding
            • +
          • Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of 0x00001FFF
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F446xx devices +
            +
          • Add “stm32f446xx.h” file
            • +
          • Add startup file “startup_stm32f446xx.s” for EWARM, MDK-ARM and TrueSTUDIO toolchains
            • +
          • Add Linker files “stm32f446xx_flash.icf” and “stm32f446xx_sram.icf” used within EWARM Workspaces
            • +
          • +
        • Header file for all STM32 devices +
            +
          • Add missing bits definition in the EXTI IMR, EMR, RTSR, FTSR, SWIER and PR registers
            • +
          • Update RCC_AHB1RSTR_OTGHRST bit definition
            • +
          • Update PWR_CR_VOS bits definition for STM32F40xx and STM32F41xx devices
            • +
          • update SAI_xCR1_MCKDIV bit definition
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • stm32f4xx.h +
            +
          • Add new constant definition STM32F4
            • +
          • +
        • system_stm32f4xx.c +
            +
          • Fix SDRAM configuration in SystemInit_ExtMemCtl(): change RowBitsNumber from 11 to 12 (for MT48LC4M32B2 available on STM324x9I_EVAL board)
            • +
          • +
        • Header file for all STM32 devices +
            +
          • Add missing bits definition for CAN, FMC and USB peripherals
            • +
          • GPIO_TypeDef: change the BSRR register definition, the two 16-bits definition BSRRH and BSRRL are merged in a single 32-bits definition BSRR
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F411xExx devices +
            +
          • Add “stm32f411xe.h” file
            • +
          • Add startup file “startup_stm32f411xx.s” for EWARM, MDK-ARM and TrueSTUDIO toolchains
            • +
          • +
        • All header files +
            +
          • Add missing defines for GPIO LCKR Register
            • +
          • Add defines for memories base and end addresses: FLASH, SRAM, BKPSRAM and CCMRAM.
            • +
          • Add the following aliases for IRQ number and handler definition to ensure compatibility across the product lines of STM32F4 Series; +
              +

            • example for STM32F405xx.h

              +

              #define FMC_IRQn FSMC_IRQn #define FMC_IRQHandler FSMC_IRQHandler

              • +

            • and for STM32F427xx.h

              +

              #define FSMC_IRQn FMC_IRQn #define FSMC_IRQHandler FMC_IRQHandler

              • +
            • +
          • +
        • “stm32f401xc.h” and “stm32f401xe.h”: update to be in line with latest version of the Reference manual +
            +
          • Remove RNG registers structures and the corresponding bit definitions
            • +
          • Remove any occurrence to RNG (clock enable, clock reset,…)
            • +
          • Add the following bit definition for PWR CR registerAdd the following bit definition for PWR CR register +
              +
            • #define PWR_CR_ADCDC1 ((uint32_t)0x00002000)
              • +
            • #define PWR_CR_LPLVDS ((uint32_t)0x00000400)
              • +
            • #define PWR_CR_MRLVDS ((uint32_t)0x00000800)
              • +
            • +
          • +
        • “stm32f427xx.h”, “stm32f437xx.h”, “stm32f429xx.h” and “stm32f439xx.h” +
            +
          • Add a new legacy bit definition for PWR to be in line with latest version of the Reference manual +
              +
            • #define PWR_CR_LPUDS PWR_CR_LPLVDS
              • +
            • #define PWR_CR_MRUDS PWR_CR_MRLVDS
              • +
            • +
          • +
        • Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version
          • +
        • system_stm32f4xx.c +
            +
          • Remove dependency vs. the HAL, to allow using this file without the need to have the HAL drivers +
              +
            • Include stm32f4xx.h instead of stm32f4xx_hal.h
              • +
            • Add definition of HSE_VALUE and HSI_VALUE, if they are not yet defined in the compilation scope (these values are defined in stm32f4xx_hal_conf).
              • +
            • +
          • Use “__IO const” instead of “__I”, to avoid any compilation issue when __cplusplus switch is defined
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Update based on STM32Cube specification
          • +
        • This version and later has to be used only with STM32CubeF4 based development
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F401xExx devices
          • +
        • Update startup files “startup_stm32f401xx.s” for EWARM, MDK-ARM, TrueSTUDIO and Ride toolchains: Add SPI4 interrupt handler entry in the vector table
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • system_stm32f4xx.c : Update FMC SDRAM configuration (RBURST mode activation)
          • +
        • Update startup files “startup_stm32f427_437xx.s” and “startup_stm32f429_439xx.s” for TrueSTUDIO and Ride toolchains and maintain the old name of startup files for legacy purpose
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add support of STM32F429/439xx and STM32F401xCxx devices
          • +
        • Update definition of STM32F427/437xx devices : extension of the features to include system clock up to 180MHz, dual bank Flash, reduced STOP Mode current, SAI, PCROP, SDRAM and DMA2D
          • +
        • stm32f4xx.h +
            +
          • Add the following device defines : +
              +
            • “#define STM32F40_41xxx” for all STM32405/415/407/417xx devices
              • +
            • “#define STM32F427_437xx” for all STM32F427/437xx devices
              • +
            • “#define STM32F429_439xx” for all STM32F429/439xx devices
              • +
            • “#define STM32F401xx” for all STM32F401xx devices
              • +
            • +
          • Maintain the old device define for legacy purpose
            • +
          • Update IRQ handler enumeration structure to support all STM32F4xx Family devices.
            • +
          • +
        • Add new startup files “startup_stm32f40_41xxx.s”,“startup_stm32f427_437xx.s”, “startup_stm32f429_439xx.s” and “startup_stm32f401xx.s” for all toolchains and maintain the old name for startup files for legacy purpose
          • +
        • system_stm32f4xx.c +
            +
          • Update the system configuration to support all STM32F4xx Family devices.
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Official release for STM32F427x/437x devices.
          • +
        • stm32f4xx.h +
            +
          • Update product define: replace “#define STM32F4XX” by “#define STM32F40XX” for STM32F40x/41x devices
            • +
          • Add new product define: “#define STM32F427X” for STM32F427x/437x devices.
            • +
          • +
        • Add new startup files “startup_stm32f427x.s” for all toolchains
          • +
        • rename startup files “startup_stm32f4xx.s” by “startup_stm32f40xx.s” for all toolchains
          • +
        • system_stm32f4xx.c +
            +
          • Prefetch Buffer enabled
            • +
          • Add reference to STM32F427x/437x devices and STM324x7I_EVAL board
            • +
          • SystemInit_ExtMemCtl() function +
              +
            • Add configuration of missing FSMC address and data lines
              • +
            • Change memory type to SRAM instead of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing values
              • +
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • All source files: license disclaimer text update and add link to the License file on ST Internet.
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • All source files: update disclaimer to add reference to the new license agreement
          • +
        • stm32f4xx.h +
            +
          • Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • First official release for STM32F40x/41x devices
          • +
        • Add startup file for TASKING toolchain
          • +
        • system_stm32f4xx.c: driver’s comments update
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
          • +
        • stm32f4xx.h +
            +
          • Add define for Cortex-M4 revision __CM4_REV
            • +
          • Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
            • +
          • Correct some bits definition to be in line with naming used in the Reference Manual (RM0090) +
              +
            • GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
              • +
            • GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
              • +
            • SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
              • +
            • RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
              • +
            • DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
              • +
            • PWR_CR_PMODE changed to PWR_CR_VOS
              • +
            • PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
              • +
            • Add new define RCC_AHB1ENR_CCMDATARAMEN
              • +
            • Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
              • +
            • +
          • GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
            • +
          • +
        • system_stm32f4xx.c +
            +
          • SystemInit(): add code to enable the FPU
            • +
          • SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
            • +
          • SystemInit_ExtMemCtl(): remove commented values
            • +
          • +
        • startup (for all compilers) +
            +
          • Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
            • +
          • File’s header updated
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
          • +
        +
        +
        +
        +
        + + + diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s index 7368496c05..0e29dd6eaa 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -228,6 +228,9 @@ g_pfnVectors: .word 0 /* Reserved */ .word SPI4_IRQHandler /* SPI4 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s index 6272f36289..e0f69baf33 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -228,6 +228,9 @@ g_pfnVectors: .word 0 /* Reserved */ .word SPI4_IRQHandler /* SPI4 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s index e463fb3ffd..917d243a89 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors @@ -229,6 +229,9 @@ g_pfnVectors: .word FPU_IRQHandler /* FPU */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s index 714d3c4faa..24fa922d1c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -227,6 +227,9 @@ g_pfnVectors: .word FPU_IRQHandler /* FPU */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s index fdcab8fef2..42977bc99c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -241,6 +241,9 @@ g_pfnVectors: .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ .word LPTIM1_IRQHandler /* LP TIM1 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s index 0d86852a3a..2821128c40 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -241,6 +241,9 @@ g_pfnVectors: .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ .word LPTIM1_IRQHandler /* LP TIM1 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s index bb60d6b52c..861a1a934a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -241,6 +241,9 @@ g_pfnVectors: .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ .word LPTIM1_IRQHandler /* LP TIM1 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s index 1b86625e56..bae927c286 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -229,6 +229,9 @@ g_pfnVectors: .word SPI4_IRQHandler /* SPI4 */ .word SPI5_IRQHandler /* SPI5 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s index d20795efb6..9dcd71e697 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -240,6 +240,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s index 1f34976a14..9f41f4f28e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -240,6 +240,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s index 45cbf1797e..903447b378 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -240,6 +240,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s index c11f39a943..117509d30d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -240,6 +240,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s index eeac1ed141..3d2871a023 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -245,6 +245,9 @@ g_pfnVectors: .word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */ .word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s index 871c499a85..f5201e08e3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -227,6 +227,9 @@ g_pfnVectors: .word FPU_IRQHandler /* FPU */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s index 2bbdc4e869..bbcc0326d3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -227,6 +227,9 @@ g_pfnVectors: .word FPU_IRQHandler /* FPU */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s index e15f80752b..e78d8bf368 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -245,6 +245,9 @@ g_pfnVectors: .word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */ .word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s index 4024d88346..e390ea5f08 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -235,6 +235,9 @@ g_pfnVectors: .word 0 /* Reserved */ .word 0 /* Reserved */ .word DMA2D_IRQHandler /* DMA2D */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s index 245231d818..56f5289cf6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -235,6 +235,9 @@ g_pfnVectors: .word LTDC_ER_IRQHandler /* LTDC_ER_IRQHandler */ .word DMA2D_IRQHandler /* DMA2D */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s index ac5dccd55f..d32ab6eb36 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit + /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +123,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -235,6 +236,9 @@ g_pfnVectors: .word 0 /* Reserved */ .word DMA2D_IRQHandler /* DMA2D */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s index 36ed7ac4af..09885e4708 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -237,6 +237,9 @@ Infinite_Loop: + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s index 41fb9f4557..eef0783487 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -242,6 +242,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C 1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C 1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s index d5470fa41f..d6481b6658 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -238,6 +238,9 @@ Infinite_Loop: .word DSI_IRQHandler /* DSI */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s index 9878def15f..02ab141d15 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, 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version: v3.0.1 */ /* Browsers resets and base typography. */ /* Core module CSS variable definitions */ :root { - --fore-color: #111; - --secondary-fore-color: #444; - --back-color: #f8f8f8; - --secondary-back-color: #f0f0f0; - --blockquote-color: #f57c00; - --pre-color: #1565c0; - --border-color: #aaa; - --secondary-border-color: #ddd; - --heading-ratio: 1.19; + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; --universal-margin: 0.5rem; - --universal-padding: 0.125rem; - --universal-border-radius: 0.125rem; - --a-link-color: #0277bd; - --a-visited-color: #01579b; } + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } html { - font-size: 14px; } + font-size: 13.5px; } a, b, del, em, i, ins, q, span, strong, u { font-size: 1em; } html, * { - font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; - line-height: 1.4; + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; -webkit-text-size-adjust: 100%; } * { @@ -42,7 +42,10 @@ html, * { body { margin: 0; color: var(--fore-color); - background: var(--back-color); } + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } details { display: block; } @@ -62,9 +65,9 @@ img { height: auto; } h1, h2, h3, h4, h5, h6 { - line-height: 1.2; + line-height: 1.25; margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 500; } + font-weight: 400; } h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { color: var(--secondary-fore-color); display: block; @@ -74,21 +77,15 @@ h1 { font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); - background: var(--mark-back-color); - font-weight: 600; - padding: 0.1em 0.5em 0.2em 0.5em; - color: var(--mark-fore-color); } - + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } h3 { - font-size: calc(1rem * var(--heading-ratio)); - padding-left: calc(2 * var(--universal-margin)); - /* background: var(--border-color); */ - } + font-size: calc(1rem * var(--heading-ratio) ); } h4 { - font-size: 1rem;); - padding-left: calc(4 * var(--universal-margin)); } + font-size: calc(1rem * var(--heading-ratio)); } h5 { font-size: 1rem; } @@ -101,7 +98,7 @@ p { ol, ul { margin: var(--universal-margin); - padding-left: calc(6 * var(--universal-margin)); } + padding-left: calc(3 * var(--universal-margin)); } b, strong { font-weight: 700; } @@ -111,7 +108,7 @@ hr { border: 0; line-height: 1.25em; margin: var(--universal-margin); - height: 0.0625rem; + height: 0.0714285714rem; background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } blockquote { @@ -121,16 +118,16 @@ blockquote { color: var(--secondary-fore-color); margin: var(--universal-margin); padding: calc(3 * var(--universal-padding)); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.375rem solid var(--blockquote-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } blockquote:before { position: absolute; top: calc(0rem - var(--universal-padding)); left: 0; font-family: sans-serif; - font-size: 3rem; - font-weight: 700; + font-size: 2rem; + font-weight: 800; content: "\201c"; color: var(--blockquote-color); } blockquote[cite]:after { @@ -160,8 +157,8 @@ pre { background: var(--secondary-back-color); padding: calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.25rem solid var(--pre-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } sup, sub, code, kbd { @@ -204,7 +201,8 @@ a { box-sizing: border-box; display: flex; flex: 0 1 auto; - flex-flow: row wrap; } + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } .col-sm, [class^='col-sm-'], @@ -565,9 +563,9 @@ a { order: 999; } } /* Card component CSS variable definitions */ :root { - --card-back-color: #f8f8f8; - --card-fore-color: #111; - --card-border-color: #ddd; } + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } .card { display: flex; @@ -578,7 +576,7 @@ a { width: 100%; background: var(--card-back-color); color: var(--card-fore-color); - border: 0.0625rem solid var(--card-border-color); + border: 0.0714285714rem solid var(--card-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); overflow: hidden; } @@ -592,7 +590,7 @@ a { margin: 0; border: 0; border-radius: 0; - border-bottom: 0.0625rem solid var(--card-border-color); + border-bottom: 0.0714285714rem solid var(--card-border-color); padding: var(--universal-padding); width: 100%; } .card > .sectione.media { @@ -617,17 +615,18 @@ a { width: auto; } .card.warning { -/* --card-back-color: #ffca28; */ --card-back-color: #e5b8b7; - --card-border-color: #e8b825; } + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } .card.error { - --card-back-color: #b71c1c; - --card-fore-color: #f8f8f8; - --card-border-color: #a71a1a; } + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } .card > .sectione.dark { - --card-back-color: #e0e0e0; } + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } .card > .sectione.double-padded { padding: calc(1.5 * var(--universal-padding)); } @@ -637,12 +636,12 @@ a { */ /* Input_control module CSS variable definitions */ :root { - --form-back-color: #f0f0f0; - --form-fore-color: #111; - --form-border-color: #ddd; - --input-back-color: #f8f8f8; - --input-fore-color: #111; - --input-border-color: #ddd; + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; --input-focus-color: #0288d1; --input-invalid-color: #d32f2f; --button-back-color: #e2e2e2; @@ -655,13 +654,13 @@ a { form { background: var(--form-back-color); color: var(--form-fore-color); - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); padding: calc(2 * var(--universal-padding)) var(--universal-padding); } fieldset { - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 4); padding: var(--universal-padding); } @@ -671,7 +670,7 @@ legend { display: table; max-width: 100%; white-space: normal; - font-weight: 700; + font-weight: 500; padding: calc(var(--universal-padding) / 2); } label { @@ -716,7 +715,7 @@ input:not([type]), [type="text"], [type="email"], [type="number"], [type="search box-sizing: border-box; background: var(--input-back-color); color: var(--input-fore-color); - border: 0.0625rem solid var(--input-border-color); + border: 0.0714285714rem solid var(--input-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 2); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } @@ -763,8 +762,8 @@ option { [type="radio"]:checked:before { border-radius: 100%; content: ''; - top: calc(0.0625rem + var(--universal-padding) / 2); - left: calc(0.0625rem + var(--universal-padding) / 2); + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); background: var(--input-fore-color); width: 0.5rem; height: 0.5rem; } @@ -793,7 +792,7 @@ a[role="button"], label[role="button"], [role="button"] { display: inline-block; background: var(--button-back-color); color: var(--button-fore-color); - border: 0.0625rem solid var(--button-border-color); + border: 0.0714285714rem solid var(--button-border-color); border-radius: var(--universal-border-radius); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); @@ -814,7 +813,7 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d .button-group { display: flex; - border: 0.0625rem solid var(--button-group-border-color); + border: 0.0714285714rem solid var(--button-group-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { @@ -826,13 +825,13 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d border-radius: 0; box-shadow: none; } .button-group > :not(:first-child) { - border-left: 0.0625rem solid var(--button-group-border-color); } + border-left: 0.0714285714rem solid var(--button-group-border-color); } @media screen and (max-width: 499px) { .button-group { flex-direction: column; } .button-group > :not(:first-child) { border: 0; - border-top: 0.0625rem solid var(--button-group-border-color); } } + border-top: 0.0714285714rem solid var(--button-group-border-color); } } /* Custom elements for forms and input elements. @@ -874,29 +873,29 @@ button.large, [type="button"].large, [type="submit"].large, [type="reset"].large */ /* Navigation module CSS variable definitions */ :root { - --header-back-color: #f8f8f8; - --header-hover-back-color: #f0f0f0; - --header-fore-color: #444; - --header-border-color: #ddd; - --nav-back-color: #f8f8f8; - --nav-hover-back-color: #f0f0f0; - --nav-fore-color: #444; - --nav-border-color: #ddd; - --nav-link-color: #0277bd; - --footer-fore-color: #444; - --footer-back-color: #f8f8f8; - --footer-border-color: #ddd; - --footer-link-color: #0277bd; - --drawer-back-color: #f8f8f8; - --drawer-hover-back-color: #f0f0f0; - --drawer-border-color: #ddd; - --drawer-close-color: #444; } + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } header { - height: 3.1875rem; + height: 2.75rem; background: var(--header-back-color); color: var(--header-fore-color); - border-bottom: 0.0625rem solid var(--header-border-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); padding: calc(var(--universal-padding) / 4) 0; white-space: nowrap; overflow-x: auto; @@ -927,7 +926,7 @@ header { nav { background: var(--nav-back-color); color: var(--nav-fore-color); - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } nav * { @@ -946,10 +945,10 @@ nav { nav .sublink-1:before { position: absolute; left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } nav .sublink-2 { position: relative; @@ -957,16 +956,16 @@ nav { nav .sublink-2:before { position: absolute; left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } footer { background: var(--footer-back-color); color: var(--footer-fore-color); - border-top: 0.0625rem solid var(--footer-border-color); + border-top: 0.0714285714rem solid var(--footer-border-color); padding: calc(2 * var(--universal-padding)) var(--universal-padding); font-size: 0.875rem; } footer a, footer a:visited { @@ -1013,7 +1012,7 @@ footer.sticky { height: 100vh; overflow-y: auto; background: var(--drawer-back-color); - border: 0.0625rem solid var(--drawer-border-color); + border: 0.0714285714rem solid var(--drawer-border-color); border-radius: 0; margin: 0; z-index: 1110; @@ -1060,38 +1059,36 @@ footer.sticky { */ /* Table module CSS variable definitions. */ :root { - --table-border-color: #aaa; - --table-border-separator-color: #666; - --table-head-back-color: #e6e6e6; - --table-head-fore-color: #111; - --table-body-back-color: #f8f8f8; - --table-body-fore-color: #111; - --table-body-alt-back-color: #eee; } + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } table { border-collapse: separate; border-spacing: 0; - : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + margin: 0; display: flex; flex: 0 1 auto; flex-flow: row wrap; padding: var(--universal-padding); - padding-top: 0; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + padding-top: 0; } table caption { - font-size: 1.25 * rem; + font-size: 1rem; margin: calc(2 * var(--universal-margin)) 0; max-width: 100%; - flex: 0 0 100%; - text-align: left;} + flex: 0 0 100%; } table thead, table tbody { display: flex; flex-flow: row wrap; - border: 0.0625rem solid var(--table-border-color); } + border: 0.0714285714rem solid var(--table-border-color); } table thead { z-index: 999; border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0625rem solid var(--table-border-separator-color); } + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } table tbody { border-top: 0; margin-top: calc(0 - var(--universal-margin)); @@ -1109,11 +1106,11 @@ table { table td { background: var(--table-body-back-color); color: var(--table-body-fore-color); - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table:not(.horizontal) { overflow: auto; - max-height: 850px; } + max-height: 100%; } table:not(.horizontal) thead, table:not(.horizontal) tbody { max-width: 100%; flex: 0 0 100%; } @@ -1134,32 +1131,33 @@ table.horizontal { border: 0; } table.horizontal thead, table.horizontal tbody { border: 0; + flex: .2 0 0; flex-flow: row nowrap; } table.horizontal tbody { overflow: auto; justify-content: space-between; - flex: 1 0 0; - margin-left: calc( 4 * var(--universal-margin)); + flex: .8 0 0; + margin-left: 0; padding-bottom: calc(var(--universal-padding) / 4); } table.horizontal tr { flex-direction: column; flex: 1 0 auto; } table.horizontal th, table.horizontal td { - width: 100%; + width: auto; border: 0; - border-bottom: 0.0625rem solid var(--table-border-color); } + border-bottom: 0.0714285714rem solid var(--table-border-color); } table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { border-top: 0; } table.horizontal th { text-align: right; - border-left: 0.0625rem solid var(--table-border-color); - border-right: 0.0625rem solid var(--table-border-separator-color); } + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } table.horizontal thead tr:first-child { padding-left: 0; } table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td { - border-right: 0.0625rem solid var(--table-border-color); } + border-right: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td:first-child { border-top-right-radius: 0.25rem; } table.horizontal tbody tr:last-child td:last-child { @@ -1191,12 +1189,12 @@ table.horizontal { display: table-row-group; } table tr, table.horizontal tr { display: block; - border: 0.0625rem solid var(--table-border-color); + border: 0.0714285714rem solid var(--table-border-color); border-radius: var(--universal-border-radius); - background: #fafafa; + background: #ffffff; padding: var(--universal-padding); margin: var(--universal-margin); - margin-bottom: calc(2 * var(--universal-margin)); } + margin-bottom: calc(1 * var(--universal-margin)); } table th, table td, table.horizontal th, table.horizontal td { width: auto; } table td, table.horizontal td { @@ -1211,9 +1209,6 @@ table.horizontal { border-top: 0; } table tbody tr:last-child td, table.horizontal tbody tr:last-child td { border-right: 0; } } -:root { - --table-body-alt-back-color: #eee; } - table tr:nth-of-type(2n) > td { background: var(--table-body-alt-back-color); } @@ -1234,8 +1229,8 @@ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focu */ /* Contextual module CSS variable definitions */ :root { - --mark-back-color: #0277bd; - --mark-fore-color: #fafafa; } + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } mark { background: var(--mark-back-color); @@ -1243,11 +1238,11 @@ mark { font-size: 0.95em; line-height: 1em; border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } mark.inline-block { display: inline-block; font-size: 1em; - line-height: 1.5; + line-height: 1.4; padding: calc(var(--universal-padding) / 2) var(--universal-padding); } :root { @@ -1314,8 +1309,8 @@ mark { :root { --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #444; - --modal-close-hover-color: #f0f0f0; } + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } [type="checkbox"].modal { height: 1px; @@ -1368,13 +1363,14 @@ mark { z-index: 1211; } :root { - --collapse-label-back-color: #e8e8e8; - --collapse-label-fore-color: #212121; - --collapse-label-hover-back-color: #f0f0f0; - --collapse-selected-label-back-color: #ececec; - --collapse-border-color: #ddd; - --collapse-content-back-color: #fafafa; - --collapse-selected-label-border-color: #0277bd; } + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } .collapse { width: calc(100% - 2 * var(--universal-margin)); @@ -1395,13 +1391,13 @@ mark { .collapse > label { flex-grow: 1; display: inline-block; - height: 1.5rem; + height: 1.25rem; cursor: pointer; - transition: background 0.3s; + transition: background 0.2s; color: var(--collapse-label-fore-color); background: var(--collapse-label-back-color); - border: 0.0625rem solid var(--collapse-border-color); - padding: calc(1.5 * var(--universal-padding)); } + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } .collapse > label:hover, .collapse > label:focus { background: var(--collapse-label-hover-back-color); } .collapse > label + div { @@ -1418,7 +1414,7 @@ mark { max-height: 1px; } .collapse > :checked + label { background: var(--collapse-selected-label-back-color); - border-bottom-color: var(--collapse-selected-label-border-color); } + border-color: var(--collapse-selected-label-border-color); } .collapse > :checked + label + div { box-sizing: border-box; position: relative; @@ -1427,13 +1423,13 @@ mark { overflow: auto; margin: 0; background: var(--collapse-content-back-color); - border: 0.0625rem solid var(--collapse-border-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); border-top: 0; padding: var(--universal-padding); clip: auto; -webkit-clip-path: inset(0%); clip-path: inset(0%); - max-height: 850px; } + max-height: 100%; } .collapse > label:not(:first-of-type) { border-top: 0; } .collapse > label:first-of-type { @@ -1450,11 +1446,8 @@ mark { /* Custom elements for contextual background elements, toasts and tooltips. */ -mark.secondary { - --mark-back-color: #d32f2f; } - mark.tertiary { - --mark-back-color: #308732; } + --mark-back-color: #3cb4e6; } mark.tag { padding: calc(var(--universal-padding)/2) var(--universal-padding); @@ -1465,7 +1458,7 @@ mark.tag { */ /* Progress module CSS variable definitions */ :root { - --progress-back-color: #ddd; + --progress-back-color: #3cb4e6; --progress-fore-color: #555; } progress { @@ -1558,45 +1551,53 @@ span[class^='icon-'] { filter: invert(100%); } span.icon-alert { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } span.icon-bookmark { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-calendar { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-credit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-edit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } span.icon-link { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } span.icon-help { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } span.icon-home { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-info { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } span.icon-lock { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } span.icon-mail { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-location { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-phone { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-rss { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-search { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } span.icon-settings { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 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r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } span.icon-cart { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } span.icon-upload { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } /* Definitions for utilities and helper classes. @@ -1604,7 +1605,7 @@ span.icon-user { /* Utility module CSS variable definitions */ :root { --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } .hidden { display: none !important; } @@ -1622,7 +1623,7 @@ span.icon-user { overflow: hidden !important; } .bordered { - border: 0.0625rem solid var(--generic-border-color) !important; } + border: 0.0714285714rem solid var(--generic-border-color) !important; } .rounded { border-radius: var(--universal-border-radius) !important; } @@ -1697,4 +1698,14 @@ span.icon-user { clip-path: inset(100%) !important; overflow: hidden !important; } } -/*# sourceMappingURL=mini-default.css.map */ +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/st_logo.png b/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/st_logo.png deleted file mode 100644 index 8b80057fd3a454a97de1c9d732b7fede82c83227..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 18616 zcmbTd^-~<*6D~X~?jgaQV8LAj0X_tm1Ydk1xVy{Z3GPmS;IP2r4oh%%cMl#Qcz~Pl zz5l>lZ`GVRHB&V|boY7A^z(F|Z=Y4=aIwg-006*MkpHOuZ?5<^0x;12-SsK9!v0Mt zmQpHG08kT${nrHb-!rC@ysj$%ki7ceKq56ESOEZeJ%x`_nqEey{^(v>eK${gL>pJ% zX8+KBAR_W-jhDrs{egi|sP<73DP`UFoa(>xj;8qknEx2bL~2@t%3k>}hnl@CWQrW@ zqfK>@e3$sL-m%ftg0YAkk!@=P!Ognuz(zhb|Tux{FeX<<7(5oLVU8=W*sUZ*$TqlSb6o1O0a zzeP#ZW!;?#>0N5v?0D|q?mzD8-<^@1V0FH{fY}2A9ooXbylcB6Y>PVo4nMxLi|AWA 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From 1e68ba4bb285dce9c834c6e5743ccc825a65645a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 29 Nov 2023 14:30:45 +0100 Subject: [PATCH 57/83] chore(spi): update library version and header Since it was fully reworked. Signed-off-by: Frederic Pillon --- libraries/SPI/library.properties | 4 +-- libraries/SPI/src/utility/spi_com.c | 47 ++++++----------------------- libraries/SPI/src/utility/spi_com.h | 46 ++++++---------------------- 3 files changed, 22 insertions(+), 75 deletions(-) diff --git a/libraries/SPI/library.properties b/libraries/SPI/library.properties index 0edf297586..a4bdcbd0e0 100644 --- a/libraries/SPI/library.properties +++ b/libraries/SPI/library.properties @@ -1,6 +1,6 @@ name=SPI -version=1.0.0 -author=Arduino, Wi6Labs +version=1.1.0 +author=Arduino, Frederic Pillon maintainer=stm32duino sentence=Enables the communication with devices that use the Serial Peripheral Interface (SPI) Bus. paragraph=This library is based on the official Arduino SPI library and adapted to STM32 boards. diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index b92b44aea9..4adeb9d488 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -1,40 +1,13 @@ -/** - ****************************************************************************** - * @file spi_com.c - * @author WI6LABS - * @version V1.0.0 - * @date 01-August-2016 - * @brief provide the SPI interface - * - ****************************************************************************** - * @attention - * - *

        © COPYRIGHT(c) 2016 STMicroelectronics

        - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ +/* + * Copyright (c) 2016 Frederic Pillon for + * STMicroelectronics. All right reserved. + * Interface utility of the spi module for arduino. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + */ #include "wiring_time.h" #include "core_debug.h" #include "stm32_def.h" diff --git a/libraries/SPI/src/utility/spi_com.h b/libraries/SPI/src/utility/spi_com.h index c6e287b8d5..4d145ff7fd 100644 --- a/libraries/SPI/src/utility/spi_com.h +++ b/libraries/SPI/src/utility/spi_com.h @@ -1,39 +1,13 @@ -/** - ****************************************************************************** - * @file spi_com.h - * @author WI6LABS - * @version V1.0.0 - * @date 01-August-2016 - * @brief Header for spi module - ****************************************************************************** - * @attention - * - *

        © COPYRIGHT(c) 2016 STMicroelectronics

        - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ +/* + * Copyright (c) 2016 Frederic Pillon for + * STMicroelectronics. All right reserved. + * Header utility of the spi module for arduino. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __SPI_COM_H From 08ab4549b71076c8fc80ee0b1d0e557f099e6e55 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 29 Nov 2023 14:20:39 +0100 Subject: [PATCH 58/83] chore: bump release version to 2.7.1 Signed-off-by: Frederic Pillon --- README.md | 2 +- cores/arduino/stm32/stm32_def.h | 6 +++--- platform.txt | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index e0da18c1b0..516b847f7c 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,7 @@ [![GitHub release](https://img.shields.io/github/release/stm32duino/Arduino_Core_STM32.svg)](https://github.com/stm32duino/Arduino_Core_STM32/releases/latest) ![GitHub All Releases](https://img.shields.io/github/downloads/stm32duino/Arduino_Core_STM32/total.svg?label=downloads%20since%201.4.0) -[![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/2.7.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/2.7.0...main) +[![GitHub commits since latest release](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/latest/main)](https://github.com/stm32duino/Arduino_Core_STM32/compare/2.7.1...main) * [Introduction](https://github.com/stm32duino/Arduino_Core_STM32#Introduction)
        diff --git a/cores/arduino/stm32/stm32_def.h b/cores/arduino/stm32/stm32_def.h index 52a27ff051..3292b0d661 100644 --- a/cores/arduino/stm32/stm32_def.h +++ b/cores/arduino/stm32/stm32_def.h @@ -6,15 +6,15 @@ * @brief STM32 core version number */ #define STM32_CORE_VERSION_MAJOR (0x02U) /*!< [31:24] major version */ -#define STM32_CORE_VERSION_MINOR (0x08U) /*!< [23:16] minor version */ -#define STM32_CORE_VERSION_PATCH (0x00U) /*!< [15:8] patch version */ +#define STM32_CORE_VERSION_MINOR (0x07U) /*!< [23:16] minor version */ +#define STM32_CORE_VERSION_PATCH (0x01U) /*!< [15:8] patch version */ /* * Extra label for development: * 0: official release * [1-9]: release candidate * F[0-9]: development */ -#define STM32_CORE_VERSION_EXTRA (0xF0U) /*!< [7:0] extra version */ +#define STM32_CORE_VERSION_EXTRA (0x00U) /*!< [7:0] extra version */ #define STM32_CORE_VERSION ((STM32_CORE_VERSION_MAJOR << 24U)\ |(STM32_CORE_VERSION_MINOR << 16U)\ |(STM32_CORE_VERSION_PATCH << 8U )\ diff --git a/platform.txt b/platform.txt index 70da3b5774..b4fbb03a97 100644 --- a/platform.txt +++ b/platform.txt @@ -5,7 +5,7 @@ # https://arduino.github.io/arduino-cli/latest/platform-specification/ name=STM32 boards groups (Board to be selected from Tools submenu 'Board part number') -version=2.8.0-dev +version=2.7.1 # STM compile variables # ---------------------- From 64bea5ce8e8264a1af66ffa1bbe78443f08389a6 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 16 Nov 2023 16:15:56 +0100 Subject: [PATCH 59/83] chore: update core version to 2.8.0-dev (0x020800F0) Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32_def.h | 6 +++--- platform.txt | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/cores/arduino/stm32/stm32_def.h b/cores/arduino/stm32/stm32_def.h index 3292b0d661..52a27ff051 100644 --- a/cores/arduino/stm32/stm32_def.h +++ b/cores/arduino/stm32/stm32_def.h @@ -6,15 +6,15 @@ * @brief STM32 core version number */ #define STM32_CORE_VERSION_MAJOR (0x02U) /*!< [31:24] major version */ -#define STM32_CORE_VERSION_MINOR (0x07U) /*!< [23:16] minor version */ -#define STM32_CORE_VERSION_PATCH (0x01U) /*!< [15:8] patch version */ +#define STM32_CORE_VERSION_MINOR (0x08U) /*!< [23:16] minor version */ +#define STM32_CORE_VERSION_PATCH (0x00U) /*!< [15:8] patch version */ /* * Extra label for development: * 0: official release * [1-9]: release candidate * F[0-9]: development */ -#define STM32_CORE_VERSION_EXTRA (0x00U) /*!< [7:0] extra version */ +#define STM32_CORE_VERSION_EXTRA (0xF0U) /*!< [7:0] extra version */ #define STM32_CORE_VERSION ((STM32_CORE_VERSION_MAJOR << 24U)\ |(STM32_CORE_VERSION_MINOR << 16U)\ |(STM32_CORE_VERSION_PATCH << 8U )\ diff --git a/platform.txt b/platform.txt index b4fbb03a97..70da3b5774 100644 --- a/platform.txt +++ b/platform.txt @@ -5,7 +5,7 @@ # https://arduino.github.io/arduino-cli/latest/platform-specification/ name=STM32 boards groups (Board to be selected from Tools submenu 'Board part number') -version=2.7.1 +version=2.8.0-dev # STM compile variables # ---------------------- From b149a92d074cbf3ac557317a665a0d971996691a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 5 Dec 2023 11:42:59 +0100 Subject: [PATCH 60/83] feat(usb): allow USB PID to be 0x0000 Fixes #2215 Signed-off-by: Frederic Pillon --- cores/arduino/stm32/usb/usbd_desc.c | 49 ++++++++++++++++++++--------- platform.txt | 5 +-- 2 files changed, 37 insertions(+), 17 deletions(-) diff --git a/cores/arduino/stm32/usb/usbd_desc.c b/cores/arduino/stm32/usb/usbd_desc.c index 651bb9cfd7..11681c8b04 100644 --- a/cores/arduino/stm32/usb/usbd_desc.c +++ b/cores/arduino/stm32/usb/usbd_desc.c @@ -26,24 +26,43 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* USB VID and PID: Either both or neither must be specified. If not - * specified, default to the ST VID, with a PID assigned to HID or a PID - * assigned to CDC devices. */ -#if !USBD_PID && !USBD_VID - // Undef the default zero values - #undef USBD_PID +/* USB VID and PID have to be specified to correct values. + * They can be defined thanks: + * - boards.txt: *.build.vid or *.build.pid + * - build_opt.h: define CUSTOM_USBD_VID or CUSTOM_USBD_PID + * Else if not defined or specified, default to the ST VID, + * with PID assigned to HID or CDC devices. + */ +#if !defined(USBD_VID) || USBD_VID == 0 + // Undef the default definition #undef USBD_VID - // Define default values, based on the USB class used - #define USBD_VID 0x0483 - #if defined(USBD_USE_HID_COMPOSITE) - #define USBD_PID 0x5711 - #elif defined(USBD_USE_CDC) - #define USBD_PID 0x5740 + #if defined(CUSTOM_USBD_VID) + #define USBD_VID CUSTOM_USBD_VID + #else + // Define default values + #define USBD_VID 0x0483 + #endif +#endif /* USBD_VID */ + +#if !defined(USBD_PID) || USBD_PID == -1 + // Undef the default definition + #undef USBD_PID + #if defined(CUSTOM_USBD_PID) + #define USBD_PID CUSTOM_USBD_PID + #else + // Define default values, based on the USB class used + #if defined(USBD_USE_HID_COMPOSITE) + #define USBD_PID 0x5711 + #elif defined(USBD_USE_CDC) + #define USBD_PID 0x5740 + #else + #error "USB PID not specified" + #endif #endif -#endif /* !USBD_PID && !USBD_VID */ +#endif /* USBD_VID */ -#if !USBD_VID || !USBD_PID - #error "USB VID or PID not specified" +#if USBD_VID == 0 + #error "USB VID not properly specified" #endif /* Manufacturer string: Use the specified string if specified, guess diff --git a/platform.txt b/platform.txt index 70da3b5774..31fd90c28c 100644 --- a/platform.txt +++ b/platform.txt @@ -82,10 +82,11 @@ compiler.arm.cmsis.c.flags="-I{runtime.tools.CMSIS-5.9.0.path}/CMSIS/Core/Includ build.usb_flags=-DUSBCON {build.usb_speed} -DUSBD_VID={build.vid} -DUSBD_PID={build.pid} -DHAL_PCD_MODULE_ENABLED # Specify defaults for vid/pid, since an empty value is impossible to -# detect in the preprocessor, but a 0 can be checked for. +# detect in the preprocessor, but a 0 can be checked for vid and -1 +# for pid (can be 0). # Boards should specify either both, or neither of these. build.vid=0 -build.pid=0 +build.pid=-1 # To customize the USB manufacturer or product string, must add defines # for them, e.g.: From 63d30964d41809b3f704f0cab8c5b64870fdcc0d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 6 Dec 2023 15:39:12 +0100 Subject: [PATCH 61/83] feat(wire): disable clock when deinit Signed-off-by: Frederic Pillon --- libraries/Wire/src/utility/twi.c | 43 ++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/libraries/Wire/src/utility/twi.c b/libraries/Wire/src/utility/twi.c index a4a2539f7c..fbaf092550 100644 --- a/libraries/Wire/src/utility/twi.c +++ b/libraries/Wire/src/utility/twi.c @@ -804,6 +804,49 @@ void i2c_deinit(i2c_t *obj) HAL_NVIC_DisableIRQ(obj->irqER); #endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx */ HAL_I2C_DeInit(&(obj->handle)); + // Reset I2Cx and disable clock +#if defined I2C1_BASE + if (obj->i2c == I2C1) { + __HAL_RCC_I2C1_FORCE_RESET(); + __HAL_RCC_I2C1_RELEASE_RESET(); + __HAL_RCC_I2C1_CLK_DISABLE(); + } +#endif // I2C1_BASE +#if defined I2C2_BASE + if (obj->i2c == I2C2) { + __HAL_RCC_I2C2_FORCE_RESET(); + __HAL_RCC_I2C2_RELEASE_RESET(); + __HAL_RCC_I2C2_CLK_DISABLE(); + } +#endif // I2C2_BASE +#if defined I2C3_BASE + if (obj->i2c == I2C3) { + __HAL_RCC_I2C3_FORCE_RESET(); + __HAL_RCC_I2C3_RELEASE_RESET(); + __HAL_RCC_I2C3_CLK_DISABLE(); + } +#endif // I2C3_BASE +#if defined I2C4_BASE + if (obj->i2c == I2C4) { + __HAL_RCC_I2C4_FORCE_RESET(); + __HAL_RCC_I2C4_RELEASE_RESET(); + __HAL_RCC_I2C4_CLK_DISABLE(); + } +#endif // I2C4_BASE +#if defined I2C5_BASE + if (obj->i2c == I2C5) { + __HAL_RCC_I2C5_FORCE_RESET(); + __HAL_RCC_I2C5_RELEASE_RESET(); + __HAL_RCC_I2C5_CLK_DISABLE(); + } +#endif // I2C5_BASE +#if defined I2C6_BASE + if (obj->i2c == I2C6) { + __HAL_RCC_I2C6_FORCE_RESET(); + __HAL_RCC_I2C6_RELEASE_RESET(); + __HAL_RCC_I2C6_CLK_DISABLE(); + } +#endif // I2C6_BASE } /** From c83db2e4f6b4b8d3bbedce67d2156a58023bc432 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 18 Dec 2023 15:34:04 +0100 Subject: [PATCH 62/83] fix(wire): reset pins to INPUT_ANALOG when deinit prevent consumption before entering in low power mode Signed-off-by: Frederic Pillon --- libraries/Wire/src/utility/twi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libraries/Wire/src/utility/twi.c b/libraries/Wire/src/utility/twi.c index fbaf092550..2f65b4a1ba 100644 --- a/libraries/Wire/src/utility/twi.c +++ b/libraries/Wire/src/utility/twi.c @@ -804,6 +804,9 @@ void i2c_deinit(i2c_t *obj) HAL_NVIC_DisableIRQ(obj->irqER); #endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx */ HAL_I2C_DeInit(&(obj->handle)); + /* Reset I2C GPIO pins as INPUT_ANALOG */ + pin_function(obj->scl, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)); + pin_function(obj->sda, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)); // Reset I2Cx and disable clock #if defined I2C1_BASE if (obj->i2c == I2C1) { From 471598d4649e8a632d732aa98583fb6cc561f769 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 2 Jan 2024 11:25:40 +0100 Subject: [PATCH 63/83] system(G0) update STM32G0xx HAL Drivers to v1.4.6 Included in STM32CubeG0 FW v1.6.2 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 341 +++----- .../Inc/stm32g0xx_hal_adc.h | 296 +++---- .../Inc/stm32g0xx_hal_adc_ex.h | 2 +- .../Inc/stm32g0xx_hal_comp.h | 189 +++-- .../Inc/stm32g0xx_hal_cortex.h | 2 + .../Inc/stm32g0xx_hal_crc.h | 2 +- .../Inc/stm32g0xx_hal_cryp.h | 29 +- .../Inc/stm32g0xx_hal_cryp_ex.h | 4 +- .../Inc/stm32g0xx_hal_dac.h | 34 +- .../Inc/stm32g0xx_hal_dac_ex.h | 6 +- .../Inc/stm32g0xx_hal_def.h | 2 + .../Inc/stm32g0xx_hal_fdcan.h | 112 +-- .../Inc/stm32g0xx_hal_flash.h | 10 +- .../Inc/stm32g0xx_hal_hcd.h | 55 +- .../Inc/stm32g0xx_hal_i2c.h | 13 +- .../Inc/stm32g0xx_hal_lptim.h | 6 +- .../Inc/stm32g0xx_hal_pcd.h | 31 +- .../Inc/stm32g0xx_hal_pwr_ex.h | 7 +- .../Inc/stm32g0xx_hal_rcc.h | 48 +- .../Inc/stm32g0xx_hal_rng.h | 6 +- .../Inc/stm32g0xx_hal_rtc.h | 24 +- .../Inc/stm32g0xx_hal_rtc_ex.h | 52 +- .../Inc/stm32g0xx_hal_smartcard_ex.h | 2 +- .../Inc/stm32g0xx_hal_smbus.h | 6 +- .../Inc/stm32g0xx_hal_spi_ex.h | 2 +- .../Inc/stm32g0xx_hal_tim.h | 54 +- .../Inc/stm32g0xx_hal_tim_ex.h | 146 ++-- .../Inc/stm32g0xx_hal_uart_ex.h | 2 +- .../Inc/stm32g0xx_hal_usart.h | 2 +- .../Inc/stm32g0xx_hal_usart_ex.h | 2 +- .../Inc/stm32g0xx_hal_wwdg.h | 2 +- .../Inc/stm32g0xx_ll_adc.h | 731 ++++++++-------- .../Inc/stm32g0xx_ll_comp.h | 115 +-- .../Inc/stm32g0xx_ll_crc.h | 22 +- .../Inc/stm32g0xx_ll_dac.h | 66 +- .../Inc/stm32g0xx_ll_dma.h | 136 +-- .../Inc/stm32g0xx_ll_dmamux.h | 122 +-- .../Inc/stm32g0xx_ll_i2c.h | 129 +-- .../Inc/stm32g0xx_ll_lptim.h | 24 +- .../Inc/stm32g0xx_ll_lpuart.h | 24 +- .../Inc/stm32g0xx_ll_pwr.h | 4 +- .../Inc/stm32g0xx_ll_rcc.h | 20 +- .../Inc/stm32g0xx_ll_rng.h | 21 +- .../Inc/stm32g0xx_ll_rtc.h | 20 +- .../Inc/stm32g0xx_ll_system.h | 12 +- .../Inc/stm32g0xx_ll_tim.h | 113 ++- .../Inc/stm32g0xx_ll_usart.h | 34 +- .../Inc/stm32g0xx_ll_usb.h | 137 +-- .../Inc/stm32g0xx_ll_utils.h | 2 +- .../Inc/stm32g0xx_ll_wwdg.h | 12 +- .../STM32G0xx_HAL_Driver/Release_Notes.html | 285 +++++-- .../STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c | 5 +- .../Src/stm32g0xx_hal_adc.c | 133 +-- .../Src/stm32g0xx_hal_adc_ex.c | 29 +- .../Src/stm32g0xx_hal_cec.c | 4 +- .../Src/stm32g0xx_hal_comp.c | 111 +-- .../Src/stm32g0xx_hal_cortex.c | 83 +- .../Src/stm32g0xx_hal_crc.c | 4 +- .../Src/stm32g0xx_hal_crc_ex.c | 79 +- .../Src/stm32g0xx_hal_cryp.c | 785 +++++++++--------- .../Src/stm32g0xx_hal_cryp_ex.c | 8 +- .../Src/stm32g0xx_hal_dac.c | 152 ++-- .../Src/stm32g0xx_hal_dac_ex.c | 100 ++- .../Src/stm32g0xx_hal_exti.c | 6 +- .../Src/stm32g0xx_hal_fdcan.c | 154 ++-- .../Src/stm32g0xx_hal_flash.c | 26 +- .../Src/stm32g0xx_hal_flash_ex.c | 4 +- .../Src/stm32g0xx_hal_hcd.c | 84 +- .../Src/stm32g0xx_hal_i2c.c | 667 +++++++++++---- .../Src/stm32g0xx_hal_irda.c | 56 +- .../Src/stm32g0xx_hal_lptim.c | 22 +- .../Src/stm32g0xx_hal_pcd.c | 56 +- .../Src/stm32g0xx_hal_pwr_ex.c | 4 +- .../Src/stm32g0xx_hal_rcc.c | 73 +- .../Src/stm32g0xx_hal_rng.c | 29 +- .../Src/stm32g0xx_hal_rtc.c | 4 +- .../Src/stm32g0xx_hal_smartcard.c | 27 +- .../Src/stm32g0xx_hal_smbus.c | 55 +- .../Src/stm32g0xx_hal_spi.c | 135 ++- .../Src/stm32g0xx_hal_spi_ex.c | 2 +- .../Src/stm32g0xx_hal_tim.c | 148 ++-- .../Src/stm32g0xx_hal_tim_ex.c | 66 +- .../Src/stm32g0xx_hal_uart.c | 206 +++-- .../Src/stm32g0xx_hal_uart_ex.c | 46 +- .../Src/stm32g0xx_hal_usart.c | 25 +- .../Src/stm32g0xx_hal_wwdg.c | 1 - .../Src/stm32g0xx_ll_adc.c | 69 +- .../Src/stm32g0xx_ll_comp.c | 15 +- .../Src/stm32g0xx_ll_crc.c | 2 +- .../Src/stm32g0xx_ll_dac.c | 77 +- .../Src/stm32g0xx_ll_i2c.c | 4 +- .../Src/stm32g0xx_ll_lptim.c | 5 +- .../Src/stm32g0xx_ll_lpuart.c | 5 +- .../Src/stm32g0xx_ll_rng.c | 2 +- .../Src/stm32g0xx_ll_tim.c | 41 +- .../Src/stm32g0xx_ll_usart.c | 15 +- .../Src/stm32g0xx_ll_usb.c | 75 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 98 files changed, 4131 insertions(+), 3088 deletions(-) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 934f1f971b..3caddb5298 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,16 +37,12 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -107,11 +103,6 @@ extern "C" { #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ -#if defined(STM32U5) -#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES -#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES -#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 -#endif /* STM32U5 */ /** * @} @@ -140,7 +131,8 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) @@ -214,6 +206,8 @@ extern "C" { #endif #endif + + /** * @} */ @@ -222,11 +216,6 @@ extern "C" { * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -#if defined(STM32U5) -#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE -#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE -#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE -#endif /* STM32U5 */ /** * @} */ @@ -234,11 +223,10 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#if defined(STM32C0) -#else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ -#endif +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ /** * @} */ @@ -268,19 +256,15 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32H7) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32U5) -#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 -#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 -#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 -#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 -#endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -345,7 +329,8 @@ extern "C" { #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif @@ -423,9 +408,6 @@ extern "C" { #endif /* STM32H7 */ -#if defined(STM32U5) -#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI -#endif /* STM32U5 */ /** * @} */ @@ -505,7 +487,7 @@ extern "C" { #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) || defined(STM32C0) +#if defined(STM32G0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else @@ -522,15 +504,6 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ -#if defined(STM32U5) -#define OB_USER_nRST_STOP OB_USER_NRST_STOP -#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY -#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW -#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 -#define OB_USER_nBOOT0 OB_USER_NBOOT0 -#define OB_nBOOT0_RESET OB_NBOOT0_RESET -#define OB_nBOOT0_SET OB_NBOOT0_SET -#endif /* STM32U5 */ /** * @} @@ -574,6 +547,8 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + + /** * @} */ @@ -641,19 +616,20 @@ extern "C" { #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB */ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -670,13 +646,6 @@ extern "C" { #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -#if defined(STM32U5) -#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ -#endif /* STM32U5 */ -#if defined(STM32U5) -#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP -#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 -#endif /* STM32U5 */ /** * @} */ @@ -684,9 +653,6 @@ extern "C" { /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose * @{ */ -#if defined(STM32U5) -#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI -#endif /* STM32U5 */ /** * @} */ @@ -867,7 +833,8 @@ extern "C" { #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -933,11 +900,6 @@ extern "C" { * @} */ -#if defined(STM32U5) -#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF -#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF -#define LPTIM_CHANNEL_ALL 0x00000000U -#endif /* STM32U5 */ /** * @} */ @@ -1101,6 +1063,9 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + + + #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK @@ -1111,12 +1076,12 @@ extern "C" { #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 */ +#endif /* STM32F7 || STM32H7 || STM32L0 */ /** * @} @@ -1283,10 +1248,6 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) || defined(STM32MP2) -#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS -#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK -#endif /** * @} */ @@ -1396,30 +1357,40 @@ extern "C" { #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ @@ -1427,6 +1398,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1475,9 +1448,7 @@ extern "C" { */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ - || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ - || defined(STM32H7) || defined(STM32U5) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7) /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ @@ -1487,7 +1458,7 @@ extern "C" { * @} */ -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ @@ -1511,10 +1482,6 @@ extern "C" { * @{ */ -#if defined(STM32U5) -#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr -#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT -#endif /* STM32U5 */ /** * @} @@ -1590,7 +1557,8 @@ extern "C" { #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1599,8 +1567,10 @@ extern "C" { #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode @@ -1634,16 +1604,21 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ - )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1717,83 +1692,19 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL -#if defined (STM32U5) -#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP -#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP -#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP -#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP -#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP -#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP -#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP -#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP -#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP -#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP -#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP -#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP -#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP - -#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP -#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP -#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP - -#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP -#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP -#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP -#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP -#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP -#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP -#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP -#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP -#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP -#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP -#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP -#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP -#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP -#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP - -#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP - -#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP -#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP -#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP -#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP -#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP -#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP -#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP -#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP -#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP -#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP -#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP -#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP -#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP -#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP - -#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP -#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP -#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP -#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP -#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP -#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP -#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP -#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP - -#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY -#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY -#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY - -#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN -#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN -#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN -#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN -#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN - -#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK -#endif /** * @} */ +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ @@ -1819,7 +1730,8 @@ extern "C" { #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback @@ -2076,7 +1988,8 @@ extern "C" { #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) @@ -2248,8 +2161,10 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ /** * @} */ @@ -2408,7 +2323,9 @@ extern "C" { #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE @@ -2417,8 +2334,12 @@ extern "C" { #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 @@ -2454,8 +2375,8 @@ extern "C" { #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -2959,6 +2880,11 @@ extern "C" { #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE @@ -3423,7 +3349,8 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3535,38 +3462,7 @@ extern "C" { #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 -#if defined(STM32U5) -#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL -#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL -#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE -#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE -#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE -#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE -#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE -#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE -#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE -#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE -#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE -#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT -#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK -#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 -#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 -#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 -#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK -#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE -#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE -#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE -#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE -#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG -#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE -#endif /* STM32U5 */ + /** * @} @@ -3584,9 +3480,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ - defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32C0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3621,6 +3515,13 @@ extern "C" { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER @@ -3639,6 +3540,7 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + /** * @} */ @@ -3897,6 +3799,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h index 8b0a24db2d..190e55f81b 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h @@ -63,7 +63,7 @@ typedef struct * @brief Structure definition of ADC instance and ADC group regular. * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC - * groups regular and injected): ClockPrescaler, Resolution, DataAlign, + * groups regular and injected): ClockPrescaler, Resolution, DataAlign, * ScanConvMode, EOCSelection, LowPowerAutoWait. * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. @@ -74,7 +74,7 @@ typedef struct * group regular. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another - * parameter (which fulfills the ADC state condition) on the fly). + * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { @@ -373,8 +373,8 @@ typedef struct respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 - LSB are ignored. */ - /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). */ @@ -385,8 +385,8 @@ typedef struct respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 - LSB are ignored.*/ - /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).*/ @@ -407,7 +407,7 @@ typedef struct /* States of ADC global scope */ #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to internal process (ex : calibration) */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy from internal process (ex : calibration, ...) */ #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ /* States of ADC errors */ @@ -538,37 +538,38 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock - without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler - configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */ + without prescaler. This configuration must be enabled only if PCLK has + a 50% duty clock cycle (APB prescaler configured inside the RCC must + be bypassed and the system clock must by 50% duty cycle) */ #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock - with prescaler division by 2 */ + with prescaler division by 2 */ #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock - with prescaler division by 4 */ + with prescaler division by 4 */ #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without - prescaler */ + prescaler */ #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler - division by 2 */ + division by 2 */ #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler - division by 4 */ + division by 4 */ #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler - division by 6 */ + division by 6 */ #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler - division by 8 */ + division by 8 */ #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler - division by 10 */ + division by 10 */ #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler - division by 12 */ + division by 12 */ #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler - division by 16 */ + division by 16 */ #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler - division by 32 */ + division by 32 */ #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler - division by 64 */ + division by 64 */ #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler - division by 128 */ + division by 128 */ #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler - division by 256 */ + division by 256 */ /** * @} */ @@ -588,9 +589,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned - (alignment on data register LSB bit 0)*/ + (alignment on data register LSB bit 0)*/ #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned - (alignment on data register MSB bit 15)*/ + (alignment on data register MSB bit 15)*/ /** * @} */ @@ -613,18 +614,20 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /* warned of change of setting choices with assert check. */ /* Sequencer set to fully configurable */ #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: - only the rank 1 is enabled (no scan sequence on several ranks) */ + only the rank 1 is enabled (no scan sequence on several ranks) */ #define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: - sequencer length and each rank affectation to a channel are configurable. */ + sequencer length and each rank affectation to a channel are configurable. */ /* Sequencer set to not fully configurable */ #define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: - sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, - channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */ + sequencer length and each rank affectation to a channel are fixed by + channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction forward: from channel 0 to channel 18 */ #define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \ | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: - sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, - channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */ + sequencer length and each rank affectation to a channel are fixed by + channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction backward: from channel 18 to channel 0 */ #define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */ #define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */ @@ -636,35 +639,32 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ /* ADC group regular trigger sources for all ADC instances */ -#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< Software start. */ -/** ADC group regular conversion trigger from external peripheral */ -#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< TIM1 TRGO. Trigger edge set to - rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< TIM1 channel 4 event (capture - compare: input capture or output - capture). Trigger edge set to - rising edge (default setting). */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion + trigger software start */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 TRGO. */ +#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 4 event (capture compare). */ #if defined(TIM2) -#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< TIM2 TRGO. Trigger edge set to - rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 TRGO. */ #endif /* TIM2 */ -#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< TIM3 TRGO. Trigger edge set to - rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM3 TRGO. */ #if defined(TIM4) -#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< TIM4 TRGO. Trigger edge set to - rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM4 TRGO. */ #endif /* TIM4 */ #if defined(TIM6) -#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< TIM6 TRGO. Trigger edge set to - rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM6 TRGO. */ #endif /* TIM6 */ #if defined(TIM15) -#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< TIM15 TRGO. Trigger edge set to - rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM15 TRGO. */ #endif /* TIM15 */ -#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< External interrupt line 11. Trigger - edge set to rising edge (default - setting). */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion + trigger from external peripheral: external interrupt line 11. */ /** * @} */ @@ -673,14 +673,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger - detection disabled (SW start)*/ -#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular trigger - polarity set to rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular trigger - polarity set to falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular trigger - polarity set to both rising and - falling edges */ + disabled (SW start)*/ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ /** * @} */ @@ -697,13 +696,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -/** - * @brief ADC group regular behavior in case of overrun - */ -#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of - overrun: data preserved */ -#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of - overrun: data overwritten */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case + of overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case + of overrun: data overwritten */ /** * @} */ @@ -711,24 +707,25 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ -#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of ranks in - the sequence is defined by number of channels enabled, rank - of each channel is defined by channel number (channel 0 fixed - on rank 0, channel 1 fixed on rank1, ...). - Setting relevant if parameter "ScanConvMode" is set to - sequencer not fully configurable. */ -#define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from sequencer. - Setting relevant if parameter "ScanConvMode" is set to - sequencer not fully configurable. */ - -#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ -#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ -#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ -#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ -#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ -#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ -#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ -#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of + ranks in the sequence is defined by number of channels enabled, rank of + each channel is defined by channel number (channel 0 fixed on rank 0, + channel 1 fixed on rank1, ...). + Setting relevant if parameter "ScanConvMode" is set to sequencer not fully + configurable. */ +#define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from + sequencer. + Setting relevant if parameter "ScanConvMode" is set to sequencer not fully + configurable. */ + +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ /** * @} */ @@ -747,13 +744,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ -#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ -#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ -#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ -#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ -#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ -#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ +#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ +#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ +#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ +#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ #define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ /** * @} @@ -762,35 +759,36 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number * @{ */ -#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ -#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ -#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ -#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ -#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ -#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ -#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ -#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ -#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ -#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ -#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ -#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ -#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ -#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ -#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ -#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ -#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ -#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ -#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ -#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel Internal voltage reference*/ -#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor */ -#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: - Vbat voltage through a divider ladder of - factor 1/3 to have Vbat always below Vdda. */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ +#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ +#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ +#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ +#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal + voltage reference. */ +#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor. */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage + through a divider ladder of factor 1/3 to have channel voltage always below + Vdda. */ /** * @} */ -/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number +/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number * @{ */ #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ @@ -800,14 +798,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ -/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode +/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ -#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a - regular group, single channel */ -#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to - regular group, all channels */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a regular + group single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular + group all channels */ /** * @} */ @@ -855,11 +853,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: - continuous mode (all conversions of - OVS ratio are done from 1 trigger) */ + continuous mode (all conversions of OVS ratio are done from 1 trigger) */ #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: - discontinuous mode (each conversion of - OVS ratio needs a trigger) */ + discontinuous mode (each conversion of OVS ratio needs a trigger) */ /** * @} */ @@ -903,13 +899,15 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ #define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< End of sampling interrupt source */ -#define ADC_IT_EOC ADC_IER_EOCIE /*!< End of regular conversion interrupt source */ -#define ADC_IT_EOS ADC_IER_EOSIE /*!< End of regular sequence of conversions interrupt source */ -#define ADC_IT_OVR ADC_IER_OVRIE /*!< overrun interrupt source */ -#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< Analog watchdog 2 interrupt source (additional analog watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< Analog watchdog 3 interrupt source (additional analog watchdog) */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog + watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog + watchdog) */ /** * @} */ @@ -923,9 +921,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ -#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag */ -#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag */ -#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag */ +#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ +#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ +#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ /** * @} */ @@ -1791,12 +1789,13 @@ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value - (unit: uV/DegCelsius). - * On STM32G0, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at - temperature and Vref+ defined in parameters below) (unit: mV). - * On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + (unit: uV/DegCelsius). + * On STM32G0, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at + temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32G0, refer to device datasheet parameter "V30" + (corresponding to TS_CAL1). * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) @@ -1879,7 +1878,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); @@ -1896,8 +1895,9 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, + const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); /** * @} @@ -1907,8 +1907,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h index dbf21eb4e7..b555431692 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h @@ -144,7 +144,7 @@ extern "C" { /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h index c5a5f3a154..12831e360e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h @@ -50,7 +50,9 @@ typedef struct uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP and COMP). - Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode, except for window mode with COMP2 and COMP3 (for devices featuring COMP3): it must be set from COMP3 instance. + Note: HAL COMP driver allows to set window mode from any COMP instance of the pair + of COMP instances composing window mode, except for window mode with COMP2 and COMP3 + (for devices featuring COMP3): it must be set from COMP3 instance. This parameter can be a value of @ref COMP_WindowMode */ uint32_t WindowOutput; /*!< Set window mode output. @@ -154,12 +156,31 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @} */ + /** @defgroup COMP_WindowMode COMP Window Mode * @{ */ -#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ -#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ -#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible). If used from COMP3 instance (when available), comparators instances pair COMP2 and COMP3 have their input plus connected together, the common input is COMP2 input plus (COMP3 input plus is no more accessible). */ +#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators + instances pair COMP1 and COMP2 are + independent */ +#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances + pair COMP1 and COMP2 have their input + plus connected together. + The common input is COMP1 input plus + (COMP2 input plus is no more accessible). + */ +#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE \ + | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or + COMP2 instance, comparators instances + pair COMP1 and COMP2 have their input + plus connected together, the common input + is COMP2 input plus (COMP1 input plus is + no more accessible). If used from COMP3 + instance (when available), comparators + instances pair COMP2 and COMP3 have their + input plus connected together, the common + input is COMP2 input plus (COMP3 input + plus is no more accessible). */ /** * @} */ @@ -167,19 +188,54 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_WindowOutput COMP Window output * @{ */ -#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. */ -#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). - Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ -#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). - Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ +#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are + indicating each their own state. + To know window mode state: each comparator output + must be read, if "((COMPx exclusive or COMPy) == 1)" + then monitored signal is within comparators window.*/ +#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthesized on COMP1 output: + COMP1 output is no more indicating its own state, but + global window mode state (logical high means + monitored signal is within comparators window). + Note: impacts only comparator output signal level + (COMPx_OUT propagated to GPIO, EXTI lines, + timers, ...), does not impact output digital state + of comparator (COMPx_VALUE) always reflecting each + comparator output state.*/ +#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT \ + | COMP_WINDOWMODE_COMP2) /*!< Window output synthesized on COMP2 output: + COMP2 output is no more indicating its own state, but + global window mode state (logical high means + monitored signal is within comparators window). + Note: impacts only comparator output signal level + (COMPx_OUT propagated to GPIO, EXTI lines, + timers, ...), does not impact output digital state + of comparator (COMPx_VALUE) always reflecting each + comparator output state.*/ #if defined(COMP3) -#define COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ +#define COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT) /*!< Window output synthesized on COMP3 output: + COMP3 output is no more indicating its own state, but + global window mode state (logical high means + monitored signal is within comparators window). */ #endif /* COMP3 */ -#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ +#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthesized on both comparators output + of pair of comparator selected (COMP1 and COMP2, or + COMP2 and COMP3 for devices featuring + COMP3 instance): + both comparators outputs are no more indicating their + own state, but global window mode state (logical high + means monitored signal is within comparators window). + This is a specific configuration (technically + possible but not relevant from application + point of view: + 2 comparators output used for the same signal level), + standard configuration for window mode is one of the + settings above. */ /** * @} */ + /** @defgroup COMP_PowerMode COMP power mode * @{ */ @@ -322,14 +378,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Disable the specified comparator. * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Lock the specified comparator configuration. @@ -340,14 +396,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) +#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) /** * @brief Check whether the specified comparator is locked. * @param __HANDLE__ COMP handle * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked */ -#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) +#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) /** * @} @@ -356,7 +412,6 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_Exti_Management COMP external interrupt line management * @{ */ - /** * @brief Enable the COMP1 EXTI line rising edge trigger. * @retval None @@ -385,19 +440,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - } while(0) +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ + } while(0) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - } while(0) +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ + } while(0) /** * @brief Enable the COMP1 EXTI line in interrupt mode. @@ -481,19 +536,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - } while(0) +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - } while(0) +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + } while(0) /** * @brief Enable the COMP2 EXTI line in interrupt mode. @@ -578,18 +633,18 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @retval None */ #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - } while(0) + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + } while(0) /** * @brief Disable the COMP3 EXTI line rising & falling edge trigger. * @retval None */ #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - } while(0) + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + } while(0) /** * @brief Enable the COMP3 EXTI line in interrupt mode. @@ -725,20 +780,20 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #if defined(COMP3) #define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \ -(((__INSTANCE__) == COMP3) \ - ? \ - (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ - ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) \ - :\ - (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ - ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \ - ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) \ -) + (((__INSTANCE__) == COMP3) \ + ? \ + (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) \ + :\ + (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) \ + ) #else #define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \ -(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ - ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \ - ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) + (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) #endif /* COMP3 */ #define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \ @@ -753,14 +808,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \ ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)) #define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \ @@ -773,17 +828,17 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2) \ ) /* Note: Output blanking source common to all COMP instances */ /* Macro kept for compatibility with other STM32 series */ #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)) + (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)) #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ @@ -847,7 +902,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp); /* Callback in interrupt mode */ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @@ -858,8 +913,8 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @addtogroup COMP_Exported_Functions_Group4 * @{ */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h index 0edbed105b..9a7e9a3bb2 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h @@ -272,6 +272,8 @@ void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1U) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_crc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_crc.h index 24607ffb00..0a4ddcc3c3 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_crc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_crc.h @@ -318,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h index 2dbb7f3377..290d327f50 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h @@ -53,7 +53,8 @@ typedef struct uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of @ref CRYP_Data_Type */ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. - 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */ + 128 or 256 bit key length in TinyAES + This parameter can be a value of @ref CRYP_Key_Size */ uint32_t *pKey; /*!< The key used for encryption/decryption */ uint32_t *pInitVect; /*!< The initialization vector used also as initialization counter in CTR mode */ @@ -96,7 +97,7 @@ typedef enum { HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */ HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */ -}HAL_SuspendTypeDef; +} HAL_SuspendTypeDef; #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ /** @@ -407,7 +408,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @arg CRYP_FLAG_OFNE: Output FIFO is not empty * @arg CRYP_FLAG_OFFU: Output FIFO is full * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define CRYP_FLAG_MASK 0x0000001FU @@ -434,7 +435,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @retval State of interruption (TRUE or FALSE). */ -#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR &\ + (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Check whether the specified CRYP interrupt is set or not. * @param __HANDLE__ specifies the CRYP handle. @@ -503,7 +505,8 @@ void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) @@ -520,8 +523,10 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp); */ /* encryption/decryption ***********************************/ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); @@ -579,11 +584,11 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) #define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \ - (((((ALGO) == CRYP_AES_CTR)) && \ - ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ - (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ - (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ - ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) + (((((ALGO) == CRYP_AES_CTR)) && \ + ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ + (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ + (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ + ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp_ex.h index 96da6f00e2..d87d7c5ee5 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp_ex.h @@ -73,8 +73,8 @@ extern "C" { */ /** - * @} - */ + * @} + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h index 0031d2c7e5..5059aeb8b1 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h @@ -78,19 +78,19 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; @@ -127,7 +127,7 @@ typedef struct uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ - uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . + uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral. This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode @@ -462,7 +462,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); @@ -488,8 +488,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA * @{ */ /* Peripheral Control functions ***********************************************/ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ @@ -498,8 +499,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); /** * @} @@ -535,4 +536,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #endif /* STM32G0xx_HAL_DAC_H */ - diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h index 9acc418305..908947263e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h @@ -81,6 +81,7 @@ extern "C" { * @} */ + /** * @} */ @@ -168,7 +169,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); @@ -188,7 +189,7 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); -uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); +uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel); /** * @} @@ -227,4 +228,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); #endif #endif /* STM32G0xx_HAL_DAC_EX_H */ - diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h index f6059105e7..d8963baa96 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h @@ -54,7 +54,9 @@ typedef enum /* Exported macros -----------------------------------------------------------*/ +#if !defined(UNUSED) #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ #define HAL_MAX_DELAY 0xFFFFFFFFU diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_fdcan.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_fdcan.h index afe4b727e9..ae852b6099 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_fdcan.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_fdcan.h @@ -318,53 +318,55 @@ typedef struct typedef struct { uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. - This parameter can be a value of @ref FDCAN_protocol_error_code */ + This parameter can be a value of @ref FDCAN_protocol_error_code */ uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. - This parameter can be a value of @ref FDCAN_protocol_error_code */ + This parameter can be a value of @ref FDCAN_protocol_error_code */ uint32_t Activity; /*!< Specifies the FDCAN module communication state. - This parameter can be a value of @ref FDCAN_communication_state */ + This parameter can be a value of @ref FDCAN_communication_state */ uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. This parameter can be: - 0 : The FDCAN is in Error_Active state - - 1 : The FDCAN is in Error_Passive state */ + - 1 : The FDCAN is in Error_Passive state */ uint32_t Warning; /*!< Specifies the FDCAN module warning status. This parameter can be: - - 0 : error counters (RxErrorCnt and TxErrorCnt) - are below the Error_Warning limit of 96 - - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ + - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the + Error_Warning limit of 96 + - 1 : at least one of error counters has reached the Error_Warning + limit of 96 */ uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. This parameter can be: - 0 : The FDCAN is not in Bus_Off state - - 1 : The FDCAN is in Bus_Off state */ + - 1 : The FDCAN is in Bus_Off state */ uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. This parameter can be: - 0 : Last received CAN FD message did not have its ESI flag set - - 1 : Last received CAN FD message had its ESI flag set */ + - 1 : Last received CAN FD message had its ESI flag set */ uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. This parameter can be: - 0 : Last received CAN FD message did not have its BRS flag set - - 1 : Last received CAN FD message had its BRS flag set */ + - 1 : Last received CAN FD message had its BRS flag set */ uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received - since last protocol status.This parameter can be: + since last protocol status. + This parameter can be: - 0 : No CAN FD message received - - 1 : CAN FD message received */ + - 1 : CAN FD message received */ uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. This parameter can be: - 0 : No protocol exception event occurred since last read access - - 1 : Protocol exception event occurred */ + - 1 : Protocol exception event occurred */ uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. - This parameter can be a number between 0 and 127 */ + This parameter can be a number between 0 and 127 */ } FDCAN_ProtocolStatusTypeDef; @@ -374,22 +376,24 @@ typedef struct typedef struct { uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. - This parameter can be a number between 0 and 255 */ + This parameter can be a number between 0 and 255 */ uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. - This parameter can be a number between 0 and 127 */ + This parameter can be a number between 0 and 127 */ uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. This parameter can be: - - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 - - 1 : The Receive Error Counter (RxErrorCnt) - has reached the error passive level of 128 */ + - 0 : The Receive Error Counter (RxErrorCnt) is below the error + passive level of 128 + - 1 : The Receive Error Counter (RxErrorCnt) has reached the error + passive level of 128 */ uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. This parameter can be a number between 0 and 255. - This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt - or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of - TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ + This counter is incremented each time when a FDCAN protocol error causes + the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; + the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag + FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ } FDCAN_ErrorCountersTypeDef; @@ -604,21 +608,21 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, * @{ */ #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ -#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ -#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ -#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ -#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ -#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ -#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ -#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ -#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ -#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ -#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ -#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ -#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ -#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ -#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ -#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ +#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */ /** * @} */ @@ -1040,7 +1044,7 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, * @retval None */ #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 -#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ @@ -1167,7 +1171,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h * @{ */ /* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig); HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt); @@ -1177,13 +1181,13 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint3 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); -uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod); HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); -uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter); @@ -1203,21 +1207,23 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); /* Control functions **********************************************************/ HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, - uint8_t *pTxData); -uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData); +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); -HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus); -HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); -HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); -uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); -uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); -uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); -uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus); +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters); +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); /** * @} @@ -1259,8 +1265,8 @@ void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorSt * @{ */ /* Peripheral State functions *************************************************/ -uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); -HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan); +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h index 753e6b9b28..25a316affe 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h @@ -763,8 +763,8 @@ typedef struct #endif /* FLASH_DBANK_SUPPORT */ /** - * @brief Clear the FLASH pending flags. - * @param __FLAG__ specifies the FLASH flags to clear. + * @brief Clear the FLASH pending flag. + * @param __FLAG__ specifies the FLASH flag to clear. * This parameter can be one of the following values : * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag @@ -788,12 +788,12 @@ typedef struct */ #if defined(FLASH_DBANK_SUPPORT) #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \ - else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); } \ - else if(((__FLAG__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECC2R = (1uL << ((__FLAG__) & 0x1Fu)); } \ + else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR |= (1uL << ((__FLAG__) & 0x1Fu)); } \ + else if(((__FLAG__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECC2R |= (1uL << ((__FLAG__) & 0x1Fu)); } \ } while(0U) #else #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \ - else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); } \ + else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR |= (1uL << ((__FLAG__) & 0x1Fu)); } \ } while(0U) #endif /* FLASH_DBANK_SUPPORT */ /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_hcd.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_hcd.h index 16e489c6cf..a6dd469e6b 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_hcd.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_hcd.h @@ -53,7 +53,7 @@ typedef enum HAL_HCD_STATE_TIMEOUT = 0x04 } HCD_StateTypeDef; -typedef USB_DRD_TypeDef HCD_TypeDef; +typedef USB_DRD_TypeDef HCD_TypeDef; typedef USB_DRD_CfgTypeDef HCD_InitTypeDef; typedef USB_DRD_HCTypeDef HCD_HCTypeDef; typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef; @@ -73,6 +73,7 @@ typedef enum * 8Bytes each Block 32Bit in each word */ #define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U)) + /** * @} */ @@ -89,11 +90,13 @@ typedef struct HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ + uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */ uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */ uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/ uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */ HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */ + HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ __IO uint32_t ErrorCode; /*!< HCD Error code */ @@ -202,7 +205,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); + HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num); + void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); @@ -265,6 +270,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping); +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr); + +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num); + /* Non-Blocking mode: Interrupt */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); @@ -272,8 +282,10 @@ void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); + void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd); void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd); + void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state); /** @@ -287,9 +299,11 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); + HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd); + /** * @} */ @@ -298,13 +312,14 @@ HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd); /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions * @{ */ -HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd); -HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum); -HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum); -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd); +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum); uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); + /* PMA Allocation functions **********************************************/ /** @addtogroup PMA Allocation * @{ @@ -315,13 +330,11 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num); HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); -/** - * @} - */ /** * @} */ + /** * @} */ @@ -330,6 +343,10 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_Private_Macros HCD Private Macros * @{ */ + +#define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) + /** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel * @{ */ @@ -475,11 +492,25 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); * @param bChNum channel Number. * @retval Counter value */ -__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(const HCD_TypeDef *Instance, uint16_t bChNum) +__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum) { - UNUSED(Instance); + uint32_t HostCoreSpeed; __IO uint32_t count = 10U; + /* Get Host core Speed */ + HostCoreSpeed = USB_GetHostSpeed(Instance); + + /* Count depends on device LS */ + if (HostCoreSpeed == USB_DRD_SPEED_LS) + { + count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U; + } + + if (count > 15U) + { + count = HCD_MAX(10U, (count - 15U)); + } + /* WA: few cycles for RX PMA descriptor to update */ while (count > 0U) { @@ -543,6 +574,7 @@ __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint1 return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum)); } + /** * @} */ @@ -554,6 +586,9 @@ __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint1 /** * @} */ +/** + * @} + */ #endif /* defined (USB_DRD_FS) */ #ifdef __cplusplus diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h index 9a7b222f81..cb78a18caa 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h @@ -118,8 +118,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; @@ -207,6 +205,7 @@ typedef struct __I2C_HandleTypeDef DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + HAL_LockTypeDef Lock; /*!< I2C locking object */ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ @@ -709,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); * @{ */ /* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); /** * @} @@ -804,8 +803,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ - (~I2C_CR2_RD_WRN))) + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) #define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_lptim.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_lptim.h index 4cd7723fd7..0a00928b01 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_lptim.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_lptim.h @@ -435,6 +435,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value + * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF. * @retval None * @note The ARR register can only be modified when the LPTIM instance is enabled. */ @@ -708,7 +709,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ * @{ */ /* Peripheral State functions ************************************************/ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -801,9 +802,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ - ((__AUTORELOAD__) <= 0x0000FFFFUL)) - #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) #define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd.h index d533fc47f6..78543fd34f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd.h @@ -96,8 +96,8 @@ typedef struct PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ __IO uint32_t ErrorCode; /*!< PCD Error code */ @@ -185,12 +185,12 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ - & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ &= (uint16_t)(~(__INTERRUPT__))) @@ -334,7 +334,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); /** * @} */ @@ -343,7 +343,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions * @{ */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** * @} */ @@ -411,14 +411,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_Private_Macros PCD Private Macros * @{ */ + +/* PMA RX counter */ +#ifndef PCD_RX_PMA_CNT +#define PCD_RX_PMA_CNT 10U +#endif /* PCD_RX_PMA_CNT */ + /* SetENDPOINT */ #define PCD_SET_ENDPOINT USB_DRD_SET_CHEP /* GetENDPOINT Register value*/ #define PCD_GET_ENDPOINT USB_DRD_GET_CHEP -/* ENDPOINT transfer */ -#define USB_EP0StartXfer USB_EPStartXfer /** * @brief free buffer used from the application realizing it to the line @@ -530,7 +534,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); __STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) { UNUSED(Instance); - __IO uint32_t count = 10U; + __IO uint32_t count = PCD_RX_PMA_CNT; /* WA: few cycles for RX PMA descriptor to update */ while (count > 0U) @@ -573,7 +577,7 @@ __STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(const PCD_TypeDef *Instance, uint16_t __STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) { UNUSED(Instance); - __IO uint32_t count = 10U; + __IO uint32_t count = PCD_RX_PMA_CNT; /* WA: few cycles for RX PMA descriptor to update */ while (count > 0U) @@ -593,7 +597,7 @@ __STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(const PCD_TypeDef *Instance, uint1 __STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) { UNUSED(Instance); - __IO uint32_t count = 10U; + __IO uint32_t count = PCD_RX_PMA_CNT; /* WA: few cycles for RX PMA descriptor to update */ while (count > 0U) @@ -604,6 +608,7 @@ __STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint1 return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum)); } + /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h index 432158d5bd..7a334980ce 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h @@ -592,13 +592,14 @@ void HAL_PWREx_DisablePVD(void); /* Power voltage monitoring configuration functions ***************************/ void HAL_PWREx_EnableVddIO2(void); void HAL_PWREx_DisableVddIO2(void); -void HAL_PWREx_EnableVddUSB(void); -void HAL_PWREx_DisableVddUSB(void); void HAL_PWREx_EnablePVMUSB(void); void HAL_PWREx_DisablePVMUSB(void); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); #endif /* PWR_PVM_SUPPORT */ - +#if defined(PWR_CR2_USV) +void HAL_PWREx_EnableVddUSB(void); +void HAL_PWREx_DisableVddUSB(void); +#endif /* PWR_CR2_USV */ /* Low Power modes configuration functions ************************************/ void HAL_PWREx_EnableLowPowerRunMode(void); HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h index 9093c827e4..dce1f7bbb4 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h @@ -145,9 +145,19 @@ extern "C" { ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) #if defined(RCC_MCO2_SUPPORT) -#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) ) +#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO_PA8) || \ + ((__MCOX__) == RCC_MCO_PA9) || \ + ((__MCOX__) == RCC_MCO_PD10) || \ + ((__MCOX__) == RCC_MCO_PF2) || \ + ((__MCOX__) == RCC_MCO_PA10) || \ + ((__MCOX__) == RCC_MCO_PA15) || \ + ((__MCOX__) == RCC_MCO_PB2) || \ + ((__MCOX__) == RCC_MCO_PD7)) #else -#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) +#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO_PA8) || \ + ((__MCOX__) == RCC_MCO_PA9) || \ + ((__MCOX__) == RCC_MCO_PD10) || \ + ((__MCOX__) == RCC_MCO_PF2)) #endif /* RCC_MCO2_SUPPORT */ #if defined(STM32G0C1xx) || defined(STM32G0B1xx) @@ -628,12 +638,36 @@ typedef struct /** @defgroup RCC_MCO_Index MCO Index * @{ */ -#define RCC_MCO1 0x00000000U + +/* 32 28 20 16 0 + -------------------------------- + | MCO | GPIO | GPIO | GPIO | + | Index | AF | Port | Pin | + -------------------------------*/ + +#define RCC_MCO_GPIOPORT_POS 16U +#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) +#define RCC_MCO_GPIOAF_POS 20U +#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) +#define RCC_MCO_INDEX_POS 28U +#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) +#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ +#define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) +#define RCC_MCO_PA9 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) +#define RCC_MCO_PD10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOD) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) /* Not defined for all stm32g0xx family lines */ +#define RCC_MCO_PF2 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) /* Not defined for all stm32g0xx family lines */ +#define RCC_MCO1 RCC_MCO_PA8 + #if defined(RCC_MCO2_SUPPORT) -#define RCC_MCO2 0x00000001U /*!< MCO2 index */ +#define RCC_MCO2_INDEX (0x1u << RCC_MCO_INDEX_POS) /*!< MCO2 index */ +#define RCC_MCO_PA10 (RCC_MCO2_INDEX | (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) +#define RCC_MCO_PA15 (RCC_MCO2_INDEX | (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_15) +#define RCC_MCO_PB2 (RCC_MCO2_INDEX | (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOB) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) +#define RCC_MCO_PD7 (RCC_MCO2_INDEX | (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOD) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_7) +#define RCC_MCO2 RCC_MCO_PA10 #endif /* RCC_MCO2_SUPPORT */ -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} */ @@ -2878,7 +2912,7 @@ typedef struct * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source @@ -2915,7 +2949,7 @@ typedef struct * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source - * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 sourcee + * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source * @arg @ref RCC_MCO2SOURCE_PLLCLK Main PLL clock selected as MCO2 source * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h index 9e0abafc59..10cc470709 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h @@ -315,7 +315,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); @@ -328,8 +328,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h index d15ea59308..6fbda727fd 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h @@ -484,7 +484,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * - YYYYY : Interrupt flag position in the XX register (5bits) * - XX : Interrupt status register (2bits) * - 01: ICSR register - * - 10: SR or SCR or MISR or SMISR registers + * - 10: SR or SCR or MISR registers * @{ */ #define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */ @@ -664,9 +664,9 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * This parameter can be: * @arg @ref RTC_IT_ALRA Alarm A interrupt * @arg @ref RTC_IT_ALRB Alarm B interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR)& ((__INTERRUPT__)>> 12U)) != 0U)? 1U : 0U) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12U)) != 0U) ? 1U : 0U) /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. @@ -675,7 +675,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * This parameter can be: * @arg @ref RTC_IT_ALRA Alarm A interrupt * @arg @ref RTC_IT_ALRB Alarm B interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) @@ -688,9 +688,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @arg @ref RTC_FLAG_ALRBF * @arg @ref RTC_FLAG_ALRAWF * @arg @ref RTC_FLAG_ALRBWF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (((((__HANDLE__)->Instance->SR) & (RTC_SR_ALRAF)) != 0U) ? 1U : 0U):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (((((__HANDLE__)->Instance->SR) & (RTC_SR_ALRBF)) != 0U) ? 1U : 0U):\ + ((__FLAG__) == RTC_FLAG_ALRAWF) ? (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_ALRAWF)) != 0U) ? 1U : 0U):\ + (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_ALRBWF)) != 0U) ? 1U : 0U)) /** * @brief Clear the RTC Alarms pending flags. @@ -701,8 +705,9 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @arg @ref RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ALRAF)) : \ - (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ALRBF))) +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? ((__HANDLE__)->Instance->SCR |= (RTC_SCR_CALRAF)):\ + ((__HANDLE__)->Instance->SCR |= (RTC_SCR_CALRBF))) /** * @brief Enable interrupt on the RTC Alarm associated Exti line. @@ -827,6 +832,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ RTC_DR_DU) +#define RTC_ICSR_RESERVED_MASK (RTC_ICSR_RECALPF | RTC_ICSR_INIT | RTC_ICSR_INITF | \ + RTC_ICSR_RSF | RTC_ICSR_INITS | RTC_ICSR_SHPF | \ + RTC_ICSR_WUTWF | RTC_ICSR_ALRBWF | RTC_ICSR_ALRAWF) #define RTC_INIT_MASK 0xFFFFFFFFu #define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h index 7b42f56ca3..b6472f3fbf 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h @@ -403,10 +403,10 @@ typedef struct * @arg @ref RTC_FLAG_WUTF Wakeup timer flag * @arg @ref RTC_FLAG_ALRBF Alarm B flag * @arg @ref RTC_FLAG_ALRAF Alarm A flag - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U) :\ - ((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U)) + ((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U)) /* ---------------------------------WAKEUPTIMER---------------------------------*/ /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer @@ -452,9 +452,9 @@ typedef struct * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. * This parameter can be: * @arg @ref RTC_IT_WUT WakeUpTimer interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12U)) != 0U) ? 1U : 0U) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. @@ -462,7 +462,7 @@ typedef struct * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg @ref RTC_IT_WUT WakeUpTimer interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) @@ -473,9 +473,11 @@ typedef struct * This parameter can be: * @arg @ref RTC_FLAG_WUTF * @arg @ref RTC_FLAG_WUTWF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_WUTF) ? (((((__HANDLE__)->Instance->SR) & (RTC_SR_WUTF)) != 0) ? 1U : 0U):\ + (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_WUTWF)) != 0) ? 1U : 0U)) /** * @brief Clear the RTC Wake Up timers pending flags. @@ -485,7 +487,7 @@ typedef struct * @arg @ref RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF)) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= (RTC_SCR_CWUTF)) /* WAKE-UP TIMER EXTI */ /* ------------------ */ @@ -561,9 +563,9 @@ typedef struct * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. * This parameter can be: * @arg @ref RTC_IT_TS TimeStamp interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12U)) != 0U) ? 1U : 0U) /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. @@ -571,7 +573,7 @@ typedef struct * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. * This parameter can be: * @arg @ref RTC_IT_TS TimeStamp interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) @@ -582,9 +584,11 @@ typedef struct * This parameter can be: * @arg @ref RTC_FLAG_TSF * @arg @ref RTC_FLAG_TSOVF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ? (((((__HANDLE__)->Instance->SR) & (RTC_SR_TSF)) != 0) ? 1U : 0U):\ + (((((__HANDLE__)->Instance->SR) & (RTC_SR_TSOVF)) != 0) ? 1U : 0U)) /** * @brief Clear the RTC Time Stamps pending flags. @@ -595,7 +599,9 @@ typedef struct * @arg @ref RTC_FLAG_TSOVF * @retval None */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ? ((__HANDLE__)->Instance->SCR |= (RTC_SCR_CTSF)):\ + ((__HANDLE__)->Instance->SCR |= (RTC_SCR_CTSOVF))) /** * @brief Enable interrupt on the RTC Timestamp associated Exti line. @@ -641,9 +647,9 @@ typedef struct * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. * This parameter can be: * @arg @ref RTC_FLAG_ITSF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (RTC_SR_ITSF)) != 0) ? 1U : 0U) /** * @brief Clear the RTC Internal Time Stamps pending flags. @@ -653,7 +659,7 @@ typedef struct * @arg @ref RTC_FLAG_ITSF * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF)) +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= (RTC_SCR_CITSF)) /** * @brief Enable the RTC TimeStamp on Tamper detection. @@ -730,9 +736,9 @@ typedef struct * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: * @arg @ref RTC_FLAG_SHPF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_SHPF)) != 0U) ? 1U : 0U) /** * @} */ @@ -810,9 +816,9 @@ typedef struct * @arg RTC_IT_INT_TAMP4: Internal Tamper4 interrupt * @arg RTC_IT_INT_TAMP5: Internal Tamper5 interrupt * @arg RTC_IT_INT_TAMP6: Internal Tamper6 interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->MISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** @@ -829,7 +835,7 @@ typedef struct * @arg RTC_IT_INT_TAMP4: Internal Tamper4 interrupt * @arg RTC_IT_INT_TAMP5: Internal Tamper5 interrupt * @arg RTC_IT_INT_TAMP6: Internal Tamper6 interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U) @@ -846,7 +852,7 @@ typedef struct * @arg RTC_FLAG_INT_TAMP4: Internal Tamper4 flag * @arg RTC_FLAG_INT_TAMP5: Internal Tamper5 flag * @arg RTC_FLAG_INT_TAMP6: Internal Tamper6 flag - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__FLAG__)) != 0U) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h index aef7ec0188..2b5c6edd9c 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h @@ -247,7 +247,7 @@ extern "C" { } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smbus.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smbus.h index 42b10d1198..0e104b1790 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smbus.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smbus.h @@ -100,8 +100,6 @@ typedef struct #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} @@ -751,8 +749,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /* Peripheral State and Errors functions **************************************************/ -uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus); /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi_ex.h index 6a83fddf54..e1fdd714b6 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi_ex.h @@ -48,7 +48,7 @@ extern "C" { /** @addtogroup SPIEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h index 8bd572f120..44e276db26 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h @@ -402,29 +402,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1034,8 +1033,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ /** * @} */ @@ -1867,6 +1866,10 @@ mode. ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) @@ -1887,8 +1890,9 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ - ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -1941,7 +1945,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -2008,8 +2011,8 @@ mode. ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ @@ -2307,7 +2310,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @{ */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); @@ -2356,7 +2359,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h index 7fb738c63a..a157ec580d 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h @@ -85,46 +85,46 @@ typedef struct /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ -#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */ #if defined(COMP1) && defined(COMP2) -#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ -#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */ #endif /* COMP1 && COMP2 */ -#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /* !< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ #if defined(COMP3) -#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to COMP3 output */ +#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to COMP3 output */ #endif /* COMP3 */ #if defined(TIM2) -#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ -#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ -#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ -#define TIM_TIM2_ETR_LSE (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to LSE */ +#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ +#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */ +#define TIM_TIM2_ETR_LSE (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ #if defined(COMP3) -#define TIM_TIM2_ETR_MCO TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to MCO */ -#define TIM_TIM2_ETR_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to MCO2 */ -#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP3 output */ +#define TIM_TIM2_ETR_MCO TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to MCO */ +#define TIM_TIM2_ETR_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MCO2 */ +#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP3 output */ #endif /* COMP3 */ #endif /* TIM2 */ #if defined(TIM3) -#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ +#define TIM_TIM3_ETR_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */ #if defined(COMP1) && defined(COMP2) -#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */ -#define TIM_TIM3_ETR_COMP2 TIM3_AF1_ETRSEL_1 /* !< TIM3_ETR is connected to COMP2 output */ +#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ +#define TIM_TIM3_ETR_COMP2 TIM3_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */ #endif /* COMP1 && COMP2 */ #if defined(COMP3) -#define TIM_TIM3_ETR_COMP3 (TIM3_AF1_ETRSEL_1 | TIM3_AF1_ETRSEL_0) /* !< TIM3_ETR is connected to COMP3 output */ +#define TIM_TIM3_ETR_COMP3 (TIM3_AF1_ETRSEL_1 | TIM3_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to COMP3 output */ #endif /* COMP3 */ #endif /* TIM3 */ #if defined(TIM4) -#define TIM_TIM4_ETR_GPIO 0x00000000U /* !< TIM4_ETR is connected to GPIO */ +#define TIM_TIM4_ETR_GPIO 0x00000000U /*!< TIM4_ETR is connected to GPIO */ #if defined(COMP1) && defined(COMP2) -#define TIM_TIM4_ETR_COMP1 TIM4_AF1_ETRSEL_0 /* !< TIM4_ETR is connected to COMP1 output */ -#define TIM_TIM4_ETR_COMP2 TIM4_AF1_ETRSEL_1 /* !< TIM4_ETR is connected to COMP2 output */ +#define TIM_TIM4_ETR_COMP1 TIM4_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */ +#define TIM_TIM4_ETR_COMP2 TIM4_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 output */ #endif /* COMP1 && COMP2 */ #if defined(COMP3) -#define TIM_TIM4_ETR_COMP3 (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0) /* !< TIM4_ETR is connected to COMP3 output */ +#define TIM_TIM4_ETR_COMP3 (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to COMP3 output */ #endif /* COMP3 */ #endif /* TIM4 */ /** @@ -143,13 +143,13 @@ typedef struct /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ -#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ #if defined(COMP1) && defined(COMP2) -#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ #endif /* COMP1 && COMP2 */ #if defined(COMP3) -#define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /* !< The COMP3 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /*!< The COMP3 output is connected to the break input */ #endif /* COMP3 */ /** * @} @@ -176,100 +176,100 @@ typedef struct /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection * @{ */ -#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */ +#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1_TI1 is connected to GPIO */ #if defined(COMP1) -#define TIM_TIM1_TI1_COMP1 0x00000001U /* !< TIM1_TI1 is connected to COMP1 OUT */ +#define TIM_TIM1_TI1_COMP1 0x00000001U /*!< TIM1_TI1 is connected to COMP1 OUT */ #endif /* COMP1 */ -#define TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */ +#define TIM_TIM1_TI2_GPIO 0x00000000U /*!< TIM1_TI2 is connected to GPIO */ #if defined(COMP2) -#define TIM_TIM1_TI2_COMP2 0x00000100U /* !< TIM1_TI2 is connected to COMP2 OUT */ +#define TIM_TIM1_TI2_COMP2 0x00000100U /*!< TIM1_TI2 is connected to COMP2 OUT */ #endif /* COMP2 */ -#define TIM_TIM1_TI3_GPIO 0x00000000U /* !< TIM1_TI3 is connected to GPIO */ +#define TIM_TIM1_TI3_GPIO 0x00000000U /*!< TIM1_TI3 is connected to GPIO */ #if defined(COMP3) -#define TIM_TIM1_TI3_COMP3 0x00010000U /* !< TIM1_TI3 is connected to COMP3 OUT */ +#define TIM_TIM1_TI3_COMP3 0x00010000U /*!< TIM1_TI3 is connected to COMP3 OUT */ #endif /* COMP3 */ #if defined(TIM2) -#define TIM_TIM2_TI1_GPIO 0x00000000U /* !< TIM2_TI1 is connected to GPIO */ -#define TIM_TIM2_TI1_COMP1 0x00000001U /* !< TIM2_TI1 is connected to COMP1 OUT */ +#define TIM_TIM2_TI1_GPIO 0x00000000U /*!< TIM2_TI1 is connected to GPIO */ +#define TIM_TIM2_TI1_COMP1 0x00000001U /*!< TIM2_TI1 is connected to COMP1 OUT */ -#define TIM_TIM2_TI2_GPIO 0x00000000U /* !< TIM2_TI2 is connected to GPIO */ -#define TIM_TIM2_TI2_COMP2 0x00000100U /* !< TIM2_TI2 is connected to COMP2 OUT */ +#define TIM_TIM2_TI2_GPIO 0x00000000U /*!< TIM2_TI2 is connected to GPIO */ +#define TIM_TIM2_TI2_COMP2 0x00000100U /*!< TIM2_TI2 is connected to COMP2 OUT */ -#define TIM_TIM2_TI3_GPIO 0x00000000U /* !< TIM2_TI3 is connected to GPIO */ +#define TIM_TIM2_TI3_GPIO 0x00000000U /*!< TIM2_TI3 is connected to GPIO */ #if defined(COMP3) -#define TIM_TIM2_TI3_COMP3 0x00010000U /* !< TIM2_TI3 is connected to COMP3 OUT */ +#define TIM_TIM2_TI3_COMP3 0x00010000U /*!< TIM2_TI3 is connected to COMP3 OUT */ #endif /* COMP3 */ #endif /* TIM2 */ -#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */ +#define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3_TI1 is connected to GPIO */ #if defined(COMP1) -#define TIM_TIM3_TI1_COMP1 0x00000001U /* !< TIM3_TI1 is connected to COMP1 OUT */ +#define TIM_TIM3_TI1_COMP1 0x00000001U /*!< TIM3_TI1 is connected to COMP1 OUT */ #endif /* COMP1 */ -#define TIM_TIM3_TI2_GPIO 0x00000000U /* !< TIM3_TI2 is connected to GPIO */ +#define TIM_TIM3_TI2_GPIO 0x00000000U /*!< TIM3_TI2 is connected to GPIO */ #if defined(COMP2) -#define TIM_TIM3_TI2_COMP2 0x00000100U /* !< TIM3_TI2 is connected to COMP2 OUT */ +#define TIM_TIM3_TI2_COMP2 0x00000100U /*!< TIM3_TI2 is connected to COMP2 OUT */ #endif /* COMP2 */ -#define TIM_TIM3_TI3_GPIO 0x00000000U /* !< TIM3_TI3 is connected to GPIO */ +#define TIM_TIM3_TI3_GPIO 0x00000000U /*!< TIM3_TI3 is connected to GPIO */ #if defined(COMP3) -#define TIM_TIM3_TI3_COMP3 0x00010000U /* !< TIM3_TI3 is connected to COMP3 OUT */ +#define TIM_TIM3_TI3_COMP3 0x00010000U /*!< TIM3_TI3 is connected to COMP3 OUT */ #endif /* COMP3 */ #if defined(TIM4) -#define TIM_TIM4_TI1_GPIO 0x00000000U /* !< TIM4_TI1 is connected to GPIO */ +#define TIM_TIM4_TI1_GPIO 0x00000000U /*!< TIM4_TI1 is connected to GPIO */ #if defined(COMP1) -#define TIM_TIM4_TI1_COMP1 0x00000001U /* !< TIM4_TI1 is connected to COMP1 OUT */ +#define TIM_TIM4_TI1_COMP1 0x00000001U /*!< TIM4_TI1 is connected to COMP1 OUT */ #endif /* COMP1 */ -#define TIM_TIM4_TI2_GPIO 0x00000000U /* !< TIM4_TI2 is connected to GPIO */ +#define TIM_TIM4_TI2_GPIO 0x00000000U /*!< TIM4_TI2 is connected to GPIO */ #if defined(COMP2) -#define TIM_TIM4_TI2_COMP2 0x00000100U /* !< TIM4_TI2 is connected to COMP2 OUT */ +#define TIM_TIM4_TI2_COMP2 0x00000100U /*!< TIM4_TI2 is connected to COMP2 OUT */ #endif /* COMP2 */ -#define TIM_TIM4_TI3_GPIO 0x00000000U /* !< TIM4_TI3 is connected to GPIO */ +#define TIM_TIM4_TI3_GPIO 0x00000000U /*!< TIM4_TI3 is connected to GPIO */ #if defined(COMP3) -#define TIM_TIM4_TI3_COMP3 0x00010000U /* !< TIM4_TI3 is connected to COMP3 OUT */ +#define TIM_TIM4_TI3_COMP3 0x00010000U /*!< TIM4_TI3 is connected to COMP3 OUT */ #endif /* COMP3 */ #endif /* TIM4 */ -#define TIM_TIM14_TI1_GPIO 0x00000000U /* !< TIM14_TI1 is connected to GPIO */ -#define TIM_TIM14_TI1_RTC 0x00000001U /* !< TIM14_TI1 is connected to RTC clock */ -#define TIM_TIM14_TI1_HSE_32 0x00000002U /* !< TIM14_TI1 is connected to HSE div 32 */ -#define TIM_TIM14_TI1_MCO 0x00000003U /* !< TIM14_TI1 is connected to MCO */ +#define TIM_TIM14_TI1_GPIO 0x00000000U /*!< TIM14_TI1 is connected to GPIO */ +#define TIM_TIM14_TI1_RTC 0x00000001U /*!< TIM14_TI1 is connected to RTC clock */ +#define TIM_TIM14_TI1_HSE_32 0x00000002U /*!< TIM14_TI1 is connected to HSE div 32 */ +#define TIM_TIM14_TI1_MCO 0x00000003U /*!< TIM14_TI1 is connected to MCO */ #if defined(RCC_MCO2_SUPPORT) -#define TIM_TIM14_TI1_MCO2 0x00000004U /* !< TIM14_TI1 is connected to MCO2 */ -#endif +#define TIM_TIM14_TI1_MCO2 0x00000004U /*!< TIM14_TI1 is connected to MCO2 */ +#endif /* RCC_MCO2_SUPPORT */ #if defined(TIM15) -#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */ -#define TIM_TIM15_TI1_TIM2_CH1 0x00000001U /* !< TIM15_TI1 is connected to TIM2 CH1 */ -#define TIM_TIM15_TI1_TIM3_CH1 0x00000002U /* !< TIM15_TI1 is connected to TIM3 CH1 */ +#define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 0x00000001U /*!< TIM15_TI1 is connected to TIM2 CH1 */ +#define TIM_TIM15_TI1_TIM3_CH1 0x00000002U /*!< TIM15_TI1 is connected to TIM3 CH1 */ -#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */ -#define TIM_TIM15_TI2_TIM2_CH2 0x00000100U /* !< TIM15_TI2 is connected to TIM2 CH2 */ -#define TIM_TIM15_TI2_TIM3_CH2 0x00000200U /* !< TIM15_TI2 is connected to TIM3 CH2 */ +#define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 0x00000100U /*!< TIM15_TI2 is connected to TIM2 CH2 */ +#define TIM_TIM15_TI2_TIM3_CH2 0x00000200U /*!< TIM15_TI2 is connected to TIM3 CH2 */ #endif /* TIM15 */ -#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to GPIO */ -#define TIM_TIM16_TI1_LSI 0x00000001U /* !< TIM16_TI1 is connected to LSI */ -#define TIM_TIM16_TI1_LSE 0x00000002U /* !< TIM16_TI1 is connected to LSE */ -#define TIM_TIM16_TI1_RTC_WAKEUP 0x00000003U /* !< TIM16_TI1 is connected to TRC wakeup interrupt */ +#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16_TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_LSI 0x00000001U /*!< TIM16_TI1 is connected to LSI */ +#define TIM_TIM16_TI1_LSE 0x00000002U /*!< TIM16_TI1 is connected to LSE */ +#define TIM_TIM16_TI1_RTC_WAKEUP 0x00000003U /*!< TIM16_TI1 is connected to TRC wakeup interrupt */ #if defined(RCC_MCO2_SUPPORT) -#define TIM_TIM16_TI1_MCO2 0x00000004U /* !< TIM16_TI1 is connected to MCO2 */ +#define TIM_TIM16_TI1_MCO2 0x00000004U /*!< TIM16_TI1 is connected to MCO2 */ #endif /* RCC_MCO2_SUPPORT */ -#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17_TI1 is connected to GPIO */ #if defined(RCC_HSI48_SUPPORT) -#define TIM_TIM17_TI1_HSI48 0x00000001U /* !< TIM17_TI1 is connected to HSI48/256 */ +#define TIM_TIM17_TI1_HSI48 0x00000001U /*!< TIM17_TI1 is connected to HSI48/256 */ #endif /* RCC_HSI48_SUPPORT */ -#define TIM_TIM17_TI1_HSE_32 0x00000002U /* !< TIM17_TI1 is connected to HSE div 32 */ -#define TIM_TIM17_TI1_MCO 0x00000003U /* !< TIM17_TI1 is connected to MCO */ +#define TIM_TIM17_TI1_HSE_32 0x00000002U /*!< TIM17_TI1 is connected to HSE div 32 */ +#define TIM_TIM17_TI1_MCO 0x00000003U /*!< TIM17_TI1 is connected to MCO */ #if defined(RCC_MCO2_SUPPORT) -#define TIM_TIM17_TI1_MCO2 0x00000004U /* !< TIM17_TI1 is connected to MCO2 */ +#define TIM_TIM17_TI1_MCO2 0x00000004U /*!< TIM17_TI1 is connected to MCO2 */ #endif /* RCC_MCO2_SUPPORT */ /** * @} @@ -433,7 +433,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h index 89e63a383f..1ad91e9d3f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h @@ -178,7 +178,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h index 300c1dcbfe..f73166a390 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h @@ -141,7 +141,7 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h index e6852fd1ab..92700675b3 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h @@ -45,7 +45,7 @@ extern "C" { * @{ */ #define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h index ed9c5d166f..86b39018e0 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h @@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__ WWDG handle + * @param __HANDLE__: WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h index 32a83aeef7..7db42c89fc 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h @@ -69,7 +69,7 @@ extern "C" { /* - regular trigger source */ /* - regular trigger edge */ #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for - compatibility with some ADC on other STM32 families + compatibility with some ADC on other STM32 series having this setting set by HW default value) */ /* Mask containing trigger source masks for each of possible */ @@ -178,7 +178,7 @@ extern "C" { /* Internal mask for ADC analog watchdog: */ /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ /* (concatenation of multiple bits used in different analog watchdogs, */ -/* (feature of several watchdogs not available on all STM32 families)). */ +/* (feature of several watchdogs not available on all STM32 series)). */ /* - analog watchdog 1: monitored channel defined by number, */ /* selection of ADC group (ADC group regular). */ /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ @@ -252,29 +252,34 @@ extern "C" { /* ADC registers bits groups */ #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \ | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with - HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ + HW property "rs": Software can read as well as set this bit. + Writing '0' has no effect on the bit value. */ /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, - address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), - Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of + parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value - with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ + with which VrefInt has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G0, - temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), - Vref+ = 3.0 V (tolerance: +-10 mV). */ + temperature sensor ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G0, - temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), - Vref+ = 3.0 V (tolerance: +-10 mV). */ + temperature sensor ADC raw data acquired at temperature 130 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor - has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ + has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor - has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ + has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) value - with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ + with which temperature sensor has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ /** * @} @@ -336,7 +341,7 @@ typedef struct * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -385,7 +390,7 @@ typedef struct * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -401,12 +406,12 @@ typedef struct This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge(default setting for compatibility - with some ADC on other STM32 families having this setting set by HW + with some ADC on other STM32 series having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetTriggerSource(). */ + @ref LL_ADC_REG_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. @note This parameter has an effect only if group regular sequencer is set @@ -414,7 +419,7 @@ typedef struct @ref LL_ADC_REG_SetSequencerConfigurable(). This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetSequencerLength(). */ + @ref LL_ADC_REG_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. @@ -467,9 +472,9 @@ typedef struct #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ #define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */ #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary - conversion */ + conversion */ #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence - conversions */ + conversions */ #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ @@ -507,12 +512,11 @@ typedef struct /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register - (corresponding to register DR) to be used with ADC - configured in independent mode. Without DMA transfer, - register accessed by LL function - @ref LL_ADC_REG_ReadConversionData32() and other - functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register + (corresponding to register DR) to be used with ADC configured in independent + mode. Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadConversionData32() and other + functions @ref LL_ADC_REG_ReadConversionDatax() */ /** * @} */ @@ -521,42 +525,53 @@ typedef struct * @{ */ #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without -prescaler */ + prescaler */ #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with -prescaler division by 2. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + prescaler division by 2. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with -prescaler division by 4. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + prescaler division by 4. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with -prescaler division by 6. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + prescaler division by 6. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with -prescaler division by 8. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + prescaler division by 8. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with -prescaler division by 10. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + prescaler division by 10. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with -prescaler division by 12. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + prescaler division by 12. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \ - | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with -prescaler division by 16. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 16. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with -prescaler division by 32. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + prescaler division by 32. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with -prescaler division by 64. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + prescaler division by 64. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with -prescaler division by 128. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + prescaler division by 128. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \ - | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with -prescaler division by 256. Setting common to ADC instances of ADC common group, applied ADC instance wise to each -instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 256. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ /** * @} */ @@ -565,9 +580,9 @@ instance clock set to clock source asynchronous (refer to function @ref LL_ADC_ * @{ */ #define LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000UL) /*!< ADC clock mode to high frequency. - On STM32G0, ADC clock frequency above 3.5MHz. */ + On STM32G0, ADC clock frequency above 3.5MHz. */ #define LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN) /*!< ADC clock mode to low frequency. - On STM32G0,ADC clock frequency below 3.5MHz. */ + On STM32G0,ADC clock frequency below 3.5MHz. */ /** * @} */ @@ -593,14 +608,14 @@ instance clock set to clock source asynchronous (refer to function @ref LL_ADC_ * @{ */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock - divided by 4 */ + divided by 4 */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock - divided by 2 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived - from AHB clock not divided */ + divided by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 \ + | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock + not divided */ #define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock - prescaler can be configured using function - @ref LL_ADC_SetCommonClock(). */ + prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */ /** * @} */ @@ -620,9 +635,9 @@ instance clock set to clock source asynchronous (refer to function @ref LL_ADC_ * @{ */ #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned - (alignment on data register LSB bit 0)*/ + (alignment on data register LSB bit 0)*/ #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned - (alignment on data register MSB bit 15)*/ + (alignment on data register MSB bit 15)*/ /** * @} */ @@ -632,12 +647,14 @@ instance clock set to clock source asynchronous (refer to function @ref LL_ADC_ */ #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power -mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). -See description with function @ref LL_ADC_SetLowPowerMode(). */ + mode, ADC conversions are performed only when necessary + (when previous ADC conversion data is read). + See description with function @ref LL_ADC_SetLowPowerMode(). */ #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC -automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered -(with startup time between trigger and start of sampling). See description with function -@ref LL_ADC_SetLowPowerMode(). */ + automatically powers-off after a ADC conversion and automatically wakes up + when a new ADC conversion is triggered (with startup time between trigger + and start of sampling). See description with function + @ref LL_ADC_SetLowPowerMode(). */ #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */ /** @@ -648,13 +665,17 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * @{ */ #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. -Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion -start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start -trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ + Note: ADC trigger frequency mode must be set to low frequency when a duration + is exceeded before ADC conversion start trigger event (between ADC enable + and ADC conversion start trigger event or between two ADC conversion start + trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". */ #define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. -Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion -start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start -trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ + Note: ADC trigger frequency mode must be set to low frequency when a duration + is exceeded before ADC conversion start trigger event (between ADC enable + and ADC conversion start trigger event or between two ADC conversion start + trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". */ /** * @} */ @@ -663,10 +684,10 @@ trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ * @{ */ #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group - of channels: sampling time nb 1 */ + of channels: sampling time nb 1 */ #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \ - | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group - of channels: sampling time nb 2 */ + | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group + of channels: sampling time nb 2 */ /** * @} */ @@ -682,31 +703,51 @@ trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number * @{ */ -#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */ -#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */ -#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */ -#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */ -#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */ -#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */ -#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */ -#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */ -#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */ -#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */ -#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */ -#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */ -#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ -#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ -#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ -#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ -#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ -#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ -#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel -connected to VrefInt: Internal voltage reference. */ -#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel -connected to Temperature sensor. */ -#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel -connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \ + | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \ + | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \ + | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \ + | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \ + | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \ + | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \ + | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \ + | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \ + | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \ + | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \ + | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \ + | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \ + | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \ + | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \ + | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \ + | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \ + | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \ + | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ +#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \ + | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to VrefInt: Internal voltage reference. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to Temperature sensor. */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/3 + to have channel voltage always below Vdda. */ /** * @} */ @@ -715,38 +756,45 @@ connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have * @{ */ #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular -conversion trigger internal: SW start. */ + conversion trigger internal: SW start. */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular -conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ + conversion trigger from external peripheral: TIM1 TRGO. + Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular -conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). -Trigger edge set to rising edge (default setting). */ + conversion trigger from external peripheral: TIM1 channel 4 event + (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ #if defined(TIM2) -#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular -conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1\ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 TRGO. + Trigger edge set to rising edge (default setting). */ #endif /* TIM2 */ #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | \ - ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular - -conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM3 TRGO. + Trigger edge set to rising edge (default setting). */ #if defined(TIM4) #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | \ - ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular -conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM4 TRGO. + Trigger edge set to rising edge (default setting). */ #endif /* TIM4 */ #if defined(TIM6) #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | \ - ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular -conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM6 TRGO. + Trigger edge set to rising edge (default setting). */ #endif /* TIM6 */ #if defined(TIM15) #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular -conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ + conversion trigger from external peripheral: TIM15 TRGO. + Trigger edge set to rising edge (default setting). */ #endif /* TIM15 */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | \ - ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular -conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge -(default setting). */ + ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: external interrupt line 11. + Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -755,11 +803,11 @@ conversion trigger from external peripheral: external interrupt line 11. Trigger * @{ */ #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion -trigger polarity set to rising edge */ + trigger polarity set to rising edge */ #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion -trigger polarity set to falling edge */ + trigger polarity set to falling edge */ #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion -trigger polarity set to both rising and falling edges */ + trigger polarity set to both rising and falling edges */ /** * @} */ @@ -768,9 +816,10 @@ trigger polarity set to both rising and falling edges */ * @{ */ #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode: -one conversion per trigger */ + one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode: -after the first trigger, following conversions launched successively automatically */ + after the first trigger, following conversions launched successively + automatically */ /** * @} */ @@ -780,11 +829,13 @@ after the first trigger, following conversions launched successively automatical */ #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, -in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of -ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ + in limited mode (one shot mode): DMA transfer requests are stopped when + number of DMA data transfers (number of ADC conversions) is reached. + This ADC mode is intended to be used with DMA mode non-circular. */ #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are -transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred -(number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ + transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. */ /** * @} */ @@ -804,11 +855,12 @@ transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, what * @{ */ #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: -sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of -function @ref LL_ADC_REG_SetSequencerChannels(). */ + sequencer length and each rank affectation to a channel are fixed + by channel HW number. Refer to description of function + @ref LL_ADC_REG_SetSequencerChannels(). */ #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: -sequencer length and each rank affectation to a channel are configurable. Refer to description of -function @ref LL_ADC_REG_SetSequencerLength(). */ + sequencer length and each rank affectation to a channel are configurable. + Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ /** * @} */ @@ -817,22 +869,21 @@ function @ref LL_ADC_REG_SetSequencerLength(). */ * @{ */ #define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable - (equivalent to sequencer of 1 rank: - ADC conversion on only 1 channel) */ + (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable - with 2 ranks in the sequence */ + with 2 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable - with 3 ranks in the sequence */ + with 3 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable - with 4 ranks in the sequence */ + with 4 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable - with 5 ranks in the sequence */ + with 5 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable - with 6 ranks in the sequence */ + with 6 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable - with 7 ranks in the sequence */ + with 7 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable - with 8 ranks in the sequence */ + with 8 ranks in the sequence */ /** * @} */ @@ -841,14 +892,18 @@ function @ref LL_ADC_REG_SetSequencerLength(). */ * @{ */ #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if -sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). -ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of -all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 series, this setting -is not available and the default scan direction is forward. */ + sequencer set to mode not fully configurable, refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan + direction forward: from lowest channel number to highest channel number + (scan of all ranks, ADC conversion of ranks with channels enabled in + sequencer). On some other STM32 series, this setting is not available + and the default scan direction is forward. */ #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if -sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). -ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of -all ranks, ADC conversion of ranks with channels enabled in sequencer) */ + sequencer set to mode not fully configurable, refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan + direction backward: from highest channel number to lowest channel number + (scan of all ranks, ADC conversion of ranks with channels enabled in + sequencer) */ /** * @} */ @@ -857,9 +912,9 @@ all ranks, ADC conversion of ranks with channels enabled in sequencer) */ * @{ */ #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer -discontinuous mode disable */ + discontinuous mode disable */ #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer -discontinuous mode enable with sequence interruption every rank */ + discontinuous mode enable with sequence interruption every rank */ /** * @} */ @@ -886,15 +941,15 @@ discontinuous mode enable with sequence interruption every rank */ #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \ - | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */ + | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \ - | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ + | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \ - | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ + | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 \ - | ADC_SMPR_SMP1_1 \ - | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */ + | ADC_SMPR_SMP1_1 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */ /** * @} */ @@ -903,11 +958,11 @@ discontinuous mode enable with sequence interruption every rank */ * @{ */ #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \ - | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ + | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \ - | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ + | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \ - | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ + | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ /** * @} */ @@ -916,77 +971,80 @@ discontinuous mode enable with sequence interruption every rank */ * @{ */ #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring -disabled */ + disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \ - | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring -of all channels, converted by group regular only */ + | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN0, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN1, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN2, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN3, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN4, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN5, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN6, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN7, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN8, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN9, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN10, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN11, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN12, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN13, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN14, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN15, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN15, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN16, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN17, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC channel ADCx_IN18, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN18, converted by group regular only */ #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal + voltage reference, converted by group regular only */ #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC internal channel connected to Temperature sensor, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to internal temperature sensor, + converted by group regular only */ #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring -of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat -always below Vdda, converted by group regular only */ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Vbat/3: Vbat + voltage through a divider ladder of factor 1/3 to have channel voltage always + below Vdda, converted by group regular only */ /** * @} */ @@ -997,7 +1055,7 @@ always below Vdda, converted by group regular only */ #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */ #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */ #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \ - | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low + | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ /** * @} @@ -1008,8 +1066,9 @@ always below Vdda, converted by group regular only */ */ #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of -ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group -injected, in this case other oversampling scope parameters are available. */ + ADC group regular. Literal suffix "continued" is kept for compatibility + with other STM32 devices featuring ADC group injected, in this case other + oversampling scope parameters are available. */ /** * @} */ @@ -1020,7 +1079,7 @@ injected, in this case other oversampling scope parameters are available. */ #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous -mode (each conversion of oversampling ratio needs a trigger) */ + mode (each conversion of oversampling ratio needs a trigger) */ /** * @} */ @@ -1029,22 +1088,30 @@ mode (each conversion of oversampling ratio needs a trigger) */ * @{ */ #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 -(sum of conversions data computed to result as oversampling conversion data (before potential shift) */ + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 -(sum of conversions data computed to result as oversampling conversion data (before potential shift) */ + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 -(sum of conversions data computed to result as oversampling conversion data (before potential shift) */ + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 -(sum of conversions data computed to result as oversampling conversion data (before potential shift) */ + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 -(sum of conversions data computed to result as oversampling conversion data (before potential shift) */ + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 -(sum of conversions data computed to result as oversampling conversion data (before potential shift) */ + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 -(sum of conversions data computed to result as oversampling conversion data (before potential shift) */ + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \ - | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 -(sum of conversions data computed to result as oversampling conversion data (before potential shift) */ + | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ /** * @} */ @@ -1053,24 +1120,33 @@ mode (each conversion of oversampling ratio needs a trigger) */ * @{ */ #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift -(sum of the ADC conversions data is not divided to result as oversampling conversion data) */ + (sum of the ADC conversions data is not divided to result as oversampling + conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 -(sum of the ADC conversions data (after OVS ratio) is divided by 2 to result as oversampling conversion data) */ + (sum of the ADC conversions data (after OVS ratio) is divided by 2 + to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 -(sum of the ADC conversions data (after OVS ratio) is divided by 4 to result as oversampling conversion data) */ + (sum of the ADC conversions data (after OVS ratio) is divided by 4 + to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3 -(sum of the ADC conversions data (after OVS ratio) is divided by 8 to result as oversampling conversion data) */ + (sum of the ADC conversions data (after OVS ratio) is divided by 8 + to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 -(sum of the ADC conversions data (after OVS ratio) is divided by 16 to result as oversampling conversion data) */ + (sum of the ADC conversions data (after OVS ratio) is divided by 16 + to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5 -(sum of the ADC conversions data (after OVS ratio) is divided by 32 to result as oversampling conversion data) */ + (sum of the ADC conversions data (after OVS ratio) is divided by 32 + to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6 -(sum of the ADC conversions data (after OVS ratio) is divided by 64 to result as oversampling conversion data) */ + (sum of the ADC conversions data (after OVS ratio) is divided by 64 + to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \ - | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 -(sum of the ADC conversions data (after OVS ratio) is divided by 128 to result as oversampling conversion data) */ + | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 + (sum of the ADC conversions data (after OVS ratio) is divided by 128 + to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 -(sum of the ADC conversions data (after OVS ratio) is divided by 256 to result as oversampling conversion data) */ + (sum of the ADC conversions data (after OVS ratio) is divided by 256 + to result as oversampling conversion data) */ /** * @} */ @@ -1749,19 +1825,19 @@ mode (each conversion of oversampling ratio needs a trigger) */ #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__)\ -((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \ - (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ - ) \ - : \ - ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \ +((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) \ + : \ + ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \ ) /** @@ -1800,7 +1876,7 @@ mode (each conversion of oversampling ratio needs a trigger) */ (at temperature and Vref+ defined in parameters below) (unit: mV). * On STM32G0, refer to datasheet parameter "V30" (corresponding to TS_CAL1). * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage - (see parameter above) is corresponding (unit: mV) + (see parameter above) is corresponding (unit: degree Celsius) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. @@ -1874,7 +1950,7 @@ mode (each conversion of oversampling ratio needs a trigger) */ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA * @retval ADC register address */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { /* Prevent unused argument(s) compilation warning */ (void)(Register); @@ -1952,7 +2028,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * is set to clock source asynchronous. * (refer to function @ref LL_ADC_SetClock() ). */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); } @@ -1989,7 +2065,7 @@ __STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COM * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_LFMEN)); } @@ -2126,7 +2202,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); } @@ -2186,7 +2262,7 @@ __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) * cycle). * Refer to reference manual. */ -__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetClock(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); } @@ -2222,7 +2298,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t Cal * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); } @@ -2260,7 +2336,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); } @@ -2294,7 +2370,7 @@ __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAli * @arg @ref LL_ADC_DATA_ALIGN_RIGHT * @arg @ref LL_ADC_DATA_ALIGN_LEFT */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); } @@ -2404,7 +2480,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @arg @ref LL_ADC_LP_AUTOPOWEROFF * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF))); } @@ -2447,7 +2523,7 @@ __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH * @arg @ref LL_ADC_TRIGGER_FREQ_LOW */ -__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); } @@ -2457,7 +2533,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx) * @note Unit: ADC clock cycles. * @note On this STM32 series, sampling time scope is on ADC instance: * Sampling time common to all channels. - * (on some other STM32 families, sampling time is channel wise) + * (on some other STM32 series, sampling time is channel wise) * @note In case of internal channel (VrefInt, TempSensor, ...) to be * converted: * sampling time constraints must be respected (sampling time can be @@ -2509,7 +2585,7 @@ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uin * @note Unit: ADC clock cycles. * @note On this STM32 series, sampling time scope is on ADC instance: * Sampling time common to all channels. - * (on some other STM32 families, sampling time is channel wise) + * (on some other STM32 series, sampling time is channel wise) * @note Conversion time is the addition of sampling time and processing time. * Refer to reference manual for ADC processing time of * this STM32 series. @@ -2529,7 +2605,7 @@ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uin * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 */ -__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY) +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY) { return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); @@ -2550,7 +2626,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other - * STM32 families having this setting set by HW default value). + * STM32 series having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_REG_SetTriggerEdge(). * @note On this STM32 series, ADC trigger frequency mode must be set @@ -2610,7 +2686,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * * (1) On STM32G0, parameter not available on all devices */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); @@ -2637,7 +2713,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); } @@ -2671,7 +2747,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); } @@ -2734,7 +2810,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_REG_SEQ_FIXED * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD)); } @@ -2865,7 +2941,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; @@ -2924,7 +3000,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uin * @note On this STM32 series, parameter relevant only is sequencer is set * to mode not fully configurable, * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). - * @note On some other STM32 families, this setting is not available and + * @note On some other STM32 series, this setting is not available and * the default scan direction is forward. * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection * @param ADCx ADC instance @@ -2932,7 +3008,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uin * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); } @@ -2968,7 +3044,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); } @@ -3057,7 +3133,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra MODIFY_REG(ADCx->CHSELR, ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) - << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); + << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } /** @@ -3129,7 +3205,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -3488,7 +3564,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch * only if sequencer is set in mode "not fully configurable", * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx) { uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); @@ -3551,7 +3627,7 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); } @@ -3621,7 +3697,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATr * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); } @@ -3659,7 +3735,7 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); } @@ -3816,7 +3892,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { __IO uint32_t smpr = READ_REG(ADCx->SMPR); @@ -4010,12 +4086,12 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_CHANNEL_17_REG * @arg @ref LL_ADC_AWD_CHANNEL_18_REG */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, - ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) - * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + __IO const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) + * ADC_AWD_CR12_REGOFFSETGAP_VAL)); uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); @@ -4139,10 +4215,10 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) - >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) - >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)) - ); + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)) + ); MODIFY_REG(*preg, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, @@ -4222,9 +4298,9 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) - >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) - >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); MODIFY_REG(*preg, AWDThresholdsHighLow, @@ -4259,7 +4335,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, + uint32_t AWDy, uint32_t AWDThresholdsHighLow) { /* Set bits with content of parameter "AWDThresholdValue" with bits */ /* position in register and register position depending on parameters */ @@ -4268,9 +4345,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ /* containing other bits reserved for other purpose. */ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) - >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) - >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_AWD1TR_LT1)) @@ -4311,7 +4388,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @arg @ref LL_ADC_OVS_DISABLE * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); } @@ -4353,7 +4430,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); } @@ -4409,7 +4486,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); } @@ -4429,7 +4506,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } @@ -4494,7 +4571,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } @@ -4554,7 +4631,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } @@ -4565,7 +4642,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } @@ -4614,7 +4691,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } @@ -4659,7 +4736,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) * @brief Stop ADC group regular conversion. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be enabled with conversion on going on group regular, + * ADC must be enabled (potentially with conversion on going on group regular), * without ADC disable command on going. * @rmtoll CR ADSTP LL_ADC_REG_StopConversion * @param ADCx ADC instance @@ -4681,7 +4758,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } @@ -4692,7 +4769,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } @@ -4706,7 +4783,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } @@ -4721,9 +4798,9 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x00000FFFUL); } /** @@ -4736,9 +4813,9 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000003FFUL); } /** @@ -4751,9 +4828,9 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL); } /** @@ -4766,9 +4843,9 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) { - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x0000003FUL); } /** @@ -4788,7 +4865,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } @@ -4815,7 +4892,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); } @@ -4826,7 +4903,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } @@ -4837,7 +4914,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } @@ -4848,7 +4925,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } @@ -4859,7 +4936,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } @@ -4870,7 +4947,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } @@ -4881,7 +4958,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } @@ -4892,7 +4969,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } @@ -4903,7 +4980,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL); } @@ -5256,7 +5333,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } @@ -5267,7 +5344,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); } @@ -5279,7 +5356,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } @@ -5291,7 +5368,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } @@ -5303,7 +5380,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } @@ -5315,7 +5392,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } @@ -5327,7 +5404,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } @@ -5339,7 +5416,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } @@ -5351,7 +5428,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } @@ -5363,7 +5440,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL); } @@ -5379,18 +5456,18 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) /* Initialization of some features of ADC common parameters and multimode */ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); /* De-initialization of ADC instance */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); /* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct); +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct); void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct); /* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h index aea263f12c..8bd0e3b9d5 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h @@ -50,9 +50,12 @@ extern "C" { /* (concatenation of multiple bits used in different registers) */ /* - Comparator instance selected as master for window mode : register offset */ /* - Window mode enable or disable: bit value */ -#define LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...) defined as reference register */ -#define LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...) offset vs register of COMP instance odd */ -#define LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) +#define LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...) + defined as reference register */ +#define LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...) + offset vs register of COMP instance odd */ +#define LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK \ + | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) #define LL_COMP_WINDOWMODE_COMPX_SETTING_MASK (COMP_CSR_WINMODE) #define LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK (COMP_CSR_WINOUT) #define LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK (COMP_CSR_WINOUT << 1UL) @@ -99,33 +102,33 @@ typedef struct { uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed. This parameter can be a value of @ref COMP_LL_EC_POWERMODE - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */ + This feature can be modified afterwards using unitary + function @ref LL_COMP_SetPowerMode(). */ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputPlus(). */ uint32_t InputMinus; /*!< Set comparator input minus (inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputMinus(). */ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputHysteresis(). */ uint32_t OutputPolarity; /*!< Set comparator output polarity. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputPolarity(). */ uint32_t OutputBlankingSource; /*!< Set comparator blanking source. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputBlankingSource(). */ } LL_COMP_InitTypeDef; @@ -139,6 +142,7 @@ typedef struct * @{ */ + /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode * @{ */ @@ -153,16 +157,17 @@ typedef struct * @{ */ #define LL_COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. The same way, if both comparators output are high, then monitored signal is below window. */ -#define LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ -#define LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ +#define LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthesized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ +#define LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window output synthesized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ #if defined(COMP3) -#define LL_COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Available only on devices featuring COMP3 instance. */ +#define LL_COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthesized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Available only on devices featuring COMP3 instance. */ #endif /* COMP3 */ -#define LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ +#define LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) /*!< Window output synthesized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ /** * @} */ + /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode * @{ */ @@ -316,13 +321,13 @@ typedef struct #if defined(COMP3) #define __LL_COMP_COMMON_INSTANCE(__COMPx__) \ ((((__COMPx__) == COMP3)) \ - ? ( \ - (COMP23_COMMON) \ - ) \ - : \ - ( \ - (COMP12_COMMON) \ - ) \ + ? ( \ + (COMP23_COMMON) \ + ) \ + : \ + ( \ + (COMP12_COMMON) \ + ) \ ) #else #define __LL_COMP_COMMON_INSTANCE(__COMPx__) \ @@ -342,10 +347,12 @@ typedef struct * @{ */ -/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances +/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: + * common to several COMP instances * @{ */ + /** * @brief Set window mode of a pair of comparators instances * (2 consecutive COMP instances COMP and COMP). @@ -371,19 +378,21 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common */ /* group of COMP2 and COMP3, instances odd and even are inverted. */ /* Perform switch of parameter selected. */ - if(COMPxy_COMMON == COMP23_COMMON) + if (COMPxy_COMMON == COMP23_COMMON) { - if(WindowMode == LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) + if (WindowMode == LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) { window_mode_tmp = LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON; } } #endif /* COMP3 */ - __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (window_mode_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); + __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, + (window_mode_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); /* Clear the potential previous setting of window mode */ - __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(window_mode_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)); + __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, + (~(window_mode_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)); CLEAR_BIT(*preg_clear, COMP_CSR_WINMODE ); @@ -409,7 +418,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM * (1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON * (2) Parameter specificity on devices STM32G0B1xx and STM32G0C1xx: only parameter that can be used only with comparator common instance COMP23_COMMON */ -__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON) +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON) { /* Note: On this STM32 series, window mode can be set from any instance */ /* of the pair of comparator instances. */ @@ -420,7 +429,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common */ /* group of COMP2 and COMP3, instances odd and even are inverted. */ /* Perform switch of parameter selected. */ - if(COMPxy_COMMON == COMP23_COMMON) + if (COMPxy_COMMON == COMP23_COMMON) { window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE); window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE); @@ -431,13 +440,14 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE); } #else - const uint32_t window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE); - const uint32_t window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + const uint32_t window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE); + const uint32_t window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE); #endif /* COMP3 */ - return (uint32_t)(window_mode_comp_odd | window_mode_comp_even - | ((window_mode_comp_even >> LL_COMP_WINDOWMODE_BITOFFSET_POS) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)); + | ((window_mode_comp_even >> LL_COMP_WINDOWMODE_BITOFFSET_POS) + * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) + ); } /** @@ -465,13 +475,13 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_C /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common */ /* group of COMP2 and COMP3, instances odd and even are inverted. */ /* Perform switch of parameter selected. */ - if(COMPxy_COMMON == COMP23_COMMON) + if (COMPxy_COMMON == COMP23_COMMON) { - if(WindowOutput == LL_COMP_WINDOWOUTPUT_COMP2) + if (WindowOutput == LL_COMP_WINDOWOUTPUT_COMP2) { window_output_tmp = LL_COMP_WINDOWOUTPUT_COMP3; } - else if(WindowOutput == LL_COMP_WINDOWOUTPUT_COMP3) + else if (WindowOutput == LL_COMP_WINDOWOUTPUT_COMP3) { window_output_tmp = LL_COMP_WINDOWOUTPUT_COMP2; } @@ -515,7 +525,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_C * (1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON * (2) Parameter available only on devices STM32G0B1xx and STM32G0C1xx, must be used with comparator common instance COMP23_COMMON */ -__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON) +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(const COMP_Common_TypeDef *COMPxy_COMMON) { #if defined(COMP3) uint32_t window_output_comp_odd; @@ -524,7 +534,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMP /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common */ /* group of COMP2 and COMP3, instances odd and even are inverted. */ /* Perform switch of parameter selected. */ - if(COMPxy_COMMON == COMP23_COMMON) + if (COMPxy_COMMON == COMP23_COMMON) { window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT); window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT); @@ -546,6 +556,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMP | (window_output_comp_odd + window_output_comp_even)); } + /** * @} */ @@ -576,7 +587,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @arg @ref LL_COMP_POWERMODE_HIGHSPEED * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED */ -__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE)); } @@ -655,7 +666,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_IO3 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL)); } @@ -707,7 +718,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_IO2 * @arg @ref LL_COMP_INPUT_MINUS_IO3 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL)); } @@ -738,7 +749,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_MEDIUM * @arg @ref LL_COMP_HYSTERESIS_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST)); } @@ -773,7 +784,7 @@ __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t Out * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED * @arg @ref LL_COMP_OUTPUTPOL_INVERTED */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY)); } @@ -822,7 +833,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * (1) Parameter availability depending on timer availability * on the selected device. */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING)); } @@ -867,7 +878,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL); } @@ -894,7 +905,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL); } @@ -919,7 +930,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE) >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS); @@ -935,7 +946,7 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) */ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx); -ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct); +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct); void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h index 14782f33bc..901a147241 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h @@ -184,7 +184,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySi * @arg @ref LL_CRC_POLYLENGTH_8B * @arg @ref LL_CRC_POLYLENGTH_7B */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); } @@ -215,7 +215,7 @@ __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD * @arg @ref LL_CRC_INDATA_REVERSE_WORD */ -__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); } @@ -242,7 +242,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT */ -__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); } @@ -270,7 +270,7 @@ __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) * @param CRCx CRC Instance * @retval Value programmed in Programmable initial CRC value register */ -__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->INIT)); } @@ -301,7 +301,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t Polyno * @param CRCx CRC Instance * @retval Value programmed in Programmable Polynomial value register */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->POL)); } @@ -359,7 +359,7 @@ __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). */ -__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->DR)); } @@ -371,7 +371,7 @@ __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). */ -__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) +__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx) { return (uint16_t)READ_REG(CRCx->DR); } @@ -383,7 +383,7 @@ __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx) { return (uint8_t)READ_REG(CRCx->DR); } @@ -395,7 +395,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx) { return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); } @@ -407,7 +407,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register). */ -__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->IDR)); } @@ -433,7 +433,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) * @{ */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h index d7938e0651..30795ff166 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h @@ -522,12 +522,10 @@ typedef struct * @arg @ref LL_DAC_RESOLUTION_8B * @retval DAC conversion data (unit: digital value) */ -#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ - __DAC_VOLTAGE__,\ - __DAC_RESOLUTION__) \ -((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ -) +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ + ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ + ) /** * @} @@ -542,6 +540,7 @@ typedef struct /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions * @{ */ + /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels * @{ */ @@ -580,7 +579,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin * @arg @ref LL_DAC_MODE_NORMAL_OPERATION * @arg @ref LL_DAC_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -619,7 +618,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_2 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ -__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -684,7 +683,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 */ -__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -727,7 +726,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -793,7 +792,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -860,7 +859,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -958,7 +957,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1001,7 +1000,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1060,7 +1059,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1102,7 +1101,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 * @arg @ref LL_DAC_CHANNEL_2 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); @@ -1140,7 +1139,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_2 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1177,7 +1176,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3 * @arg @ref LL_DAC_CHANNEL_2 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1239,7 +1238,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_2 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1278,7 +1277,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED * @retval DAC register address */ -__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ @@ -1339,7 +1338,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_2 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1397,7 +1396,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann * @arg @ref LL_DAC_CHANNEL_2 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1570,7 +1569,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_2 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); @@ -1592,7 +1591,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); } @@ -1604,7 +1603,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); } @@ -1616,7 +1615,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); } @@ -1627,7 +1626,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); } @@ -1639,7 +1638,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); } @@ -1651,7 +1650,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); } @@ -1743,7 +1742,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); } @@ -1755,7 +1754,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); } @@ -1770,8 +1769,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) * @{ */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); /** @@ -1798,4 +1797,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); #endif #endif /* STM32G0xx_LL_DAC_H */ - diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h index 51ac3b34a6..57db1bc6c0 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h @@ -497,7 +497,7 @@ typedef struct * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); @@ -517,7 +517,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); @@ -537,7 +537,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -573,7 +573,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -600,7 +600,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -625,7 +625,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -651,7 +651,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint * @arg @ref LL_DMA_MODE_CIRCULAR * @retval None */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC, @@ -674,7 +674,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ * @arg @ref LL_DMA_MODE_NORMAL * @arg @ref LL_DMA_MODE_CIRCULAR */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -698,7 +698,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_PERIPH_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC, @@ -721,7 +721,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_PERIPH_INCREMENT * @arg @ref LL_DMA_PERIPH_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -745,7 +745,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_MEMORY_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC, @@ -768,7 +768,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_MEMORY_INCREMENT * @arg @ref LL_DMA_MEMORY_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -793,7 +793,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE, @@ -817,7 +817,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u * @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -842,7 +842,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE, @@ -866,7 +866,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u * @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -892,7 +892,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL, @@ -917,7 +917,7 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, @@ -964,7 +964,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, @@ -994,7 +994,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1029,7 +1029,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); @@ -1052,7 +1052,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); @@ -1073,7 +1073,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); @@ -1094,7 +1094,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); @@ -1117,7 +1117,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); @@ -1140,7 +1140,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); @@ -1161,7 +1161,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); @@ -1182,7 +1182,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); @@ -1267,7 +1267,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMAMUX_REQ_UCPD2_TX * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -1351,7 +1351,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMAMUX_REQ_UCPD2_RX * @arg @ref LL_DMAMUX_REQ_UCPD2_TX */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID)); @@ -1371,7 +1371,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1382,7 +1382,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1393,7 +1393,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1404,7 +1404,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1415,7 +1415,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1427,7 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1440,7 +1440,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1452,7 +1452,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1463,7 +1463,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1474,7 +1474,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1485,7 +1485,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1496,7 +1496,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1508,7 +1508,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1521,7 +1521,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1533,7 +1533,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1544,7 +1544,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1555,7 +1555,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1566,7 +1566,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1577,7 +1577,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1589,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1602,7 +1602,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1625,7 +1625,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1636,7 +1636,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1647,7 +1647,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1658,7 +1658,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1670,7 +1670,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1683,7 +1683,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -2062,7 +2062,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); @@ -2082,7 +2082,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); @@ -2102,7 +2102,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); @@ -2122,7 +2122,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); @@ -2142,7 +2142,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); @@ -2162,7 +2162,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); @@ -2182,7 +2182,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -2203,7 +2203,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -2224,7 +2224,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h index 1868fe870f..c8086345cf 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h @@ -521,7 +521,7 @@ extern "C" { * @arg @ref LL_DMAMUX_REQ_UCPD2_TX * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -612,7 +612,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_UCPD2_RX * @arg @ref LL_DMAMUX_REQ_UCPD2_TX */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); @@ -642,7 +642,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); @@ -671,7 +671,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); @@ -705,7 +705,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); @@ -738,7 +738,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_SYNC_POL_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); @@ -767,7 +767,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); @@ -796,7 +796,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); @@ -825,7 +825,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); @@ -854,7 +854,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); @@ -883,7 +883,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); @@ -912,7 +912,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); @@ -965,7 +965,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_SYNC_TIM14_OC * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); @@ -1017,7 +1017,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT * @arg @ref LL_DMAMUX_SYNC_TIM14_OC */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); @@ -1034,7 +1034,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * @@ -1052,7 +1052,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * @@ -1070,7 +1070,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * @@ -1093,7 +1093,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) { (void)(DMAMUXx); @@ -1116,7 +1116,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + @@ -1136,7 +1136,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { (void)(DMAMUXx); @@ -1155,7 +1155,7 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + @@ -1197,7 +1197,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) { (void)(DMAMUXx); @@ -1239,7 +1239,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + @@ -1260,7 +1260,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); @@ -1272,7 +1272,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); @@ -1284,7 +1284,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); @@ -1296,7 +1296,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); @@ -1308,7 +1308,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); @@ -1321,7 +1321,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); @@ -1335,7 +1335,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); @@ -1349,7 +1349,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); @@ -1363,7 +1363,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); @@ -1377,7 +1377,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); @@ -1391,7 +1391,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); @@ -1405,7 +1405,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); @@ -1418,7 +1418,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); @@ -1430,7 +1430,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); @@ -1442,7 +1442,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); @@ -1454,7 +1454,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); @@ -1466,7 +1466,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); @@ -1478,7 +1478,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); @@ -1490,7 +1490,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); @@ -1502,7 +1502,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); @@ -1514,7 +1514,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); @@ -1527,7 +1527,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); @@ -1541,7 +1541,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); @@ -1555,7 +1555,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); @@ -1569,7 +1569,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); @@ -1583,7 +1583,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); @@ -1597,7 +1597,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); @@ -1611,7 +1611,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); @@ -1624,7 +1624,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); @@ -1636,7 +1636,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); @@ -1648,7 +1648,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); @@ -1660,7 +1660,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); @@ -1697,7 +1697,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); @@ -1726,7 +1726,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); @@ -1755,7 +1755,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_11 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL); @@ -1772,7 +1772,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); @@ -1789,7 +1789,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); @@ -1806,7 +1806,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_i2c.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_i2c.h index bf396dd210..4a2b154768 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_i2c.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_i2c.h @@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); } @@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); } @@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); } @@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); } @@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); } @@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) { uint32_t data_reg_addr; @@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); } @@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); } @@ -737,7 +737,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); } @@ -772,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); } @@ -800,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT */ -__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); } @@ -849,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); } @@ -905,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); } @@ -930,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); } @@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); } @@ -952,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); } @@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); } @@ -974,7 +974,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); } @@ -1011,7 +1011,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) * @arg @ref LL_I2C_MODE_SMBUS_DEVICE * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP */ -__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); } @@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); } @@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); } @@ -1150,7 +1150,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); } @@ -1182,7 +1182,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); } @@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); } @@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ (ClockTimeout)) ? 1UL : 0UL); @@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); } @@ -1339,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); } @@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); } @@ -1405,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); } @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); } @@ -1477,7 +1477,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); } @@ -1528,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); } @@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); } @@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); } @@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); } @@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); } @@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); } @@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); } @@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); } @@ -1653,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); } @@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); } @@ -1679,7 +1679,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); } @@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); } @@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); } @@ -1725,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); } @@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); } @@ -1899,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); } @@ -1934,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); } @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); } @@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); } @@ -2063,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans * @arg @ref LL_I2C_REQUEST_WRITE * @arg @ref LL_I2C_REQUEST_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); } @@ -2087,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); } @@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** @@ -2150,7 +2157,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr * @arg @ref LL_I2C_DIRECTION_WRITE * @arg @ref LL_I2C_DIRECTION_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); } @@ -2161,7 +2168,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); } @@ -2191,7 +2198,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); } @@ -2204,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); } @@ -2215,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) { return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); } @@ -2241,8 +2248,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) * @{ */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); -ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h index 28a232436a..3cc9bdf943 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h @@ -331,12 +331,25 @@ typedef struct * @{ */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM +/** +@endcond + */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions * @{ */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); @@ -1048,13 +1061,14 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTI * @{ */ + /** * @brief Clear the compare match flag (CMPMCF) - * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM + * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); } @@ -1072,11 +1086,11 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx) /** * @brief Clear the autoreload match flag (ARRMCF) - * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h index 438f971d1c..1450dda58a 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h @@ -1637,8 +1637,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUART return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not @@ -1662,8 +1661,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not @@ -1937,8 +1935,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -1962,8 +1959,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -2090,8 +2086,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -2115,8 +2110,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -2243,8 +2237,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -2268,8 +2261,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h index f739042380..07089678f5 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h @@ -482,7 +482,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) { return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL); } +#endif /* STM32G0C1xx || STM32G0B1xx */ +#if defined(PWR_CR2_USV) /** * @brief Enable VDDUSB supply * @rmtoll CR2 USV LL_PWR_EnableVddUSB @@ -512,7 +514,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) { return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); } -#endif /* STM32G0C1xx || STM32G0B1xx */ +#endif /* PWR_CR2_USV */ #if defined (PWR_PVM_SUPPORT) /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h index 8f1d92a28d..135b67097b 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h @@ -374,10 +374,12 @@ typedef struct #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */ +#if defined(RCC_CCIPR_USART2SEL) #define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */ #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */ +#endif /* RCC_CCIPR_USART2SEL */ #if defined(RCC_CCIPR_USART3SEL) #define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */ #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ @@ -563,7 +565,9 @@ typedef struct * @{ */ #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */ +#if defined(RCC_CCIPR_USART2SEL) #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */ +#endif /* RCC_CCIPR_USART2SEL */ #if defined(RCC_CCIPR_USART3SEL) #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */ #endif /* RCC_CCIPR_USART3SEL */ @@ -1916,10 +1920,10 @@ __STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescal * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) @@ -2160,10 +2164,10 @@ __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h index e165b8d9f1..1cbd5c1436 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h @@ -38,6 +38,7 @@ extern "C" { */ /* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -174,7 +175,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); } @@ -207,7 +208,7 @@ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); } @@ -226,7 +227,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); } @@ -237,7 +238,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); } @@ -248,7 +249,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); } @@ -259,7 +260,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); } @@ -270,7 +271,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); } @@ -336,7 +337,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); } @@ -355,7 +356,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval Generated 32-bit random value */ -__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_REG(RNGx->DR)); } @@ -370,7 +371,7 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) */ ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h index 670ebabb51..50e812bc94 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h @@ -1121,7 +1121,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1155,7 +1155,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1190,7 +1190,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1225,7 +1225,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1275,7 +1275,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1421,7 +1421,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n @@ -1455,7 +1455,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1502,7 +1502,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n @@ -1544,7 +1544,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n @@ -1606,7 +1606,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h index 3e02102edd..fc1806e349 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h @@ -96,12 +96,12 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation * @{ */ -#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IRDA Modulation enveloppe source */ -#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IRDA Modulation enveloppe source */ +#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IRDA Modulation envelope source */ +#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IRDA Modulation envelope source */ #if defined(USART4) -#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IRDA Modulation enveloppe source */ +#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IRDA Modulation envelope source */ #else -#define LL_SYSCFG_IR_MOD_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IRDA Modulation enveloppe source */ +#define LL_SYSCFG_IR_MOD_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IRDA Modulation envelope source */ #endif /* USART4 */ /** * @} @@ -1018,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void) #if defined(SYSCFG_ITLINE12_SR_COMP1) /** - * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21). + * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 17). * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1 * @retval State of bit (1 or 0). */ @@ -1030,7 +1030,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void) #if defined(SYSCFG_ITLINE12_SR_COMP2) /** - * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22). + * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 18). * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2 * @retval State of bit (1 or 0). */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h index 1af48637c4..ad8d1def4e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h @@ -123,7 +123,7 @@ static const uint8_t SHIFT_TAB_OISx[] = (Source == LL_TIM_BKIN_SOURCE_BKCOMP2) ? 2U :3U) #else #define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL) -#endif +#endif /* COMP3 */ /* Generic bit definitions for TIMx_AF1 register */ #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ @@ -662,10 +662,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!> 16U) >> TIM_CCMR1_IC1PSC_Pos))) -/** - * @} - */ - - /** * @} */ @@ -2011,6 +2021,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); } +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check @@ -2155,7 +2176,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) { return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } @@ -2241,8 +2262,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) @@ -2281,8 +2302,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { @@ -2496,7 +2517,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2572,7 +2593,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2657,7 +2678,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3206,7 +3227,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } @@ -3705,18 +3726,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); } -/** - * @brief Re-arm the break input (when it operates in bidirectional mode). - * @note The Break input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); -} - /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -3806,18 +3815,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); } -/** - * @brief Re-arm the break 2 input (when it operates in bidirectional mode). - * @note The Break 2 input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); -} - /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -5236,7 +5233,7 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) * @{ */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h index 69405e8878..09b8d76aac 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART4) || defined(USART5) || defined(USART6) /** @defgroup USART_LL USART * @{ @@ -63,6 +63,12 @@ static const uint32_t USART_PRESCALER_TAB[] = */ /* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup USART_LL_Private_Macros USART Private Macros @@ -1560,7 +1566,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME */ -__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); } @@ -2978,8 +2984,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not @@ -3005,8 +3010,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not @@ -3461,8 +3465,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3488,8 +3491,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -3678,8 +3680,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3705,8 +3706,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -3897,8 +3897,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -3924,8 +3923,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usb.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usb.h index fc419a7350..5e77e649dc 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usb.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usb.h @@ -37,17 +37,19 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ +#ifndef HAL_USB_TIMEOUT +#define HAL_USB_TIMEOUT 0xF000000U +#endif /* define HAL_USB_TIMEOUT */ /** * @brief USB Mode definition */ - typedef enum { - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1 -} USB_DRD_ModeTypeDef; + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1 +} USB_ModeTypeDef; /** * @brief URB States definition @@ -60,7 +62,7 @@ typedef enum URB_NYET, URB_ERROR, URB_STALL -} USB_DRD_URBStateTypeDef; +} USB_URBStateTypeDef; /** * @brief Host channel States definition @@ -77,7 +79,7 @@ typedef enum HC_XACTERR, HC_BBLERR, HC_DATATGLERR -} USB_DRD_HCStateTypeDef; +} USB_HCStateTypeDef; /** @@ -85,39 +87,40 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t Host_channels; /*!< Host Channels number. + uint8_t Host_channels; /*!< Host Channels number. This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t dma_enable; /*!< USB DMA state. + If DMA is not supported this parameter shall be set by default to zero */ - uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - uint32_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ + uint8_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ - uint32_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ -} USB_DRD_CfgTypeDef; + uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ +} USB_CfgTypeDef; typedef struct { @@ -133,6 +136,10 @@ typedef struct uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_LL_EP_Type */ + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ @@ -145,11 +152,6 @@ typedef struct uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ - uint8_t data_pid_start; /*!< Initial data PID - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint16_t tx_fifo_num; /*!< Transmission FIFO number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ @@ -163,7 +165,7 @@ typedef struct uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ -} USB_DRD_EPTypeDef; +} USB_EPTypeDef; typedef struct { @@ -183,6 +185,9 @@ typedef struct This parameter can be any value of @ref HCD_Device_Speed: (HCD_DEVICE_SPEED_xxx) */ + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ + uint8_t ep_type; /*!< Endpoint Type. This parameter can be any value of @ref USB_LL_EP_Type */ @@ -198,6 +203,7 @@ typedef struct uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ uint8_t toggle_in; /*!< IN transfer current toggle flag. @@ -220,22 +226,25 @@ typedef struct uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ - USB_DRD_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - - USB_DRD_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ -} USB_DRD_HCTypeDef; + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; +typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; +typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; +typedef USB_EPTypeDef USB_DRD_EPTypeDef; +typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; +typedef USB_HCTypeDef USB_DRD_HCTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ */ - - /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ @@ -259,6 +268,27 @@ typedef struct * @} */ +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type + * @{ + */ +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U +/** + * @} + */ + /** @defgroup USB_LL Device Speed * @{ */ @@ -268,25 +298,19 @@ typedef struct * @} */ -#define BTABLE_ADDRESS 0x000U - #define EP_ADDR_MSK 0x7U #ifndef USE_USB_DOUBLE_BUFFER #define USE_USB_DOUBLE_BUFFER 1U #endif /* USE_USB_DOUBLE_BUFFER */ +#define USB_EMBEDDED_PHY 2U + /*!< USB Speed */ #define USB_DRD_SPEED_FS 1U #define USB_DRD_SPEED_LS 2U #define USB_DRD_SPEED_LSFS 3U -/*!< PID */ -#define HC_PID_DATA0 0U -#define HC_PID_DATA2 1U -#define HC_PID_DATA1 2U -#define HC_PID_SETUP 3U - /*!< Channel Direction */ #define CH_IN_DIR 1U #define CH_OUT_DIR 0U @@ -360,7 +384,7 @@ typedef struct \ _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) ; \ \ - /*Set Setup bit*/ \ + /* Set Setup bit */ \ USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_SETUP)); \ } while(0) @@ -660,7 +684,7 @@ typedef struct do { \ uint32_t wNBlocks; \ \ - (pdwReg) &= USB_PMA_RXBD_COUNTMSK; \ + (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ if ((wCount) > 62U) \ { \ @@ -670,7 +694,6 @@ typedef struct { \ if ((wCount) == 0U) \ { \ - (pdwReg) &= (uint32_t)~USB_CNTRX_NBLK_MSK; \ (pdwReg) |= USB_CNTRX_BLSIZE; \ } \ else \ @@ -709,8 +732,8 @@ typedef struct * @param bEpChNum Endpoint Number. * @retval Counter value */ -#define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >>16U) -#define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >>16U) +#define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >> 16U) +#define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >> 16U) #define USB_DRD_GET_EP_TX_CNT USB_GET_CHEP_TX_CNT #define USB_DRD_GET_CH_TX_CNT USB_GET_CHEP_TX_CNT @@ -804,6 +827,7 @@ typedef struct */ #define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) #define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) + /** * @} */ @@ -825,6 +849,9 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode); +HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num); + #if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); @@ -838,7 +865,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx); -uint32_t USB_ReadInterrupts(USB_DRD_TypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); @@ -846,8 +873,8 @@ HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); -uint32_t USB_GetHostSpeed(USB_DRD_TypeDef *USBx); -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef *USBx); +uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, @@ -856,10 +883,10 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); -void USB_WritePMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, +void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void USB_ReadPMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, +void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_utils.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_utils.h index 6f664b8621..c0dd8bc2ef 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_utils.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_utils.h @@ -290,7 +290,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) * @note When a RTOS is used, it is recommended to avoid changing the SysTick * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks + * @param Ticks Frequency of Ticks (Hz) * @retval None */ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_wwdg.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_wwdg.h index bfe4ba1de3..6916f62d21 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_wwdg.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_wwdg.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } @@ -162,7 +162,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Counter value */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } @@ -203,7 +203,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale * @arg @ref LL_WWDG_PRESCALER_64 * @arg @ref LL_WWDG_PRESCALER_128 */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } @@ -235,7 +235,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Window value */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } @@ -256,7 +256,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } @@ -298,7 +298,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32G0xx_HAL_Driver/Release_Notes.html index ee4a9a8689..1ba7c1bd2d 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32G0xx_HAL_Driver/Release_Notes.html @@ -39,36 +39,153 @@

        Purpose

        Update History

        - +

        Main Changes

        Maintenance release

          -
        • General updates to fix known defects and enhancements implementation.
          • -

        • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers

          • -
        • HAL/LL Drivers updates +
        • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
          • +
        • HAL/LL GENERIC update
            -
          • HAL CEC updates +
          • Fix the COMP EXTI line in the comments.
            • +
          • Allow redefinition of macro UNUSED(x).
            • +
          • Update of HAL_GetTickFreq() brief.
            • +
          • +
        • HAL EXTI update
            -
          • Better performance by removing multiple volatile reads or writes in interrupt handler.
            • +
          • Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine().
            • +
          • Fix the wrong references in the “How to use this driver” section.
          • -
        • HAL RTC updates +
        • HAL CRC update
            -
          • Check if the RTC calendar has been previously initialized before entering Initialization mode.
            • +
          • Add filter in HAL_CRCEx_Polynomial_Set() to exclude even polynomials.
          • -
        • HAL I2C updates +
        • HAL CRYP update
            -
          • I2C_IsErrorOccurred does not return error if timeout is detected.
            • -
          • The ADDRF flag is cleared too early when the restart is received but the direction has changed
            • +
          • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment.
            • +
          • Update AES GCM in interrupt mode to avoid Computation Completed IRQ fires before the DINR pointer increment.
          • -
        • HAL UART updates +
        • LL ADC update
            -
          • Removal of HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs
            • +
          • Remove useless action of conversion trigger change in function LL_ADC_DeInit(). Moreover, this action was not compliant with ADC enable state (cf reference manual).
          • -
        • HAL USB updates +
        • HAL DAC update +
            +
          • Fix incorrect word ‘surcharged’ in functions headers.
            • +
          • Fix HAL_GetTick() timeout vulnerability.
            • +
          • Updated DAC buffer calibration according to RM.
            • +
          • +
        • HAL/LL RTC update +
            +
          • Optimize the way RSF flag is cleared in HAL_RTC_WaitForSynchro().
            • +
          • Correct misleading note about shadow registers.
            • +
          • Update HAL_RTC_XXX_GET_IT(), HAL_RTC_XXX_GET_FLAG(), and HAL_RTC_XXX_CLEAR_FLAG() macros with correct registers and bitmasks.
            • +
          • +
        • HAL RCC update +
            +
          • Rework HAL_RCC_MCOConfig() API to support all RCC_MCOx parameter values (GPIO pins) from Datasheet.
            • +
          • Enclose in parentheses parameters of a group of macros to avoid Misra-C 2012 Rule-20.7 warnings.
            • +
          • Add else statement in the end of HAL_RCC_MCOConfig API to avoid Misra-C 2012 Rule-15.7 warnings.
            • +
          • Add defined(RCC_CCIPR_USART2SEL) for selecting the USART2 clock source in stm32g0xx_ll_rcc.h file.
            • +
          • +
        • HAL PWR update +
            +
          • Update to support USB supply enable feature for STM32G0B0 devices.
            • +
          • +
        • HAL CORTEX update +
            +
          • Update HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
            • +
          • Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().
            • +
          • +
        • HAL/LL TIM update
            -
          • HAL: HCD: add missing call to MspDeInit API during HCD DeInit
            • +
          • Remove useless check on IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() to fix Break Filter configuration problem with specific TIM instances.
            • +
          • Remove lock management from callback management functions.
            • +
          • Remove multiple volatile reads or writes in interrupt handler for better performance.
            • +
          • Improve HAL TIM driver’s operational behavior.
            • +
          • Assert check for the right channels.
            • +
          • Improve period configuration parameter check.
            • +
          • Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init().
          • +
        • HAL/LL LPTIM update +
            +
          • Apply the same naming rule to clear FLAG related functions.
            • +
          • Remove Lock management from callback management functions.
            • +
          • Remove redundant IS_LPTIM_AUTORELOAD macro.
            • +
          • +
        • HAL FDCAN update +
            +
          • Fix GetIndex issue in HAL_FDCAN_GetRxMessage.
            • +
          • +
        • HAL FLASH update +
            +
          • Remove the plural form in the description of the __HAL_FLASH_CLEAR_FLAG macro.
            • +
          • Fix __HAL_FLASH_CLEAR_FLAG macro.
            • +
          • Fix timeout check in FLASH_WaitForLastOperation().
            • +
          • Update HAL_FLASH_Unlock/HAL_FLASH_Lock and HAL_FLASH_OB_Unlock/HAL_FLASH_OB_Lock functions to check BSY1, BSY2 and CFGBSY bits before performing Unlock/Lock sequence.
            • +
          • Fix Misra-C:2012 Rule-17.7 warnings: The return value of `FLASH_WaitForLastOperation()’ call is discarded.
            • +
          • +
        • HAL UART update +
            +
          • Disable the Receiver Timeout Interrupt when data reception is completed.
            • +
          • Remove lock management from callback management functions.
            • +
          • Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.
            • +
          • Remove __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
            • +
          • Update initialisation sequence for TXINV, RXINV and TXRXSWAP settings.
            • +
          • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to allow user Rx Event Callback registration when a transmit is ongoing.
            • +
          • Avoid RTOF flag to be cleared by a transmit process in polling mode.
            • +
          • +
        • HAL USART update +
            +
          • Remove __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
            • +
          • +
        • HAL IRDA update +
            +
          • Remove __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
            • +
          • +
        • HAL SMARTCARD update +
            +
          • Correct USART3 clock source computation for smartcard initialisation.
            • +
          • Remove __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
            • +
          • +
        • HAL/LL I2C update +
            +
          • Duplicate the test condition after timeout detection to avoid false timeout detection.
            • +
          • Update HAL_I2C_IsDeviceReady API to support 10_bit addressing mode: Update done on the macro I2C_GENERATE_START.
            • +
          • Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
            • +
          • Update HAL I2C driver to disable all interrupts after end of transaction.
            • +
          • Update HAL_I2C_Init API to clear ADD10 bit in 7 bit addressing mode.
            • +
          • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice.
            • +
          • Solve Slave No stretch not functional by using HAL Slave interface.
            • +
          • Update HAL_I2C_Mem_Write_IT API to initialize XferSize at 0.
            • +
          • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE.
            • +
          • Remove the unusable code in function HAL_I2C_IsDeviceReady.
            • +
          • Update I2C_WaitOnFlagUntilTimeout to handle error case.
            • +
          • Update HAL_I2C_Slave_Transmit to check if the received NACK is the good one.
            • +
          • Update LL_I2C_HandleTranfer function to prevent undefined behavior of volatile usage before updating the CR2 register.
            • +
          • +
        • HAL SMBUS update +
            +
          • Update HAL SMBUS driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte
            • +
          • Update SMBUS_ITErrorHandler to flash TXDR just in case of error.
            • +
          • +
        • HAL/LL SPI update +
            +
          • Fix driver to don’t update state in case of error (HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT).
            • +
          • Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of one byte transaction.
            • +
          • Update IT API to enable interrupts after process unlock.
            • +
          • +
        • HAL/LL USB update +
            +
          • hal_hcd.c/ll_usb.c: fix double buffer mode configuration in host mode for isochronous and bulk transfers.
            • +
          • ll_usb.h: use correct macro to clear RXBD register block numbers.
            • +
          • hcd.h: update delay before reading RXBD register.
            • +
          • hcd.c: prevent channel auto start of periodic interrupt transfer during NAK.
            • +
          • ll_usb.c: increase timeout value to allow core reset to complete.
            • +
          • +
        • LL UTILS update +
            +
          • Fix a note about Ticks parameter.

        Known limitations

        @@ -77,9 +194,9 @@

        Known limitations

      Development Toolchains and Compilers

        -
      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
        • -
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
        • -
      • STM32CubeIDE toolchain (gcc9_2020_q2_update) v1.7.0
        • +
      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
        • +
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38
        • +
      • STM32CubeIDE toolchain V1.14.0

      Supported Devices and boards

      Supported Devices:

      @@ -97,11 +214,45 @@

      Dependencies

      - +

      Main Changes

      Maintenance release

        +
      • General updates to fix known defects and enhancements implementation.
        • +
      • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers
        • +
      +

      Known limitations

      +
        +
      • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
        • +
      +

      Development Toolchains and Compilers

      +
        +
      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
        • +
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
        • +
      • STM32CubeIDE toolchain (gcc9_2020_q2_update) v1.7.0
        • +
      +

      Supported Devices and boards

      +

      Supported Devices:

      +
        +
      • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
        • +
      • STM32G061xx, STM32G051xx, STM32G050xx
        • +
      • STM32G081xx, STM32G071xx, STM32G070xx
        • +
      • STM32G041xx, STM32G031xx, STM32G030xx
        • +
      +

      Backward Compatibility

      +

      This release is compatible with the previous versions.

      +

      Dependencies

      +


      +

      +
      +
      +
      + +
      +

      Main Changes

      +

      Maintenance release

      +

      • General updates to fix known defects and enhancements implementation.

      • HAL/LL Drivers updates
          @@ -129,7 +280,7 @@

          Maintenance release

        • HAL/LL RCC updates
          • Enhance the PLL configuration in HAL_RCC_ClockConfig() API.
            • -
          • Add the followings new APIs to check if PLL output mapped on different domain clock is enabled: +
          • Add the following new APIs to check if PLL output mapped on different domain clock is enabled:
            • LL_RCC_PLL_IsEnabledDomain_ADC()
            • LL_RCC_PLL_IsEnabledDomain_I2S1()
              • @@ -234,17 +385,17 @@

              Maintenance release

        -

        Known limitations

        +

        Known limitations

        • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
        -

        Development Toolchains and Compilers

        +

        Development Toolchains and Compilers

        • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
        • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
        • STM32CubeIDE toolchain (gcc9_2020_q2_update) v1.7.0
        -

        Supported Devices and boards

        +

        Supported Devices and boards

        Supported Devices:

        • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
          • @@ -252,9 +403,9 @@

          Supported Devices and boards

        • STM32G081xx, STM32G071xx, STM32G070xx
        • STM32G041xx, STM32G031xx, STM32G030xx
        -

        Backward Compatibility

        +

        Backward Compatibility

        This release is compatible with the previous versions.

        -

        Dependencies

        +

        Dependencies


      @@ -262,8 +413,8 @@

      Dependencies

      -

      Main Changes

      -

      Maintenance release

      +

      Main Changes

      +

      Maintenance release

      • HAL/LL Drivers updates
          @@ -276,17 +427,17 @@

          Maintenance release

    -

    Known limitations

    +

    Known limitations

    • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
    • STM32CubeIDE toolchain v1.7.0
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    Supported Devices:

    • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
      • @@ -295,7 +446,7 @@

      Supported Devices and boards

    • STM32G041xx, STM32G031xx, STM32G030xx ## Backward Compatibility

    This release is compatible with the previous versions.

    -

    Dependencies

    +

    Dependencies


@@ -303,8 +454,8 @@

Dependencies

-

Main Changes

-

Maintenance release

+

Main Changes

+

Maintenance release

  • General updates to fix known defects and enhancements implementation.

  • HAL/LL Drivers updates

    • @@ -434,17 +585,17 @@

    Maintenance release

  • Add fix transfer complete for IN Interrupt transaction in single buffer mode.
-

Known limitations

+

Known limitations

  • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
-

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
  • STM32CubeIDE toolchain v1.7.0
-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
    • @@ -453,7 +604,7 @@

    Supported Devices and boards

  • STM32G041xx, STM32G031xx, STM32G030xx ## Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies


@@ -461,7 +612,7 @@

Dependencies

-

Main Changes

+

Main Changes

Patch release

Patch release of HAL and Low Layer drivers

Additional features

@@ -477,17 +628,17 @@

Patch release

-

Known limitations

+

Known limitations

  • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
-

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29
  • STM32CubeIDE toolchain v1.5.0
-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
    • @@ -495,9 +646,9 @@

    Supported Devices and boards

  • STM32G081xx, STM32G071xx, STM32G070xx
  • STM32G041xx, STM32G031xx, STM32G030xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies


@@ -505,7 +656,7 @@

Dependencies

-

Main Changes

+

Main Changes

Maintenance release and Product Update

Official release of HAL and Low layers drivers introducing STM32G0C1xx/STM32G0B1xx/STM32G0B0xx devices and STM32G061xx/STM32G051xx/STM32G050xx devices.

Maintenance release of HAL and Low layers drivers supporting STM32G041xx/STM32G031xx/STM32G030xx and STM32G081xx/STM32G071xx/STM32G070xx devices.

@@ -972,17 +1123,17 @@

Maintenance release and Product -

Known limitations

+

Known limitations

  • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
-

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29
  • STM32CubeIDE toolchain v1.5.0
-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
    • @@ -990,9 +1141,9 @@

    Supported Devices and boards

  • STM32G081xx, STM32G071xx, STM32G070xx
  • STM32G041xx, STM32G031xx, STM32G030xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies


@@ -1000,8 +1151,8 @@

Dependencies

-

Main Changes

-

Maintenance release

+

Main Changes

+

Maintenance release

Maintenance release of HAL and Low layers drivers supporting STM32G041xx/STM32G031xx/STM32G030xx and STM32G081xx/STM32G071xx/STM32G070xx devices.

Fixed bugs list

@@ -1070,27 +1221,27 @@

Maintenance release

-

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G081xx, STM32G071xx, STM32G070xx
  • STM32G041xx, STM32G031xx, STM32G030xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies

-

Main Changes

+

Main Changes

Maintenance release and product update

First release of HAL and Low layers drivers to introduce support of STM32G041xx/STM32G031xx/STM32G030xx devices.

Maintenance release of HAL and Low layers drivers supporting STM32G081xx/STM32G071xx/STM32G070xx devices.

@@ -1177,27 +1328,27 @@

Maintenance release and produc -

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G081xx, STM32G071xx, STM32G070xx
  • STM32G041xx, STM32G031xx, STM32G030xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies

-

Main Changes

+

Main Changes

Maintenance release and product update

Maintenance release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx devices.

Additional features

@@ -1286,32 +1437,32 @@

Maintenance release and produc -

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G081xx
  • STM32G071xx
  • STM32G070xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies

-

Main Changes

+

Main Changes

First release

First official release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx

-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G081xx
  • STM32G071xx
  • STM32G070xx
-

Dependencies

+

Dependencies

diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c index 0c58338208..f03e8946c8 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c @@ -57,7 +57,7 @@ */ #define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ -#define __STM32G0xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ +#define __STM32G0xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ #define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\ |(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\ @@ -362,7 +362,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) /** * @brief return tick frequency. - * @retval tick period in Hz + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. */ HAL_TickFreqTypeDef HAL_GetTickFreq(void) { diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c index 17ea3a6690..3300b4d315 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c @@ -253,11 +253,11 @@ all callbacks are set to the corresponding weak functions: examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_ADC_Init()/HAL_ADC_DeInit() only when + reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the HAL_ADC_Init()/HAL_ADC_DeInit() + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] @@ -277,6 +277,7 @@ are set to the corresponding weak functions. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -378,8 +379,8 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpCFGR1 = 0UL; - uint32_t tmpCFGR2 = 0UL; + uint32_t tmp_cfgr1 = 0UL; + uint32_t tmp_cfgr2 = 0UL; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; @@ -540,14 +541,14 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* - internal measurement paths (VrefInt, ...) */ /* (set into HAL_ADC_ConfigChannel() ) */ - tmpCFGR1 |= (hadc->Init.Resolution | - ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | - ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | - hadc->Init.DataAlign | - ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | - ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + tmp_cfgr1 |= (hadc->Init.Resolution | + ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + hadc->Init.DataAlign | + ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | + ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); /* Update setting of discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) @@ -555,7 +556,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) if (hadc->Init.ContinuousConvMode == DISABLE) { /* Enable the selected ADC group regular discontinuous mode */ - tmpCFGR1 |= ADC_CFGR1_DISCEN; + tmp_cfgr1 |= ADC_CFGR1_DISCEN; } else { @@ -578,37 +579,38 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { - tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | - hadc->Init.ExternalTrigConvEdge); + tmp_cfgr1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | + hadc->Init.ExternalTrigConvEdge); } /* Update ADC configuration register with previous settings */ MODIFY_REG(hadc->Instance->CFGR1, - ADC_CFGR1_RES | - ADC_CFGR1_DISCEN | - ADC_CFGR1_AUTOFF | - ADC_CFGR1_WAIT | - ADC_CFGR1_CONT | - ADC_CFGR1_OVRMOD | - ADC_CFGR1_EXTSEL | - ADC_CFGR1_EXTEN | - ADC_CFGR1_ALIGN | - ADC_CFGR1_SCANDIR | + ADC_CFGR1_RES | + ADC_CFGR1_DISCEN | + ADC_CFGR1_CHSELRMOD | + ADC_CFGR1_AUTOFF | + ADC_CFGR1_WAIT | + ADC_CFGR1_CONT | + ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTSEL | + ADC_CFGR1_EXTEN | + ADC_CFGR1_ALIGN | + ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG, - tmpCFGR1); + tmp_cfgr1); - tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - hadc->Init.TriggerFrequencyMode - ); + tmp_cfgr2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + hadc->Init.TriggerFrequencyMode + ); if (hadc->Init.OversamplingMode == ENABLE) { - tmpCFGR2 |= (ADC_CFGR2_OVSE | - (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - hadc->Init.Oversampling.Ratio | - hadc->Init.Oversampling.RightBitShift | - hadc->Init.Oversampling.TriggeredMode - ); + tmp_cfgr2 |= (ADC_CFGR2_OVSE | + (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode + ); } MODIFY_REG(hadc->Instance->CFGR2, @@ -618,7 +620,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) ADC_CFGR2_OVSR | ADC_CFGR2_OVSS | ADC_CFGR2_TOVS, - tmpCFGR2); + tmp_cfgr2); /* Configuration of ADC clock mode: asynchronous clock source */ /* with selectable prescaler. */ @@ -670,11 +672,15 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) | (hadc->ADCGroupRegularSequencerRanks) ); } + else + { + /* Nothing to do */ + } /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core peripheral clocking. */ - if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) - == hadc->Init.SamplingTimeCommon1) + if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) + == hadc->Init.SamplingTimeCommon1) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); @@ -785,29 +791,32 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Reset register CFGR1 */ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN | - ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | + ADC_CFGR1_CHSELRMOD | ADC_CFGR1_AUTOFF | + ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN); - /* Reset register CFGR2 */ - /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ - /* already done above. */ - hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; - /* Reset register SMPR */ hadc->Instance->SMPR &= ~ADC_SMPR_SMP1; - /* Reset registers AWDxTR */ - hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1); - hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2); - hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3); - /* Reset register CHSELR */ hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL); /* Reset register DR */ /* bits in access mode read only, no direct reset applicable */ + /* Reset registers AWDxTR */ + hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1); + hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2); + hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3); + + /* Reset register CFGR2 */ + /* Note: CFGR2 reset done at the end of de-initialization due to */ + /* clock source reset */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; + /* Reset register CCR */ ADC1_COMMON->CCR &= ~(ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC); @@ -1018,7 +1027,7 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca { HAL_StatusTypeDef status = HAL_OK; - if ((hadc->State & HAL_ADC_STATE_READY) != 0) + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) { @@ -1107,7 +1116,7 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca */ /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions - * @brief ADC IO operation functions + * @brief ADC IO operation functions * @verbatim =============================================================================== @@ -1369,12 +1378,12 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event - * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all - * STM32 series) - * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all - * STM32 series) - * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all - * STM32 series) + * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on + * all STM32 series) + * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on + * all STM32 series) + * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on + * all STM32 series) * @arg @ref ADC_OVR_EVENT ADC Overrun event * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. @@ -1830,7 +1839,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2155,7 +2164,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig) +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_config_internal_channel; @@ -2363,7 +2372,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_awd_high_threshold_shifted; @@ -2599,7 +2608,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2613,7 +2622,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c index c3a9bf63bb..35a512148e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c @@ -26,6 +26,7 @@ available in file of generic functions "stm32g0xx_hal_adc.c". [..] @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -106,6 +107,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) uint32_t calibration_index; uint32_t calibration_factor_accumulated = 0; uint32_t tickstart; + uint32_t adc_clk_async_presc; + __IO uint32_t delay_cpu_cycles; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -164,8 +167,30 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) } /* Compute average */ calibration_factor_accumulated /= calibration_index; - /* Apply calibration factor */ + + /* Apply calibration factor (requires ADC enable and disable process) */ LL_ADC_Enable(hadc->Instance); + + /* Case of ADC clocked at low frequency: Delay required between ADC enable and disable actions */ + if (LL_ADC_GetClock(hadc->Instance) == LL_ADC_CLOCK_ASYNC) + { + adc_clk_async_presc = LL_ADC_GetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + if (adc_clk_async_presc >= LL_ADC_CLOCK_ASYNC_DIV16) + { + /* Delay loop initialization and execution */ + /* Delay depends on ADC clock prescaler: Compute ADC clock asynchronous prescaler to decimal format */ + delay_cpu_cycles = (1UL << ((adc_clk_async_presc >> ADC_CCR_PRESC_Pos) - 3UL)); + /* Divide variable by 2 to compensate partially CPU processing cycles */ + delay_cpu_cycles >>= 1UL; + + while (delay_cpu_cycles != 0UL) + { + delay_cpu_cycles--; + } + } + } + LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated); LL_ADC_Disable(hadc->Instance); @@ -217,7 +242,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) * @param hadc ADC handle. * @retval Calibration value. */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c index 2ae97e46e6..b31d4a761f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c @@ -830,7 +830,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) __HAL_CEC_LAST_BYTE_TX_SET(hcec); } /* In all cases transmit the byte */ - hcec->Instance->TXDR = (uint8_t)*hcec->pTxBuffPtr; + hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr; hcec->pTxBuffPtr++; /* clear Tx-Byte request flag */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); @@ -856,7 +856,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* ----------------------------Rx/Tx Error Management----------------------------------*/ if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | - CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U) + CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U) { hcec->ErrorCode = itflag; __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE | diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c index 052e15d737..5b5f3caa84 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c @@ -21,9 +21,9 @@ * ****************************************************************************** @verbatim -================================================================================ + ============================================================================== ##### COMP Peripheral features ##### -================================================================================ + ============================================================================== [..] The STM32G0xx device family integrates two analog comparators instances: @@ -47,7 +47,7 @@ using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). ##### How to use this driver ##### -================================================================================ + ============================================================================== [..] This driver provides functions to configure and program the comparator instances of STM32G0xx devices. @@ -153,7 +153,6 @@ @endverbatim ****************************************************************************** - */ /* Includes ------------------------------------------------------------------*/ @@ -183,7 +182,7 @@ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */ +#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */ /* Delay for COMP voltage scaler stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ @@ -235,16 +234,16 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) __IO uint32_t wait_loop_index = 0UL; HAL_StatusTypeDef status = HAL_OK; #if defined(COMP3) - __IO uint32_t * comp_common_odd; - __IO uint32_t * comp_common_even; + __IO uint32_t *comp_common_odd; + __IO uint32_t *comp_common_even; #endif /* COMP3 */ /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -259,13 +258,15 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); + assert_param(IS_COMP_WINDOWMODE(hcomp->Instance, hcomp->Init.WindowMode)); - if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) + if (hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) { assert_param(IS_COMP_WINDOWOUTPUT(hcomp->Init.WindowOutput)); } - if(hcomp->State == HAL_COMP_STATE_RESET) + + if (hcomp->State == HAL_COMP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; @@ -273,7 +274,6 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); - #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) /* Init the COMP Callback settings */ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ @@ -301,7 +301,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)); /* Set COMP parameters */ - tmp_csr = ( hcomp->Init.InputMinus + tmp_csr = (hcomp->Init.InputMinus | hcomp->Init.InputPlus | hcomp->Init.BlankingSrce | hcomp->Init.Hysteresis @@ -314,16 +314,18 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_WINMODE | COMP_CSR_POLARITY | COMP_CSR_HYST | - COMP_CSR_BLANKING , + COMP_CSR_BLANKING, tmp_csr ); + /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ + #if defined(COMP3) - if(hcomp->Instance == COMP3) + if (hcomp->Instance == COMP3) { /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common */ /* group of COMP2 and COMP3, instances odd and even are inverted. */ @@ -337,12 +339,12 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) comp_common_even = &(COMP12_COMMON->CSR_EVEN); } - if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) + if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) { CLEAR_BIT(*comp_common_odd, COMP_CSR_WINMODE); SET_BIT(*comp_common_even, COMP_CSR_WINMODE); } - else if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) + else if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) { SET_BIT(*comp_common_odd, COMP_CSR_WINMODE); CLEAR_BIT(*comp_common_even, COMP_CSR_WINMODE); @@ -380,12 +382,12 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) break; } #else - if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) + if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) { CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); } - else if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) + else if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) { SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); @@ -424,17 +426,18 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) } #endif /* COMP3 */ + /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is required and not already enabled */ if ((READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)) != 0UL) && - (comp_voltage_scaler_initialized == 0UL) ) + (comp_voltage_scaler_initialized == 0UL)) { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - while(wait_loop_index != 0UL) + while (wait_loop_index != 0UL) { wait_loop_index--; } @@ -444,10 +447,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); /* Manage EXTI settings */ - if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) + if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) { /* Configure EXTI rising edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) { LL_EXTI_EnableRisingTrig_0_31(exti_line); } @@ -457,7 +460,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) } /* Configure EXTI falling edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) { LL_EXTI_EnableFallingTrig_0_31(exti_line); } @@ -471,7 +474,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) LL_EXTI_ClearFallingFlag_0_31(exti_line); /* Configure EXTI event mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) { LL_EXTI_EnableEvent_0_31(exti_line); } @@ -481,7 +484,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) } /* Configure EXTI interrupt mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) { LL_EXTI_EnableIT_0_31(exti_line); } @@ -523,11 +526,11 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -606,7 +609,8 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, + pCOMP_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -782,11 +786,11 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -795,7 +799,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - if(hcomp->State == HAL_COMP_STATE_READY) + if (hcomp->State == HAL_COMP_STATE_READY) { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN); @@ -809,7 +813,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - while(wait_loop_index != 0UL) + while (wait_loop_index != 0UL) { wait_loop_index--; } @@ -833,11 +837,11 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -848,7 +852,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */ /* (all states except HAL_COMP_STATE_RESET and except locked status. */ - if(hcomp->State != HAL_COMP_STATE_RESET) + if (hcomp->State != HAL_COMP_STATE_RESET) { /* Disable the selected comparator */ CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN); @@ -878,7 +882,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) uint32_t comparator_window_exti_lines; #if defined(COMP3) - if(hcomp->Instance == COMP3) + if (hcomp->Instance == COMP3) { /* Case of window mode with COMP2 and COMP3 */ comparator_window_mode = READ_BIT(COMP23_COMMON->CSR_EVEN, COMP_CSR_WINMODE); @@ -887,7 +891,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) else { comparator_window_mode = READ_BIT(COMP23_COMMON->CSR_EVEN, COMP_CSR_WINMODE); - if( (hcomp->Instance == COMP2) && (comparator_window_mode != 0UL)) + if ((hcomp->Instance == COMP2) && (comparator_window_mode != 0UL)) { /* Case of window mode with COMP2 and COMP3 */ comparator_window_exti_lines = (COMP_EXTI_LINE_COMP2 | COMP_EXTI_LINE_COMP3); @@ -901,16 +905,16 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) } } #else - comparator_window_mode = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); - comparator_window_mode |= READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); - comparator_window_exti_lines = (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2); + comparator_window_mode = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + comparator_window_mode |= READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + comparator_window_exti_lines = (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2); #endif /* COMP3 */ /* Check COMP EXTI flag */ - if(LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL) + if (LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL) { /* Check whether comparator is in independent or window mode */ - if(comparator_window_mode != 0UL) + if (comparator_window_mode != 0UL) { /* Clear COMP EXTI line pending bit of the pair of comparators */ /* in window mode. */ @@ -934,10 +938,10 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) HAL_COMP_TriggerCallback(hcomp); #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } - else if(LL_EXTI_IsActiveFallingFlag_0_31(exti_line) != 0UL) + else if (LL_EXTI_IsActiveFallingFlag_0_31(exti_line) != 0UL) { /* Check whether comparator is in independent or window mode */ - if(comparator_window_mode != 0UL) + if (comparator_window_mode != 0UL) { /* Clear COMP EXTI line pending bit of the pair of comparators */ /* in window mode. */ @@ -998,11 +1002,11 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -1012,7 +1016,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); /* Set HAL COMP handle state */ - switch(hcomp->State) + switch (hcomp->State) { case HAL_COMP_STATE_RESET: hcomp->State = HAL_COMP_STATE_RESET_LOCKED; @@ -1024,10 +1028,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; break; } - } - if(status == HAL_OK) - { /* Set the lock bit corresponding to selected comparator */ __HAL_COMP_LOCK(hcomp); } @@ -1054,7 +1055,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * @arg COMP_OUTPUT_LEVEL_HIGH * */ -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); @@ -1102,10 +1103,10 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval HAL state */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ - if(hcomp == NULL) + if (hcomp == NULL) { return HAL_COMP_STATE_RESET; } @@ -1122,7 +1123,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval COMP error code */ -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp) { /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c index 40a9be15be..aafab80bca 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c @@ -352,6 +352,37 @@ void HAL_MPU_Disable(void) MPU->CTRL = 0; } +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} /** * @brief Initialize and configure the Region and the memory to be protected. @@ -364,38 +395,32 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; - if ((MPU_Init->Enable) != 0U) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00U; - MPU->RASR = 0x00U; - } + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } #endif /* __MPU_PRESENT */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c index 4ebb0afe2c..d170c8b5a6 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + CLEAR_REG(hcrc->Instance->IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); @@ -403,7 +403,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t * @param hcrc CRC handle * @retval HAL state */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) { /* Return CRC handle state */ return hcrc->State; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c index 6e37e11436..37b78f407b 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c @@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); - /* check polynomial definition vs polynomial size: - * polynomial length must be aligned with polynomial - * definition. HAL_ERROR is reported if Pol degree is - * larger than that indicated by PolyLength. - * Look for MSB position: msb will contain the degree of - * the second to the largest polynomial member. E.g., for - * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + /* Ensure that the generating polynomial is odd */ + if ((Pol & (uint32_t)(0x1U)) == 0U) { + status = HAL_ERROR; } - - switch (PolyLength) + else { - case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_8B: - if (msb >= HAL_CRC_LENGTH_8B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_16B: - if (msb >= HAL_CRC_LENGTH_16B) - { - status = HAL_ERROR; - } - break; - - case CRC_POLYLENGTH_32B: - /* no polynomial definition vs. polynomial length issue possible */ - break; - default: - status = HAL_ERROR; - break; + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } } if (status == HAL_OK) { diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c index c0c9deb809..590a5a6803 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c @@ -30,7 +30,8 @@ The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows: (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral + (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE() + or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT()) (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() @@ -58,8 +59,10 @@ (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication algorithms) is in words or bytes. (##) The Header used only in AES GCM and CCM Algorithm for authentication. - (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field. - (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes. + (##) The HeaderSize providing the size of the header buffer in words or bytes, + depending upon HeaderWidthUnit field. + (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) + is in words or bytes. (##) The B0 block is the first authentication block used only in AES CCM mode. (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below). @@ -78,7 +81,7 @@ the CRYP peripheral is configured and processes the buffer in input. At second call, no need to Initialize the CRYP, user have to get current configuration via HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set - new parametres, finally user can start encryption/decryption. + new parameters, finally user can start encryption/decryption. (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. @@ -200,7 +203,7 @@ (##) To perform message payload encryption or decryption AES is configured in CTR mode. (##) For authentication two phases are performed : - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message - only cleartext payload (not the ciphertext payload) is used and no outpout. + only cleartext payload (not the ciphertext payload) is used and no output. (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. *** Callback registration *** @@ -316,7 +319,8 @@ * @{ */ #define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey + is 299 clock cycles.*/ #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/ #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */ @@ -350,7 +354,8 @@ * @{ */ -#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__)) +#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR,\ + AES_CR_GCMPH, (uint32_t)(__PHASE__)) /** * @} @@ -390,12 +395,12 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) -static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output); -static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input); -static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output); -static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input); -static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize); -static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize); +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output); +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input); +static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output); +static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input); +static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize); +static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize); static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ @@ -488,7 +493,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and Algorithm */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /* Reset Error Code field */ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; @@ -511,7 +517,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ @@ -600,7 +606,8 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /*clear error flags*/ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); @@ -733,7 +740,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -954,14 +962,14 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) /* If authentication algorithms on-going, carry out first saving steps before disable the peripheral */ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \ - (hcryp->Init.Algorithm == CRYP_AES_CCM)) + (hcryp->Init.Algorithm == CRYP_AES_CCM)) { - /* Save Suspension registers */ - CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); - /* Save Key */ - CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); - /* Save IV */ - CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); + /* Save Suspension registers */ + CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); + /* Save Key */ + CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); + /* Save IV */ + CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); } /* Disable AES */ __HAL_CRYP_DISABLE(hcryp); @@ -974,7 +982,8 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) hcryp->CrypOutCount_saved = hcryp->CrypOutCount; hcryp->Phase_saved = hcryp->Phase; hcryp->State_saved = hcryp->State; - hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size); + hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \ + (hcryp->Size / 4U) : hcryp->Size); hcryp->SizesSum_saved = hcryp->SizesSum; hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation; hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount; @@ -1032,7 +1041,7 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) hcryp->AutoKeyDerivation = hcryp->AutoKeyDerivation_saved; if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ - (hcryp->Init.Algorithm == CRYP_AES_CTR)) + (hcryp->Init.Algorithm == CRYP_AES_CTR)) { hcryp->Init.pInitVect = hcryp->IV_saved; } @@ -1065,14 +1074,16 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) hcryp->ResumingFlag = 1U; if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) { - if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \ + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) { return HAL_ERROR; } } else { - if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \ + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) { return HAL_ERROR; } @@ -1200,7 +1211,8 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { uint32_t algo; HAL_StatusTypeDef status; @@ -1300,7 +1312,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t algo; @@ -1420,26 +1433,26 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) - if (hcryp->ResumingFlag == 1U) - { - hcryp->ResumingFlag = 0U; - if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) - { - hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; - hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; - } - else - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } - } - else + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) + { + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + } + else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } hcryp->pCrypInBuffPtr = Input; hcryp->pCrypOutBuffPtr = Output; @@ -1530,26 +1543,26 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) - if (hcryp->ResumingFlag == 1U) - { - hcryp->ResumingFlag = 0U; - if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) - { - hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; - hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; - } - else - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } - } - else + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) + { + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + } + else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } hcryp->pCrypInBuffPtr = Input; hcryp->pCrypOutBuffPtr = Output; @@ -1703,7 +1716,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu hcryp->Phase = CRYP_PHASE_PROCESS; /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), \ + (uint32_t)(hcryp->pCrypOutBuffPtr)); status = HAL_OK; break; @@ -1856,49 +1870,51 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { + uint32_t itsource = hcryp->Instance->CR; + uint32_t itflag = hcryp->Instance->SR; /* Check if error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET) + if ((itsource & CRYP_IT_ERRIE) != RESET) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET) + if ((itflag & CRYP_IT_WRERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET) + if ((itflag & CRYP_IT_RDERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; } } - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) - { - if(__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + if ((itflag & CRYP_IT_CCF) != RESET) { - /* Clear computation complete flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) + if ((itsource & CRYP_IT_CCFIE) != RESET) { + /* Clear computation complete flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* if header phase */ - if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + + /* if header phase */ + if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } } - else /* if payload phase */ + else /* AES Algorithm ECB,CBC or CTR*/ { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + CRYP_AES_IT(hcryp); } } - else /* AES Algorithm ECB,CBC or CTR*/ - { - CRYP_AES_IT(hcryp); - } } } -} /** * @brief Return the CRYP error code. @@ -2106,15 +2122,17 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); } else { @@ -2134,7 +2152,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure * @param Timeout Specify Timeout value * @retval HAL status -*/ + */ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint16_t incount; /* Temporary CrypInCount Value */ @@ -2307,8 +2325,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2352,15 +2369,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); } else { @@ -2436,8 +2455,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2504,8 +2522,9 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) uint32_t headersize_in_bytes; uint32_t tmp; static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); @@ -2587,7 +2606,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) This case can only occur for GCM and CCM with a payload length not a multiple of 16 bytes */ if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \ - (((hcryp->Size) % 16U) != 0U))) + (((hcryp->Size) % 16U) != 0U))) { /* Call input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -2677,12 +2696,13 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /*Read the output block from the output FIFO */ for (count = 0U; count < 4U; count++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[count] = hcryp->Instance->DOUTR; } count = 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U)) + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; hcryp->CrypOutCount++; @@ -2690,7 +2710,8 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) } } - if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) + if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) + && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) { /* Disable CRYP (not allowed in GCM)*/ __HAL_CRYP_DISABLE(hcryp); @@ -2887,13 +2908,14 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer*/ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUTR; } - i= 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -2916,19 +2938,20 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) if (hcryp->State == HAL_CRYP_STATE_BUSY) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer*/ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUTR; } - i= 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; i++; } - if (hcryp->CrypOutCount == (hcryp->Size / 4U)) + if (hcryp->CrypOutCount == (hcryp->Size / 4U)) { /* Disable Computation Complete flag and errors interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); @@ -2964,13 +2987,13 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } else @@ -2986,7 +3009,7 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if (hcryp->CrypInCount == (hcryp->Size / 4U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3242,7 +3265,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUTR; } for (index = 0U; index < lastwordsize; index++) @@ -3272,8 +3296,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t headersize_in_bytes; uint32_t tmp; static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) @@ -3358,8 +3383,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3408,7 +3432,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3499,10 +3523,10 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++ ; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -3526,10 +3550,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) header has already been processed; only process here message payload */ { - - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); @@ -3555,7 +3575,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3566,6 +3586,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); } else /* Size < 16Bytes : first block is the last block*/ { @@ -3614,6 +3637,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); } } @@ -3696,8 +3722,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3842,7 +3867,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -3910,10 +3935,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t for (loopcounter = 0U; loopcounter < 4U; loopcounter++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[loopcounter] = hcryp->Instance->DOUTR; } - for (loopcounter = 0U; loopcounterpCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; hcryp->CrypOutCount++; @@ -3942,8 +3968,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t headersize_in_bytes; uint32_t tmp; static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -4016,8 +4043,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4070,16 +4096,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) } else if (hcryp->Size >= 16U) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -4164,12 +4190,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; loopcounter++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } - } /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) /*Call registered Input complete callback*/ @@ -4183,14 +4209,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) { /* Write the first input header block in the Input FIFO, the following header data will be fed after interrupt occurrence */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/ } /* end of if (dokeyivconfig == 1U) */ else /* Key and IV have already been configured, @@ -4211,16 +4237,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) } else if (hcryp->Size >= 16U) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -4358,8 +4384,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4405,13 +4430,14 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /***************************** Payload phase *******************************/ - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer*/ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUTR; } - i= 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -4419,15 +4445,15 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) } incount = hcryp->CrypInCount; outcount = hcryp->CrypOutCount; - if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) + if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) { - /* When in CCM with Key and IV configuration skipped, don't disable interruptions */ - if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U))) - { + /* When in CCM with Key and IV configuration skipped, don't disable interruptions */ + if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U))) + { /* Disable computation complete flag and errors interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - } + } /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -4459,40 +4485,40 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) - { - /* Call input transfer complete callback */ + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } } - } else /* Last block of payload < 128bit*/ { /* Compute the number of padding bytes in last block of payload */ @@ -4528,13 +4554,13 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } - /* Call input transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4579,9 +4605,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr npblb = 16U - (uint32_t)hcryp->Size; /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/ - reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE); - if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\ - (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT))) + reg = hcryp->Instance->CR & (AES_CR_CHMOD | AES_CR_MODE); + if ((reg == (CRYP_AES_GCM_GMAC | CRYP_OPERATINGMODE_ENCRYPT)) || \ + (reg == (CRYP_AES_CCM | CRYP_OPERATINGMODE_DECRYPT))) { /* Specify the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); @@ -4636,8 +4662,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4645,7 +4670,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUTR; } for (index = 0U; index < lastwordsize; index++) @@ -4660,13 +4686,13 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr /* Process unlocked */ __HAL_UNLOCK(hcryp); - /* Call Output transfer complete callback */ + /* Call Output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } @@ -4686,8 +4712,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t size_in_bytes; uint32_t tmp; static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4789,17 +4816,17 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - /* Enter last bytes, padded with zeros */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; - hcryp->Instance->DINR = tmp; - loopcounter++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) @@ -4846,8 +4873,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry uint32_t headersize_in_bytes; uint32_t tmp; static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4874,7 +4902,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry if (headersize_in_bytes >= 16U) { /* Initiate header DMA transfer */ - if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK) + if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), + (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK) { return HAL_ERROR; } @@ -4967,8 +4996,9 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t headersize_in_bytes; uint32_t tmp; static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { @@ -5019,7 +5049,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call the input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -5089,28 +5119,28 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - } + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } } else /* Write last header block (4 words), padded with zeros if needed */ { @@ -5140,10 +5170,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -5207,15 +5237,14 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout hcryp->State = HAL_CRYP_STATE_READY; #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); #else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5231,17 +5260,17 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout * as soon as the suspended processing has to be resumed. * @retval None */ -static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output) +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR3; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR2; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR1; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR0; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR3; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR2; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR1; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR0; } /** @@ -5254,17 +5283,17 @@ static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output) * @note AES must be disabled when reconfiguring the IV values. * @retval None */ -static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input) +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input) { uint32_t ivaddr = (uint32_t)Input; - hcryp->Instance->IVR3 = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->IVR2 = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->IVR1 = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->IVR0 = *(uint32_t*)(ivaddr); + hcryp->Instance->IVR3 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR2 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR1 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR0 = *(uint32_t *)(ivaddr); } /** @@ -5277,52 +5306,52 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input) * as soon as the suspended processing has to be resumed. * @retval None */ -static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output) +static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; __IO uint32_t count = 0U; /* In case of GCM payload phase encryption, check that suspension can be carried out */ - if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U)) + if (READ_BIT(hcryp->Instance->CR, + (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | AES_CR_GCMPH_1 | 0x0U)) { - /* Wait for BUSY flag to be cleared */ - count = 0xFFF; - do + /* Wait for BUSY flag to be cleared */ + count = 0xFFF; + do + { + count-- ; + if (count == 0U) { - count-- ; - if(count == 0U) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - HAL_CRYP_ErrorCallback(hcryp); - return; - } + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + HAL_CRYP_ErrorCallback(hcryp); + return; } - while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)); + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)); } - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP7R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP6R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP5R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP4R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP3R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP2R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP1R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP0R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP7R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP6R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP5R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP4R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP3R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP2R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP1R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP0R; } /** @@ -5335,25 +5364,25 @@ static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Outp * @note AES must be disabled when reconfiguring the suspend registers. * @retval None */ -static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input) +static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input) { uint32_t ivaddr = (uint32_t)Input; - hcryp->Instance->SUSP7R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP6R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP5R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP4R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP3R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP2R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP1R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP0R = *(uint32_t*)(ivaddr); + hcryp->Instance->SUSP7R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP6R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP5R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP4R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP3R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP2R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP1R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP0R = *(uint32_t *)(ivaddr); } /** @@ -5366,37 +5395,37 @@ static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Inp * as soon as the suspended processing has to be resumed. * @retval None */ -static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize) +static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize) { uint32_t keyaddr = (uint32_t)Output; switch (KeySize) { case CRYP_KEYSIZE_256B: - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U); + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U); break; case CRYP_KEYSIZE_128B: - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); break; default: break; @@ -5414,29 +5443,29 @@ static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, * @note AES must be disabled when reconfiguring the Key registers. * @retval None */ -static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize) +static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize) { uint32_t keyaddr = (uint32_t)Input; if (KeySize == CRYP_KEYSIZE_256B) { - hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr); - keyaddr+=4U; + hcryp->Instance->KEYR7 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR6 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR5 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR4 = *(uint32_t *)(keyaddr); + keyaddr += 4U; } - hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr); + hcryp->Instance->KEYR3 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR2 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR1 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR0 = *(uint32_t *)(keyaddr); } /** @@ -5464,7 +5493,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) /* Case of header phase resumption =================================================*/ if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) { - /* Set the phase */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; /* Select header phase */ @@ -5473,24 +5502,24 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; } else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ { /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++) + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5513,18 +5542,18 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U) + if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) @@ -5539,32 +5568,32 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) else /* Last block of payload < 128bit*/ { /* Compute the number of padding bytes in last block of payload */ - npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size); + npblb = (((hcryp->Size / 16U) + 1U) * 16U) - (hcryp->Size); cr_temp = hcryp->Instance->CR; - if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || - (((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + if ((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + (((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) { /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U); + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb) << 20U); } /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) ==0U) + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5588,5 +5617,5 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) */ /** - * @} - */ + * @} + */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c index 136cd6cc85..f7c8fcf44d 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c @@ -71,8 +71,8 @@ */ /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions - * @brief Extended processing functions. - * + * @brief Extended processing functions. + * @verbatim ============================================================================== ##### Extended AES processing functions ##### @@ -161,7 +161,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -267,7 +267,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c index 6cd2a31739..7347d8531c 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c @@ -232,7 +232,7 @@ and a pointer to the user callback function. Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. @@ -247,9 +247,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + reset to the legacy weak (overridden) functions in the HAL_DAC_Init and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -264,7 +264,7 @@ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** DAC HAL driver macros list *** ============================================= @@ -343,7 +343,7 @@ */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -404,7 +404,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -507,6 +507,12 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -562,6 +568,12 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -592,11 +604,17 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; - uint32_t tmpreg = 0U; + uint32_t tmpreg; + + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -633,12 +651,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; - default: - break; } } @@ -667,17 +683,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Get DHR12L2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L2; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R2; break; - default: - break; } } - - /* Enable the DMA channel */ if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ @@ -726,6 +738,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -774,10 +792,13 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + uint32_t itsource = hdac->Instance->CR; + uint32_t itflag = hdac->Instance->SR; + + if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) { /* Check underrun flag of DAC channel 1 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -789,7 +810,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); /* Disable the selected DAC channel1 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -801,10 +822,10 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) } - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) + if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) { /* Check underrun flag of DAC channel 2 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -816,7 +837,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); /* Disable the selected DAC channel2 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -849,6 +870,12 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui { __IO uint32_t tmp = 0UL; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); @@ -966,10 +993,13 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) { uint32_t result; + /* Check the DAC peripheral handle */ + assert_param(hdac != NULL); + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -998,12 +1028,20 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpreg1; uint32_t tmpreg2; uint32_t tickstart; + /* Check the DAC peripheral handle and channel configuration struct */ + if ((hdac == NULL) || (sConfig == NULL)) + { + return HAL_ERROR; + } + /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); @@ -1042,16 +1080,19 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { - /* Update error code */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); - /* Change the DMA state */ - hdac->State = HAL_DAC_STATE_TIMEOUT; + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } - HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } @@ -1063,16 +1104,19 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { - /* Update error code */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); - /* Change the DMA state */ - hdac->State = HAL_DAC_STATE_TIMEOUT; + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } - HAL_Delay(1U); hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } @@ -1137,7 +1181,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf __HAL_UNLOCK(hdac); /* Return function status */ - return HAL_OK; + return status; } /** @@ -1166,7 +1210,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * the configuration information for the specified DAC. * @retval HAL state */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac) { /* Return DAC handle state */ return hdac->State; @@ -1179,7 +1223,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) * the configuration information for the specified DAC. * @retval DAC Error Code */ -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac) { return hdac->ErrorCode; } @@ -1202,7 +1246,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief Register a User DAC Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback + * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -1226,6 +1272,12 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call { HAL_StatusTypeDef status = HAL_OK; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + if (pCallback == NULL) { /* Update the error code */ @@ -1233,9 +1285,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdac); - if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) @@ -1306,14 +1355,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } /** * @brief Unregister a User DAC Callback - * DAC Callback is redirected to the weak (surcharged) predefined callback + * DAC Callback is redirected to the weak (overridden) predefined callback + * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1334,8 +1383,11 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hdac); + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } if (hdac->State == HAL_DAC_STATE_READY) { @@ -1421,8 +1473,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ @@ -1508,8 +1558,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) #endif /* DAC1 */ #endif /* HAL_DAC_MODULE_ENABLED */ - /** * @} */ - diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c index 6d0c61a688..0d5c73179c 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c @@ -23,15 +23,6 @@ ##### How to use this driver ##### ============================================================================== [..] - - *** Dual mode IO operation *** - ============================== - [..] - (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : - Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in - Channel 1 and Channel 2. - *** Signal generation operation *** =================================== [..] @@ -67,6 +58,16 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/* Delay for DAC minimum trimming time. */ +/* Note: minimum time needed between two calibration steps */ +/* The delay below is specified under conditions: */ +/* - DAC channel output buffer enabled */ +/* Literal set to maximum value (refer to device datasheet, */ +/* electrical characteristics, parameter "tTRIM"). */ +/* Unit: us */ +#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -106,6 +107,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) { uint32_t tmp_swtrig = 0UL; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Process locked */ __HAL_LOCK(hdac); @@ -147,6 +154,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); @@ -186,6 +199,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -236,6 +255,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 */ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -281,6 +306,12 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Align uint32_t data; uint32_t tmp; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); @@ -388,9 +419,9 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo { HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t tmp; uint32_t trimmingvalue; uint32_t delta; + __IO uint32_t wait_loop_index; /* store/restore channel configuration structure purpose */ uint32_t oldmodeconfiguration; @@ -400,7 +431,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Check the DAC handle allocation */ /* Check if DAC running */ - if (hdac == NULL) + if ((hdac == NULL) || (sConfig == NULL)) { status = HAL_ERROR; } @@ -422,20 +453,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set mode in MCR for calibration */ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); - /* Set DAC Channel1 DHR register to the middle value */ - tmp = (uint32_t)hdac->Instance; - - if (Channel == DAC_CHANNEL_1) - { - tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); - } - else - { - tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R); - } - - *(__IO uint32_t *) tmp = 0x0800UL; - /* Enable the selected DAC channel calibration */ /* i.e. set DAC_CR_CENx bit */ SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); @@ -449,9 +466,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); - /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ - /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1); + /* Wait minimum time needed between two calibration steps (OTRIM) */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ + /* 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) { @@ -471,9 +494,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); - /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ - /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1U); + /* Wait minimum time needed between two calibration steps (OTRIM) */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ + /* 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { @@ -521,8 +550,8 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue)); - /* Check the DAC handle allocation */ - if (hdac == NULL) + /* Check the DAC handle and channel configuration struct allocation */ + if ((hdac == NULL) || (sConfig == NULL)) { status = HAL_ERROR; } @@ -554,7 +583,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * @retval Trimming value : range: 0->31 * */ -uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameter */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -588,7 +617,7 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac) { uint32_t tmp = 0UL; @@ -689,4 +718,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) /** * @} */ - diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c index b13cef3dfc..35bba78b6d 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c @@ -64,7 +64,7 @@ (++) Provide exiting handle as parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). (++) Provide exiting handle as parameter. (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). @@ -75,7 +75,7 @@ (#) Get interrupt pending bit using HAL_EXTI_GetPending(). - (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @@ -343,7 +343,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = EXTI->EXTICR[linepos >> 2u]; - pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + pExtiConfig->GPIOSel = (regval >> (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & EXTI_EXTICR1_EXTI0; } } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_fdcan.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_fdcan.c index 29c0341ef6..08c445d76b 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_fdcan.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_fdcan.c @@ -96,7 +96,7 @@ *** Callback registration *** ============================================= - The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 + The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() to register an interrupt callback. @@ -114,7 +114,7 @@ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated - register callbacks : respectively HAL_FDCAN_RegisterTxEventFifoCallback(), + register callbacks: respectively HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback() and HAL_FDCAN_RegisterErrorStatusCallback(). @@ -134,7 +134,7 @@ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated - unregister callbacks : respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(), + unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback() and HAL_FDCAN_UnRegisterErrorStatusCallback(). @@ -249,9 +249,15 @@ static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, */ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FDCAN_Private_Functions_Prototypes + * @{ + */ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, - uint32_t BufferIndex); +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions @@ -327,22 +333,17 @@ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) hfdcan->Lock = HAL_UNLOCKED; /* Reset callbacks to legacy functions */ - hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ - hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ - hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ - hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ - hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak - TxBufferCompleteCallback */ - hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak - TxBufferAbortCallback */ - hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak - HighPriorityMessageCallback */ - hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak - TimestampWraparoundCallback */ - hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak - TimeoutOccurredCallback */ - hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */ - hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */ + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */ + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */ + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */ + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */ + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */ + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */ + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */ + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* TimeoutOccurredCallback */ + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* ErrorCallback */ + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* ErrorStatusCallback */ if (hfdcan->MspInitCallback == NULL) { @@ -582,7 +583,7 @@ __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_MspInit could be implemented in the user file */ } @@ -597,7 +598,7 @@ __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_MspDeInit could be implemented in the user file */ } @@ -1292,7 +1293,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h * contains the filter configuration information * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig) +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig) { uint32_t FilterElementW1; uint32_t FilterElementW2; @@ -1417,7 +1418,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @param Mask Extended ID Mask. - This parameter must be a number between 0 and 0x1FFFFFFF + * This parameter must be a number between 0 and 0x1FFFFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask) @@ -1607,7 +1608,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan) * the configuration information for the specified FDCAN. * @retval Timestamp counter value */ -uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan) { return (uint16_t)(hfdcan->Instance->TSCV); } @@ -1730,7 +1731,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) * the configuration information for the specified FDCAN. * @retval Timeout counter value */ -uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan) { return (uint16_t)(hfdcan->Instance->TOCV); } @@ -2103,8 +2104,8 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) * @param pTxData pointer to a buffer containing the payload of the Tx frame. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, - uint8_t *pTxData) +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData) { uint32_t PutIndex; @@ -2171,7 +2172,7 @@ HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDC * - Any value of @arg FDCAN_Tx_location if Tx request has been submitted. * - 0 if no Tx FIFO/Queue request have been submitted. */ -uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan) { /* Return Last Tx FIFO/Queue Request Buffer */ return hfdcan->LatestTxFifoQRequest; @@ -2223,7 +2224,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R uint32_t *RxAddress; uint8_t *pData; uint32_t ByteCounter; - uint32_t GetIndex; + uint32_t GetIndex = 0; HAL_FDCAN_StateTypeDef state = hfdcan->State; /* Check function parameters */ @@ -2243,8 +2244,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Check that the Rx FIFO 0 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 0 element index */ + GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + /* Calculate Rx FIFO 0 element address */ - GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE)); } } @@ -2260,8 +2273,19 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Check that the Rx FIFO 1 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 1 element index */ + GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); /* Calculate Rx FIFO 1 element address */ - GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE)); } } @@ -2292,7 +2316,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS); /* Retrieve DataLength */ - pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC); + pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); /* Retrieve BitRateSwitch */ pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS); @@ -2311,7 +2335,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R /* Retrieve Rx payload */ pData = (uint8_t *)RxAddress; - for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++) + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++) { pRxData[ByteCounter] = pData[ByteCounter]; } @@ -2393,7 +2417,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS); /* Retrieve DataLength */ - pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC); + pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); /* Retrieve BitRateSwitch */ pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS); @@ -2429,7 +2453,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus) { HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos); @@ -2448,7 +2472,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hf * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus) +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus) { uint32_t StatusReg; @@ -2479,7 +2504,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters) +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters) { uint32_t CountersReg; @@ -2503,10 +2529,10 @@ HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ * @param TxBufferIndex Tx buffer index. * This parameter can be any combination of @arg FDCAN_Tx_location. * @retval Status - * - 0 : No pending transmission request on TxBufferIndex list + * - 0 : No pending transmission request on TxBufferIndex list. * - 1 : Pending transmission request on TxBufferIndex. */ -uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) { /* Check function parameters */ assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex)); @@ -2529,7 +2555,7 @@ uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_ * @arg FDCAN_RX_FIFO1: Rx FIFO 1 * @retval Rx FIFO fill level. */ -uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) { uint32_t FillLevel; @@ -2556,7 +2582,7 @@ uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi * the configuration information for the specified FDCAN. * @retval Tx FIFO free level. */ -uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan) { uint32_t FreeLevel; @@ -2574,7 +2600,7 @@ uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan) * - 0 : Normal FDCAN operation. * - 1 : Restricted Operation Mode active. */ -uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan) { uint32_t OperationMode; @@ -3145,7 +3171,7 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) * @brief Tx Event callback. * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. - * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled. + * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts. * @retval None */ @@ -3155,7 +3181,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t UNUSED(hfdcan); UNUSED(TxEventFifoITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file */ } @@ -3164,7 +3190,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t * @brief Rx FIFO 0 callback. * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. - * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled. + * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts. * @retval None */ @@ -3174,7 +3200,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi UNUSED(hfdcan); UNUSED(RxFifo0ITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxFifo0Callback could be implemented in the user file */ } @@ -3183,7 +3209,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi * @brief Rx FIFO 1 callback. * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. - * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled. + * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts. * @retval None */ @@ -3193,7 +3219,7 @@ __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi UNUSED(hfdcan); UNUSED(RxFifo1ITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxFifo1Callback could be implemented in the user file */ } @@ -3209,7 +3235,7 @@ __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file */ } @@ -3228,7 +3254,7 @@ __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint UNUSED(hfdcan); UNUSED(BufferIndexes); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file */ } @@ -3247,7 +3273,7 @@ __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_ UNUSED(hfdcan); UNUSED(BufferIndexes); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file */ } @@ -3263,7 +3289,7 @@ __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file */ } @@ -3279,7 +3305,7 @@ __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file */ } @@ -3295,7 +3321,7 @@ __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file */ } @@ -3311,7 +3337,7 @@ __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorCallback could be implemented in the user file */ } @@ -3330,7 +3356,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t UNUSED(hfdcan); UNUSED(ErrorStatusITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file */ } @@ -3360,7 +3386,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t * the configuration information for the specified FDCAN. * @retval HAL state */ -HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan) +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan) { /* Return FDCAN state */ return hfdcan->State; @@ -3372,7 +3398,7 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan) * the configuration information for the specified FDCAN. * @retval FDCAN Error Code */ -uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan) { /* Return FDCAN error code */ return hfdcan->ErrorCode; @@ -3448,8 +3474,8 @@ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) * @param BufferIndex index of the buffer to be configured. * @retval none */ -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, - uint32_t BufferIndex) +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex) { uint32_t TxElementW1; uint32_t TxElementW2; @@ -3477,7 +3503,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy pTxHeader->TxEventFifoControl | pTxHeader->FDFormat | pTxHeader->BitRateSwitch | - pTxHeader->DataLength); + (pTxHeader->DataLength << 16U)); /* Calculate Tx element address */ TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE)); @@ -3489,7 +3515,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy TxAddress++; /* Write Tx payload to the message RAM */ - for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U) + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U) { *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) | ((uint32_t)pTxData[ByteCounter + 2U] << 16U) | diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c index 281ffe78c2..0cb7b6326e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c @@ -458,6 +458,9 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) { HAL_StatusTypeDef status = HAL_ERROR; + /* Wait for last operation to be completed */ + (void)FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); @@ -502,6 +505,9 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { HAL_StatusTypeDef status = HAL_ERROR; + /* Wait for last operation to be completed */ + (void)FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); @@ -590,12 +596,12 @@ uint32_t HAL_FLASH_GetError(void) HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { uint32_t error; + uint32_t tickstart = HAL_GetTick(); + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - uint32_t timeout = HAL_GetTick() + Timeout; - /* Wait if any operation is ongoing */ #if defined(FLASH_DBANK_SUPPORT) error = (FLASH_SR_BSY1 | FLASH_SR_BSY2); #else @@ -604,9 +610,12 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) while ((FLASH->SR & error) != 0x00U) { - if (HAL_GetTick() >= timeout) + if(Timeout != HAL_MAX_DELAY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) >= Timeout) + { + return HAL_TIMEOUT; + } } } @@ -624,13 +633,14 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) } /* Wait for control register to be written */ - timeout = HAL_GetTick() + Timeout; - while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U) { - if (HAL_GetTick() >= timeout) + if(Timeout != HAL_MAX_DELAY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) >= Timeout) + { + return HAL_TIMEOUT; + } } } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c index b590066f65..b31c687f0d 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c @@ -606,6 +606,9 @@ void FLASH_PageErase(uint32_t Banks, uint32_t Page) { tmp &= ~FLASH_CR_BKER; } +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Banks); #endif /* FLASH_DBANK_SUPPORT */ /* Set page number, Page Erase bit & Start bit */ @@ -630,7 +633,6 @@ void FLASH_FlushCaches(void) } } - /** * @brief Configure the write protection of the desired pages. * @note When WRP is active in a zone, it cannot be erased or programmed. diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_hcd.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_hcd.c index 90ed5c72c1..97f288aedb 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_hcd.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_hcd.c @@ -77,8 +77,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); static void HAL_HCD_ClearPhyChannel(HCD_HandleTypeDef *hhcd); -static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef *hhcd, uint8_t phy_chnum, uint8_t dir); -static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef const *hhcd, uint8_t phy_chnum, uint8_t dir); +static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef const *hhcd, uint8_t ch_num); static uint8_t HAL_HCD_Get_FreePhyChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t ep_type); #if (USE_USB_DOUBLE_BUFFER == 1U) @@ -170,7 +170,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) (void)USB_HostInit(hhcd->Instance, hhcd->Init); /* Deactivate the power down */ - hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; + hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; hhcd->State = HAL_HCD_STATE_READY; @@ -714,8 +714,8 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n } hhcd->hc[ch_num & 0xFU].xfer_buff = pbuff; - hhcd->hc[ch_num & 0xFU].xfer_len = length; - hhcd->hc[ch_num & 0xFU].xfer_len_db = length; + hhcd->hc[ch_num & 0xFU].xfer_len = length; + hhcd->hc[ch_num & 0xFU].xfer_len_db = length; hhcd->hc[ch_num & 0xFU].urb_state = URB_IDLE; hhcd->hc[ch_num & 0xFU].xfer_count = 0U; hhcd->hc[ch_num & 0xFU].state = HC_IDLE; @@ -1353,7 +1353,7 @@ HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd) /* wait for Suspend Ready */ while ((hhcd->Instance->CNTR & USB_CNTR_SUSPRDY) == 0U) { - if (++count > 0xFFFFFFU) + if (++count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1438,7 +1438,7 @@ and the data flow. * @param hhcd HCD handle * @retval HAL state */ -HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd) { return hhcd->State; } @@ -1457,7 +1457,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) * URB_ERROR/ * URB_STALL */ -HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) { return hhcd->hc[chnum].urb_state; } @@ -1470,7 +1470,7 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu * This parameter can be a value from 1 to 15 * @retval last transfer size in byte */ -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum) { return hhcd->hc[chnum].xfer_count; } @@ -1492,7 +1492,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) * HC_BBLERR/ * HC_DATATGLERR */ -HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) { return hhcd->hc[chnum].state; } @@ -1520,6 +1520,40 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) return (USB_GetHostSpeed(hhcd->Instance)); } +/** + * @brief Set host channel Hub Information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 8 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr) +{ + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + + return HAL_OK; +} + + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + + return HAL_OK; +} + #if (USE_USB_DOUBLE_BUFFER == 1U) /** * @brief Handle Host Channel OUT Double Buffer Bulk requests. @@ -1553,7 +1587,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { /* manage multiple Xfer */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; /* check if we need to free user buffer */ if ((regvalue & USB_CH_DTOG_RX) != 0U) @@ -1592,7 +1626,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, else { /* Transfer complete state */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; @@ -1614,7 +1648,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { /* manage multiple Xfer */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; /* check if we need to free user buffer */ if ((regvalue & USB_CH_DTOG_RX) == 0U) @@ -1655,7 +1689,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, else { /* Transfer complete state */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; @@ -1904,11 +1938,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; hhcd->hc[ch_num & 0xFU].state = HC_NAK; + + if (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR) + { + /* Close the channel */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + } } /* manage STALL Response */ else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) { - (void)HAL_HCD_HC_Halt(hhcd, (uint8_t)ch_num); + (void)HAL_HCD_HC_Halt(hhcd, ch_num); hhcd->hc[ch_num & 0xFU].state = HC_STALL; hhcd->hc[ch_num & 0xFU].urb_state = URB_STALL; @@ -1931,9 +1971,9 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ /*Clear VTRX */ @@ -1961,9 +2001,9 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } @@ -2056,7 +2096,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { /* manage multiple Xfer */ hhcd->hc[chnum & 0xFU].xfer_buff += data_xfr; - hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; + hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; /* start a new transfer */ (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[chnum & 0xFU]); @@ -2246,7 +2286,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 1 to 15 * @retval HAL status */ -static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef const *hhcd, uint8_t ch_num) { uint8_t idx; @@ -2280,7 +2320,7 @@ static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num * -1 IN_Channel * @retval HAL status */ -static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef *hhcd, +static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef const *hhcd, uint8_t phy_chnum, uint8_t dir) { /* Out Channel Direction */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c index 1f6ef3a30b..7107a410c7 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c @@ -400,9 +400,15 @@ * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ /* Macro to get remaining data to transfer on DMA side */ #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -418,6 +424,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAError(DMA_HandleTypeDef *hdma); static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + /* Private functions to handle IT transfer */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); @@ -601,7 +608,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); @@ -1108,6 +1120,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1131,18 +1144,39 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferCount = Size; hi2c->XferISR = NULL; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_GENERATE_START_WRITE); + xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); } @@ -1345,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1379,6 +1415,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData return HAL_ERROR; } + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1425,31 +1474,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -1652,7 +1718,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_START_WRITE); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1775,6 +1860,20 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1861,6 +1960,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1893,6 +1993,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t xfermode = I2C_AUTOEND_MODE; } + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + if (hi2c->XferSize > 0U) { if (hi2c->hdmatx != NULL) @@ -1908,8 +2022,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { @@ -1930,7 +2044,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), + xfermode, I2C_GENERATE_START_WRITE); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -1969,7 +2084,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ @@ -2125,11 +2240,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -2173,67 +2288,99 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - if (hi2c->hdmatx != NULL) + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; - /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + hi2c->XferCount--; + hi2c->XferSize--; } - else + + if (hi2c->XferCount != 0U) { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - return HAL_ERROR; - } + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); } return HAL_OK; @@ -2347,6 +2494,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD return HAL_BUSY; } } + /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2661,6 +2809,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ + hi2c->XferSize = 0U; hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -2782,11 +2931,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } @@ -2795,6 +2944,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre return HAL_BUSY; } } + /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -3191,22 +3341,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - /* Increment Trials */ I2C_Trials++; } while (I2C_Trials < Trials); @@ -3245,6 +3379,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3276,6 +3411,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3297,7 +3447,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 } /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3337,6 +3494,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3368,6 +3526,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 xfermode = hi2c->XferOptions; } + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3403,8 +3576,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { @@ -3424,7 +3597,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 if (dmaxferstatus == HAL_OK) { /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -3463,8 +3643,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_WRITE); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3727,11 +3913,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -3891,7 +4077,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA RX */ @@ -3913,7 +4099,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ if (hi2c->hdmatx != NULL) { /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA TX */ @@ -4435,7 +4621,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA * the configuration information for the specified I2C. * @retval None */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ { /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); @@ -4688,7 +4874,7 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval HAL state */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) { /* Return I2C handle state */ return hi2c->State; @@ -4700,7 +4886,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) * the configuration information for I2C module * @retval HAL mode */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) { return hi2c->Mode; } @@ -4711,7 +4897,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval I2C Error Code */ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; } @@ -4774,17 +4960,22 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ + ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) { /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; + if (hi2c->XferCount != 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; - hi2c->XferSize--; - hi2c->XferCount--; + hi2c->XferSize--; + hi2c->XferCount--; + } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) @@ -4883,7 +5074,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @retval HAL status */ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint32_t direction = I2C_GENERATE_START_WRITE; uint32_t tmpITFlags = ITFlags; @@ -4971,6 +5162,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -5035,9 +5232,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5301,7 +5497,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @retval HAL status */ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint32_t direction = I2C_GENERATE_START_WRITE; @@ -5337,6 +5533,9 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Enable only Error interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); @@ -5379,6 +5578,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -5456,9 +5661,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -6057,6 +6261,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ @@ -6073,6 +6278,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } else { /* Do nothing */ @@ -6139,6 +6349,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -6266,6 +6527,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ @@ -6293,18 +6555,36 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { @@ -6479,6 +6759,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C slave transmit process complete callback. * @param hdma DMA handle @@ -6507,6 +6788,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C master receive process complete callback. * @param hdma DMA handle @@ -6557,6 +6839,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C slave receive process complete callback. * @param hdma DMA handle @@ -6585,6 +6868,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C communication error callback. * @param hdma DMA handle @@ -6602,6 +6886,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); } + /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). @@ -6626,6 +6911,7 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_TreatErrorCallback(hi2c); } + /** * @brief This function handles I2C Communication Timeout. It waits * until a flag is no longer in the specified status. @@ -6642,18 +6928,27 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } } } } @@ -6684,14 +6979,17 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -6720,14 +7018,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6744,16 +7045,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -6761,19 +7064,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -6787,23 +7085,30 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } } } - return HAL_OK; + return status; } /** @@ -6857,7 +7162,7 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) { - error_code |=HAL_I2C_ERROR_TIMEOUT; + error_code |= HAL_I2C_ERROR_TIMEOUT; status = HAL_ERROR; @@ -6986,8 +7291,9 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { @@ -6995,6 +7301,18 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ @@ -7004,32 +7322,27 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); - } - - if (InterruptRequest == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; + tmpisr |= I2C_IT_STOPI; } } + else { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ + /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } @@ -7042,7 +7355,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; } } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_irda.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_irda.c index ff6a4148bd..bba137e701 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_irda.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_irda.c @@ -142,7 +142,7 @@ [..] Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -159,10 +159,10 @@ [..] By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + reset to the legacy weak functions in the HAL_IRDA_Init() and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -179,7 +179,7 @@ [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim ****************************************************************************** @@ -462,7 +462,9 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /** * @brief Register a User IRDA Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback + * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -491,8 +493,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hirda); if (hirda->gState == HAL_IRDA_STATE_READY) { @@ -577,15 +577,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } /** * @brief Unregister an IRDA callback * IRDA callback is redirected to the weak predefined callback + * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -605,9 +604,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hirda); - if (HAL_IRDA_STATE_READY == hirda->gState) { switch (CallbackID) @@ -693,9 +689,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ @@ -805,7 +798,8 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -909,9 +903,10 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pD */ /** * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using u16 pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -1018,7 +1013,8 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { @@ -1078,9 +1074,10 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t */ /** * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using u16 pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { @@ -1157,7 +1154,8 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { @@ -1252,9 +1250,10 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t */ /** * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { @@ -2531,7 +2530,6 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) hirda->gState = HAL_IRDA_STATE_READY; } - /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_lptim.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_lptim.c index 8386ef2994..9f2685eaff 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_lptim.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_lptim.c @@ -206,7 +206,7 @@ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag); /* Exported functions --------------------------------------------------------*/ @@ -359,10 +359,10 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) } else { - /* Check LPTIM2 Input1 source */ + /* Check LPTIM Input1 source */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); - /* Configure LPTIM2 Input1 source */ + /* Configure LPTIM Input1 source */ hlptim->Instance->CFGR2 = hlptim->Init.Input1Source; } @@ -2098,9 +2098,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2171,9 +2168,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } @@ -2199,9 +2193,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2283,9 +2274,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -2313,7 +2301,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti * @param hlptim LPTIM handle * @retval HAL state */ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim) { /* Return LPTIM handle state */ return hlptim->State; @@ -2360,7 +2348,7 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) * @param flag The lptim flag * @retval HAL status */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag) { HAL_StatusTypeDef result = HAL_OK; uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd.c index 94a4cefe4a..420e0894e0 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd.c @@ -37,7 +37,7 @@ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral + (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -169,9 +169,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; - /* DMA Not supported for FS instance, Force to Zero */ - hpcd->Init.dma_enable = 0U; - /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); @@ -181,7 +178,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; hpcd->IN_ep[i].num = i; - hpcd->IN_ep[i].tx_fifo_num = i; /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; hpcd->IN_ep[i].maxpacket = 0U; @@ -297,7 +293,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function @@ -411,7 +407,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status @@ -1417,11 +1413,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->maxpacket = ep_mps; ep->type = ep_type; - if (ep->is_in != 0U) - { - /* Assign a Tx FIFO */ - ep->tx_fifo_num = ep->num; - } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) { @@ -1455,7 +1446,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; ep->is_in = 0U; } - ep->num = ep_addr & EP_ADDR_MSK; + ep->num = ep_addr & EP_ADDR_MSK; __HAL_LOCK(hpcd); (void)USB_DeactivateEndpoint(hpcd->Instance, ep); @@ -1485,14 +1476,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0U; ep->num = ep_addr & EP_ADDR_MSK; - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep); - } + (void)USB_EPStartXfer(hpcd->Instance, ep); return HAL_OK; } @@ -1503,7 +1487,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u * @param ep_addr endpoint address * @retval Data Size */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) { return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; } @@ -1530,14 +1514,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->is_in = 1U; ep->num = ep_addr & EP_ADDR_MSK; - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep); - } + (void)USB_EPStartXfer(hpcd->Instance, ep); return HAL_OK; } @@ -1650,9 +1627,18 @@ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(ep_addr); + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -1701,7 +1687,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval HAL state */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) { return hpcd->State; } @@ -1909,7 +1895,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - (void) USB_EPStartXfer(hpcd->Instance, ep); + (void)USB_EPStartXfer(hpcd->Instance, ep); } } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c index 4d9c89b33c..96ac916ee4 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c @@ -246,7 +246,7 @@ void HAL_PWREx_DisablePVD(void) } #endif /* PWR_PVD_SUPPORT */ -#if defined(PWR_PVM_SUPPORT) +#if defined(PWR_CR2_USV) /** * @brief Enable VDDUSB supply. * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. @@ -265,7 +265,7 @@ void HAL_PWREx_DisableVddUSB(void) { CLEAR_BIT(PWR->CR2, PWR_CR2_USV); } -#endif /* PWR_PVM_SUPPORT */ +#endif /* PWR_CR2_USV */ #if defined(PWR_CR2_IOSV) /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c index 656db75994..38a6175e52 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c @@ -85,15 +85,14 @@ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ -#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 -#if defined(RCC_MCO2_SUPPORT) -#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO2_GPIO_PORT GPIOA -#define MCO2_PIN GPIO_PIN_10 -#endif /* RCC_MCO2_SUPPORT */ +#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK) + +#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS) + +#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) + +#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (IOPORT_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__))) #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) @@ -979,15 +978,21 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @note PA8, PA10(*) should be configured in alternate function mode. * @param RCC_MCOx specifies the output direction for the clock source. * For STM32G0xx family this parameter can have only one value: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PA10)(*). + * @arg @ref RCC_MCO_PA8 Clock source to output on MCO1 pin(PA8). + * @arg @ref RCC_MCO_PA9 Clock source to output on MCO1 pin(PA9). + * @arg @ref RCC_MCO_PD10 Clock source to output on MCO1 pin(PD10)(*). + * @arg @ref RCC_MCO_PF2 Clock source to output on MCO1 pin(PF2)(*). + * @arg @ref RCC_MCO_PA10 Clock source to output on MCO2 pin(PA10)(*). + * @arg @ref RCC_MCO_PA15 Clock source to output on MCO2 pin(PA15)(*). + * @arg @ref RCC_MCO_PB2 Clock source to output on MCO2 pin(PB2)(*). + * @arg @ref RCC_MCO_PD7 Clock source to output on MCO2 pin(PD7)(*). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48(*) * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLLR clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source @@ -1034,44 +1039,54 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { - GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitTypeDef gpio_initstruct; + uint32_t mcoindex; + uint32_t mco_gpio_index; + GPIO_TypeDef * mco_gpio_port; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); /* Common GPIO init parameters */ - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; + gpio_initstruct.Mode = GPIO_MODE_AF_PP; + gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpio_initstruct.Pull = GPIO_NOPULL; + + /* Get MCOx selection */ + mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK; - if (RCC_MCOx == RCC_MCO1) + /* Get MCOx GPIO Port */ + mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx); + + /* MCOx Clock Enable */ + mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx); + SET_BIT(RCC->IOPENR, (1UL << mco_gpio_index )); + + /* Configure the MCOx pin in alternate function mode */ + gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx); + gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx); + HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct); + + if (mcoindex == RCC_MCO1_INDEX) { assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - /* MCO1 Clock Enable */ - MCO1_CLK_ENABLE(); - /* Configure the MCO1 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO1_PIN; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); } #if defined(RCC_MCO2_SUPPORT) - else if (RCC_MCOx == RCC_MCO2) + else if (mcoindex == RCC_MCO2_INDEX) { assert_param(IS_RCC_MCO2DIV(RCC_MCODiv)); assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); - /* MCO2 Clock Enable */ - MCO2_CLK_ENABLE(); - /* Configure the MCO2 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO2_PIN; - GPIO_InitStruct.Alternate = GPIO_AF3_MCO2; - HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), (RCC_MCOSource | RCC_MCODiv)); } #endif /* RCC_MCO2_SUPPORT */ + else + { + /* Nothing to do */ + } } /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rng.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rng.c index 77ca36224e..2f8e27cd44 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rng.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rng.c @@ -52,7 +52,7 @@ [..] Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -66,10 +66,10 @@ [..] By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak (overridden) functions: example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -86,7 +86,7 @@ [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -312,8 +312,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -367,8 +365,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -387,8 +383,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -442,8 +436,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -664,15 +656,16 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; /* RNG clock error interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } - else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; @@ -703,7 +696,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) } /* Check RNG data ready interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) { /* Generate random number once, so disable the IT */ __HAL_RNG_DISABLE_IT(hrng); @@ -735,7 +728,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval random value */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) { return (hrng->RandomNumber); } @@ -802,7 +795,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval HAL state */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) { return hrng->State; } @@ -812,7 +805,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code */ -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ return hrng->ErrorCode; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c index 8a96b96aa5..ee8559977b 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c @@ -1688,8 +1688,8 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) { uint32_t tickstart; - /* Clear RSF flag */ - hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK; + /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ + hrtc->Instance->ICSR = ((uint32_t)(RTC_RSF_MASK & RTC_ICSR_RESERVED_MASK)); tickstart = HAL_GetTick(); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c index acc7987734..5380da57b5 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c @@ -136,7 +136,7 @@ [..] Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -153,10 +153,10 @@ [..] By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + reset to the legacy weak functions in the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -173,7 +173,7 @@ [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -467,7 +467,10 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /** * @brief Register a User SMARTCARD Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback + * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -497,8 +500,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmartcard); if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { @@ -584,15 +585,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } /** * @brief Unregister an SMARTCARD callback * SMARTCARD callback is redirected to the weak predefined callback + * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -613,9 +614,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmartcard); - if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) { switch (CallbackID) @@ -701,9 +699,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c index 91ba763bb8..2bf6ff5ef5 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c @@ -926,6 +926,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; + uint32_t sizetoxfer; /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -958,11 +959,35 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint hsmbus->XferSize = Size; } + sizetoxfer = hsmbus->XferSize; + if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || + (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) + { + if (hsmbus->pBuffPtr != NULL) + { + /* Preload TX register */ + /* Write data to TXDR */ + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + hsmbus->XferCount--; + hsmbus->XferSize--; + } + else + { + return HAL_ERROR; + } + } + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + if ((sizetoxfer < hsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } @@ -977,7 +1002,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ @@ -987,7 +1012,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } @@ -996,8 +1021,15 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { - hsmbus->XferSize--; - hsmbus->XferCount--; + if (hsmbus->XferSize > 0U) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } } } @@ -1813,7 +1845,7 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval HAL state */ -uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus) { /* Return SMBUS handle state */ return hsmbus->State; @@ -1825,7 +1857,7 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval SMBUS Error Code */ -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus) { return hsmbus->ErrorCode; } @@ -2587,8 +2619,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c index 61718ac4f2..d40532656b 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c @@ -908,6 +908,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -937,6 +938,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -966,9 +968,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error: - hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); return errorcode; @@ -993,6 +998,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1006,12 +1017,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1089,6 +1094,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1112,6 +1118,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1206,9 +1213,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1327,6 +1337,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { @@ -1365,6 +1389,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1377,6 +1402,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { @@ -1415,6 +1453,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1484,8 +1523,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + else + { + hspi->State = HAL_SPI_STATE_READY; + } + error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1505,8 +1552,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); if ((pData == NULL) || (Size == 0U)) { @@ -1520,6 +1565,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1559,10 +1607,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1570,8 +1614,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } -error : + /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1587,6 +1635,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1594,14 +1649,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); } - /* Process Locked */ - __HAL_LOCK(hspi); - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -1609,6 +1656,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1661,9 +1711,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current process unlock */ @@ -1675,9 +1722,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1699,9 +1749,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; @@ -1719,6 +1766,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p goto error; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1775,8 +1825,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1785,9 +1833,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1891,7 +1942,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1931,6 +1981,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1945,12 +2001,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -2036,7 +2086,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -2204,7 +2253,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -2226,7 +2274,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c index 32b180ec30..a25079cde3 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c @@ -76,7 +76,7 @@ * the configuration information for the specified SPI module. * @retval HAL status */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) { __IO uint32_t tmpreg; uint8_t count = 0U; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c index a56ceda919..b7a3213501 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c @@ -896,7 +896,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) @@ -988,7 +988,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1067,7 +1067,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) @@ -1229,7 +1229,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1565,7 +1565,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) @@ -1657,7 +1657,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1736,7 +1736,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) @@ -1897,7 +1897,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -2141,7 +2141,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) @@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); @@ -2225,7 +2225,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) @@ -2313,7 +2313,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -2389,7 +2389,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Set the TIM channel state */ @@ -2544,7 +2544,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Disable the Input Capture channel */ @@ -3035,7 +3035,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; @@ -3841,13 +3841,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3875,11 +3878,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3905,11 +3908,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3935,11 +3938,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3965,11 +3968,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3978,11 +3981,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else @@ -3991,9 +3995,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break2 input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4004,11 +4008,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -4017,11 +4021,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM commutation event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else @@ -4573,7 +4577,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status; @@ -6016,8 +6021,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call { return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { @@ -6213,9 +6216,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } @@ -6259,9 +6259,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(htim); - if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) @@ -6498,9 +6495,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -7007,6 +7001,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } } /** @@ -7021,11 +7022,12 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7096,11 +7098,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7129,7 +7132,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7172,11 +7174,12 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7246,11 +7249,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7307,11 +7311,12 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7360,11 +7365,12 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7548,9 +7554,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) @@ -7638,9 +7644,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; @@ -7677,9 +7683,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; @@ -7721,9 +7727,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; @@ -7769,9 +7775,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c index aab8dd356e..ee268d8bf7 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c @@ -848,7 +848,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1094,17 +1094,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1330,7 +1319,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -2066,6 +2055,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); @@ -2082,15 +2072,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - - /* Set BREAK AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -2098,20 +2080,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - - /* Set BREAK2 AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } /* Set TIMx_BDTR */ @@ -2135,7 +2110,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; @@ -2465,7 +2439,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B uint32_t tmpbdtr; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -2482,7 +2456,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } - case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -2514,13 +2487,13 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B * @note Break input is automatically armed as soon as MOE bit is set. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -2599,7 +2572,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2613,7 +2586,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2628,7 +2601,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2643,7 +2616,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break2 detection callback in non blocking mode + * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ @@ -2794,15 +2767,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } else { /* nothing to do */ @@ -2871,13 +2835,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha { uint32_t tmp; - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ } /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c index a7703e7665..292c78f35f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c @@ -107,7 +107,7 @@ [..] Use function HAL_UART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -131,10 +131,10 @@ [..] By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + reset to the legacy weak functions in the HAL_UART_Init() and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -151,7 +151,7 @@ [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -197,8 +197,8 @@ /** @addtogroup UART_Private_Functions * @{ */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); @@ -348,15 +348,17 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In asynchronous mode, the following bits must be kept cleared: @@ -413,15 +415,17 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In half-duplex mode, the following bits must be kept cleared: @@ -499,15 +503,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In LIN mode, the following bits must be kept cleared: @@ -583,15 +589,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In multiprocessor mode, the following bits must be kept cleared: @@ -696,7 +704,10 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /** * @brief Register a User UART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -728,8 +739,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ return HAL_ERROR; } - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_READY) { switch (CallbackID) @@ -819,14 +828,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } /** * @brief Unregister an UART Callback * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -849,8 +859,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - __HAL_LOCK(huart); - if (HAL_UART_STATE_READY == huart->gState) { switch (CallbackID) @@ -942,8 +950,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } @@ -965,10 +971,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = pCallback; } @@ -979,9 +982,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -995,10 +995,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ } @@ -1009,8 +1006,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); return status; } @@ -1174,6 +1169,9 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { + + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1191,6 +1189,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } @@ -1282,6 +1282,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { + huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -3311,6 +3313,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { @@ -3332,13 +3341,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { @@ -3396,6 +3398,13 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3407,6 +3416,15 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3444,35 +3462,39 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); return HAL_TIMEOUT; } - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; huart->ErrorCode = HAL_UART_ERROR_RTO; /* Process Unlocked */ @@ -4252,6 +4274,16 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4335,6 +4367,16 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4469,6 +4511,16 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4623,6 +4675,16 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c index e40c2e6b96..29e6724369 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c @@ -211,15 +211,17 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ @@ -854,7 +856,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) @@ -879,24 +881,20 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; - status = UART_Start_Receive_IT(huart, pData, Size); + (void)UART_Start_Receive_IT(huart, pData, Size); - /* Check Rx process has been successfully started */ - if (status == HAL_OK) + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; } return status; @@ -1008,10 +1006,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * @param huart UART handle. * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) */ -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) { /* Return Rx Event type value, as stored in UART handle */ - return(huart->RxEventType); + return (huart->RxEventType); } /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c index 7678509387..243b93d3af 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c @@ -91,7 +91,7 @@ [..] Use function HAL_USART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -109,10 +109,10 @@ [..] By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_USART_Init() + reset to the legacy weak functions in the HAL_USART_Init() and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -129,7 +129,7 @@ [..] When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -406,7 +406,9 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /** * @brief Register a User USART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -436,8 +438,6 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(husart); if (husart->State == HAL_USART_STATE_READY) { @@ -526,15 +526,14 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } /** * @brief Unregister an USART Callback * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -555,9 +554,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(husart); - if (HAL_USART_STATE_READY == husart->State) { switch (CallbackID) @@ -645,9 +641,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c index cda5996aec..603dd465a4 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c @@ -122,7 +122,6 @@ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt @endverbatim - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c index e6e1a1f6ff..24aa073a48 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c @@ -269,7 +269,7 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) * - SUCCESS: ADC common registers are initialized * - ERROR: ADC common registers are not initialized */ -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { ErrorStatus status = SUCCESS; @@ -339,24 +339,13 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - /* Disable ADC instance if not already disabled. */ + /* Disable ADC instance if not already disabled. */ if (LL_ADC_IsEnabled(ADCx) == 1UL) { - /* Set ADC group regular trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); + /* Stop potential ADC conversion on going on ADC group regular. */ + LL_ADC_REG_StopConversion(ADCx); - /* Stop potential ADC conversion on going on ADC group regular. */ - if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) - { - if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) - { - LL_ADC_REG_StopConversion(ADCx); - } - } - - /* Wait for ADC conversions are effectively stopped */ + /* Wait for ADC conversions are effectively stopped */ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL) { @@ -432,32 +421,14 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register CFGR1 */ CLEAR_BIT(ADCx->CFGR1, (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN - | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD + | ADC_CFGR1_CHSELRMOD | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) ); - /* Reset register CFGR2 */ - /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ - /* already done above. */ - CLEAR_BIT(ADCx->CFGR2, - (ADC_CFGR2_CKMODE - | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR - | ADC_CFGR2_OVSE) - ); - /* Reset register SMPR */ CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL); - /* Reset register AWD1TR */ - MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1); - - /* Reset register AWD2TR */ - MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2); - - /* Reset register AWD3TR */ - MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3); - /* Reset register CHSELR */ CLEAR_BIT(ADCx->CHSELR, (ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 @@ -467,6 +438,15 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0) ); + /* Reset register AWD1TR */ + MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1); + + /* Reset register AWD2TR */ + MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2); + + /* Reset register AWD3TR */ + MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3); + /* Wait for ADC channel configuration ready */ timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES; while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL) @@ -489,6 +469,17 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register CALFACT */ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT); + /* Reset register CFGR2 */ + /* Note: CFGR2 reset done at the end of de-initialization due to */ + /* clock source reset */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + CLEAR_BIT(ADCx->CFGR2, + (ADC_CFGR2_CKMODE + | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR + | ADC_CFGR2_OVSE) + ); + } else { @@ -513,7 +504,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -540,7 +531,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct) +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct) { ErrorStatus status = SUCCESS; @@ -614,7 +605,7 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -644,7 +635,7 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c index f04e72ae5d..cb0ffd21b8 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c @@ -15,6 +15,7 @@ * ****************************************************************************** */ + #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ @@ -49,7 +50,7 @@ /* COMP instance. */ #define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \ - ( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \ + (((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \ || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \ ) @@ -58,7 +59,7 @@ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ - ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ + (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \ ) @@ -68,7 +69,7 @@ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ @@ -80,19 +81,19 @@ ) #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \ - ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \ + (((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \ ) #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \ - ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \ + (((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \ ) #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC4) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3) \ @@ -164,7 +165,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) * - SUCCESS: COMP registers are initialized * - ERROR: COMP registers are not initialized */ -ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct) +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crc.c index 261291eaec..a4ed6e1f00 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crc.c @@ -59,7 +59,7 @@ * - SUCCESS: CRC registers are de-initialized * - ERROR: CRC registers are not de-initialized */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dac.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dac.c index de0f04801b..bb07220abe 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dac.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dac.c @@ -46,12 +46,12 @@ * @{ */ #define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \ - ( ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ - || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ + (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ ) #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ - ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ @@ -64,55 +64,55 @@ ) #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ - ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ ) \ ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ - ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \ - ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \ - || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ + (((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \ + || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ ) #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \ - ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \ - || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ + (((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \ + || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ ) /** @@ -139,7 +139,7 @@ * - SUCCESS: DAC registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) +ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx) { /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); @@ -178,7 +178,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) * - SUCCESS: DAC registers are initialized * - ERROR: DAC registers are not initialized */ -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; @@ -290,4 +290,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_i2c.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_i2c.c index 04b77436e5..2396ddef5b 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_i2c.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_i2c.c @@ -83,7 +83,7 @@ * - SUCCESS: I2C registers are de-initialized * - ERROR: I2C registers are not de-initialized */ -ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) { ErrorStatus status = SUCCESS; @@ -133,7 +133,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) * - SUCCESS: I2C registers are initialized * - ERROR: Not applicable */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct) { /* Check the I2C Instance I2Cx */ assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lptim.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lptim.c index 909447fd3f..656d2cc039 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lptim.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lptim.c @@ -92,7 +92,7 @@ * - SUCCESS: LPTIMx registers are de-initialized * - ERROR: invalid LPTIMx instance */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx) +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx) { ErrorStatus result = SUCCESS; @@ -276,8 +276,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lpuart.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lpuart.c index 13c86b3f1f..8389725aa1 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lpuart.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lpuart.c @@ -44,6 +44,9 @@ * @{ */ +/* Definition of default baudrate value used for LPUART initialisation */ +#define LPUART_DEFAULT_BAUDRATE (9600U) + /** * @} */ @@ -282,7 +285,7 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) { /* Set LPUART_InitStruct fields to default values */ LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; - LPUART_InitStruct->BaudRate = 9600U; + LPUART_InitStruct->BaudRate = LPUART_DEFAULT_BAUDRATE; LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c index f787d13ebc..3d3c105116 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c @@ -68,7 +68,7 @@ * - SUCCESS: RNG registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c index d8d7b7df48..151a31b345 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c @@ -66,8 +66,8 @@ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) @@ -219,7 +219,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM * - SUCCESS: TIMx registers are de-initialized * - ERROR: invalid TIMx instance */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) { ErrorStatus result = SUCCESS; @@ -738,6 +738,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -750,14 +752,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); - if (IS_TIM_ADVANCED_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(TIMx)) { @@ -809,8 +805,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -838,8 +832,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -888,8 +884,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -917,8 +911,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -967,8 +963,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -996,8 +990,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -1046,8 +1042,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1075,7 +1069,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the Output Idle state */ @@ -1342,7 +1335,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c index d77ee9ae95..2126079609 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c @@ -31,7 +31,7 @@ * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART4) || defined(USART5) || defined(USART6) /** @addtogroup USART_LL * @{ @@ -40,6 +40,17 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for USART initialisation */ +#define USART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @addtogroup USART_LL_Private_Macros * @{ @@ -363,7 +374,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) { /* Set USART_InitStruct fields to default values */ USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; - USART_InitStruct->BaudRate = 9600U; + USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; USART_InitStruct->StopBits = LL_USART_STOPBITS_1; USART_InitStruct->Parity = LL_USART_PARITY_NONE ; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usb.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usb.c index 4356814429..da131b227f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usb.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usb.c @@ -27,7 +27,7 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. (#) Call USB_CoreInit() API to initialize the USB Core peripheral. @@ -91,16 +91,21 @@ static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx) */ HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) { + HAL_StatusTypeDef ret; UNUSED(cfg); - HAL_StatusTypeDef state; + + if (USBx == NULL) + { + return HAL_ERROR; + } /* Reset after a PHY select */ - state = USB_CoreReset(USBx); + ret = USB_CoreReset(USBx); /* Clear pending interrupts */ USBx->ISTR = 0U; - return state; + return ret; } /** @@ -164,10 +169,14 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef { USBx->CNTR &= ~USB_CNTR_HOST; } - else + else if (mode == USB_HOST_MODE) { USBx->CNTR |= USB_CNTR_HOST; } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -182,8 +191,11 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef */ HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) { + HAL_StatusTypeDef ret; + /* Prevent unused argument(s) compilation warning */ UNUSED(cfg); + /* Force Reset */ USBx->CNTR = USB_CNTR_USBRST; @@ -191,14 +203,55 @@ HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) USBx->CNTR &= ~USB_CNTR_USBRST; /* Set the Device Mode */ - (void)USB_SetCurrentMode(USBx, USB_DEVICE_MODE); + ret = USB_SetCurrentMode(USBx, USB_DEVICE_MODE); /* Clear pending interrupts */ USBx->ISTR = 0U; + return ret; +} + +/** + * @brief USB_FlushTxFifo : Flush a Tx FIFO + * @param USBx : Selected device + * @param num : FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(num); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; } + #if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint @@ -778,7 +831,7 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx) * @param USBx Selected device * @retval USB Global Interrupt status */ -uint32_t USB_ReadInterrupts(USB_DRD_TypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx) { uint32_t tmpreg; @@ -818,7 +871,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx) * @param wNBytes no. of bytes to be copied. * @retval None */ -void USB_WritePMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { UNUSED(USBx); uint32_t WrVal; @@ -875,7 +928,7 @@ void USB_WritePMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr * @param wNBytes no. of bytes to be copied. * @retval None */ -void USB_ReadPMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { UNUSED(USBx); uint32_t count; @@ -989,7 +1042,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx) * @arg USB_DRD_SPEED_FS Full speed mode * @arg USB_DRD_SPEED_LS Low speed mode */ -uint32_t USB_GetHostSpeed(USB_DRD_TypeDef *USBx) +uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx) { if ((USBx->ISTR & USB_ISTR_LS_DCONN) != 0U) { @@ -1006,7 +1059,7 @@ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef *USBx) * @param USBx Selected device * @retval current frame number */ -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef *USBx) +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) { return USBx->FNR & 0x7FFU; } diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 4476fdd94e..764893475a 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -7,7 +7,7 @@ * STM32F3: 1.5.7 * STM32F4: 1.8.2 * STM32F7: 1.3.0 - * STM32G0: 1.4.4 + * STM32G0: 1.4.6 * STM32G4: 1.2.2 * STM32H5: 1.1.0 * STM32H7: 1.11.1 From 213ec659e7d9052357e3151ca8165faf01852fa8 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 2 Jan 2024 11:25:40 +0100 Subject: [PATCH 64/83] system(G0): update STM32G0xx CMSIS Drivers to v1.4.4 Included in STM32CubeG0 FW v1.6.2 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32G0xx/Include/stm32g030xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g031xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g041xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g050xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g051xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g061xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g070xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g071xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g081xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g0b0xx.h | 11 ++- .../Device/ST/STM32G0xx/Include/stm32g0b1xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g0c1xx.h | 6 ++ .../Device/ST/STM32G0xx/Include/stm32g0xx.h | 2 +- .../ST/STM32G0xx/{License.md => LICENSE.md} | 0 .../CMSIS/Device/ST/STM32G0xx/README.md | 23 +++--- .../Device/ST/STM32G0xx/Release_Notes.html | 81 ++++++++++++++----- .../Templates/gcc/startup_stm32g030xx.s | 3 +- .../Templates/gcc/startup_stm32g031xx.s | 3 +- .../Templates/gcc/startup_stm32g041xx.s | 3 +- .../Templates/gcc/startup_stm32g050xx.s | 3 +- .../Templates/gcc/startup_stm32g051xx.s | 3 +- .../Templates/gcc/startup_stm32g061xx.s | 3 +- .../Templates/gcc/startup_stm32g070xx.s | 3 +- .../Templates/gcc/startup_stm32g071xx.s | 3 +- .../Templates/gcc/startup_stm32g081xx.s | 3 +- .../Templates/gcc/startup_stm32g0b0xx.s | 3 +- .../Templates/gcc/startup_stm32g0b1xx.s | 3 +- .../Templates/gcc/startup_stm32g0c1xx.s | 3 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 29 files changed, 176 insertions(+), 45 deletions(-) rename system/Drivers/CMSIS/Device/ST/STM32G0xx/{License.md => LICENSE.md} (100%) diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h index af20715c2c..2d51ab5392 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h @@ -4045,6 +4045,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h index 62f929b4ba..941f888120 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h @@ -4225,6 +4225,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h index d8ede70694..23ce34d604 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h @@ -4461,6 +4461,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h index 53490b7e6e..20130942a4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h @@ -4064,6 +4064,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h index dd3e7c999e..dbf1d633fc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h @@ -4561,6 +4561,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h index 4738a947a9..6e7973946a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h @@ -4797,6 +4797,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h index 702c42af7e..2d79b255a8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h @@ -4193,6 +4193,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h index b8b11b384b..1ba718629d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h @@ -4896,6 +4896,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h index d6ebdd4bea..a552e1bc2a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h @@ -5132,6 +5132,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h index 6c54693572..c693338ed9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h @@ -325,7 +325,7 @@ typedef struct typedef struct { __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ @@ -4363,6 +4363,9 @@ typedef struct #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */ +#define PWR_CR2_USV_Pos (10U) +#define PWR_CR2_USV_Msk (0x1UL << PWR_CR2_USV_Pos) /*!< 0x00000400 */ +#define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */ /******************** Bit definition for PWR_CR3 register ********************/ #define PWR_CR3_EWUP_Pos (0U) @@ -5162,6 +5165,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h index 36e2cba5d2..b97b0091a8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h @@ -6146,6 +6146,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h index 8ebf0a7b55..2c36f00615 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h @@ -6382,6 +6382,12 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h index 1749bdf86e..b10d5cfe45 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h @@ -90,7 +90,7 @@ */ #define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ -#define __STM32G0_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ +#define __STM32G0_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ #define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/License.md b/system/Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.md similarity index 100% rename from system/Drivers/CMSIS/Device/ST/STM32G0xx/License.md rename to system/Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.md diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md index 1455645d59..6dac671722 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md @@ -1,19 +1,21 @@ # STM32CubeG0 CMSIS Device MCU Component +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_g0.svg?color=brightgreen) + ## Overview **STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product - * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio - * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series - * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ... - * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series. + * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library... + * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. -Two models of publication are proposed for the STM32Cube embedded software : - * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) - * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions. +Two models of publication are proposed for the STM32Cube embedded software: + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. ## Description @@ -30,6 +32,5 @@ It is **crucial** that you use a consistent set of versions for the CMSIS Core - The full **STM32CubeG0** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG0). ## Troubleshooting -If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_g0/issues/new). -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Release_Notes.html index 35c0be0a69..f27e809d6f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Release_Notes.html @@ -45,10 +45,53 @@

Purpose

Update History

- +

Main Changes

    +
  • Update USB RXBD count mask.
    • +
  • Add RCC_CFGR_SWS_HSE, HSI, PLL, LSI, LSE system clock definitions.
    • +
  • Update to support USB supply enable feature for STM32G0B0 devices.
    • +
  • Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.
    • +
+

Contents

+
    +
  • CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.
    • +
  • CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.
    • +
  • CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.
    • +
  • CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.
    • +
+

Known Limitations

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • README.md update: Remove compatibility table from “Compatibility information” section.
    • +
+

Contents

+
    +
  • CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.
    • +
  • CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.
    • +
  • CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.
    • +
  • CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.
    • +
+

Known Limitations

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+
  • Rename ADC TRx registers AWDxTR to be compliant with the reference manual.
  • Fix Doxygen grouping issues.
  • Update IRQ handler enumeration structure to be aligned with template CMSIS device.h file defined by ARM. @@ -60,14 +103,14 @@

    Main Changes

  • #define SVC_IRQn SVCall_IRQn
-

Contents

+

Contents

  • CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.
  • CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.
  • CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.
  • CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.
-

Known Limitations

+

Known Limitations

  • None
@@ -76,7 +119,7 @@

Known Limitations

-

Main Changes

+

Main Changes

  • Update to remove wrong bits defined for DMAMUX Req ID.
  • Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.
    • @@ -89,14 +132,14 @@

    Main Changes

  • Update header files with new license format
-

Contents

+

Contents

  • CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.
  • CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.
  • CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.
  • CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.
-

Known Limitations

+

Known Limitations

  • None
@@ -105,7 +148,7 @@

Known Limitations

-

Main Changes

+

Main Changes

Maintenance release and Product Update

Official release for STM32G0xx CMSIS introducing stm32g0b0xx, stm32g0b1xx, stm32g0c1xx devices and stm32g050xx, stm32g051xx, stm32g061xx devices.

Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.

@@ -186,19 +229,19 @@

Maintenance release and Product -

Contents

+

Contents

-CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.

-CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.

-CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.

-CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.

-

Known Limitations

+

Known Limitations

None

-

Main Changes

+

Main Changes

Maintenance release

Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.

Fixed bugs list

@@ -214,10 +257,10 @@

Maintenance release

-

Contents

+

Contents

CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.

CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.

-

Known Limitations

+

Known Limitations

Requirements not met or planned in a forthcoming release

@@ -247,7 +290,7 @@

Supported Devices and boards

-

Main Changes

+

Main Changes

Maintenance release and Product Update

First release for STM32G0xx CMSIS introducing stm32g030xx, stm32g031xx, stm32g041xx devices.

Additional features

@@ -279,10 +322,10 @@

Maintenance release and Produc

-

Contents

+

Contents

CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.

CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.

-

Known Limitations

+

Known Limitations

Requirements not met or planned in a forthcoming release

@@ -315,7 +358,7 @@

Supported Devices and boards

-

Main Changes

+

Main Changes

Maintenance release

Maintenance release for STM32G0xx devices (stm32g070xx, stm32g071xx, stm32g081xx devices)

Fixed bugs list

@@ -340,17 +383,17 @@

Maintenance release

-

Contents

+

Contents

CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.

-

Main Changes

+

Main Changes

First release

First official release for STM32G0xx devices

-

Contents

+

Contents

  • CMSIS devices files for STM32G070xx, STM32G071xx and STM32G081xx
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s index fd82f1008b..a168383fdd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -177,6 +176,8 @@ g_pfnVectors: .word USART2_IRQHandler /* USART2 */ .word 0 /* reserved */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s index 51c922b9f0..473af2c47d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -178,6 +177,8 @@ g_pfnVectors: .word LPUART1_IRQHandler /* LPUART1 */ .word 0 /* reserved */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s index af334332a1..dd8cb858da 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -179,6 +178,8 @@ g_pfnVectors: .word 0 /* reserved */ .word AES_RNG_IRQHandler /* AES and RNG */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g050xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g050xx.s index 4f4d13b30b..1b893c8f1a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g050xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g050xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -176,6 +175,8 @@ g_pfnVectors: .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g051xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g051xx.s index 8a71dec2c7..a38cee68a7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g051xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g051xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -177,6 +176,8 @@ g_pfnVectors: .word USART2_IRQHandler /* USART2 */ .word LPUART1_IRQHandler /* LPUART1 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g061xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g061xx.s index 15c8dbb084..79d1e4866e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g061xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g061xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -179,6 +178,8 @@ g_pfnVectors: .word 0 /* reserved */ .word AES_RNG_IRQHandler /* AES and RNG */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s index 7dfdd8445d..83e6c3c891 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -177,6 +176,8 @@ g_pfnVectors: .word USART2_IRQHandler /* USART2 */ .word USART3_4_IRQHandler /* USART3, USART4 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s index 5b4d4d8778..ac013044a5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -178,6 +177,8 @@ g_pfnVectors: .word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */ .word CEC_IRQHandler /* CEC */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s index e4ee41bfb0..60f8caa6d0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -179,6 +178,8 @@ g_pfnVectors: .word CEC_IRQHandler /* CEC */ .word AES_RNG_IRQHandler /* AES and RNG */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b0xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b0xx.s index a32177c4ad..969d388c8a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b0xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b0xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -177,6 +176,8 @@ g_pfnVectors: .word USART2_IRQHandler /* USART2 */ .word USART3_4_5_6_IRQHandler /* USART3, USART4, USART5, USART6 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b1xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b1xx.s index 7bf683abd1..88a1208864 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b1xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b1xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -178,6 +177,8 @@ g_pfnVectors: .word USART3_4_5_6_LPUART1_IRQHandler /* USART3, USART4, USART5, USART6, LPUART1 */ .word CEC_IRQHandler /* CEC */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0c1xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0c1xx.s index 0fd5896d2f..6aaf18f818 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0c1xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0c1xx.s @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -179,6 +178,8 @@ g_pfnVectors: .word CEC_IRQHandler /* CEC */ .word AES_RNG_IRQHandler /* AES and RNG */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index e40eb0aabc..6a5af926c1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -7,7 +7,7 @@ * STM32F3: 2.3.7 * STM32F4: 2.6.9 * STM32F7: 1.2.8 - * STM32G0: 1.4.3 + * STM32G0: 1.4.4 * STM32G4: 1.2.2 * STM32H5: 1.1.0 * STM32H7: 1.10.3 From 17ca401912a00fef90ae80fbbc2686c2f7b59390 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 2 Jan 2024 15:35:59 +0100 Subject: [PATCH 65/83] ci(stm32cube): remove STM32G4 CMSIS patch Included in STM32CubeG4 1.5.2. Signed-off-by: Frederic Pillon --- ...491-and-stm32g4a1-add-missing-aliase.patch | 51 ------------------- 1 file changed, 51 deletions(-) delete mode 100644 CI/update/patch/CMSIS/G4/0001-Fix-CMSIS-stm32g491-and-stm32g4a1-add-missing-aliase.patch diff --git a/CI/update/patch/CMSIS/G4/0001-Fix-CMSIS-stm32g491-and-stm32g4a1-add-missing-aliase.patch b/CI/update/patch/CMSIS/G4/0001-Fix-CMSIS-stm32g491-and-stm32g4a1-add-missing-aliase.patch deleted file mode 100644 index af22f672f3..0000000000 --- a/CI/update/patch/CMSIS/G4/0001-Fix-CMSIS-stm32g491-and-stm32g4a1-add-missing-aliase.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 43d68baed68625b2e99d15d841c31cb1bfb2475a Mon Sep 17 00:00:00 2001 -From: Alexandre Bourdiol -Date: Mon, 20 Jun 2022 13:58:28 +0200 -Subject: [PATCH] Fix: CMSIS stm32g491 and stm32g4a1 add missing aliases for - TIM7 and COMP4/5/6 - -Internal ticket 130525 - -Signed-off-by: Alexandre Bourdiol ---- - .../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g491xx.h | 4 ++++ - .../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4a1xx.h | 4 ++++ - 2 files changed, 8 insertions(+) - -diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g491xx.h b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g491xx.h -index ca9874b3..84f12c6e 100644 ---- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g491xx.h -+++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g491xx.h -@@ -13694,8 +13694,12 @@ typedef struct - /******************************************************************************/ - - /* Aliases for __IRQn */ -+#define TIM7_DAC_IRQn TIM7_IRQn -+#define COMP4_5_6_IRQn COMP4_IRQn - - /* Aliases for __IRQHandler */ -+#define TIM7_DAC_IRQHandler TIM7_IRQHandler -+#define COMP4_5_6_IRQHandler COMP4_IRQHandler - - #ifdef __cplusplus - } -diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4a1xx.h b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4a1xx.h -index 2fb6e6f5..2431b284 100644 ---- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4a1xx.h -+++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4a1xx.h -@@ -13926,8 +13926,12 @@ typedef struct - /******************************************************************************/ - - /* Aliases for __IRQn */ -+#define TIM7_DAC_IRQn TIM7_IRQn -+#define COMP4_5_6_IRQn COMP4_IRQn - - /* Aliases for __IRQHandler */ -+#define TIM7_DAC_IRQHandler TIM7_IRQHandler -+#define COMP4_5_6_IRQHandler COMP4_IRQHandler - - #ifdef __cplusplus - } --- -2.31.1.windows.1 - From b35b14023c8ed8ce16d4b63452eea585d1c92f45 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 2 Jan 2024 15:36:20 +0100 Subject: [PATCH 66/83] system(G4) update STM32G4xx HAL Drivers to v1.2.3 Included in STM32CubeG4 FW v1.5.2 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 265 +- .../STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h | 3 + .../Inc/stm32g4xx_hal_adc.h | 922 +++-- .../Inc/stm32g4xx_hal_adc_ex.h | 583 ++-- .../Inc/stm32g4xx_hal_comp.h | 323 +- .../Inc/stm32g4xx_hal_cordic.h | 16 +- .../Inc/stm32g4xx_hal_crc.h | 2 +- .../Inc/stm32g4xx_hal_cryp.h | 29 +- .../Inc/stm32g4xx_hal_cryp_ex.h | 4 +- .../Inc/stm32g4xx_hal_dac.h | 50 +- .../Inc/stm32g4xx_hal_dac_ex.h | 14 +- .../Inc/stm32g4xx_hal_def.h | 4 +- .../Inc/stm32g4xx_hal_fdcan.h | 127 +- .../Inc/stm32g4xx_hal_flash.h | 3 +- .../Inc/stm32g4xx_hal_fmac.h | 145 +- .../Inc/stm32g4xx_hal_hrtim.h | 62 +- .../Inc/stm32g4xx_hal_i2c.h | 17 +- .../Inc/stm32g4xx_hal_irda.h | 4 +- .../Inc/stm32g4xx_hal_lptim.h | 28 +- .../Inc/stm32g4xx_hal_nand.h | 43 +- .../Inc/stm32g4xx_hal_nor.h | 2 +- .../Inc/stm32g4xx_hal_pcd.h | 71 +- .../Inc/stm32g4xx_hal_qspi.h | 32 +- .../Inc/stm32g4xx_hal_rcc.h | 4 +- .../Inc/stm32g4xx_hal_rcc_ex.h | 2 +- .../Inc/stm32g4xx_hal_rng.h | 6 +- .../Inc/stm32g4xx_hal_rtc.h | 11 + .../Inc/stm32g4xx_hal_sai.h | 16 +- .../Inc/stm32g4xx_hal_sai_ex.h | 3 +- .../Inc/stm32g4xx_hal_smartcard.h | 4 +- .../Inc/stm32g4xx_hal_smbus.h | 6 +- .../Inc/stm32g4xx_hal_spi_ex.h | 2 +- .../Inc/stm32g4xx_hal_sram.h | 2 +- .../Inc/stm32g4xx_hal_tim.h | 232 +- .../Inc/stm32g4xx_hal_tim_ex.h | 672 ++-- .../Inc/stm32g4xx_hal_uart.h | 31 +- .../Inc/stm32g4xx_hal_uart_ex.h | 2 + .../Inc/stm32g4xx_hal_usart.h | 9 +- .../Inc/stm32g4xx_hal_usart_ex.h | 2 +- .../Inc/stm32g4xx_ll_adc.h | 2995 +++++++++++------ .../Inc/stm32g4xx_ll_comp.h | 40 +- .../Inc/stm32g4xx_ll_cordic.h | 42 +- .../Inc/stm32g4xx_ll_crc.h | 22 +- .../Inc/stm32g4xx_ll_dac.h | 139 +- .../Inc/stm32g4xx_ll_fmac.h | 106 +- .../Inc/stm32g4xx_ll_fmc.h | 8 +- .../Inc/stm32g4xx_ll_hrtim.h | 364 +- .../Inc/stm32g4xx_ll_i2c.h | 129 +- .../Inc/stm32g4xx_ll_iwdg.h | 12 +- .../Inc/stm32g4xx_ll_lptim.h | 96 +- .../Inc/stm32g4xx_ll_lpuart.h | 165 +- .../Inc/stm32g4xx_ll_rcc.h | 48 +- .../Inc/stm32g4xx_ll_rng.h | 21 +- .../Inc/stm32g4xx_ll_rtc.h | 20 +- .../Inc/stm32g4xx_ll_tim.h | 336 +- .../Inc/stm32g4xx_ll_ucpd.h | 6 +- .../Inc/stm32g4xx_ll_usart.h | 242 +- .../Inc/stm32g4xx_ll_usb.h | 102 +- .../Inc/stm32g4xx_ll_utils.h | 39 +- .../Inc/stm32g4xx_ll_wwdg.h | 12 +- .../Drivers/STM32G4xx_HAL_Driver/LICENSE.md | 27 + .../STM32G4xx_HAL_Driver/Release_Notes.html | 285 +- .../STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c | 34 +- .../Src/stm32g4xx_hal_adc.c | 306 +- .../Src/stm32g4xx_hal_adc_ex.c | 327 +- .../Src/stm32g4xx_hal_comp.c | 122 +- .../Src/stm32g4xx_hal_cordic.c | 48 +- .../Src/stm32g4xx_hal_crc.c | 4 +- .../Src/stm32g4xx_hal_crc_ex.c | 79 +- .../Src/stm32g4xx_hal_cryp.c | 797 ++--- .../Src/stm32g4xx_hal_cryp_ex.c | 8 +- .../Src/stm32g4xx_hal_dac.c | 185 +- .../Src/stm32g4xx_hal_dac_ex.c | 157 +- .../Src/stm32g4xx_hal_exti.c | 4 +- .../Src/stm32g4xx_hal_fdcan.c | 186 +- .../Src/stm32g4xx_hal_flash.c | 32 +- .../Src/stm32g4xx_hal_flash_ex.c | 23 +- .../Src/stm32g4xx_hal_fmac.c | 23 +- .../Src/stm32g4xx_hal_hrtim.c | 170 +- .../Src/stm32g4xx_hal_i2c.c | 1300 +++++-- .../Src/stm32g4xx_hal_irda.c | 30 +- .../Src/stm32g4xx_hal_lptim.c | 107 +- .../Src/stm32g4xx_hal_nand.c | 68 +- .../Src/stm32g4xx_hal_nor.c | 257 +- .../Src/stm32g4xx_hal_pcd.c | 93 +- .../Src/stm32g4xx_hal_pcd_ex.c | 36 +- .../Src/stm32g4xx_hal_qspi.c | 222 +- .../Src/stm32g4xx_hal_rcc.c | 11 +- .../Src/stm32g4xx_hal_rng.c | 31 +- .../Src/stm32g4xx_hal_rtc.c | 47 +- .../Src/stm32g4xx_hal_sai.c | 71 +- .../Src/stm32g4xx_hal_sai_ex.c | 3 +- .../Src/stm32g4xx_hal_smartcard.c | 31 +- .../Src/stm32g4xx_hal_smbus.c | 80 +- .../Src/stm32g4xx_hal_spi.c | 135 +- .../Src/stm32g4xx_hal_spi_ex.c | 2 +- .../Src/stm32g4xx_hal_sram.c | 40 +- .../Src/stm32g4xx_hal_tim.c | 278 +- .../Src/stm32g4xx_hal_tim_ex.c | 89 +- .../Src/stm32g4xx_hal_uart.c | 285 +- .../Src/stm32g4xx_hal_uart_ex.c | 84 +- .../Src/stm32g4xx_hal_usart.c | 34 +- .../Src/stm32g4xx_hal_wwdg.c | 1 - .../Src/stm32g4xx_ll_adc.c | 214 +- .../Src/stm32g4xx_ll_comp.c | 351 +- .../Src/stm32g4xx_ll_cordic.c | 2 +- .../Src/stm32g4xx_ll_crc.c | 2 +- .../Src/stm32g4xx_ll_dac.c | 132 +- .../Src/stm32g4xx_ll_fmac.c | 2 +- .../Src/stm32g4xx_ll_fmc.c | 3 +- .../Src/stm32g4xx_ll_i2c.c | 4 +- .../Src/stm32g4xx_ll_lptim.c | 7 +- .../Src/stm32g4xx_ll_lpuart.c | 9 +- .../Src/stm32g4xx_ll_rng.c | 2 +- .../Src/stm32g4xx_ll_tim.c | 96 +- .../Src/stm32g4xx_ll_usart.c | 21 +- .../Src/stm32g4xx_ll_usb.c | 139 +- .../Src/stm32g4xx_ll_utils.c | 129 +- .../STM32G4xx_HAL_Driver/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../{mini-st.css => mini-st_2020.css} | 357 +- .../STM32G4xx_HAL_Driver/_htmresc/st_logo.png | Bin 18616 -> 0 bytes .../_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 123 files changed, 9722 insertions(+), 6599 deletions(-) create mode 100644 system/Drivers/STM32G4xx_HAL_Driver/LICENSE.md create mode 100644 system/Drivers/STM32G4xx_HAL_Driver/_htmresc/favicon.png rename system/Drivers/STM32G4xx_HAL_Driver/_htmresc/{mini-st.css => mini-st_2020.css} (78%) delete mode 100644 system/Drivers/STM32G4xx_HAL_Driver/_htmresc/st_logo.png create mode 100644 system/Drivers/STM32G4xx_HAL_Driver/_htmresc/st_logo_2020.png diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 46d02f5894..3caddb5298 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,14 +37,12 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -104,6 +102,8 @@ extern "C" { #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ + + /** * @} */ @@ -131,7 +131,8 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) @@ -205,6 +206,8 @@ extern "C" { #endif #endif + + /** * @} */ @@ -213,11 +216,6 @@ extern "C" { * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -#if defined(STM32U5) -#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE -#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE -#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE -#endif /* STM32U5 */ /** * @} */ @@ -225,8 +223,10 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ /** * @} */ @@ -256,19 +256,15 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32H7) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32U5) -#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 -#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 -#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 -#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 -#endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -333,7 +329,8 @@ extern "C" { #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif @@ -410,6 +407,7 @@ extern "C" { #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ + /** * @} */ @@ -506,15 +504,6 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ -#if defined(STM32U5) -#define OB_USER_nRST_STOP OB_USER_NRST_STOP -#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY -#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW -#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 -#define OB_USER_nBOOT0 OB_USER_NBOOT0 -#define OB_nBOOT0_RESET OB_NBOOT0_RESET -#define OB_nBOOT0_SET OB_NBOOT0_SET -#endif /* STM32U5 */ /** * @} @@ -558,6 +547,8 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + + /** * @} */ @@ -625,19 +616,20 @@ extern "C" { #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB */ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -654,9 +646,6 @@ extern "C" { #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -#if defined(STM32U5) -#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ -#endif /* STM32U5 */ /** * @} */ @@ -664,9 +653,6 @@ extern "C" { /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose * @{ */ -#if defined(STM32U5) -#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI -#endif /* STM32U5 */ /** * @} */ @@ -847,7 +833,8 @@ extern "C" { #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -913,22 +900,6 @@ extern "C" { * @} */ -/** @defgroup HAL_LPTIM_Aliased_Defines LL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 -#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 -#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 -#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 -/** - * @} - */ - -#if defined(STM32U5) -#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF -#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF -#define LPTIM_CHANNEL_ALL 0x00000000U -#endif /* STM32U5 */ /** * @} */ @@ -1080,8 +1051,8 @@ extern "C" { #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE @@ -1092,15 +1063,25 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + + + +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL -#endif /* STM32H7 */ +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 */ /** * @} @@ -1376,30 +1357,40 @@ extern "C" { #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ @@ -1407,6 +1398,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1455,9 +1448,7 @@ extern "C" { */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ - || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ - || defined(STM32H7) || defined(STM32U5) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7) /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ @@ -1467,7 +1458,7 @@ extern "C" { * @} */ -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ @@ -1491,10 +1482,6 @@ extern "C" { * @{ */ -#if defined(STM32U5) -#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr -#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT -#endif /* STM32U5 */ /** * @} @@ -1570,7 +1557,8 @@ extern "C" { #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1579,8 +1567,10 @@ extern "C" { #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode @@ -1614,16 +1604,21 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ - )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1697,10 +1692,19 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + /** * @} */ +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ @@ -1726,7 +1730,8 @@ extern "C" { #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback @@ -1983,7 +1988,8 @@ extern "C" { #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) @@ -2155,8 +2161,10 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ /** * @} */ @@ -2315,7 +2323,9 @@ extern "C" { #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE @@ -2324,8 +2334,12 @@ extern "C" { #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 @@ -2361,8 +2375,8 @@ extern "C" { #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -2866,6 +2880,11 @@ extern "C" { #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE @@ -3330,7 +3349,8 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3442,31 +3462,7 @@ extern "C" { #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 -#if defined(STM32U5) -#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL -#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL -#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE -#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE -#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE -#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE -#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE -#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE -#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE -#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE -#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE -#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT -#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK -#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 -#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 -#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 -#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK -#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#endif + /** * @} @@ -3484,7 +3480,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3519,6 +3515,13 @@ extern "C" { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER @@ -3537,6 +3540,7 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + /** * @} */ @@ -3548,7 +3552,7 @@ extern "C" { #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE @@ -3795,6 +3799,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h index 9cc3513af0..5786f8a428 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h @@ -544,6 +544,9 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h index 6b0c3b2724..97bc1bbce0 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h @@ -60,9 +60,10 @@ typedef struct uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected sequence interruption. - If oversampling is enabled on both regular and injected groups, this parameter - is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" - (the oversampling buffer is zeroed during injection sequence). + If oversampling is enabled on both regular and injected groups, this + parameter is discarded and forced to setting + "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed + during injection sequence). This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ } ADC_OversamplingTypeDef; @@ -73,27 +74,36 @@ typedef struct * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, * GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait. * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, - * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, SamplingMode. + * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, + * SamplingMode. * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled - * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. - * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. + * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled + * without conversion on going on group regular. + * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going + * on groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter - * (which fulfills the ADC state condition) on the fly). + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { - uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous + clock derived from system clock or PLL (Refer to reference manual for list of + clocks available)) and clock prescaler. This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. Note: The ADC clock configuration is common to all ADC instances. - Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, - AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. - Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only - if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC - must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. - Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. + Note: In case of usage of channels on injected group, ADC frequency should be + lower than AHB clock frequency /4 for resolution 12 or 10 bits, + AHB clock frequency /3 for resolution 8 bits, + AHB clock frequency /2 for resolution 6 bits. + Note: In case of synchronous clock mode based on HCLK/1, the configuration must + be enabled only if the system clock has a 50% duty clock cycle (APB + prescaler configured inside RCC must be bypassed and PCLK clock must have + 50% duty cycle). Refer to reference manual for details. + Note: In case of usage of asynchronous clock, the selected clock must be + preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled. */ uint32_t Resolution; /*!< Configure the ADC resolution. @@ -103,94 +113,141 @@ typedef struct Refer to reference manual for alignments formats versus resolutions. This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ - uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion data, based on following formula: - DATA = DATA(raw) * (gain compensation coef) / 4096 - 2.12 bit format, unsigned: 2 bits exponents / 12 bits mantissa - Gain step is 1/4096 = 0.000244 - Gain range is 0.0000 to 3.999756 + uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion + data, based on following formula: + DATA = DATA(raw) * (gain compensation coef) / 4096 + "2.12" bit format, unsigned: 2 bits exponents / 12 bits mantissa + Gain step is 1/4096 = 0.000244 + Gain range is 0.0000 to 3.999756 This parameter value can be 0 Gain compensation will be disabled and coefficient set to 0 - 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value - + 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified + value Note: Gain compensation when enabled is applied to all channels. */ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. - This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. - If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). - Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). - If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). - Scan direction is upward: from rank 1 to rank 'n'. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have + main sequence subdivided in successive parts. + If disabled: Conversion is performed in single mode (one channel converted, the + one defined in rank 1). Parameters 'NbrOfConversion' and + 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If enabled: Conversions are performed in sequence mode (multiple ranks defined + by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each + channel in sequencer). Scan direction is upward: from rank 1 to + rank 'n'. This parameter can be a value of @ref ADC_Scan_mode */ - uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. + uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and + interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of @ref ADC_EOCSelection. */ - FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous - conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, - using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). - This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun - for low frequency applications. + FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the + previous conversion (for ADC group regular) or previous sequence (for ADC group + injected) has been retrieved by user software, using function HAL_ADC_GetValue() + or HAL_ADCEx_InjectedGetValue(). + This feature automatically adapts the frequency of ADC conversions triggers to + the speed of the system that reads the data. Moreover, this avoids risk of + overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. - Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). - Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). - Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: - use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. - (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ - - FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, - after the first ADC conversion start trigger occurred (software start or external trigger). - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. - To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 16. - Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without - continuous mode or external trigger that could launch a conversion). */ - - FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence - (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), + HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC + flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended + benefit (except specific case of high load of CPU or DMA transfers which + can justify usage of auto wait). + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, + when ADC conversion data is needed: + use HAL_ADC_PollForConversion() to ensure that conversion is completed and + HAL_ADC_GetValue() to retrieve conversion result and trig another + conversion start. (in case of usage of ADC group injected, use the + equivalent functions HAL_ADCExInjected_Start(), + HAL_ADCEx_InjectedGetValue(), ...). */ + + FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) + or continuous mode for ADC group regular, after the first ADC conversion + start trigger occurred (software start or external trigger). This parameter + can be set to ENABLE or DISABLE. */ + + uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group + sequencer. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Number of ranks in the scan sequence is configurable using this parameter. + Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to + parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. + Afterwards, when all needed sequencer ranks are set, parameter + 'NbrOfConversion' can be updated without modifying configuration of + sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). + - sequencer configured to not fully configurable: + Number of ranks in the scan sequence is defined by number of channels set in + the sequence. This parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. + Note: This parameter must be modified when no conversion is on going on regular + group (ADC disabled, or ADC enabled without continuous mode or external + trigger that could launch a conversion). */ + + FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed + in Complete-sequence/Discontinuous-sequence (main sequence subdivided in + successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter + 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. + If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: On this STM32 series, ADC group regular number of discontinuous + ranks increment is fixed to one-by-one. */ + + uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence + of ADC group regular (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ - uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. - If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. + uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion + start. + If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger + is used instead. This parameter can be a value of @ref ADC_regular_external_trigger_source. Caution: external trigger source is common to all ADC instances. */ - uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. + uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. This parameter can be a value of @ref ADC_regular_sampling_mode */ - FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) - or in continuous mode (DMA transfer unlimited, whatever number of conversions). - This parameter can be set to ENABLE or DISABLE. - Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ + FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA + transfer stops when number of conversions is reached) or in continuous + mode (DMA transfer unlimited, whatever number of conversions). + This parameter can be set to ENABLE or DISABLE. + Note: In continuous mode, DMA must be configured in circular mode. + Otherwise an overrun will be triggered when DMA buffer maximum + pointer is reached. */ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. - Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear - end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function - HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). + Note: In case of overrun set to data preserved and usage with programming model + with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of + conversion flags, this induces the release of the preserved data. If + needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), + placed in user program code (called before end of conversion flags clear) Note: Error reporting with respect to the conversion mode: - - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data - overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ + - Usage with ADC conversion by polling for event or interruption: Error is + reported only if overrun is set to data preserved. If overrun is set to + data overwritten, user can willingly not read all the converted data, + this is not considered as an erroneous case. + - Usage with ADC conversion by DMA: Error is reported whatever overrun + setting (DMA is expected to process all data from data register). */ FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ + Note: This parameter can be modified only if there is no conversion is + ongoing on ADC groups regular and injected */ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ + Caution: this setting overwrites the previous oversampling configuration + if oversampling is already enabled. */ } ADC_InitTypeDef; @@ -199,65 +256,84 @@ typedef struct * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') - * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. - * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. + * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion + * on going on regular group. + * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on + * regular and injected groups. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) - * on the fly). + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL - Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ + Note: Depending on devices and ADC instances, some channels may not be available + on device package pins. Refer to device datasheet for channels + availability. */ uint32_t Rank; /*!< Specify the rank in the regular group sequencer. This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS - Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by - the new channel setting (or parameter number of conversions adjusted) */ + Note: to disable a channel or change order of conversion sequencer, rank + containing a previous channel setting can be overwritten by the new channel + setting (or parameter number of conversions adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time - (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME - Caution: This parameter applies to a channel that can be used into regular and/or injected group. - It overwrites the last setting. - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Caution: This parameter applies to a channel that can be used into regular + and/or injected group. It overwrites the last setting. + Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...), + sampling time constraints must be respected (sampling time can be adjusted + in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values. */ uint32_t SingleDiff; /*!< Select single-ended or differential input. - In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). - Only channel 'i' has to be configured, channel 'i+1' is configured automatically. + In differential mode: Differential measurement is carried out between the + selected channel 'i' (positive input) and channel 'i+1' (negative input). + Only channel 'i' has to be configured, channel 'i+1' is configured automatically This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING - Caution: This parameter applies to a channel that can be used in a regular and/or injected group. + Caution: This parameter applies to a channel that can be used in a regular + and/or injected group. It overwrites the last setting. - Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. - Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case - of another parameter update on the fly) */ + Note: Refer to Reference Manual to ensure the selected channel is available in + differential mode. + Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is + not usable separately. + Note: This parameter must be modified when ADC is disabled (before ADC start + conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error + reporting (as it can be the expected behavior in case of another parameter + update on the fly) */ uint32_t OffsetNumber; /*!< Select the offset number This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB - Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ + Caution: Only one offset is allowed per channel. This parameter overwrites the + last setting. */ uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter + must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled - without continuous mode or external trigger that could launch a conversion). */ - - uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. - This parameter can be a value of @ref ADCEx_OffsetSign. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled - without continuous mode or external trigger that could launch a conversion). */ + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without + continuous mode or external trigger that could launch a conversion). */ + + uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive + sign) from or to the raw converted data. + This parameter can be a value of @ref ADCEx_OffsetSign. + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without + continuous mode or external trigger that could launch a conversion).*/ FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. This parameter value can be ENABLE or DISABLE. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled - without continuous mode or external trigger that could launch a conversion). */ + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without + continuous mode or external trigger that could launch a conversion). */ } ADC_ChannelConfTypeDef; @@ -265,53 +341,74 @@ typedef struct * @brief Structure definition of ADC analog watchdog * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. * ADC state can be either: - * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. - * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups. + * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion + on going on ADC groups regular and injected. + * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and + injected groups. */ typedef struct { uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. - For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') - For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) + For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels + by setting parameter 'WatchdogMode') + For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls + of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. - For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. - For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all + channels, ADC groups regular and-or injected. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying + successively the AWD init structure. Channels on ADC + group regular and injected are not differentiated: Set + value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 + channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor + all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no + channel. This parameter can be a value of @ref ADC_analog_watchdog_mode. */ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. - For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). - For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). + For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' + is configured on single channel (only 1 channel can be + monitored). + For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, + call successively the function HAL_ADC_AnalogWDGConfig() + for each channel to be added (or removed with value + 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number - between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number - between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): - ADC data register bitfield [15:4] (12 most significant bits). */ + ADC data register bitfield [15:4] (12 most significant bits).*/ uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. Before setting flag or raising interrupt, analog watchdog can wait to have several consecutive out-of-window samples. This parameter allows to configure this number. - This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE. + This parameter only applies to Analog watchdog 1. For others, use value + ADC_AWD_FILTERING_NONE. This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ } ADC_AnalogWDGConfTypeDef; @@ -343,7 +440,8 @@ typedef struct /* States of ADC global scope */ #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, + calibration, ...) */ #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ /* States of ADC errors */ @@ -352,15 +450,20 @@ typedef struct #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur + (either by continuous mode, external trigger, low power + auto power-on (if feature available), multimode ADC master + control (if feature available)) */ #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag + raised */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur + (either by auto-injection mode, external trigger, low + power auto power-on (if feature available), multimode + ADC master control (if feature available)) */ #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ @@ -370,7 +473,8 @@ typedef struct #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ /* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC + master (when feature available) */ /** * @} @@ -385,20 +489,25 @@ typedef struct __ADC_HandleTypeDef typedef struct #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ { - ADC_TypeDef *Instance; /*!< Register base address */ - ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - HAL_LockTypeDef Lock; /*!< ADC locking object */ - __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ - __IO uint32_t ErrorCode; /*!< ADC Error code */ - ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ + ADC_TypeDef *Instance; /*!< Register base address */ + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular + conversions setting */ + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + HAL_LockTypeDef Lock; /*!< ADC locking object */ + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + __IO uint32_t ErrorCode; /*!< ADC Error code */ + ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up + structure */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ - void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer + callback */ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ - void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ - void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ + void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete + callback */ + void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue + overflow callback */ void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ @@ -463,22 +572,37 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ -#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ -#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ - -#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ -#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ -#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ -#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ -#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ -#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ -#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ -#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ -#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ -#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ -#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ -#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ + +#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock + without prescaler */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock + with prescaler division by 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock + with prescaler division by 4 */ +#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without + prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler + division by 2 */ +#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler + division by 4 */ +#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler + division by 6 */ +#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler + division by 8 */ +#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler + division by 10 */ +#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler + division by 12 */ +#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler + division by 16 */ +#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler + division by 32 */ +#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler + division by 64 */ +#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler + division by 128 */ +#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler + division by 256 */ /** * @} */ @@ -497,8 +621,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment * @{ */ -#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ /** * @} */ @@ -516,46 +642,86 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ /* ADC group regular trigger sources for all ADC instances */ -#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ -#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion + trigger software start */ +#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 TRGO. */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 TRGO2. */ +#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 2 event (capture compare). */ +#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 3 event (capture compare). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 TRGO. */ +#define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 channel 2 event (capture compare). */ +#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 channel 3 event (capture compare). */ +#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM3 TRGO. */ +#define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion + trigger from external peripheral: TIM3 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion + trigger from external peripheral: TIM3 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM4 TRGO. */ +#define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion + trigger from external peripheral: TIM4 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion + trigger from external peripheral: TIM4 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM6 TRGO. */ +#define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM7 TRGO. */ +#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM8 TRGO. */ +#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion + trigger from external peripheral: TIM8 TRGO2. */ +#define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion + trigger from external peripheral: TIM8 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM15 TRGO. */ +#define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM20 TRGO. */ +#define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion + trigger from external peripheral: TIM20 TRGO2. */ +#define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion + trigger from external peripheral: TIM20 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion + trigger from external peripheral: TIM20 channel 2 event (capture compare). */ +#define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion + trigger from external peripheral: TIM20 channel 3 event (capture compare). */ +#define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 1 event. */ +#define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 2 event. */ +#define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 3 event. */ +#define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 4 event. */ +#define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 5 event. */ +#define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 6 event. */ +#define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 7 event. */ +#define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 8 event. */ +#define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 9 event. */ +#define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion + trigger from external peripheral: HRTIMER ADC trigger 10 event. */ +#define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion + trigger from external peripheral: external interrupt line 2. */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion + trigger from external peripheral: external interrupt line 11. */ +#define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion + trigger from external peripheral: LPTIMER OUT event. */ /** * @} */ @@ -563,10 +729,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger + disabled (SW start)*/ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ /** * @} */ @@ -574,12 +744,16 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode * @{ */ -#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ -#define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. - Note: First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ -#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: - Trigger rising edge = start sampling - Trigger falling edge = stop sampling and start conversion */ +#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is + defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ +#define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts + immediately after end of conversion, and stops upon trigger event. + Note: First conversion is using minimal sampling time + (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ +#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled + by trigger events: + Trigger rising edge = start sampling + Trigger falling edge = stop sampling and start conversion */ /** * @} */ @@ -596,8 +770,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ -#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case + of overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case + of overrun: data overwritten */ /** * @} */ @@ -636,7 +812,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ -#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ +#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 + ADC clock cycles. If selected, this sampling time replaces sampling time + 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ /** * @} */ @@ -646,41 +824,61 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ /* all ADC instances (refer to Reference Manual). */ -#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ -#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ -#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ -#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ -#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ -#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ -#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ -#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ -#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ -#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ -#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ -#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ -#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ -#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ -#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ -#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ -#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ -#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ -#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ -#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ -#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ -#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ -#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ -#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ -#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ -#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ -#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ -#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ -#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ -#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ +#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ +#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ +#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ +#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal + voltage reference. On this STM32 series, ADC channel available on all + instances but ADC2. */ +#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< Internal channel Temperature sensor. + On this STM32 series, ADC channel available only on ADC1 instance. */ +#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< Internal channel Temperature sensor. + On this STM32 series, ADC channel available only on ADC5 instance. + Refer to device datasheet for ADC5 availability */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage + through a divider ladder of factor 1/3 to have channel voltage always below + Vdda. + On this STM32 series, ADC channel available on all Instances but ADC2 & ADC4. + Refer to device datasheet for ADC4 availability */ +#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< Internal channel OPAMP1 output. + On this STM32 series, ADC channel available only on ADC1 instance. */ +#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< Internal channel OPAMP2 output. + On this STM32 series, ADC channel available only on ADC2 instance. */ +#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< Internal channel OPAMP3 output. + On this STM32 series, ADC channel available only on ADC2 instance. */ +#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< Internal channel OPAMP3 output. + On this STM32 series, ADC channel available only on ADC3 instance. + Refer to device datasheet for ADC3 availability */ +#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< Internal channel OPAMP4 output. + On this STM32 series, ADC channel available only on ADC5 instance. + Refer to device datasheet for ADC5 availability */ +#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< Internal channel OPAMP5 output. + On this STM32 series, ADC channel available only on ADC5 instance. + Refer to device datasheet for ADC5 availability */ +#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< Internal channel OPAMP6 output. + On this STM32 series, ADC channel available only on ADC4 instance. + Refer to device datasheet for ADC4 availability */ /** * @} */ -/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number +/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number * @{ */ #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ @@ -690,31 +888,47 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ -/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration +/** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration * @{ */ -#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC AWD no filtering, one +out-of-window sample to raise flag or interrupt */ +#define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC AWD 2 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC AWD 3 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC AWD 5 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \ + | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 8 consecutives + out-of-window samples to raise flag or interrupt */ /** * @} */ -/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode +/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ -#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ -#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ -#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ -#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ -#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ -#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular + group single channel */ +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an + injected group single channel */ +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\ + | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular + and injected groups single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular + group all channels */ +#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected + group all channels */ +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular + and injected groups all channels */ /** * @} */ @@ -722,14 +936,18 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio * @{ */ -#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +/** + * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed + * to result as the ADC oversampling conversion data (before potential shift) + */ +#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ +#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ +#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ +#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ +#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ +#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ +#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ +#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ /** * @} */ @@ -737,15 +955,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ -#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ +/** + * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling + * conversion data) + */ +#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ /** * @} */ @@ -753,8 +975,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ -#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ -#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: + continuous mode (all conversions of OVS ratio are done from 1 trigger) */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: + discontinuous mode (each conversion of OVS ratio needs a trigger) */ /** * @} */ @@ -762,8 +986,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular * @{ */ -#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ -#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ +#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained + during injection sequence */ +#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during + injection sequence */ /** * @} */ @@ -771,16 +997,21 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_Event_type ADC Event type * @{ */ +/** + * @note Analog watchdog 1 is available on all stm32 series + * Analog watchdog 2 and 3 are not available on all series + */ #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ -#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ -#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ -#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ +#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ +#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ +#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ /** * @} */ -#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ +#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility + with other STM32 devices having only one analog watchdog */ /** @defgroup ADC_interrupts_definition ADC interrupts definition * @{ @@ -793,12 +1024,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog + watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog + watchdog) */ #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ -#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ - /** * @} */ @@ -870,7 +1101,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** * @brief Verify the length of the scheduled regular conversions group. * @param __LENGTH__ number of programmed conversions. - * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) + * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) + * or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) @@ -878,7 +1110,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** * @brief Verify the number of scheduled regular conversions in discontinuous mode. * @param NUMBER number of scheduled regular conversions in discontinuous mode. - * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) + * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) + * or RESET (NUMBER is null or too large) */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) @@ -985,7 +1218,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + ((((__HANDLE__)->Instance == ADC1) || \ + ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ @@ -994,7 +1228,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ - ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ + ((((__HANDLE__)->Instance == ADC3) || \ + ((__HANDLE__)->Instance == ADC4) || \ + ((__HANDLE__)->Instance == ADC5)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ @@ -1020,7 +1256,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + ((((__HANDLE__)->Instance == ADC1) || \ + ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ @@ -1029,7 +1266,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ - ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ + ((((__HANDLE__)->Instance == ADC3) || \ + ((__HANDLE__)->Instance == ADC4) || \ + ((__HANDLE__)->Instance == ADC5)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ @@ -1050,7 +1289,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + ((((__HANDLE__)->Instance == ADC1) || \ + ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ @@ -1101,7 +1341,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + ((((__HANDLE__)->Instance == ADC1) || \ + ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ @@ -1118,7 +1359,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#endif +#endif /* STM32G4xx */ /** * @brief Verify the ADC regular conversions external trigger. @@ -1400,9 +1641,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 */ #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ @@ -1454,9 +1698,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) + * to convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). @@ -1520,10 +1767,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel + * connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ @@ -1581,9 +1832,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 @@ -1642,7 +1896,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ @@ -1764,6 +2019,30 @@ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ (__ADC_DATA__),\ (__ADC_RESOLUTION__)) +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) + * in differential ended mode. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) + /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage @@ -1875,11 +2154,15 @@ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). - * On STM32G4, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). - * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + (unit: uV/DegCelsius). + * On STM32G4, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at + temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32G4, refer to device datasheet parameter "V30" + (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see + parameter above) is corresponding (unit: mV) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. @@ -1960,7 +2243,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC sampling control */ HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); @@ -1981,8 +2264,9 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, + const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); /** * @} @@ -1992,8 +2276,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} @@ -2003,7 +2287,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); * @} */ -/* Private functions -----------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ /** @addtogroup ADC_Private_Functions ADC Private Functions * @{ */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h index b32f2ca089..7acf6e663c 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h @@ -55,132 +55,205 @@ typedef struct /** * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected * @note Parameters of this structure are shared within 2 scopes: - * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation - * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, - * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. + * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, + * InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation + * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, + * InjectedDiscontinuousConvMode, + * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, + * InjecOversamplingMode, InjecOversampling. * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. * ADC state can be either: - * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') - * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. - * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. - * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going + * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter + * 'InjectedSingleDiff') + * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled + * without conversion on going on injected group. + * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', + * 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and + * injected groups. + * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', + * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going * on ADC groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL - Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ + Note: Depending on devices and ADC instances, some channels may not be + available on device package pins. Refer to device datasheet for + channels availability. */ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. - Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by - the new channel setting (or parameter number of conversions adjusted) */ + Note: to disable a channel or change order of conversion sequencer, + rank containing a previous channel setting can be overwritten by + the new channel setting (or parameter number of conversions + adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time - (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. - Caution: This parameter applies to a channel that can be used in a regular and/or injected group. - It overwrites the last setting. - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values. */ + Caution: This parameter applies to a channel that can be used in a + regular and/or injected group. It overwrites the last setting. + Note: In case of usage of internal measurement channels (VrefInt, ...), + sampling time constraints must be respected (sampling time can be + adjusted in function of ADC clock frequency and sampling time + setting). Refer to device datasheet for timings values. */ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. - In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). - Only channel 'i' has to be configured, channel 'i+1' is configured automatically. - This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. - Caution: This parameter applies to a channel that can be used in a regular and/or injected group. - It overwrites the last setting. - Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. - Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case - of another parameter update on the fly) */ + In differential mode: Differential measurement is between the selected + channel 'i' (positive input) and channel 'i+1' (negative input). + Only channel 'i' has to be configured, channel 'i+1' is configured + automatically. + This parameter must be a value of + @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. + Caution: This parameter applies to a channel that can be used in a + regular and/or injected group. It overwrites the last setting. + Note: Refer to Reference Manual to ensure the selected channel is + available in differential mode. + Note: When configuring a channel 'i' in differential mode, the channel + 'i+1' is not usable separately. + Note: This parameter must be modified when ADC is disabled (before ADC + start conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error + reporting (as it can be the expected behavior in case of another + parameter update on the fly) */ uint32_t InjectedOffsetNumber; /*!< Selects the offset number. This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. - Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ + Caution: Only one offset is allowed per channel. This parameter + overwrites the last setting. */ uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data. Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number - between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled - without continuous mode or external trigger that could launch a conversion). */ - - uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. - This parameter can be a value of @ref ADCEx_OffsetSign. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this + parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, + 0x3FF, 0xFF or 0x3F respectively. + Note: This parameter must be modified when no conversion is on going + on both regular and injected groups (ADC disabled, or ADC enabled + without continuous mode or external trigger that could launch a + conversion). */ + + uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added + (positive sign) from or to the raw converted data. + This parameter can be a value of @ref ADCEx_OffsetSign. + Note: This parameter must be modified when no conversion is on going + on both regular and injected groups (ADC disabled, or ADC + enabled without continuous mode or external trigger that could + launch a conversion). */ FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. This parameter value can be ENABLE or DISABLE. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - - uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. - To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + Note: This parameter must be modified when no conversion is on going + on both regular and injected groups (ADC disabled, or ADC enabled + without continuous mode or external trigger that could launch a + conversion). */ + + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group + injected sequencer. + To use the injected group sequencer and convert several ranks, parameter + 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on + injected group can impact the configuration of other channels previously + set. */ - FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected + is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode is used only if sequencer is enabled (parameter + 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - - FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one + Note: This parameter must be modified when ADC is disabled (before ADC + start conversion or after ADC stop conversion). + Note: For injected group, discontinuous mode converts the sequence + channel by channel (discontinuous length fixed to 1 rank). + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the + configuration of other channels previously set. */ + + FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion + after regular one This parameter can be set to ENABLE or DISABLE. - Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) - Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) - Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. - To maintain JAUTO always enabled, DMA must be configured in circular mode. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ + Note: To use Automatic injected conversion, discontinuous mode must + be disabled ('DiscontinuousConvMode' and + 'InjectedDiscontinuousConvMode' set to DISABLE) + Note: To use Automatic injected conversion, injected group external + triggers must be disabled ('ExternalTrigInjecConv' set to + ADC_INJECTED_SOFTWARE_START) + Note: In case of DMA used with regular group: if DMA configured in + normal mode (single shot) JAUTO will be stopped upon DMA transfer + complete. + To maintain JAUTO always enabled, DMA must be configured in + circular mode. + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to configure a channel + on injected group can impact the configuration of other channels + previously set. */ FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. - If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a - new injected context is set when queue is full, error is triggered by interruption and through function + If context queue is enabled, injected sequencer&channels configurations + are queued on up to 2 contexts. If a + new injected context is set when queue is full, error is triggered by + interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. - Caution: This feature request that the sequence is fully configured before injected conversion start. - Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ - - uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. - If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. - This parameter can be a value of @ref ADC_injected_external_trigger_source. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ + Caution: This feature request that the sequence is fully configured + before injected conversion start. + Therefore, configure channels with as many calls to + HAL_ADCEx_InjectedConfigChannel() as the + 'InjectedNbrOfConversion' parameter. + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the + configuration of other channels previously set. + Note: This parameter must be modified when ADC is disabled (before ADC + start conversion or after ADC stop conversion). */ + + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of + injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled + and software trigger is used instead. + This parameter can be a value of + @ref ADC_injected_external_trigger_source. + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to configure a channel + on injected group can impact the configuration of other channels + previously set. */ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. This parameter can be a value of @ref ADC_injected_external_trigger_edge. - If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ + If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter + is discarded. + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the + configuration of other channels previously set. */ FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ + Note: This parameter can be modified only if there is no + conversion is ongoing (both ADSTART and JADSTART cleared). */ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ + Caution: this setting overwrites the previous oversampling + configuration if oversampling already enabled. + Note: This parameter can be modified only if there is no + conversion is ongoing (both ADSTART and JADSTART cleared).*/ } ADC_InjectionConfTypeDef; #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Structure definition of ADC multimode - * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). + * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state + * (both Master and Slave ADCs). * Both Master and Slave ADCs must be disabled. */ typedef struct @@ -189,7 +262,8 @@ typedef struct This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: - selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) + selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel + (one DMA channel for both ADC, DMA of ADC master). This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. @@ -214,45 +288,84 @@ typedef struct * @{ */ /* ADC group regular trigger sources for all ADC instances */ -#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ +#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion + trigger software start */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM1 TRGO. */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion + trigger from external peripheral: TIM1 TRGO2. */ +#define ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion + trigger from external peripheral: TIM1 channel 3 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion + trigger from external peripheral: TIM1 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM2 TRGO. */ +#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion + trigger from external peripheral: TIM2 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM3 TRGO. */ +#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion + trigger from external peripheral: TIM3 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion + trigger from external peripheral: TIM3 channel 3 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion + trigger from external peripheral: TIM3 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM4 TRGO. */ +#define ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion + trigger from external peripheral: TIM4 channel 3 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion + trigger from external peripheral: TIM4 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM6 TRGO. */ +#define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM7 TRGO. */ +#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM8 TRGO. */ +#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion + trigger from external peripheral: TIM8 TRGO2. */ +#define ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion + trigger from external peripheral: TIM8 channel 2 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion + trigger from external peripheral: TIM8 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM15 TRGO. */ +#define ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion + trigger from external peripheral: TIM8 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM20 TRGO. */ +#define ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion + trigger from external peripheral: TIM20 TRGO2. */ +#define ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion + trigger from external peripheral: TIM20 channel 2 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion + trigger from external peripheral: TIM20 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 1 event. */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 2 event. */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 3 event. */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 4 event. */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 5 event. */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 6 event. */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 7 event. */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 8 event. */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 9 event. */ +#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion + trigger from external peripheral: HRTIMER ADC trigger 10 event. */ +#define ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion + trigger from external peripheral: external interrupt line 3. */ +#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion + trigger from external peripheral: external interrupt line 15. */ +#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion + trigger from external peripheral: LPTIMER OUT event. */ /** * @} */ @@ -260,10 +373,14 @@ typedef struct /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger + disabled (SW start)*/ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger + polarity set to rising edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger + polarity set to falling edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger + polarity set to both rising and falling edges */ /** * @} */ @@ -271,8 +388,8 @@ typedef struct /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ -#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ -#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ +#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */ +#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */ /** * @} */ @@ -280,11 +397,20 @@ typedef struct /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number * @{ */ -#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ -#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ +#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected + ADC channel */ +#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ /** * @} */ @@ -292,7 +418,7 @@ typedef struct /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign * @{ */ -#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ +#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ #define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ /** * @} @@ -313,21 +439,33 @@ typedef struct /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode * @{ */ -#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ -#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ -#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ -#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ -#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ -#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ -#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ -#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ +#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled + (ADC independent mode) */ +#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular + simultaneous */ +#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined + group regular interleaved */ +#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group + injected simultaneous */ +#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group + injected alternate trigger. Works only with external triggers (not internal + SW start) */ +#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined + group regular simultaneous + group injected simultaneous */ +#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined + group regular simultaneous + group injected alternate trigger */ +#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined + group regular interleaved + group injected simultaneous */ /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution * @{ */ -#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ -#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ -#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ +#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own + DMA channel */ +#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, + DMA of ADC master) for 12 and 10 bits resolution */ +#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, + DMA of ADC master) for 8 and 6 bits resolution */ /** * @} */ @@ -335,18 +473,30 @@ typedef struct /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ -#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two + sampling phases: 1 ADC clock cycle */ +#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two + sampling phases: 2 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two + sampling phases: 3 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two + sampling phases: 4 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two + sampling phases: 5 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two + sampling phases: 6 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two + sampling phases: 7 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two + sampling phases: 8 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two + sampling phases: 9 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two + sampling phases: 10 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two + sampling phases: 11 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two + sampling phases: 12 ADC clock cycles */ /** * @} */ @@ -359,9 +509,11 @@ typedef struct /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups * @{ */ -#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ -#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ -#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ +#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on + all STM32 devices) */ +#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on + all STM32 devices) */ +#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ /** * @} */ @@ -489,36 +641,41 @@ typedef struct * @param __RANKNB__ Rank number. * @retval None */ -#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ - & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) +#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \ + ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \ + << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) /** * @brief Configure ADC injected context queue * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. * @retval None */ -#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) +#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \ + ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) /** * @brief Configure ADC discontinuous conversion mode for injected group * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. * @retval None */ -#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) +#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \ + ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) /** * @brief Configure ADC discontinuous conversion mode for regular group * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. * @retval None */ -#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) +#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \ + ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) /** * @brief Configure the number of discontinuous conversions for regular group. * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. * @retval None */ -#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) +#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \ + (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) /** * @brief Configure the ADC auto delay mode. @@ -620,7 +777,8 @@ typedef struct * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. * @param __HANDLE_SLAVE__ ADC slave handle. - * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. + * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is + * set to NULL. * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ @@ -637,7 +795,8 @@ typedef struct * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. * @param __HANDLE_SLAVE__ ADC slave handle. - * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. + * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set + * to NULL. * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ @@ -646,7 +805,7 @@ typedef struct : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) -#endif +#endif /* STM32G4xx */ /** @@ -655,7 +814,8 @@ typedef struct * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) +#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \ + ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ @@ -666,12 +826,13 @@ typedef struct * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) +#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \ + ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) -#endif +#endif /* STM32G4xx */ /** * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. @@ -683,7 +844,8 @@ typedef struct /** * @brief Verify the length of scheduled injected conversions group. * @param __LENGTH__ number of programmed conversions. - * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) + * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) + * or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) @@ -702,7 +864,8 @@ typedef struct * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ + ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ @@ -754,7 +917,8 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) #elif defined(STM32G471xx) -#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ + ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ @@ -784,7 +948,8 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) -#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ + ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ @@ -809,7 +974,8 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))) #elif defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ + ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ @@ -919,7 +1085,7 @@ typedef struct ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13))) ) -#endif +#endif /* STM32G4xx */ /** * @brief Verify the ADC single-ended input or differential mode setting. @@ -988,7 +1154,8 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + ((((__HANDLE__)->Instance == ADC1) || \ + ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ @@ -996,7 +1163,9 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ - ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ + ((((__HANDLE__)->Instance == ADC3) || \ + ((__HANDLE__)->Instance == ADC4) || \ + ((__HANDLE__)->Instance == ADC5)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ @@ -1022,7 +1191,8 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + ((((__HANDLE__)->Instance == ADC1) || \ + ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ @@ -1030,7 +1200,9 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ - ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ + ((((__HANDLE__)->Instance == ADC3) || \ + ((__HANDLE__)->Instance == ADC4) || \ + ((__HANDLE__)->Instance == ADC5)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ @@ -1052,7 +1224,8 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + ((((__HANDLE__)->Instance == ADC1) || \ + ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ @@ -1103,7 +1276,8 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + ((((__HANDLE__)->Instance == ADC1) || \ + ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ @@ -1119,7 +1293,7 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#endif +#endif /* STM32G4xx */ /** * @brief Verify the ADC edge trigger setting for injected group. @@ -1188,27 +1362,28 @@ typedef struct * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) */ -#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) +#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) /** * @brief Verify the ADC analog watchdog filtering setting. * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) */ -#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) +#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \ + (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) /** @@ -1314,7 +1489,7 @@ typedef struct /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); @@ -1331,11 +1506,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); #endif /* ADC_MULTIMODE_SUPPORT */ /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); @@ -1345,11 +1520,11 @@ void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *h void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); /* ADC group regular conversions stop */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); #if defined(ADC_MULTIMODE_SUPPORT) -HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); #endif /* ADC_MULTIMODE_SUPPORT */ /** @@ -1361,10 +1536,12 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, - ADC_InjectionConfTypeDef *sConfigInjected); + const ADC_InjectionConfTypeDef *pConfigInjected); #if defined(ADC_MULTIMODE_SUPPORT) -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, + const ADC_MultiModeTypeDef *pMultimode); #endif /* ADC_MULTIMODE_SUPPORT */ + HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h index f7e724c9d2..f575d605e3 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h @@ -164,7 +164,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */ #define COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */ #define COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */ -#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */ +#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */ #define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */ /** * @} @@ -307,14 +307,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Disable the specified comparator. * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Lock the specified comparator configuration. @@ -325,14 +325,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) +#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) /** * @brief Check whether the specified comparator is locked. * @param __HANDLE__ COMP handle * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked */ -#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) +#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) /** * @} @@ -341,7 +341,6 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_Exti_Management COMP external interrupt line management * @{ */ - /** * @brief Enable the COMP1 EXTI line rising edge trigger. * @retval None @@ -370,19 +369,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - } while(0) +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ + } while(0) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - } while(0) +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ + } while(0) /** * @brief Enable the COMP1 EXTI line in interrupt mode. @@ -454,19 +453,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - } while(0) +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - } while(0) + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + } while(0) /** * @brief Enable the COMP2 EXTI line in interrupt mode. @@ -539,18 +538,18 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @retval None */ #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - } while(0) + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + } while(0) /** * @brief Disable the COMP3 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - } while(0) + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + } while(0) /** * @brief Enable the COMP3 EXTI line in interrupt mode. @@ -623,18 +622,18 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @retval None */ #define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \ - } while(0) + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \ + } while(0) /** * @brief Disable the COMP4 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \ - } while(0) + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \ + } while(0) /** * @brief Enable the COMP4 EXTI line in interrupt mode. @@ -708,18 +707,18 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @retval None */ #define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \ - } while(0) + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \ + } while(0) /** * @brief Disable the COMP5 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \ - } while(0) + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \ + } while(0) /** * @brief Enable the COMP5 EXTI line in interrupt mode. @@ -794,18 +793,18 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @retval None */ #define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \ - LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \ - } while(0) + LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \ + LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \ + } while(0) /** * @brief Disable the COMP6 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \ - LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \ - } while(0) + LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \ + LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \ + } while(0) /** * @brief Enable the COMP6 EXTI line in interrupt mode. @@ -880,18 +879,18 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @retval None */ #define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \ - LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \ - } while(0) + LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \ + LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \ + } while(0) /** * @brief Disable the COMP7 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \ - LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \ - } while(0) + LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \ + LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \ + } while(0) /** * @brief Enable the COMP7 EXTI line in interrupt mode. @@ -1020,62 +1019,62 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)) #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\ (((__COMP_INSTANCE__) == COMP1) && \ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP2) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ ) || \ (((__COMP_INSTANCE__) == COMP3) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP4) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ ) || \ (((__COMP_INSTANCE__) == COMP5) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP6) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2)) \ ) || \ (((__COMP_INSTANCE__) == COMP7) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \ )) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\ (((__COMP_INSTANCE__) == COMP1) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP2) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ ) || \ (((__COMP_INSTANCE__) == COMP3) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP4) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ )) #endif @@ -1100,157 +1099,157 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Macro kept for compatibility with other STM32 series */ #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ ) #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ + ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ + || \ + (((__INSTANCE__) == COMP2) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ - || \ - (((__INSTANCE__) == COMP3) && \ + || \ + (((__INSTANCE__) == COMP3) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ - || \ - (((__INSTANCE__) == COMP4) && \ + || \ + (((__INSTANCE__) == COMP4) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ - || \ - (((__INSTANCE__) == COMP5) && \ + || \ + (((__INSTANCE__) == COMP5) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5))) \ - || \ - (((__INSTANCE__) == COMP6) && \ + || \ + (((__INSTANCE__) == COMP6) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6))) \ - || \ - (((__INSTANCE__) == COMP7) && \ + || \ + (((__INSTANCE__) == COMP7) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7))) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ - ) + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ + ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ + || \ + (((__INSTANCE__) == COMP2) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ - || \ - (((__INSTANCE__) == COMP3) && \ + || \ + (((__INSTANCE__) == COMP3) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ - || \ - (((__INSTANCE__) == COMP4) && \ + || \ + (((__INSTANCE__) == COMP4) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ - ) + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ + ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ + || \ + (((__INSTANCE__) == COMP2) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ - || \ - (((__INSTANCE__) == COMP3) && \ + || \ + (((__INSTANCE__) == COMP3) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ - || \ - (((__INSTANCE__) == COMP4) && \ + || \ + (((__INSTANCE__) == COMP4) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ - ) + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + ) #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ @@ -1314,7 +1313,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp); /* Callback in interrupt mode */ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @@ -1325,8 +1324,8 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @addtogroup COMP_Exported_Functions_Group4 * @{ */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h index f71c735e34..2f06845385 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h @@ -64,7 +64,7 @@ typedef struct { CORDIC_TypeDef *Instance; /*!< Register base address */ - int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */ + const int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */ int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */ @@ -546,14 +546,14 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig); -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig); +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc); -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection); /** * @} @@ -582,8 +582,8 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); * @{ */ /* Peripheral State functions *************************************************/ -HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic); -uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic); +HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); +uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h index 307c6cbeac..a452e1f72e 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h @@ -318,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp.h index b4da993c6e..106f617339 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp.h @@ -53,7 +53,8 @@ typedef struct uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of @ref CRYP_Data_Type */ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. - 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */ + 128 or 256 bit key length in TinyAES + This parameter can be a value of @ref CRYP_Key_Size */ uint32_t *pKey; /*!< The key used for encryption/decryption */ uint32_t *pInitVect; /*!< The initialization vector used also as initialization counter in CTR mode */ @@ -96,7 +97,7 @@ typedef enum { HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */ HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */ -}HAL_SuspendTypeDef; +} HAL_SuspendTypeDef; #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ /** @@ -407,7 +408,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @arg CRYP_FLAG_OFNE: Output FIFO is not empty * @arg CRYP_FLAG_OFFU: Output FIFO is full * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define CRYP_FLAG_MASK 0x0000001FU @@ -434,7 +435,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @retval State of interruption (TRUE or FALSE). */ -#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR &\ + (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Check whether the specified CRYP interrupt is set or not. * @param __HANDLE__ specifies the CRYP handle. @@ -503,7 +505,8 @@ void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) @@ -520,8 +523,10 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp); */ /* encryption/decryption ***********************************/ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); @@ -579,11 +584,11 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) #define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \ - (((((ALGO) == CRYP_AES_CTR)) && \ - ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ - (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ - (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ - ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) + (((((ALGO) == CRYP_AES_CTR)) && \ + ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ + (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ + (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ + ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp_ex.h index 22928545a8..b2e7630dfb 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp_ex.h @@ -73,8 +73,8 @@ extern "C" { */ /** - * @} - */ + * @} + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h index 1548104766..a331446b98 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h @@ -78,19 +78,19 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; @@ -143,7 +143,7 @@ typedef struct uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ - uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . + uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral. This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode @@ -349,6 +349,20 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @} */ +/* Delay for DAC channel voltage settling time from DAC channel startup */ +/* (transition from disable to enable). */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm (min), 50pF (max) */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tWAKEUP"). */ +/* Unit: us */ +#define DAC_DELAY_STARTUP_US (15UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup DAC_Exported_Macros DAC Exported Macros @@ -496,7 +510,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define IS_DAC_CHANNEL(DACX, CHANNEL) \ (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2)) -#endif +#endif /* STM32G474xx || STM32G484xx || STM32G473xx */ #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ @@ -538,7 +552,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); @@ -564,8 +578,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA * @{ */ /* Peripheral Control functions ***********************************************/ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ @@ -574,8 +589,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); /** * @} @@ -611,4 +626,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #endif /* STM32G4xx_HAL_DAC_H */ - diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h index 3ef83610ef..d042af1a6f 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h @@ -90,6 +90,7 @@ extern "C" { /** * @} */ + /** * @} */ @@ -152,7 +153,7 @@ extern "C" { : ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) -#endif +#endif /* STM32G474xx || STM32G484xx */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_DAC_TRIGGER2(DACX, TRIGGER) \ @@ -200,7 +201,7 @@ extern "C" { :((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) -#endif +#endif /* STM32G474xx || STM32G484xx */ #define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \ @@ -279,11 +280,11 @@ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); -HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, - uint32_t Alignment); +HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, + const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); @@ -303,7 +304,7 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); -uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); +uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel); /** * @} @@ -342,4 +343,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); #endif #endif /* STM32G4xx_HAL_DAC_EX_H */ - diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h index caadf5d6db..dcb73f6779 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h @@ -65,7 +65,9 @@ typedef enum (__DMA_HANDLE__).Parent = (__HANDLE__); \ } while(0) -#define UNUSED(X) (void)X +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h index 9adf47fd1f..e956f7f693 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h @@ -230,12 +230,15 @@ typedef struct uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. This parameter must be a number between: - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID - - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */ + - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID + When the frame is a Non-Filter matching frame, this parameter + is unused. */ uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. - Acceptance of non-matching frames may be enabled via - HAL_FDCAN_ConfigGlobalFilter(). - This parameter can be 0 or 1 */ + Acceptance of non-matching frames may be enabled via + HAL_FDCAN_ConfigGlobalFilter(). + This parameter takes 0 if the frame matched an Rx filter or + 1 if it did not match any Rx filter */ } FDCAN_RxHeaderTypeDef; @@ -315,53 +318,55 @@ typedef struct typedef struct { uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. - This parameter can be a value of @ref FDCAN_protocol_error_code */ + This parameter can be a value of @ref FDCAN_protocol_error_code */ uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. - This parameter can be a value of @ref FDCAN_protocol_error_code */ + This parameter can be a value of @ref FDCAN_protocol_error_code */ uint32_t Activity; /*!< Specifies the FDCAN module communication state. - This parameter can be a value of @ref FDCAN_communication_state */ + This parameter can be a value of @ref FDCAN_communication_state */ uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. This parameter can be: - 0 : The FDCAN is in Error_Active state - - 1 : The FDCAN is in Error_Passive state */ + - 1 : The FDCAN is in Error_Passive state */ uint32_t Warning; /*!< Specifies the FDCAN module warning status. This parameter can be: - - 0 : error counters (RxErrorCnt and TxErrorCnt) - are below the Error_Warning limit of 96 - - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ + - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the + Error_Warning limit of 96 + - 1 : at least one of error counters has reached the Error_Warning + limit of 96 */ uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. This parameter can be: - 0 : The FDCAN is not in Bus_Off state - - 1 : The FDCAN is in Bus_Off state */ + - 1 : The FDCAN is in Bus_Off state */ uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. This parameter can be: - 0 : Last received CAN FD message did not have its ESI flag set - - 1 : Last received CAN FD message had its ESI flag set */ + - 1 : Last received CAN FD message had its ESI flag set */ uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. This parameter can be: - 0 : Last received CAN FD message did not have its BRS flag set - - 1 : Last received CAN FD message had its BRS flag set */ + - 1 : Last received CAN FD message had its BRS flag set */ uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received - since last protocol status.This parameter can be: + since last protocol status. + This parameter can be: - 0 : No CAN FD message received - - 1 : CAN FD message received */ + - 1 : CAN FD message received */ uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. This parameter can be: - 0 : No protocol exception event occurred since last read access - - 1 : Protocol exception event occurred */ + - 1 : Protocol exception event occurred */ uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. - This parameter can be a number between 0 and 127 */ + This parameter can be a number between 0 and 127 */ } FDCAN_ProtocolStatusTypeDef; @@ -371,22 +376,24 @@ typedef struct typedef struct { uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. - This parameter can be a number between 0 and 255 */ + This parameter can be a number between 0 and 255 */ uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. - This parameter can be a number between 0 and 127 */ + This parameter can be a number between 0 and 127 */ uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. This parameter can be: - - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 - - 1 : The Receive Error Counter (RxErrorCnt) - has reached the error passive level of 128 */ + - 0 : The Receive Error Counter (RxErrorCnt) is below the error + passive level of 128 + - 1 : The Receive Error Counter (RxErrorCnt) has reached the error + passive level of 128 */ uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. This parameter can be a number between 0 and 255. - This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt - or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of - TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ + This counter is incremented each time when a FDCAN protocol error causes + the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; + the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag + FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ } FDCAN_ErrorCountersTypeDef; @@ -601,21 +608,21 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, * @{ */ #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ -#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ -#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ -#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ -#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ -#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ -#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ -#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ -#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ -#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ -#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ -#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ -#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ -#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ -#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ -#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ +#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */ /** * @} */ @@ -1037,7 +1044,7 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, * @retval None */ #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 -#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ @@ -1164,7 +1171,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h * @{ */ /* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig); HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt); @@ -1174,13 +1181,13 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint3 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); -uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod); HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); -uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter); @@ -1200,21 +1207,23 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); /* Control functions **********************************************************/ HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, - uint8_t *pTxData); -uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData); +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); -HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus); -HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); -HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); -uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); -uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); -uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); -uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus); +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters); +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); /** * @} @@ -1256,8 +1265,8 @@ void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorSt * @{ */ /* Peripheral State functions *************************************************/ -uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); -HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan); +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan); /** * @} */ @@ -1406,6 +1415,10 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) + +#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h index f65e444e27..6da587a788 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h @@ -873,7 +873,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) -#define FLASH_PAGE_NB 128U +#define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 128U : \ + ((FLASH_SIZE == 0x00040000U) ? 64U : 32U)) #define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */ #else #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h index 1f06c35be5..ca8926986d 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h @@ -69,10 +69,12 @@ typedef struct uint32_t FilterParam; /*!< Filter configuration (operation and parameters). Set to 0 if no valid configuration was applied. */ - uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None. + uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None. + uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ int16_t *pInput; /*!< Pointer to FMAC input data buffer */ @@ -95,7 +97,8 @@ typedef struct DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */ - DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters */ + DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle + parameters */ #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */ @@ -164,37 +167,39 @@ typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer */ typedef struct { - uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF). - Ignored if InputBufferSize is set to 0 + uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory + (0x00 to 0xFF). Ignored if InputBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ - uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom"). + uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer + (including the optional "headroom"). 0 if a previous configuration should be kept. */ - uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces - in the buffer is lower than this threshold. + uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number + of free spaces in the buffer is lower than this threshold. This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ - uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF). - Ignored if CoeffBufferSize is set to 0 + uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal + memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer. 0 if a previous configuration should be kept. */ - uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF). - Ignored if OuputBufferSize is set to 0 + uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal + memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ - uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom"). + uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer + (including the optional "headroom"). 0 if a previous configuration should be kept. */ - uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values - in the buffer is lower than this threshold. + uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number + of unread values in the buffer is lower than this threshold. This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ @@ -209,14 +214,16 @@ typedef struct uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */ - uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None. + uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None. + uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping - is done when the clipping feature is disabled + uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range + is exceeded, wrapping is done when the clipping feature is disabled and saturation is done when the clipping feature is enabled. This parameter can be a value of @ref FMAC_Clip_State. */ @@ -266,11 +273,11 @@ typedef struct /** @defgroup FMAC_Functions FMAC Functions * @{ */ -#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ -#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ -#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ -#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ -#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ +#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ /** * @} */ @@ -279,18 +286,22 @@ typedef struct * @{ * @note This parameter sets a watermark for buffer full (input) or buffer empty (output). */ -#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 1. */ -#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 2. */ -#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 4. */ -#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 8. */ +#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 1. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 1. */ +#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 2. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 2. */ +#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 4. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 4. */ +#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 8. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 8. */ #define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */ /** * @} @@ -323,7 +334,8 @@ typedef struct #define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ #define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ #define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ -#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */ +#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag + (this helps in debugging a filter) */ /** * @} */ @@ -335,7 +347,8 @@ typedef struct #define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ #define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ #define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ -#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */ +#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable + (this helps in debugging a filter) */ /** * @} */ @@ -345,8 +358,8 @@ typedef struct */ -/* External variables --------------------------------------------------------*/ -/** @defgroup FMAC_External_variables FMAC External variables +/* Exported variables --------------------------------------------------------*/ +/** @defgroup FMAC_Exported_variables FMAC Exported variables * @{ */ /** @@ -358,7 +371,8 @@ typedef struct * @{ */ -/** @brief Reset FMAC handle state. +/** + * @brief Reset FMAC handle state. * @param __HANDLE__ FMAC handle. * @retval None */ @@ -402,7 +416,8 @@ typedef struct #define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) -/** @brief Check whether the specified FMAC interrupt occurred or not. +/** + * @brief Check whether the specified FMAC interrupt occurred or not. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to check. * This parameter can be any combination of the following values: @@ -416,7 +431,8 @@ typedef struct #define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__)) -/** @brief Clear specified FMAC interrupt status. Dummy macro as the +/** + * @brief Clear specified FMAC interrupt status. Dummy macro as the interrupt status flags are read-only. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to clear. @@ -424,7 +440,8 @@ typedef struct */ #define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */ -/** @brief Check whether the specified FMAC status flag is set or not. +/** + * @brief Check whether the specified FMAC status flag is set or not. * @param __HANDLE__ FMAC handle. * @param __FLAG__ FMAC flag to check. * This parameter can be any combination of the following values: @@ -438,7 +455,8 @@ typedef struct #define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) -/** @brief Clear specified FMAC status flag. Dummy macro as no +/** + * @brief Clear specified FMAC status flag. Dummy macro as no flag can be cleared. * @param __HANDLE__ FMAC handle. * @param __FLAG__ FMAC flag to clear. @@ -446,7 +464,8 @@ typedef struct */ #define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */ -/** @brief Check whether the specified FMAC interrupt is enabled or not. +/** + * @brief Check whether the specified FMAC interrupt is enabled or not. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to check. * This parameter can be one of the following values: @@ -460,6 +479,22 @@ typedef struct #define __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup FMAC_Private_Constants + * @{ + */ + +#define FMAC_PARAM_P_MAX_IIR 64U /*!< Maximum value of P parameter with IIR */ +#define FMAC_PARAM_P_MAX_FIR 127U /*!< Maximum value of P parameter with FIR */ +#define FMAC_PARAM_P_MIN 2U /*!< Minimum value of P parameter */ +#define FMAC_PARAM_Q_MAX 63U /*!< Maximum value of Q parameter */ +#define FMAC_PARAM_Q_MIN 1U /*!< Minimum value of Q parameter */ +#define FMAC_PARAM_R_MAX 7U /*!< Maximum value of R parameter */ + /** * @} */ @@ -530,10 +565,12 @@ typedef struct * @param __FUNCTION__ ID of the filter function. * @retval SET (__P__ is a valid value) or RESET (__P__ is invalid) */ -#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \ - (((__P__) >= 2U) && ((__P__) <= 127U))) || \ - (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ - (((__P__) >= 2U) && ((__P__) <= 64U))) ) +#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \ + (((__P__) >= FMAC_PARAM_P_MIN) && \ + ((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__P__) >= FMAC_PARAM_P_MIN) && \ + ((__P__) <= FMAC_PARAM_P_MAX_IIR)))) /** * @brief Verify the FMAC filter parameter Q. @@ -543,7 +580,7 @@ typedef struct */ #define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ - (((__Q__) >= 1U) && ((__Q__) <= 63U))) ) + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) /** * @brief Verify the FMAC filter parameter R. @@ -553,7 +590,7 @@ typedef struct */ #define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \ - ((__R__) <= 7U)) + ((__R__) <= FMAC_PARAM_R_MAX)) /** * @brief Verify the FMAC buffer access. @@ -663,8 +700,8 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac); * @{ */ /* Peripheral State functions *************************************************/ -HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac); -uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac); +HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac); +uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h index 8573edec7f..8210cdbee3 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h @@ -4629,7 +4629,7 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, uint32_t CalibrationRate); @@ -4681,7 +4681,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel, - HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); + const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -4721,7 +4721,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, - HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); + const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -4761,7 +4761,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, - HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); + const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -4801,7 +4801,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel, - HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); + const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -4827,29 +4827,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, * @{ */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, - HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); + const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - HRTIM_EventCfgTypeDef* pEventCfg); + const HRTIM_EventCfgTypeDef* pEventCfg); HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - HRTIM_FaultCfgTypeDef* pFaultCfg); + const HRTIM_FaultCfgTypeDef* pFaultCfg); HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim, uint32_t Fault, - HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg); + const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg); HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Fault, - HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg); + const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg); HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim, uint32_t Fault); @@ -4862,7 +4862,7 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); + const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t ADCTrigger, @@ -4887,30 +4887,30 @@ HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim, /* Waveform related functions *************************************************/ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef * pTimerCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCtlTypeDef * pTimerCtl); + const HRTIM_TimerCtlTypeDef * pTimerCtl); HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCtlTypeDef * pTimerCtl); + const HRTIM_TimerCtlTypeDef * pTimerCtl); HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - HRTIM_CompareCfgTypeDef* pCompareCfg); + const HRTIM_CompareCfgTypeDef* pCompareCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - HRTIM_CaptureCfgTypeDef* pCaptureCfg); + const HRTIM_CaptureCfgTypeDef* pCaptureCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef * pOutputCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -4920,12 +4920,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); + const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t EventCounter, - HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg); + const HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg); HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, @@ -4941,11 +4941,11 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); + const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); + const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -5010,38 +5010,38 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, * @{ */ /* HRTIM peripheral state functions */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim); +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim); -uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); -uint32_t HAL_HRTIM_GetCapturedDir(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); -HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(HRTIM_HandleTypeDef * hhrtim, +HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); -uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim, +uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim); +uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim); -uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim, +uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); -uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim, +uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /** diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h index 6f3b71329a..0a0781d2f6 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h @@ -118,8 +118,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; @@ -207,6 +205,7 @@ typedef struct __I2C_HandleTypeDef DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + HAL_LockTypeDef Lock; /*!< I2C locking object */ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ @@ -217,6 +216,10 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ @@ -705,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); * @{ */ /* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); /** * @} @@ -800,8 +803,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ - (~I2C_CR2_RD_WRN))) + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) #define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda.h index 87d2b3250b..1f6e721772 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda.h @@ -865,8 +865,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); */ /* Peripheral State and Error functions ***************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h index 187b351bea..6ceca1a251 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h @@ -448,6 +448,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value + * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF. * @retval None * @note The ARR register can only be modified when the LPTIM instance is enabled. */ @@ -659,9 +660,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); * @{ */ /* Reading operation functions ************************************************/ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -697,7 +698,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ * @{ */ /* Peripheral State functions ************************************************/ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -809,11 +810,10 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL) - #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) -#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL) +#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ + ((__PERIOD__) <= 0x0000FFFFUL)) #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) @@ -825,7 +825,15 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP5) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP7)))) +#else +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3)))) +#endif /* COMP5 && COMP6 && COMP7 */ +#if defined(COMP5) && defined(COMP6) && defined(COMP7) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ (((__INSTANCE__) == LPTIM1) && \ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ @@ -833,12 +841,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4) || \ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP6))) #else -#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ - ((((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3)))) - #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ (((__INSTANCE__) == LPTIM1) && \ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nand.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nand.h index 32c048f447..6206a559eb 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nand.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nand.h @@ -105,9 +105,8 @@ typedef struct FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This parameter is mandatory for some NAND parts after the read command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. - Example: Toshiba THTH58BYG3S0HBAI6. This parameter could be ENABLE or DISABLE - Please check the Read Mode sequnece in the NAND device datasheet */ + Please check the Read Mode sequence in the NAND device datasheet */ } NAND_DeviceConfigTypeDef; /** @@ -127,7 +126,7 @@ typedef struct __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ - NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ + NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ @@ -215,27 +214,27 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ @@ -265,8 +264,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, * @{ */ /* NAND State functions *******************************************************/ -HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand); +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nor.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nor.h index 960ebef87e..885a52ee26 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nor.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nor.h @@ -234,7 +234,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); */ /* NOR State functions ********************************************************/ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor); HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h index 59c02173a0..1aee8202d1 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h @@ -101,8 +101,8 @@ typedef struct PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ __IO uint32_t ErrorCode; /*!< PCD Error code */ @@ -190,12 +190,12 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ - & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ &= (uint16_t)(~(__INTERRUPT__))) @@ -262,12 +262,10 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); @@ -289,14 +287,10 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, - pPCD_BcdCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, - pPCD_LpmCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -335,22 +329,17 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint16_t ep_mps, uint8_t ep_type); - +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); /** * @} */ @@ -359,7 +348,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions * @{ */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** * @} */ @@ -433,14 +422,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define USB_CNTRX_BLSIZE (0x1U << 15) /* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)\ - (&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) +#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \ + (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) /* GetENDPOINT */ #define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) -/* ENDPOINT transfer */ -#define USB_EP0StartXfer USB_EPStartXfer /** * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -449,8 +436,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wType Endpoint Type. * @retval None */ -#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\ - & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) \ + (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) /** @@ -740,11 +728,13 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\ - + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_TX_CNT(USBx, bEpNum) \ + ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \ + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\ - + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_RX_CNT(USBx, bEpNum) \ + ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \ + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) /** @@ -797,7 +787,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); { \ (wNBlocks)--; \ } \ - *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ + *(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ } while(0) /* PCD_CALC_BLK32 */ #define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ @@ -807,13 +797,15 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); { \ (wNBlocks)++; \ } \ - *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ + *(pdwReg) |= (uint16_t)((wNBlocks) << 10); \ } while(0) /* PCD_CALC_BLK2 */ #define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ do { \ uint32_t wNBlocks; \ \ + *(pdwReg) &= 0x3FFU; \ + \ if ((wCount) > 62U) \ { \ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ @@ -822,7 +814,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); { \ if ((wCount) == 0U) \ { \ - *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ *(pdwReg) |= USB_CNTRX_BLSIZE; \ } \ else \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_qspi.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_qspi.h index 062ad6b36a..fd820e1ddc 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_qspi.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_qspi.h @@ -456,7 +456,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); * @{ */ /** @brief Reset QSPI handle state. - * @param __HANDLE__ : QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) @@ -470,20 +470,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #endif /** @brief Enable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -496,8 +496,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -509,8 +509,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -523,8 +523,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -537,8 +537,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag @@ -623,13 +623,13 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); -uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); +HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi); +uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); -uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); +uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h index 5ee980c30c..c8f077352d 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h @@ -1042,7 +1042,7 @@ typedef struct #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); -#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDG2EN) +#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) @@ -3107,7 +3107,7 @@ typedef struct * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h index b2e8c2541c..6cebf27795 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h @@ -515,7 +515,7 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ /** diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rng.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rng.h index 7b28233421..8d0da09f72 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rng.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rng.h @@ -315,7 +315,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); @@ -328,8 +328,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc.h index 88757fd582..07c2aed5e2 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc.h @@ -559,6 +559,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to (__HANDLE__)->Instance->WPR = 0xFFU; \ } while(0U) +/** + * @brief Check whether the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U) + /** * @brief Add 1 hour (summer time change). * @note This interface is deprecated. @@ -877,6 +884,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ RTC_DR_DU) +#define RTC_ICSR_RESERVED_MASK (RTC_ICSR_RECALPF | RTC_ICSR_INIT | RTC_ICSR_INITF | \ + RTC_ICSR_RSF | RTC_ICSR_INITS | RTC_ICSR_SHPF | \ + RTC_ICSR_WUTWF | RTC_ICSR_ALRBWF | RTC_ICSR_ALRAWF) +#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) #define RTC_INIT_MASK 0xFFFFFFFFU #define RTC_TIMEOUT_VALUE 1000U diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h index f33cae8bf5..771d4d6232 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h @@ -308,8 +308,6 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); * @{ */ #define SAI_SYNCEXT_DISABLE 0U -#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U -#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U /** * @} */ @@ -439,8 +437,6 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); */ #define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */ #define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */ -#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */ -#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */ /** * @} */ @@ -807,8 +803,8 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); * @{ */ /* Peripheral State functions ************************************************/ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai); -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); /** * @} */ @@ -821,9 +817,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Private_Macros SAI Private Macros * @{ */ -#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ - ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ - ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) +#define IS_SAI_BLOCK_SYNCEXT(STATE) ((STATE) == SAI_SYNCEXT_DISABLE) #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\ ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\ @@ -873,9 +867,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) + ((SYNCHRO) == SAI_SYNCHRONOUS)) #define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \ ((VALUE) == SAI_MCK_OUTPUT_DISABLE)) diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h index b582ba4182..05771bea8b 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h @@ -69,7 +69,8 @@ typedef struct /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ -HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard.h index ca334d07c0..a2f700dd11 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard.h @@ -1185,8 +1185,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) * @{ */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus.h index c5eb648f9c..c36b5b7cff 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus.h @@ -100,8 +100,6 @@ typedef struct #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} @@ -751,8 +749,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /* Peripheral State and Errors functions **************************************************/ -uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h index e1526da0a6..991dac5e28 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h @@ -48,7 +48,7 @@ extern "C" { /** @addtogroup SPIEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sram.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sram.h index 44b7bc08d5..e91667a1d3 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sram.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sram.h @@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); */ /* SRAM State functions ******************************************************/ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h index 3f46616e99..034b6ad425 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h @@ -416,29 +416,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -781,6 +780,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ @@ -825,16 +833,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ #if defined (TIM5) #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ #endif /* TIM5 */ @@ -1073,8 +1081,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ /** @@ -1088,10 +1096,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ -#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ -#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ -#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ -#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #if defined (TIM5) #define TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR9) */ #endif /* TIM5 */ @@ -1104,7 +1108,11 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #endif /* TIM20 */ #define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ -#define TIM_TS_NONE 0xFFFFFFFFU /*!< No trigger selected */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} */ @@ -1825,6 +1833,17 @@ mode. TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + /** * @} */ @@ -1903,7 +1922,7 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ - ((__MODE__) == TIM_UIFREMAP_ENALE)) + ((__MODE__) == TIM_UIFREMAP_ENABLE)) #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ @@ -1943,6 +1962,10 @@ mode. ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) @@ -1969,6 +1992,10 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ @@ -1976,15 +2003,15 @@ mode. #if defined(TIM5) && defined(TIM20) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -1995,15 +2022,15 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #elif defined(TIM5) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -2012,15 +2039,15 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #elif defined(TIM20) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -2029,15 +2056,15 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #else #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -2081,7 +2108,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -2150,8 +2176,8 @@ mode. ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ @@ -2164,59 +2190,6 @@ mode. ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) -#if defined (TIM5) && defined(TIM20) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR9) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ - ((__SELECTION__) == TIM_TS_ITR11)|| \ - ((__SELECTION__) == TIM_TS_NONE)) -#elif defined (TIM5) -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ - ((__SELECTION__) == TIM_TS_ITR11)|| \ - ((__SELECTION__) == TIM_TS_NONE)) -#elif defined (TIM20) -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR9) || \ - ((__SELECTION__) == TIM_TS_ITR11)|| \ - ((__SELECTION__) == TIM_TS_NONE)) -#else -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR11)|| \ - ((__SELECTION__) == TIM_TS_NONE)) -#endif /* TIM5 && TIM20 */ - #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ @@ -2381,7 +2354,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} @@ -2403,7 +2376,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2425,7 +2399,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2477,7 +2452,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @{ */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); @@ -2510,21 +2485,26 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, @@ -2534,7 +2514,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ @@ -2571,17 +2551,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @{ */ /* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); /** * @} */ @@ -2595,9 +2575,9 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h index 4fdd43009f..339387f5c4 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h @@ -104,153 +104,153 @@ typedef struct /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ -#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ -#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ -#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ -#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ -#define TIM_TIM1_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ +#define TIM_TIM1_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) -#define TIM_TIM1_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#define TIM_TIM1_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) -#define TIM_TIM1_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#define TIM_TIM1_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) -#define TIM_TIM1_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ +#define TIM_TIM1_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ -#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC1 analog watchdog 1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC1 analog watchdog 2 */ -#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC1 analog watchdog 3 */ +#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */ #if defined (ADC4) -#define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 1 */ -#define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC4 analog watchdog 2 */ -#define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 3 */ +#define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */ +#define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */ +#define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */ #endif /* ADC4 */ -#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ -#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ -#define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ -#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ -#define TIM_TIM2_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ +#define TIM_TIM2_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) -#define TIM_TIM2_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#define TIM_TIM2_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) -#define TIM_TIM2_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#define TIM_TIM2_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) -#define TIM_TIM2_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)/* !< ETR input is connected to COMP7_OUT */ +#define TIM_TIM2_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)/*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ -#define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM3 ETR */ -#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM4 ETR */ +#define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ +#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ #if defined (TIM5) -#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to TIM5 ETR */ +#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */ #endif /* TIM5 */ -#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to LSE */ +#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */ -#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ -#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ -#define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ -#define TIM_TIM3_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ -#define TIM_TIM3_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#define TIM_TIM3_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#define TIM_TIM3_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ +#define TIM_TIM3_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) -#define TIM_TIM3_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#define TIM_TIM3_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) -#define TIM_TIM3_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#define TIM_TIM3_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) -#define TIM_TIM3_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ +#define TIM_TIM3_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ -#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM2 ETR */ -#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM4 ETR */ -#define TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 1 */ -#define TIM_TIM3_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC2 analog watchdog 2 */ -#define TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 3 */ - -#define TIM_TIM4_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ -#define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ -#define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ -#define TIM_TIM4_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ -#define TIM_TIM4_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */ +#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ +#define TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */ +#define TIM_TIM3_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC2 analog watchdog 2 */ +#define TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */ + +#define TIM_TIM4_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#define TIM_TIM4_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ +#define TIM_TIM4_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) -#define TIM_TIM4_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#define TIM_TIM4_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) -#define TIM_TIM4_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#define TIM_TIM4_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) -#define TIM_TIM4_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ +#define TIM_TIM4_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ -#define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM3 ETR */ +#define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ #if defined (TIM5) -#define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM5 ETR */ +#define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */ #endif /* TIM5 */ #if defined (TIM5) -#define TIM_TIM5_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ -#define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ -#define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ -#define TIM_TIM5_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ -#define TIM_TIM5_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#define TIM_TIM5_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#define TIM_TIM5_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ +#define TIM_TIM5_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) -#define TIM_TIM5_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#define TIM_TIM5_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) -#define TIM_TIM5_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#define TIM_TIM5_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) -#define TIM_TIM5_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ +#define TIM_TIM5_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ -#define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM2 ETR */ -#define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM3 ETR */ +#define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */ +#define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */ #endif /* TIM5 */ -#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ -#define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ -#define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ -#define TIM_TIM8_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ -#define TIM_TIM8_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#define TIM_TIM8_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#define TIM_TIM8_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ +#define TIM_TIM8_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) -#define TIM_TIM8_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#define TIM_TIM8_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) -#define TIM_TIM8_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#define TIM_TIM8_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) -#define TIM_TIM8_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ +#define TIM_TIM8_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ -#define TIM_TIM8_ETR_ADC2_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC2 analog watchdog 1 */ -#define TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 2 */ -#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC2 analog watchdog 3 */ +#define TIM_TIM8_ETR_ADC2_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC2 analog watchdog 1 */ +#define TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 2 */ +#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 3 */ #if defined (ADC3) -#define TIM_TIM8_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 1 */ -#define TIM_TIM8_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC3 analog watchdog 2 */ -#define TIM_TIM8_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 3 */ +#define TIM_TIM8_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 1 */ +#define TIM_TIM8_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC3 analog watchdog 2 */ +#define TIM_TIM8_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 3 */ #endif /* ADC3 */ #if defined (TIM20) -#define TIM_TIM20_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ -#define TIM_TIM20_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ -#define TIM_TIM20_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ -#define TIM_TIM20_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ -#define TIM_TIM20_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#define TIM_TIM20_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#define TIM_TIM20_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ +#define TIM_TIM20_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#define TIM_TIM20_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ +#define TIM_TIM20_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) -#define TIM_TIM20_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#define TIM_TIM20_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) -#define TIM_TIM20_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#define TIM_TIM20_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) -#define TIM_TIM20_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ +#define TIM_TIM20_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ -#define TIM_TIM20_ETR_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC3 analog watchdog 1 */ -#define TIM_TIM20_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 2 */ -#define TIM_TIM20_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC3 analog watchdog 3 */ +#define TIM_TIM20_ETR_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 1 */ +#define TIM_TIM20_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */ +#define TIM_TIM20_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 3 */ #if defined (ADC5) -#define TIM_TIM20_ETR_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 1 */ -#define TIM_TIM20_ETR_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC5 analog watchdog 2 */ -#define TIM_TIM20_ETR_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 3 */ +#define TIM_TIM20_ETR_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */ +#define TIM_TIM20_ETR_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC5 analog watchdog 2 */ +#define TIM_TIM20_ETR_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */ #endif /* ADC5 */ #endif /* TIM20 */ /** @@ -269,19 +269,19 @@ typedef struct /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ -#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /* !< The COMP3 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP4 0x00000010U /* !< The COMP4 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /*!< The COMP3 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP4 0x00000010U /*!< The COMP4 output is connected to the break input */ #if defined(COMP5) -#define TIM_BREAKINPUTSOURCE_COMP5 0x00000020U /* !< The COMP5 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP5 0x00000020U /*!< The COMP5 output is connected to the break input */ #endif /* COMP5 */ #if defined(COMP6) -#define TIM_BREAKINPUTSOURCE_COMP6 0x00000040U /* !< The COMP6 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP6 0x00000040U /*!< The COMP6 output is connected to the break input */ #endif /* COMP6 */ #if defined(COMP7) -#define TIM_BREAKINPUTSOURCE_COMP7 0x00000080U /* !< The COMP7 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP7 0x00000080U /*!< The COMP7 output is connected to the break input */ #endif /* COMP7 */ /** * @} @@ -715,14 +715,14 @@ typedef struct #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -733,14 +733,14 @@ typedef struct || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -752,14 +752,14 @@ typedef struct || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -770,15 +770,15 @@ typedef struct || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -788,15 +788,15 @@ typedef struct || \ (((INSTANCE) == TIM5) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -806,15 +806,15 @@ typedef struct || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -824,13 +824,13 @@ typedef struct || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -840,15 +840,15 @@ typedef struct || \ (((INSTANCE) == TIM20) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -858,13 +858,13 @@ typedef struct #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ - (((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -874,13 +874,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM2) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -891,13 +891,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -907,14 +907,14 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM4) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -923,14 +923,14 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM5) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -939,14 +939,14 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM8) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -955,13 +955,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM15) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -970,14 +970,14 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM20) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -1095,14 +1095,14 @@ typedef struct #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -1111,14 +1111,14 @@ typedef struct || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -1128,14 +1128,14 @@ typedef struct || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -1144,14 +1144,14 @@ typedef struct || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -1160,15 +1160,15 @@ typedef struct || \ (((INSTANCE) == TIM5) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1176,15 +1176,15 @@ typedef struct || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1192,13 +1192,13 @@ typedef struct || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1206,13 +1206,13 @@ typedef struct #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ - (((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -1220,13 +1220,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -1235,13 +1235,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -1249,13 +1249,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -1263,41 +1263,41 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -1385,14 +1385,14 @@ typedef struct #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1401,14 +1401,14 @@ typedef struct || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1418,14 +1418,14 @@ typedef struct || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1434,14 +1434,14 @@ typedef struct || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1450,15 +1450,15 @@ typedef struct || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ @@ -1466,13 +1466,13 @@ typedef struct || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ @@ -1480,15 +1480,15 @@ typedef struct || \ (((INSTANCE) == TIM20) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1496,13 +1496,13 @@ typedef struct #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ - (((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -1510,13 +1510,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM2) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -1525,13 +1525,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -1539,13 +1539,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM4) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -1553,41 +1553,41 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM8) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM15) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM20) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -1675,14 +1675,14 @@ typedef struct #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1691,13 +1691,13 @@ typedef struct (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1706,14 +1706,14 @@ typedef struct || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1722,13 +1722,13 @@ typedef struct (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -1737,53 +1737,53 @@ typedef struct (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ - (((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -1791,52 +1791,52 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) @@ -1904,6 +1904,7 @@ typedef struct ((__SELECTION__) == TIM_TS_NONE)))) #endif /* TIM5 && TIM20 */ + #define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ (IS_TIM_OC_MODE(__MODE__) \ && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \ @@ -1942,7 +1943,6 @@ typedef struct #define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN)) - /** * @} */ @@ -1958,7 +1958,7 @@ typedef struct * @{ */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); @@ -1991,7 +1991,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2010,7 +2011,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2044,17 +2046,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); + const TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, @@ -2100,8 +2102,8 @@ void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); * @{ */ /* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h index 3df0add1f0..bb06ee89f0 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h @@ -194,7 +194,7 @@ typedef enum /** * @brief HAL UART Reception type definition * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : + * This parameter can be a value of @ref UART_Reception_Type_Values : * HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_TOIDLE = 0x01U, * HAL_UART_RECEPTION_TORTO = 0x02U, @@ -202,6 +202,17 @@ typedef enum */ typedef uint32_t HAL_UART_RxTypeTypeDef; +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -236,6 +247,8 @@ typedef struct __UART_HandleTypeDef __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ @@ -805,7 +818,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values +/** @defgroup UART_Reception_Type_Values UART Reception type values * @{ */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ @@ -816,6 +829,16 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + /** * @} */ @@ -1666,8 +1689,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); */ /* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h index ac2154d67a..34c17155ef 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h @@ -178,6 +178,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); + /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart.h index 757a952bfd..8e012b8567 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart.h @@ -142,7 +142,7 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value @@ -920,7 +920,8 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); @@ -957,8 +958,8 @@ void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); */ /* Peripheral State and Error functions ***************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart_ex.h index a818a37131..a60f797866 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart_ex.h @@ -45,7 +45,7 @@ extern "C" { * @{ */ #define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h index 7d8a421d5c..dc64ef1a41 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h @@ -59,7 +59,7 @@ extern "C" { #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \ | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) -#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ +#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/ #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) /* Definition of ADC group regular sequencer bits information to be inserted */ @@ -98,7 +98,7 @@ extern "C" { #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \ | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) -#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ +#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/ /* Definition of ADC group injected sequencer bits information to be inserted */ /* into ADC group injected sequencer ranks literals definition. */ @@ -113,23 +113,25 @@ extern "C" { /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ /* - regular trigger source */ /* - regular trigger edge */ -#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for + compatibility with some ADC on other STM32 series + having this setting set by HW default value) */ /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 3UL)) ) +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group regular trigger bits information. */ #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos) @@ -141,23 +143,25 @@ extern "C" { /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ /* - injected trigger source */ /* - injected trigger edge */ -#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ +#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for + compatibility with some ADC on other STM32 series + having this setting set by HW default value) */ /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) +#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) +#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group injected trigger bits information. */ #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos) @@ -182,11 +186,14 @@ extern "C" { #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \ | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK + >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ /* Channel differentiation between external and internal channels */ #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ -#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ +#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case + of different ADC internal channels mapped on same channel + number on different ADC instances */ #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /* Internal register offset for ADC channel sampling time configuration */ @@ -194,10 +201,12 @@ extern "C" { #define ADC_SMPR1_REGOFFSET (0x00000000UL) #define ADC_SMPR2_REGOFFSET (0x02000000UL) #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) -#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ +#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET + in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL) -#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */ +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" + position in register */ /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ @@ -246,25 +255,27 @@ extern "C" { /* Definition of channels sampling time information to be inserted into */ /* channels literals definition. */ -#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */ -#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */ -#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */ -#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */ -#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */ -#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */ -#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */ -#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */ -#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */ -#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */ -#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */ -#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */ -#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */ -#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */ -#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */ -#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */ -#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */ -#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */ -#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */ +/* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */ +/* in register. */ +#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Internal mask for ADC mode single or differential ended: */ @@ -276,15 +287,20 @@ extern "C" { #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF) #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ -#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ +#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen + to perform of shift when single mode is selected, shift value out of + channels bits range. */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: + mask of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: + position of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit + ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */ /* Internal mask for ADC analog watchdog: */ /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ /* (concatenation of multiple bits used in different analog watchdogs, */ -/* (feature of several watchdogs not available on all STM32 families)). */ +/* (feature of several watchdogs not available on all STM32 series)). */ /* - analog watchdog 1: monitored channel defined by number, */ /* selection of ADC group (ADC groups regular and-or injected). */ /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ @@ -306,20 +322,25 @@ extern "C" { #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) -#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ +#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET + in ADC_AWD_CRX_REGOFFSET_MASK */ /* Internal register offset for ADC analog watchdog threshold configuration */ #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) -#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ -#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */ -#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */ -#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ +#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET + in ADC_AWD_TRX_REGOFFSET_MASK */ +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate + threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate + threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to + position to perform a shift of 4 ranks */ /* Internal mask for ADC offset: */ -/* Internal register offset for ADC offset number configuration */ +/* Internal register offset for ADC offset instance configuration */ #define ADC_OFR1_REGOFFSET (0x00000000UL) #define ADC_OFR2_REGOFFSET (0x00000001UL) #define ADC_OFR3_REGOFFSET (0x00000002UL) @@ -337,19 +358,37 @@ extern "C" { /* ADC registers bits groups */ -#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ +#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \ + | ADC_CR_JADSTART | ADC_CR_JADSTP \ + | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with + HW property "rs": Software can read as well as set this bit. + Writing '0' has no effect on the bit value. */ /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of + parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value + with which VrefInt has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G4, + temperature sensor ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G4, + temperature sensor ADC raw data acquired at temperature 110 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (30L) /* Temperature at which temperature sensor + has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (110L) /* Temperature at which temperature sensor + has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) value + with which temperature sensor has been calibrated in production + (tolerance +-10 mV) (unit: mV). */ /** * @} @@ -397,27 +436,28 @@ typedef struct { uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - @note On this STM32 series, if ADC group injected is used, some - clock ratio constraints between ADC clock and AHB clock - must be respected. Refer to reference manual. - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ + @note On this STM32 series, if ADC group injected is used, some clock ratio + constraints between ADC clock and AHB clock must be respected. + Refer to reference manual. + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetCommonClock(). */ #if defined(ADC_MULTIMODE_SUPPORT) - uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). + uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode + (for devices with several ADC instances). This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetMultimode(). */ uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetMultiDMATransfer(). */ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetMultiTwoSamplingDelay(). */ #endif /* ADC_MULTIMODE_SUPPORT */ } LL_ADC_CommonInitTypeDef; @@ -426,14 +466,14 @@ typedef struct * @brief Structure definition of some features of ADC instance. * @note These parameters have an impact on ADC scope: ADC instance. * Affects both group regular and group injected (availability - * of ADC group injected depends on STM32 families). + * of ADC group injected depends on STM32 series). * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Instance . * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -446,18 +486,18 @@ typedef struct { uint32_t Resolution; /*!< Set ADC resolution. This parameter can be a value of @ref ADC_LL_EC_RESOLUTION - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetResolution(). */ uint32_t DataAlignment; /*!< Set ADC conversion data alignment. This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetDataAlignment(). */ uint32_t LowPowerMode; /*!< Set ADC low power mode. This parameter can be a value of @ref ADC_LL_EC_LP_MODE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetLowPowerMode(). */ } LL_ADC_InitTypeDef; @@ -471,7 +511,7 @@ typedef struct * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -482,42 +522,52 @@ typedef struct */ typedef struct { - uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or + from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge - (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). - In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ + @note On this STM32 series, setting trigger source to external trigger also + set trigger polarity to rising edge(default setting for compatibility + with some ADC on other STM32 series having this setting set by HW + default value). + In case of need to modify trigger edge, use function + @ref LL_ADC_REG_SetTriggerEdge(). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerLength(). */ - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided + and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE - @note This parameter has an effect only if group regular sequencer is enabled - (scan length of 2 ranks or more). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ - - uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). + @note This parameter has an effect only if group regular sequencer is + enabled (scan length of 2 ranks or more). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC + conversions are performed in single mode (one conversion per trigger) or in + continuous mode (after the first trigger, following conversions launched + successively automatically). This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE - Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ + Note: It is not possible to enable both ADC group regular continuous mode + and discontinuous mode. + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetContinuousMode(). */ - uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer + by DMA, and DMA requests mode. This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetDMATransfer(). */ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetOverrun(). */ } LL_ADC_REG_InitTypeDef; @@ -531,7 +581,7 @@ typedef struct * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -542,31 +592,38 @@ typedef struct */ typedef struct { - uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) + or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE - @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge - (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). - In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ + @note On this STM32 series, setting trigger source to external trigger also + set trigger polarity to rising edge (default setting for + compatibility with some ADC on other STM32 series having this + setting set by HW default value). + In case of need to modify trigger edge, use function + @ref LL_ADC_INJ_SetTriggerEdge(). + This feature can be modified afterwards using unitary function + @ref LL_ADC_INJ_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH + This feature can be modified afterwards using unitary function + @ref LL_ADC_INJ_SetSequencerLength(). */ - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided + and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE - @note This parameter has an effect only if group injected sequencer is enabled - (scan length of 2 ranks or more). + @note This parameter has an effect only if group injected sequencer is + enabled (scan length of 2 ranks or more). + This feature can be modified afterwards using unitary function + @ref LL_ADC_INJ_SetSequencerDiscont(). */ - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ - - uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. + uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group + regular. This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO - Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ + Note: This parameter must be set to set to independent trigger if injected + trigger source is set to an external trigger. + This feature can be modified afterwards using unitary function + @ref LL_ADC_INJ_SetTrigAuto(). */ } LL_ADC_INJ_InitTypeDef; @@ -585,39 +642,64 @@ typedef struct * @{ */ #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ -#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ -#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */ +#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary + conversion */ +#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence + conversions */ #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ -#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */ -#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */ -#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */ +#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary + conversion */ +#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence + conversions */ +#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue + overflow */ #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ #if defined(ADC_MULTIMODE_SUPPORT) #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */ #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */ -#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */ -#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */ -#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */ -#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */ -#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */ -#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */ -#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */ -#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */ -#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */ -#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */ -#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */ -#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */ -#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */ -#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */ -#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ -#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */ -#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */ -#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */ -#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */ -#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */ +#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of + unitary conversion */ +#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of + unitary conversion */ +#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of + sequence conversions */ +#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of + sequence conversions */ +#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular + overrun */ +#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular + overrun */ +#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of + sampling phase */ +#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of + sampling phase */ +#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of + unitary conversion */ +#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of + unitary conversion */ +#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of + sequence conversions */ +#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of + sequence conversions */ +#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected + contexts queue overflow */ +#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected + contexts queue overflow */ +#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 + of the ADC master */ +#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 + of the ADC slave */ +#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 + of the ADC master */ +#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 + of the ADC slave */ +#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 + of the ADC master */ +#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 + of the ADC slave */ #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -628,13 +710,19 @@ typedef struct * @{ */ #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ -#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ -#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */ +#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary + conversion */ +#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence + conversions */ #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ -#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ -#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */ -#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */ -#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */ +#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling + phase */ +#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary + conversion */ +#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence + conversions */ +#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue + overflow */ #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ @@ -648,9 +736,17 @@ typedef struct /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register + (corresponding to register DR) to be used with ADC configured in independent + mode. Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadConversionData32() and other + functions @ref LL_ADC_REG_ReadConversionDatax() */ #if defined(ADC_MULTIMODE_SUPPORT) -#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ +#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register + (corresponding to register CDR) to be used with ADC configured in multimode + (available on STM32 devices with several ADC instances). + Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadMultiConversionData32() */ #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -659,21 +755,38 @@ typedef struct /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ -#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ -#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ -#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */ -#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */ -#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */ -#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */ -#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */ -#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */ -#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */ -#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */ -#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */ -#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from + AHB clock without prescaler */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from + AHB clock with prescaler division by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from + AHB clock with prescaler division by 4 */ +#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without + prescaler */ +#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 2 */ +#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 4 */ +#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 6 */ +#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with + prescaler division by 8 */ +#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 10 */ +#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 12 */ +#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 16 */ +#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with + prescaler division by 32 */ +#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 64 */ +#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 128 */ +#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 256 */ /** * @} */ @@ -686,10 +799,11 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ -#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ -#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel temperature sensor */ -#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel + temperature sensor */ +#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */ /** * @} */ @@ -708,8 +822,10 @@ typedef struct /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment * @{ */ -#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ /** * @} */ @@ -717,19 +833,30 @@ typedef struct /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode * @{ */ -#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ -#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power + mode, ADC conversions are performed only when necessary + (when previous ADC conversion data is read). + See description with function @ref LL_ADC_SetLowPowerMode(). */ /** * @} */ -/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number +/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance * @{ */ -#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ +#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + mapped on ADC group regular or injected) */ +#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + mapped on ADC group regular or injected) */ +#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + mapped on ADC group regular or injected) */ +#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + mapped on ADC group regular or injected) */ /** * @} */ @@ -737,8 +864,10 @@ typedef struct /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state * @{ */ -#define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ -#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled + (setting offset instance wise) */ +#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled + (setting offset instance wise) */ /** * @} */ @@ -746,8 +875,8 @@ typedef struct /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign * @{ */ -#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */ -#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative */ +#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive */ /** * @} */ @@ -755,17 +884,20 @@ typedef struct /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode * @{ */ -#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */ -#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC + selected offset instance 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC + selected offset instance 1, 2, 3 or 4) */ /** * @} */ /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups * @{ */ -#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ -#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/ -#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ +#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 + devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ /** * @} */ @@ -773,36 +905,83 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number * @{ */ -#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ -#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ -#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ -#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ -#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ -#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ -#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ -#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ -#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ -#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ -#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ -#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ -#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ -#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ -#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ -#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ -#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ -#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ -#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ -#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ -#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ -#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ -#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ -#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ -#define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ -#define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ -#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */ -#define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */ -#define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP \ + | ADC_CHANNEL_0_BITFIELD) /*!< ADC channel ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP \ + | ADC_CHANNEL_1_BITFIELD) /*!< ADC channel ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP \ + | ADC_CHANNEL_2_BITFIELD) /*!< ADC channel ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP \ + | ADC_CHANNEL_3_BITFIELD) /*!< ADC channel ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP \ + | ADC_CHANNEL_4_BITFIELD) /*!< ADC channel ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP \ + | ADC_CHANNEL_5_BITFIELD) /*!< ADC channel ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP \ + | ADC_CHANNEL_6_BITFIELD) /*!< ADC channel ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP \ + | ADC_CHANNEL_7_BITFIELD) /*!< ADC channel ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP \ + | ADC_CHANNEL_8_BITFIELD) /*!< ADC channel ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP \ + | ADC_CHANNEL_9_BITFIELD) /*!< ADC channel ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \ + | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \ + | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \ + | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \ + | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \ + | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \ + | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \ + ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \ + ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ +#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \ + ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to VrefInt: Internal voltage reference. + On this STM32 series, ADC channel available on all instances but ADC2. */ +#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to internal temperature sensor. + On this STM32 series, ADC channel available only on ADC1 instance. */ +#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to internal temperature sensor. + On this STM32 series, ADC channel available only on ADC5 instance. + Refer to device datasheet for ADC5 availability */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 + to have channel voltage always below Vdda. On this STM32 series, ADC channel + available on all ADC instances but ADC2 & ADC4. Refer to device datasheet + for ADC4 availability */ +#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to OPAMP1 output. + On this STM32 series, ADC channel available only on ADC1 instance. */ +#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | \ + ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 + output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \ + ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 + output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | \ + ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 + output. On this STM32 series, ADC channel available only on ADC3 instance. + Refer to device datasheet for ADC3 availability */ +#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel +connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. +Refer to device datasheet for ADC5 & OPAMP4 availability */ +#define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel +connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. +Refer to device datasheet for ADC5 & OPAMP5 availability */ +#define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \ + ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel + connected to OPAMP6 output. + On this STM32 series, ADC channel available only on ADC4 instance. + Refer to device datasheet for ADC4 & OPAMP6 availability */ /** * @} */ @@ -810,113 +989,233 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source * @{ */ -#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< - ADC group regular conversion trigger internal: SW start. */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular + conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 TRGO2. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 channel 1 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC1/2 instances */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 channel 2 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC1/2 instances */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 channel 3 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \ + ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ + ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< + conversion trigger from external peripheral: TIM2 channel 1 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 channel 2 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC1/2 instances */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 channel 3 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM3 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM3 channel 1 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ + ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM3 channel 4 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC1/2 instances */ +#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM4 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM4 channel 1 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM4 channel 4 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC1/2 instances */ +#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ + ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM6 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ + ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< + conversion trigger from external peripheral: TIM7 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \ + ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM8 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM8 TRGO2. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM8 channel 1 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ + ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM15 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM20 TRGO. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, TIM20 is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM20 TRGO2. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, TIM20 is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM20 channel 1 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, TIM20 is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \ + ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM20 channel 2 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC1/2 instances, and TIM20 is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM20 channel 3 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC1/2 instances, and TIM20 is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ + ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \ + ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC3/4/5 instances, and HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ + ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC3/4/5 instances, and HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ + ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ + ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ + ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ + ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ + ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. + Refer to device datasheet for more details */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: external interrupt line 11. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC1/2 instances */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: external interrupt line 2. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on + ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ + ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \ + ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: LPTIMER OUT event. + Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -924,9 +1223,12 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge * @{ */ -#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ -#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ -#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +#define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ /** * @} */ @@ -934,12 +1236,15 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode * @{ */ -#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */ -#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. - Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */ -#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: - Trigger rising edge = start sampling - Trigger falling edge = stop sampling and start conversion */ +#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration + is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */ +#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts + immediately after end of conversion, and stops upon trigger event. + Note: First conversion is using minimal sampling time + (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */ +#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is + controlled by trigger events: trigger rising edge for start sampling, + trigger falling edge for stop sampling and start conversion */ /** * @} */ @@ -947,8 +1252,11 @@ typedef struct /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode * @{ */ -#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ -#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode: + one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions performed in continuous mode: + after the first trigger, following conversions launched successively + automatically */ /** * @} */ @@ -956,9 +1264,15 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ -#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ -#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA + in limited mode (one shot mode): DMA transfer requests are stopped when + number of DMA data transfers (number of ADC conversions) is reached. + This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are + transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. */ /** * @} */ @@ -968,17 +1282,22 @@ typedef struct * @{ */ #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */ -#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */ +#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock + cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped + with selection sampling time 2.5 ADC clock cycles, whatever channels mapped + on ADC groups regular or injected). */ /** * @} */ -#endif +#endif /* ADC_SMPR1_SMPPLUS */ /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ -#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: + data preserved */ +#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: + data overwritten */ /** * @} */ @@ -986,22 +1305,43 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length * @{ */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable + (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable + with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable + with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable + with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1 \ + | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 8 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable + with 9 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 10 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable + with 11 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \ + | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 12 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable + with 13 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \ + | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 14 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \ + | ADC_SQR1_L_1) /*!< ADC group regular sequencerenable + with 15 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \ + | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 16 ranks in the sequence */ /** * @} */ @@ -1009,15 +1349,28 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ -#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ -#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer + discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every rank */ +#define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every 2 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 3 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \ + | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 4 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 5 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \ + | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 6 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \ + | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 7 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \ + | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 8 ranks */ /** * @} */ @@ -1025,22 +1378,38 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ -#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ -#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ -#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ -#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ -#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ -#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ -#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ -#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ -#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ -#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ -#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ -#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ -#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ -#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ -#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ -#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ +#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 8 */ +#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 9 */ +#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 10 */ +#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 11 */ +#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 12 */ +#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 13 */ +#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 14 */ +#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 15 */ +#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 16 */ /** * @} */ @@ -1048,109 +1417,218 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source * @{ */ -#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< - ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances. */ -#define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected + conversion trigger internal: SW start. */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM1 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \ + ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM1 + channel 3 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC3/4/5 + instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM1 + channel 4 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM2 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM2 + channel 1 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC1/2 + instances */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM3 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ + ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM3 + channel 1 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC1/2 + instances */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \ + ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM3 + channel 3 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC1/2 + instances */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM3 + channel 4 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC1/2 + instances */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM4 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM4 + channel 3 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC3/4/5 + instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM4 + channel 4 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC3/4/5 + instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ + ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM6 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ + ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM7 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM8 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM8 + channel 2 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC3/4/5 + instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \ + ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM8 + channel 4 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ + ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM15 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ + ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM8 + channel 4 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC1/2 + instances */ +#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM20 TRGO. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, TIM20 is not available on all devices. Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. + Trigger edge set to rising edge (default setting). + Note: On this STM32 series, TIM20 is not available on all devices. Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM20 + channel 2 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is + not available on all devices. Refer to device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: TIM20 + channel 4 event (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). + Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is + not available on all devices. Refer to device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ + ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER + ADC trigger 1 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC3/4/5 + instances, and HRTIM is not available on all devices. Refer to device + datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \ + ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER ADC + trigger 2 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ + ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER + ADC trigger 3 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC3/4/5 + instances, and HRTIM is not available on all devices. Refer to device + datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER ADC + trigger 4 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \ + ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER ADC + trigger 5 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \ + ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER ADC + trigger 6 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \ + ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER ADC + trigger 7 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER ADC + trigger 8 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ + ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER ADC + trigger 9 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices. Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ + ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: HRTIMER ADC + trigger 10 event. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, HRTIM is not available on all devices.Refer to + device datasheet for more details */ +#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ + ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: external + interrupt line 3. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC3/4/5 + instances. Refer to device datasheet for ADCx availability */ +#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \ + ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: external + interrupt line 15. Trigger edge set to rising edge (default setting). + Note: On this STM32 series, this trigger is available only on ADC1/2 + instances. */ +#define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ + ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< + ADC group injected conversion trigger from external peripheral: LPTIMER OUT + event. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -1158,9 +1636,12 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge * @{ */ -#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ -#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ -#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ +#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion + trigger polarity set to rising edge */ +#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion + trigger polarity set to falling edge */ +#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion + trigger polarity set to both rising and falling edges */ /** * @} */ @@ -1168,8 +1649,14 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode * @{ */ -#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ -#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ +#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. + Setting mandatory if ADC group injected injected trigger source is set to + an external trigger. */ +#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group + regular. Setting compliant only with group injected trigger source set to + SW start, without any further action on ADC group injected conversion start + or stop: in this case, ADC group injected is controlled only from ADC group + regular. */ /** * @} */ @@ -1177,9 +1664,14 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode * @{ */ -#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ -#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ -#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ +#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled + and can contain up to 2 contexts. When all contexts have been processed, + the queue maintains the last context active perpetually. */ +#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled + and can contain up to 2 contexts. When all contexts have been processed, + the queue is empty and injected group triggers are disabled. */ +#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: + only 1 sequence can be configured and is active perpetually. */ /** * @} */ @@ -1187,10 +1679,14 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length * @{ */ -#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable + (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable + with 2 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable + with 3 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable + with 4 ranks in the sequence */ /** * @} */ @@ -1198,8 +1694,10 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode * @{ */ -#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */ -#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode + disable */ +#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode + enable with sequence interruption every rank */ /** * @} */ @@ -1207,10 +1705,14 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ -#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */ -#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */ -#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */ -#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */ +#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \ + | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */ +#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \ + | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */ +#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \ + | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */ +#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \ + | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */ /** * @} */ @@ -1218,14 +1720,19 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_24CYCLES_5 (ADC_SMPR2_SMP10_1 \ + | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \ + | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \ + | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \ + | ADC_SMPR2_SMP10_1 \ + | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */ /** * @} */ @@ -1233,9 +1740,13 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ -#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ -#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ -#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */ +#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending + set to single ended (literal also used to set calibration mode) */ +#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending + set to differential (literal also used to set calibration mode) */ +#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending + set to both single ended and differential (literal used only to set + calibration factors) */ /** * @} */ @@ -1243,9 +1754,12 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number * @{ */ -#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ -#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ -#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \ + | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ +#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ /** * @} */ @@ -1253,100 +1767,353 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ -#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ -#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ -#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ -#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ -#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ -#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group regular only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group injected only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group regular only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group injected only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ -#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ -#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ -#define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP5_REG ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP5_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP5_REG_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP6_REG ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP6_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP6_REG_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by either group regular or injected */ +#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring + disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by group regular only */ +#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by group injected only */ +#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by group only */ +#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + monitoring of ADC channel ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN15, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN15, converted by either group + regular or injected */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN18, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN18, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN18, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal + voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal + voltage reference, converted by group injected only */ +#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal + voltage reference, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC1 internal channel connected to internal temperature sensor, + converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog + of ADC1 internal channel connected to internal temperature sensor, + converted by group injected only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC1 internal channel connected to internal temperature sensor, + converted by either group regular or injected */ +#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC5 internal channel connected to internal temperature sensor, + converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog + of ADC5 internal channel connected to internal temperature sensor, + converted by group injected only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC5 internal channel connected to internal temperature sensor, + converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Vbat/3: Vbat + voltage through a divider ladder of factor 1/3 to have channel voltage always below + Vdda, converted by group regular only */ +#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Vbat/3: Vbat + voltage through a divider ladder of factor 1/3 to have channel voltage always below + Vdda, converted by group injected only */ +#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Vbat/3: Vbat + voltage through a divider ladder of factor 1/3 to have channel voltage always below + Vdda */ +#define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP1 output, + channel specific to ADC1, converted by group regular only */ +#define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP1 output, + channel specific to ADC1, converted by group injected only */ +#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP1 output, + channel specific to ADC1, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + channel specific to ADC2, converted by group regular only */ +#define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP2 output, + channel specific to ADC2, converted by group injected only */ +#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP2 output, + channel specific to ADC2, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP3 output, + channel specific to ADC2, converted by group regular only */ +#define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP3 output, + channel specific to ADC2, converted by group injected only */ +#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP3 output, + channel specific to ADC2, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP3 output, + channel specific to ADC3, converted by group regular only */ +#define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP3 output, + channel specific to ADC3, converted by group injected only */ +#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP3 output, + channel specific to ADC3, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP4 output, + channel specific to ADC5, converted by group regular only */ +#define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP4 output, + channel specific to ADC5, converted by group injected only */ +#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP4 output, + channel specific to ADC5, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VOPAMP5_REG ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP5 output, + channel specific to ADC5, converted by group regular only */ +#define LL_ADC_AWD_CH_VOPAMP5_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP5 output, + channel specific to ADC5, converted by group injected only */ +#define LL_ADC_AWD_CH_VOPAMP5_REG_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP5 output, + channel specific to ADC5, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VOPAMP6_REG ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP6 output, + channel specific to ADC4, converted by group regular only */ +#define LL_ADC_AWD_CH_VOPAMP6_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP6 output, + channel specific to ADC4, converted by group injected only */ +#define LL_ADC_AWD_CH_VOPAMP6_REG_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to OPAMP6 output, + channel specific to ADC4, converted by either group regular or injected */ /** * @} */ @@ -1354,9 +2121,11 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds * @{ */ -#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */ -#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ -#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ +#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \ + | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low + concatenated into the same data */ /** * @} */ @@ -1364,14 +2133,23 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config * @{ */ -#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, + one out-of-window sample is needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_2SAMPLES (ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 2 + out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_3SAMPLES (ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 3 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_4SAMPLES (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 4 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2) /*!< ADC analog watchdog 5 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 6 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 7 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \ + | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 8 + consecutives out-of-window samples are needed to raise flag or interrupt */ /** * @} */ @@ -1379,11 +2157,21 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope * @{ */ -#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ -#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ -#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ -#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ -#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of + ADC group regular. If group injected interrupts group regular: + when ADC group injected is triggered, the oversampling on ADC group regular + is temporary stopped and continued afterwards. */ +#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of + ADC group regular. If group injected interrupts group regular: + when ADC group injected is triggered, the oversampling on ADC group regular + is resumed from start (oversampler buffer reset). */ +#define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of + ADC group injected. */ +#define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of + both ADC groups regular and injected. If group injected interrupting group + regular: when ADC group injected is triggered, the oversampling on ADC group + regular is resumed from start (oversampler buffer reset). */ /** * @} */ @@ -1391,8 +2179,10 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ -#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ -#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode +(all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous + mode (each conversion of oversampling ratio needs a trigger) */ /** * @} */ @@ -1400,30 +2190,66 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio * @{ */ -#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \ + | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ /** * @} */ -/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift +/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift * @{ */ -#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift + (sum of the ADC conversions data is not divided to result as oversampling + conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 + (sum of the ADC conversions data (after OVS ratio) is divided by 2 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 + (sum of the ADC conversions data (after OVS ratio) is divided by 4 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3 + (sum of the ADC conversions data (after OVS ratio) is divided by 8 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 + (sum of the ADC conversions data (after OVS ratio) is divided by 16 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5 + (sum of the ADC conversions data (after OVS ratio) is divided by 32 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6 + (sum of the ADC conversions data (after OVS ratio) is divided by 64 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \ + | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 + (sum of the ADC conversions data (after OVS ratio) is divided by 128 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 + (sum of the ADC conversions data (after OVS ratio) is divided by 256 + to result as oversampling conversion data) */ /** * @} */ @@ -1432,14 +2258,23 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode * @{ */ -#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */ -#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ -#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ -#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ -#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ -#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ -#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ -#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ +#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC + independent mode) */ +#define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular + simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTERL (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \ + | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group + regular interleaved */ +#define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected + simultaneous */ +#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected + alternate trigger. Works only with external triggers (not SW start) */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group + regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group + regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group + regular interleaved + group injected simultaneous */ /** * @} */ @@ -1447,11 +2282,34 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer * @{ */ -#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ -#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ -#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ -#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ -#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular + conversions are transferred by DMA: each ADC uses its own DMA channel, + with its individual DMA transfer settings */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1) /*!< ADC multimode group regular + conversions are transferred by DMA, one DMA channel for both ADC(DMA of + ADC master), in limited mode (one shot mode): DMA transfer requests + are stopped when number of DMA data transfers (number of ADC conversions) + is reached. This ADC mode is intended to be used with DMA mode + non-circular. Setting for ADC resolution of 12 and 10 bits */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular + conversions are transferred by DMA, one DMA channel for both ADC(DMA of + ADC master), in limited mode (one shot mode): DMA transfer requests + are stopped when number of DMA data transfers (number of ADC conversions) + is reached. This ADC mode is intended to be used with DMA mode + non-circular. Setting for ADC resolution of 8 and 6 bits */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular + conversions are transferred by DMA, one DMA channel for both ADC(DMA of + ADC master), in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. + Setting for ADC resolution of 12 and 10 bits */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \ + | ADC_CCR_MDMA_0) /*!< ADC multimode group regular + conversions are transferred by DMA, one DMA channel for both ADC (DMA of + ADC master), in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. + Setting for ADC resolution of 8 and 6 bits */ /** * @} */ @@ -1459,18 +2317,32 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ -#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two + sampling phases: 1 ADC clock cycle */ +#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 2 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two + sampling phases: 3 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 4 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two + sampling phases: 5 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 6 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two + sampling phases: 7 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \ + | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 8 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two + sampling phases: 9 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 10 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two + sampling phases: 11 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \ + | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 12 ADC clock cycles */ /** * @} */ @@ -1478,15 +2350,30 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave * @{ */ -#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ -#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ -#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ +#define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC + instances: ADC master */ +#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC + instances: ADC slave */ +#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \ + | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC + instances: both ADC master and ADC slave */ /** * @} */ #endif /* ADC_MULTIMODE_SUPPORT */ +/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro + * @{ + */ +#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro + @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on + calibration parameters. This value is coded on 16 bits + (to fit on signed word or double word) and corresponds + to an inconsistent temperature value. */ +/** + * @} + */ /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, @@ -1518,19 +2405,24 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tADCVREG_STUP"). */ /* Unit: us */ -#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage + regulator start-up time) */ /* Delay for internal voltage reference stabilization time. */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tstart_vrefint"). */ /* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization + time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization + time (starting from ADC enable, refer to + @ref LL_ADC_Enable()) */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 series, a minimum number of ADC clock cycles */ @@ -1539,7 +2431,8 @@ typedef struct /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration + and ADC enable */ /** * @} @@ -1631,9 +2524,12 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ @@ -1693,9 +2589,12 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). @@ -1704,13 +2603,13 @@ typedef struct (((__DECIMAL_NB__) <= 9UL) ? \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ ) \ : \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ ) \ ) @@ -1771,10 +2670,14 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel + connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ @@ -1832,9 +2735,12 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 @@ -1893,7 +2799,8 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ @@ -2010,7 +2917,7 @@ typedef struct ) \ ) \ ) -#endif +#endif /* STM32G4xx */ /** * @brief Helper macro to define ADC analog watchdog parameter: @@ -2060,9 +2967,12 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). @@ -2174,7 +3084,8 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ @@ -2243,8 +3154,9 @@ typedef struct * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ - (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) +#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ + (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \ + & LL_ADC_AWD_THRESHOLD_LOW) /** * @brief Helper macro to set the ADC calibration value with both single ended @@ -2387,7 +3299,7 @@ typedef struct #else #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) -#endif +#endif /* ADC345_COMMON */ /** * @brief Helper macro to define the ADC conversion data full-scale digital @@ -2454,6 +3366,32 @@ typedef struct / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ ) +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) in + * differential ended mode. + * @note ADC data from ADC data register is unsigned and centered around + * middle code in. Converted voltage can be positive or negative + * depending on differential input voltages. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__)\ +((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\ + / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\ + - (int32_t)(__VREFANALOG_VOLTAGE__)) + /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage @@ -2531,19 +3469,24 @@ typedef struct * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval Temperature (unit: degree Celsius) + * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value) */ #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ + __ADC_RESOLUTION__)\ +((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) \ + : \ + ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \ ) /** @@ -2575,12 +3518,15 @@ typedef struct * @note ADC measurement data must correspond to a resolution of 12 bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + * (unit: uV/DegCelsius). * On STM32G4, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). - * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value + * (at temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32G4, refer to datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage + * (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: @@ -2659,7 +3605,7 @@ typedef struct * @retval ADC register address */ #if defined(ADC_MULTIMODE_SUPPORT) -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { uint32_t data_reg_addr; @@ -2677,7 +3623,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis return data_reg_addr; } #else -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { /* Prevent unused argument(s) compilation warning */ (void)(Register); @@ -2691,7 +3637,8 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis * @} */ -/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several + * ADC instances * @{ */ @@ -2757,7 +3704,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); } @@ -2776,7 +3723,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) * temperature sensor stabilization time. * Refer to device datasheet. * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. - * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. * @note ADC internal channel sampling time constraint: * For ADC conversion of internal channels, * a sampling time minimum value is required. @@ -2811,7 +3759,8 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO * temperature sensor stabilization time. * Refer to device datasheet. * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. - * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. * @note ADC internal channel sampling time constraint: * For ADC conversion of internal channels, * a sampling time minimum value is required. @@ -2874,7 +3823,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); } @@ -2922,7 +3871,9 @@ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t Sin { MODIFY_REG(ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, - CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); + CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) + >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) + & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); } /** @@ -2941,15 +3892,16 @@ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t Sin * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff) { /* Retrieve bits with position in register depending on parameter */ /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ return (uint32_t)(READ_BIT(ADCx->CALFACT, - (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> - ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); + (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) + >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> + ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); } /** @@ -2986,7 +3938,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); } @@ -3021,7 +3973,7 @@ __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAli * @arg @ref LL_ADC_DATA_ALIGN_RIGHT * @arg @ref LL_ADC_DATA_ALIGN_LEFT */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN)); } @@ -3054,12 +4006,6 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * conversion to ensure that conversion is completed and * retrieve ADC conversion data. This will trig another * ADC conversion start. - * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): - * the ADC automatically powers-off after a conversion and - * automatically wakes up when a new conversion is triggered - * (with startup time between trigger and start of sampling). - * This feature can be combined with low power mode "auto wait". * @note With ADC low power mode "auto wait", the ADC conversion data read * is corresponding to previous ADC conversion start, independently * of delay during which ADC was idle. @@ -3110,12 +4056,6 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * conversion to ensure that conversion is completed and * retrieve ADC conversion data. This will trig another * ADC conversion start. - * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): - * the ADC automatically powers-off after a conversion and - * automatically wakes up when a new conversion is triggered - * (with startup time between trigger and start of sampling). - * This feature can be combined with low power mode "auto wait". * @note With ADC low power mode "auto wait", the ADC conversion data read * is corresponding to previous ADC conversion start, independently * of delay during which ADC was idle. @@ -3128,13 +4068,13 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); } /** - * @brief Set ADC selected offset number 1, 2, 3 or 4. + * @brief Set ADC selected offset instance 1, 2, 3 or 4. * @note This function set the 2 items of offset configuration: * - ADC channel to which the offset programmed will be applied * (independently of channel mapped on ADC group regular @@ -3211,9 +4151,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ @@ -3227,7 +4170,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 } /** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * Channel to which the offset programmed will be applied * (independently of channel mapped on ADC group regular * or group injected) @@ -3293,14 +4236,17 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3308,7 +4254,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off } /** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * Offset level (offset to be subtracted from the raw * converted data). * @note Caution: Offset format is dependent to ADC resolution: @@ -3326,7 +4272,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off * @arg @ref LL_ADC_OFFSET_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3334,7 +4280,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse } /** - * @brief Set for the ADC selected offset number 1, 2, 3 or 4: + * @brief Set for the ADC selected offset instance 1, 2, 3 or 4: * force offset state disable or enable * without modifying offset channel or offset value. * @note This function should be needed only in case of offset to be @@ -3369,7 +4315,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, } /** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * offset state disabled or enabled. * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n @@ -3385,7 +4331,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3393,7 +4339,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse } /** - * @brief Set for the ADC selected offset number 1, 2, 3 or 4: + * @brief Set for the ADC selected offset instance 1, 2, 3 or 4: * choose offset sign. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: @@ -3424,7 +4370,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u } /** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * offset sign if positive or negative. * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n @@ -3440,7 +4386,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3448,7 +4394,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offset } /** - * @brief Set for the ADC selected offset number 1, 2, 3 or 4: + * @brief Set for the ADC selected offset instance 1, 2, 3 or 4: * choose offset saturation mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: @@ -3479,7 +4425,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offs } /** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * offset saturation if enabled or disabled. * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n * OFR2 SATEN LL_ADC_GetOffsetSaturation\n @@ -3495,7 +4441,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offs * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3537,9 +4483,10 @@ __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t Gain * 0 Gain compensation is disabled * 1 -> 16393 Gain compensation is enabled with returned value */ -__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx) { - return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL); + return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? + READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL); } #if defined(ADC_SMPR1_SMPPLUS) @@ -3571,7 +4518,7 @@ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint3 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 */ -__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS)); } @@ -3592,7 +4539,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other - * STM32 families having this setting set by HW default value). + * STM32 series having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_REG_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer @@ -3648,7 +4595,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) @@ -3715,21 +4663,22 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { - __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); + __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL) - | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN) + return ((trigger_source + & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN) ); } @@ -3744,7 +4693,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); } @@ -3779,7 +4728,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); } @@ -3817,7 +4766,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t Samp * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG)); } @@ -3930,7 +4879,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); } @@ -3985,7 +4934,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); } @@ -4083,9 +5032,12 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) @@ -4094,11 +5046,13 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, + ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), - ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } /** @@ -4194,16 +5148,20 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, + ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -4247,7 +5205,7 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); } @@ -4322,7 +5280,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATr * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); } @@ -4361,7 +5319,7 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); } @@ -4381,7 +5339,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other - * STM32 families having this setting set by HW default value). + * STM32 series having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_INJ_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer @@ -4436,7 +5394,8 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) @@ -4502,21 +5461,22 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx) { - __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL) - | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN) + return ((trigger_source + & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL) + | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN) ); } @@ -4531,7 +5491,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } @@ -4566,7 +5526,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); } @@ -4613,7 +5573,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); } @@ -4646,7 +5606,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); } @@ -4715,9 +5675,12 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) @@ -4727,8 +5690,10 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ MODIFY_REG(ADCx->JSQR, - (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), - ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); } /** @@ -4796,17 +5761,21 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, - (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -4855,7 +5824,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); } @@ -4916,7 +5885,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMo * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); } @@ -4999,7 +5968,8 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for + * more details. * @param ExternalTriggerEdge This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING @@ -5051,9 +6021,12 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @param Rank2_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) @@ -5093,9 +6066,12 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @param Rank3_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) @@ -5135,9 +6111,12 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @param Rank4_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) @@ -5177,9 +6156,12 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, @@ -5208,10 +6190,14 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, ADC_JSQR_JL, (TriggerSource & ADC_JSQR_JEXTSEL) | (ExternalTriggerEdge * (is_trigger_not_sw)) | - (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | - (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | - (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | - (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) | SequencerNbRanks ); } @@ -5309,9 +6295,12 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @param SamplingTime This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 @@ -5333,7 +6322,8 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, + ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), @@ -5410,9 +6400,12 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. + * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to + * convert in 12-bit resolution. + * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles + * (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 @@ -5427,12 +6420,14 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * can be replaced by 3.5 ADC clock cycles. * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) + >> ADC_SMPRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, - ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) + ADC_SMPR1_SMP0 + << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) ); } @@ -5494,20 +6489,13 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { - /* Bits for single or differential mode selection for each channel are set */ - /* to 1 only when the differential mode is selected, and to 0 when the */ - /* single mode is selected. */ - - if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED) - { - SET_BIT(ADCx->DIFSEL, - Channel & ADC_SINGLEDIFF_CHANNEL_MASK); - } - else - { - CLEAR_BIT(ADCx->DIFSEL, - Channel & ADC_SINGLEDIFF_CHANNEL_MASK); - } + /* Bits of channels in single or differential mode are set only for */ + /* differential mode (for single mode, mask of bits allowed to be set is */ + /* shifted out of range of bits of channels in single or differential mode. */ + MODIFY_REG(ADCx->DIFSEL, + Channel & ADC_SINGLEDIFF_CHANNEL_MASK, + (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) + & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); } /** @@ -5557,7 +6545,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * @arg @ref LL_ADC_CHANNEL_15 * @retval 0: channel in single-ended mode, else: channel in differential mode */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel) { return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); } @@ -5719,7 +6707,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet + * for more details. * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) @@ -5728,8 +6717,10 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) + * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), @@ -5858,60 +6849,62 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * * (0) On STM32G4, parameter available only on analog watchdog number: AWD1. */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) + * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK); + uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); - /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ + /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ - if (AnalogWDMonitChannels != 0UL) + if (analog_wd_monit_channels != 0UL) { if (AWDy == LL_ADC_AWD1) { - if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) + if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ((AnalogWDMonitChannels - | (ADC_AWD_CR23_CHANNEL_MASK) - ) - & (~(ADC_CFGR_AWD1CH)) - ); + analog_wd_monit_channels = ((analog_wd_monit_channels + | (ADC_AWD_CR23_CHANNEL_MASK) + ) + & (~(ADC_CFGR_AWD1CH)) + ); } else { /* AWD monitoring a single channel */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos)) - ); + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos)) + ); } } else { - if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK - | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) - ); + analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK + | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) + ); } else { /* AWD monitoring a single channel */ /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) - | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) - ); + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos) + ); } } } - return AnalogWDMonitChannels; + return analog_wd_monit_channels; } /** @@ -5947,6 +6940,16 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * impacted: the comparison of analog watchdog thresholds is done on * oversampling final computation (after ratio and shift application): * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n @@ -5970,7 +6973,8 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, @@ -6010,6 +7014,16 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * impacted: the comparison of analog watchdog thresholds is done on * oversampling final computation (after ratio and shift application): * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. * @note On this STM32 series, setting of this feature is not conditioned to * ADC state: * ADC can be disabled, enabled with or without conversion on going @@ -6075,7 +7089,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, + uint32_t AWDy, uint32_t AWDThresholdsHighLow) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); @@ -6134,7 +7149,7 @@ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES */ -__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy) { /* Prevent unused argument(s) compilation warning */ (void)(AWDy); @@ -6151,7 +7166,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, /** * @brief Set ADC oversampling scope: ADC groups regular and-or injected - * (availability of ADC group injected depends on STM32 families). + * (availability of ADC group injected depends on STM32 series). * @note If both groups regular and injected are selected, * specify behavior of ADC group injected interrupting * group regular: when ADC group injected is triggered, @@ -6181,7 +7196,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs /** * @brief Get ADC oversampling scope: ADC groups regular and-or injected - * (availability of ADC group injected depends on STM32 families). + * (availability of ADC group injected depends on STM32 series). * @note If both groups regular and injected are selected, * specify behavior of ADC group injected interrupting * group regular: when ADC group injected is triggered, @@ -6199,7 +7214,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); } @@ -6245,7 +7260,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); } @@ -6304,7 +7319,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); } @@ -6325,7 +7340,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } @@ -6389,7 +7404,7 @@ __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint3 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ -__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); } @@ -6486,7 +7501,7 @@ __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); } @@ -6554,7 +7569,7 @@ __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_C * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n * (3) Parameter available only if ADC resolution is 12 bits. */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); } @@ -6617,7 +7632,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } @@ -6666,7 +7681,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } @@ -6726,7 +7741,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } @@ -6737,7 +7752,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } @@ -6781,7 +7796,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleD * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } @@ -6848,7 +7863,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } @@ -6859,7 +7874,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } @@ -6915,7 +7930,7 @@ __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -6930,7 +7945,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -6945,7 +7960,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -6960,7 +7975,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -6975,7 +7990,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7002,7 +8017,8 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_MULTI_MASTER_SLAVE * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, + uint32_t ConversionData) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) @@ -7073,7 +8089,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } @@ -7084,7 +8100,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } @@ -7106,9 +8122,10 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank) { - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7133,9 +8150,10 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank) { - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7160,9 +8178,10 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank) { - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7187,9 +8206,10 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank) { - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7214,9 +8234,10 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank) { - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7240,7 +8261,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } @@ -7251,7 +8272,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } @@ -7262,7 +8283,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } @@ -7273,7 +8294,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } @@ -7284,7 +8305,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } @@ -7295,7 +8316,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } @@ -7306,7 +8327,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } @@ -7317,7 +8338,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } @@ -7328,7 +8349,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } @@ -7339,7 +8360,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } @@ -7350,7 +8371,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } @@ -7487,7 +8508,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); } @@ -7499,7 +8520,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); } @@ -7511,7 +8532,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7523,7 +8544,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7535,7 +8556,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); } @@ -7547,7 +8568,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); } @@ -7559,7 +8580,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); } @@ -7571,7 +8592,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); } @@ -7583,7 +8604,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); } @@ -7595,7 +8616,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); } @@ -7607,7 +8628,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); } @@ -7619,7 +8640,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); } @@ -7631,7 +8652,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); } @@ -7643,7 +8664,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); } @@ -7655,7 +8676,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); } @@ -7667,7 +8688,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); } @@ -7679,7 +8700,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); } @@ -7691,7 +8712,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); } @@ -7703,7 +8724,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); } @@ -7715,7 +8736,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); } @@ -7727,7 +8748,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); } @@ -7739,7 +8760,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); } @@ -8002,7 +9023,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } @@ -8014,7 +9035,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } @@ -8026,7 +9047,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } @@ -8038,7 +9059,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } @@ -8050,7 +9071,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } @@ -8062,7 +9083,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } @@ -8074,7 +9095,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } @@ -8086,7 +9107,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } @@ -8098,7 +9119,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } @@ -8110,7 +9131,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } @@ -8122,7 +9143,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } @@ -8137,25 +9158,25 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) */ /* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); /* De-initialization of ADC instance, ADC group regular and ADC group injected */ -/* (availability of ADC group injected depends on STM32 families) */ +/* (availability of ADC group injected depends on STM32 series) */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); /* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct); /* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); /* Initialization of some features of ADC instance and ADC group injected */ -ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); -void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct); +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_comp.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_comp.h index 52de521aea..0a7ca2d330 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_comp.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_comp.h @@ -63,28 +63,28 @@ typedef struct { uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputPlus(). */ uint32_t InputMinus; /*!< Set comparator input minus (inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputMinus(). */ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputHysteresis(). */ uint32_t OutputPolarity; /*!< Set comparator output polarity. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputPolarity(). */ uint32_t OutputBlankingSource; /*!< Set comparator blanking source. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputBlankingSource(). */ } LL_COMP_InitTypeDef; @@ -121,7 +121,7 @@ typedef struct #define LL_COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */ #define LL_COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */ #define LL_COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */ -#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */ +#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */ #define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */ /** @@ -362,7 +362,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @arg @ref LL_COMP_INPUT_PLUS_IO1 * @arg @ref LL_COMP_INPUT_PLUS_IO2 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL)); } @@ -437,7 +437,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_IO1 * @arg @ref LL_COMP_INPUT_MINUS_IO2 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN)); } @@ -479,7 +479,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_60MV * @arg @ref LL_COMP_HYSTERESIS_70MV */ -__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST)); } @@ -514,7 +514,7 @@ __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t Out * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED * @arg @ref LL_COMP_OUTPUTPOL_INVERTED */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY)); } @@ -617,7 +617,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * those without COMPx suffix that are common to all instances) * Note: For COMPx & TIMx instances availability, please refer to datasheet */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING)); } @@ -662,7 +662,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL); } @@ -689,7 +689,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL); } @@ -708,7 +708,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE) >> COMP_CSR_VALUE_Pos); @@ -724,7 +724,7 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) */ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx); -ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct); +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct); void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); /** diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h index 71d42fd0b4..8adb69beb8 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h @@ -241,13 +241,13 @@ extern "C" { * - @ref LL_CORDIC_SetNbRead() * - @ref LL_CORDIC_SetInSize() * - @ref LL_CORDIC_SetOutSize() - * @rmtoll CSR FUNC LL_CORDIC_Configure\n - * CSR PRECISION LL_CORDIC_Configure\n - * CSR SCALE LL_CORDIC_Configure\n - * CSR NARGS LL_CORDIC_Configure\n - * CSR NRES LL_CORDIC_Configure\n - * CSR ARGSIZE LL_CORDIC_Configure\n - * CSR RESIZE LL_CORDIC_Configure + * @rmtoll CSR FUNC LL_CORDIC_Config\n + * CSR PRECISION LL_CORDIC_Config\n + * CSR SCALE LL_CORDIC_Config\n + * CSR NARGS LL_CORDIC_Config\n + * CSR NRES LL_CORDIC_Config\n + * CSR ARGSIZE LL_CORDIC_Config\n + * CSR RESIZE LL_CORDIC_Config * @param CORDICx CORDIC instance * @param Function parameter can be one of the following values: * @arg @ref LL_CORDIC_FUNCTION_COSINE @@ -347,7 +347,7 @@ __STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Fun * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT */ -__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC)); } @@ -400,7 +400,7 @@ __STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Pr * @arg @ref LL_CORDIC_PRECISION_14CYCLES * @arg @ref LL_CORDIC_PRECISION_15CYCLES */ -__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION)); } @@ -439,7 +439,7 @@ __STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale) * @arg @ref LL_CORDIC_SCALE_6 * @arg @ref LL_CORDIC_SCALE_7 */ -__STATIC_INLINE uint32_t LL_CORDIC_GetScale(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetScale(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE)); } @@ -466,7 +466,7 @@ __STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWr * @arg @ref LL_CORDIC_NBWRITE_1 * @arg @ref LL_CORDIC_NBWRITE_2 */ -__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS)); } @@ -493,7 +493,7 @@ __STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRea * @arg @ref LL_CORDIC_NBREAD_1 * @arg @ref LL_CORDIC_NBREAD_2 */ -__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES)); } @@ -520,7 +520,7 @@ __STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSiz * @arg @ref LL_CORDIC_INSIZE_32BITS * @arg @ref LL_CORDIC_INSIZE_16BITS */ -__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE)); } @@ -547,7 +547,7 @@ __STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutS * @arg @ref LL_CORDIC_OUTSIZE_32BITS * @arg @ref LL_CORDIC_OUTSIZE_16BITS */ -__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE)); } @@ -588,7 +588,7 @@ __STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx) * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U); } @@ -629,7 +629,7 @@ __STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx) * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U); } @@ -662,7 +662,7 @@ __STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx) * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); } @@ -677,7 +677,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx) * @arg @ref LL_CORDIC_DMA_REG_DATA_OUT * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(const CORDIC_TypeDef *CORDICx, uint32_t Direction) { uint32_t data_reg_addr; @@ -709,7 +709,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint3 * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U); } @@ -740,7 +740,7 @@ __STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InDat * @param CORDICx CORDIC Instance * @retval 32-bit output data of CORDIC processing. */ -__STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_REG(CORDICx->RDATA)); } @@ -755,7 +755,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx); +ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crc.h index 0ca92022a9..bd2072d95e 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crc.h @@ -184,7 +184,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySi * @arg @ref LL_CRC_POLYLENGTH_8B * @arg @ref LL_CRC_POLYLENGTH_7B */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); } @@ -215,7 +215,7 @@ __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD * @arg @ref LL_CRC_INDATA_REVERSE_WORD */ -__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); } @@ -242,7 +242,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT */ -__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); } @@ -270,7 +270,7 @@ __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) * @param CRCx CRC Instance * @retval Value programmed in Programmable initial CRC value register */ -__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->INIT)); } @@ -301,7 +301,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t Polyno * @param CRCx CRC Instance * @retval Value programmed in Programmable Polynomial value register */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->POL)); } @@ -359,7 +359,7 @@ __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). */ -__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->DR)); } @@ -371,7 +371,7 @@ __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). */ -__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) +__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx) { return (uint16_t)READ_REG(CRCx->DR); } @@ -383,7 +383,7 @@ __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx) { return (uint8_t)READ_REG(CRCx->DR); } @@ -395,7 +395,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx) { return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); } @@ -407,7 +407,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register). */ -__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->IDR)); } @@ -433,7 +433,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) * @{ */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h index b5c75eba48..7bad679f70 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h @@ -612,12 +612,10 @@ typedef struct * @arg @ref LL_DAC_RESOLUTION_8B * @retval DAC conversion data (unit: digital value) */ -#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ - __DAC_VOLTAGE__,\ - __DAC_RESOLUTION__) \ -((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ -) +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ + ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ + ) /** * @brief Helper macro to format sawtooth wave generation configuration @@ -628,13 +626,11 @@ typedef struct * @param __STEP_DATA__ sawtooth step data * @retval Sawtooth configuration organized in DAC_STRx compatible format. */ -#define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__,\ - __RESET_DATA__,\ - __STEP_DATA__) \ -( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \ - | ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \ - | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \ -) +#define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__, __RESET_DATA__, __STEP_DATA__) \ + ( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \ + | ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \ + | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \ + ) /** * @} @@ -676,7 +672,7 @@ __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t Hig * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ */ -__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *DACx) { return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL)); } @@ -684,6 +680,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx) * @} */ + /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels * @{ */ @@ -728,7 +725,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin * @arg @ref LL_DAC_MODE_NORMAL_OPERATION * @arg @ref LL_DAC_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -773,7 +770,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha * Refer to device datasheet for channels availability. * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ -__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -878,7 +875,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * (5) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -929,7 +926,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1001,7 +998,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1074,7 +1071,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1104,7 +1101,9 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint */ __STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, + (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & + DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); MODIFY_REG(*preg, DAC_STR1_STDIR1, @@ -1126,9 +1125,11 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT * @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, + (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); return (uint32_t) READ_BIT(*preg, DAC_STR1_STDIR1); } @@ -1155,7 +1156,9 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint3 */ __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, + (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & + DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); MODIFY_REG(*preg, DAC_STR1_STRSTDATA1, @@ -1176,15 +1179,17 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t * @retval Returned value is the sawtooth reset value. * Range is from 0 to DAC full range 4095 (0xFFF) */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, + (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); return (uint32_t)(READ_BIT(*preg, DAC_STR1_STRSTDATA1) >> DAC_STR1_STRSTDATA1_Pos); } /** - * @brief Set the swatooth waveform generation step data. + * @brief Set the sawtooth waveform generation step data. * @note For wave generation to be effective, DAC channel * wave generation mode must be enabled using * function @ref LL_DAC_SetWaveAutoGeneration(). @@ -1207,7 +1212,9 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(DAC_TypeDef *DACx, uint */ __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, + (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & + DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); MODIFY_REG(*preg, DAC_STR1_STINCDATA1, @@ -1230,15 +1237,17 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t * Step value step is 1/16 = 0.0625 * Step value range is 0.0000 to 4095.9375 (0xFFF.F) */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, + (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0); return (uint32_t)(READ_BIT(*preg, DAC_STR1_STINCDATA1) >> DAC_STR1_STINCDATA1_Pos); } /** - * @brief Set the swatooth waveform generation reset trigger source. + * @brief Set the sawtooth waveform generation reset trigger source. * @note For wave generation to be effective, DAC channel * wave generation mode must be enabled using * function @ref LL_DAC_SetWaveAutoGeneration(). @@ -1288,7 +1297,8 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, { MODIFY_REG(DACx->STMODR, DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), - ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + (((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos) + << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); } /** @@ -1331,7 +1341,7 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, * (5) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)((READ_BIT(DACx->STMODR, DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1386,7 +1396,9 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, { MODIFY_REG(DACx->STMODR, DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), - ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); + (((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos) + << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + )); } /** @@ -1424,7 +1436,7 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, * (3) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)((READ_BIT(DACx->STMODR, DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1533,7 +1545,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1582,7 +1594,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1647,7 +1659,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1695,7 +1707,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); @@ -1739,7 +1751,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1782,7 +1794,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3 * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1834,7 +1846,7 @@ __STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE */ -__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1905,7 +1917,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1964,7 +1976,7 @@ __STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->MCR, DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -2006,7 +2018,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, ui * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED * @retval DAC register address */ -__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ @@ -2076,7 +2088,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -2097,7 +2109,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsReady(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsReady(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->SR, DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -2164,7 +2176,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -2387,7 +2399,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); @@ -2409,7 +2421,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); } @@ -2421,7 +2433,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); } @@ -2433,7 +2445,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); } @@ -2444,7 +2456,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); } @@ -2456,7 +2468,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL); } @@ -2468,7 +2480,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL); } @@ -2480,7 +2492,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL); } @@ -2492,7 +2504,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL); } @@ -2503,7 +2515,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); } @@ -2515,7 +2527,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); } @@ -2607,7 +2619,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); } @@ -2619,7 +2631,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); } @@ -2634,8 +2646,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) * @{ */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); /** @@ -2662,4 +2674,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); #endif #endif /* STM32G4xx_LL_DAC_H */ - diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmac.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmac.h index c339a2fa5c..102cac0ff5 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmac.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmac.h @@ -48,11 +48,12 @@ extern "C" { * @brief Flag defines which can be used with LL_FMAC_ReadReg function * @{ */ -#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */ -#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ -#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ -#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ -#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */ +#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag + (this helps in debugging a filter) */ +#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ +#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ +#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ +#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */ /** * @} */ @@ -61,11 +62,12 @@ extern "C" { * @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions * @{ */ -#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */ -#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ -#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ -#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ -#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */ +#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable + (this helps in debugging a filter) */ +#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ +#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ +#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ +#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */ /** * @} */ @@ -74,10 +76,14 @@ extern "C" { * @brief Watermark defines that can be used for buffer full (input) or buffer empty (output) * @{ */ -#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */ -#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */ -#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */ -#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */ +#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there + is less than 1 free/unread space. */ +#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there + are less than 2 free/unread spaces. */ +#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there + are less than 4 free/unread spaces. */ +#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there + are less than 8 free/empty spaces. */ /** * @} */ @@ -85,11 +91,11 @@ extern "C" { /** @defgroup FMAC_LL_EC_FUNC FMAC functions * @{ */ -#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ -#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ -#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ -#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ -#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ +#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ /** * @} */ @@ -97,8 +103,8 @@ extern "C" { /** @defgroup FMAC_LL_EC_PROCESSING FMAC processing * @{ */ -#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */ -#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */ +#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */ +#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */ /** * @} */ @@ -178,7 +184,7 @@ __STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Wa * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 * @arg @ref LL_FMAC_WM_3_THRESHOLD_8 */ -__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(const FMAC_TypeDef *FMACx) { return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM)); } @@ -203,7 +209,7 @@ __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @retval uint8_t Number of 16-bit words allocated to the input buffer * (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos); } @@ -228,7 +234,7 @@ __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base) * @retval uint8_t Base address of the input buffer (X1) within the internal memory * (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos); } @@ -253,7 +259,7 @@ __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer * (value between Min_Data=0x01 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos); } @@ -278,7 +284,7 @@ __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base) * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory * (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos); } @@ -309,7 +315,7 @@ __STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Wa * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 * @arg @ref LL_FMAC_WM_3_THRESHOLD_8 */ -__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(const FMAC_TypeDef *FMACx) { return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM)); } @@ -334,7 +340,7 @@ __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferS * @retval uint8_t Number of 16-bit words allocated to the output buffer * (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos); } @@ -359,7 +365,7 @@ __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base) * @retval uint8_t Base address of the output buffer (Y) within the internal memory * (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetYBase(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos); } @@ -392,7 +398,7 @@ __STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL); } @@ -425,7 +431,7 @@ __STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function) * @arg @ref LL_FMAC_FUNC_CONVO_FIR * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1 */ -__STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_GetFunction(const FMAC_TypeDef *FMACx) { return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC)); } @@ -449,7 +455,7 @@ __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param) * @param FMACx FMAC instance * @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetParamR(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos); } @@ -473,7 +479,7 @@ __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param) * @param FMACx FMAC instance * @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos); } @@ -498,7 +504,7 @@ __STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param) * @retval uint8_t Parameter P (vector length, number of filter taps, etc.) * (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetParamP(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P)); } @@ -528,7 +534,7 @@ __STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL); } @@ -569,7 +575,7 @@ __STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL); } @@ -610,7 +616,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL); } @@ -643,7 +649,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL); } @@ -684,7 +690,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL); } @@ -717,7 +723,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL); } @@ -750,7 +756,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL); } @@ -783,7 +789,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL); } @@ -816,7 +822,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL); } @@ -835,7 +841,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL); } @@ -846,7 +852,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL); } @@ -857,7 +863,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL); } @@ -868,7 +874,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL); } @@ -879,7 +885,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL); } @@ -911,7 +917,7 @@ __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData) * @param FMACx FMAC instance * @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF). */ -__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint16_t LL_FMAC_ReadData(const FMAC_TypeDef *FMACx) { return (uint16_t)(READ_REG(FMACx->RDATA)); } @@ -1034,7 +1040,7 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @{ */ ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); -ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx); +ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); /** diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmc.h index a34e61a691..bddf9677db 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmc.h @@ -97,7 +97,7 @@ extern "C" { #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) #endif /* FMC_BANK1 */ -#if defined(FMC_BANK3) +#if defined(FMC_BANK3) #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ @@ -305,7 +305,7 @@ typedef struct delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ } FMC_NAND_InitTypeDef; -#endif +#endif /* FMC_BANK3 */ #if defined(FMC_BANK3) /** @@ -498,11 +498,13 @@ typedef struct * @} */ +#if defined(FMC_BCR1_WFDIS) /** @defgroup FMC_Write_FIFO FMC Write FIFO * @{ */ #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS #define FMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FMC_BCR1_WFDIS */ /** * @} */ @@ -691,7 +693,7 @@ typedef struct /** * @} */ -#endif +#endif /* FMC_BANK3 */ #if defined(FMC_BANK3) /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_hrtim.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_hrtim.h index 4b419859d4..7b2a7dbecb 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_hrtim.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_hrtim.h @@ -318,6 +318,16 @@ static const uint8_t REG_SHIFT_TAB_FLTxF[] = 40U /* LL_HRTIM_FAULT_6 */ }; +static const uint8_t REG_SHIFT_TAB_FLTxCNT[] = +{ + 2U, /* LL_HRTIM_FAULT_1 */ + 10U, /* LL_HRTIM_FAULT_2 */ + 18U, /* LL_HRTIM_FAULT_3 */ + 26U, /* LL_HRTIM_FAULT_4 */ + 2U, /* LL_HRTIM_FAULT_5 */ + 10U /* LL_HRTIM_FAULT_6 */ +}; + static const uint8_t REG_SHIFT_TAB_FLTx[] = { 0, /* LL_HRTIM_FAULT_1 */ @@ -2115,7 +2125,7 @@ __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncI * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT */ -__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN)); } @@ -2166,7 +2176,7 @@ __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t S * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE */ -__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT)); } @@ -2197,7 +2207,7 @@ __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t Sync * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 */ -__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC)); } @@ -2388,7 +2398,7 @@ __STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t * 0: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1, * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2 */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU); @@ -2495,7 +2505,7 @@ __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outp * @arg @ref LL_HRTIM_OUTPUT_TF2 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL); } @@ -2530,7 +2540,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_OUTPUT_TF2 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL); } @@ -2913,7 +2923,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t A * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F */ -__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) +__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + REG_OFFSET_TAB_ADCUR[ADCTrig])); @@ -3512,7 +3522,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER */ -__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) +__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCER[ADCTrig])); @@ -3589,7 +3599,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t A * @arg @ref LL_HRTIM_ADCTRIG_10 * @retval PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_HRTIM_GetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) +__STATIC_INLINE uint32_t LL_HRTIM_GetADCPostScaler(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { uint32_t reg1 = READ_REG(HRTIMx->sCommonRegs.ADCPS1); @@ -3711,7 +3721,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL); } @@ -3772,7 +3782,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3827,7 +3837,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_MODE_SINGLESHOT * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3897,7 +3907,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_TIMER_F * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3971,7 +3981,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_TIMER_F * @retval State of RSYNC bit in HRTIM_TIMxCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + @@ -4039,7 +4049,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE * @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -4107,7 +4117,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_TIMER_F * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -4174,7 +4184,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_TIMER_F * @retval None */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -4228,7 +4238,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -4297,7 +4307,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -4388,7 +4398,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION * @arg @ref LL_HRTIM_UPDATETRIG_RESET */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -4465,7 +4475,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -4527,7 +4537,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_TIMER_F * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + @@ -4589,7 +4599,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + @@ -4643,7 +4653,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval Counter Value between 0 and 0xFFFF */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + @@ -4690,7 +4700,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_F * @retval Period Value between 0 and 0xFFFF */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + @@ -4737,7 +4747,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval Repetition Value between 0 and 0xFF */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + @@ -4788,7 +4798,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + @@ -4839,7 +4849,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + @@ -4890,7 +4900,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + @@ -4941,7 +4951,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + @@ -5118,7 +5128,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + @@ -5139,7 +5149,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32 * @arg @ref LL_HRTIM_TIMER_F * @retval Captured value */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + @@ -5162,7 +5172,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_COUNTING_MODE_UP * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + @@ -5183,7 +5193,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_TIMER_F * @retval Captured value */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + @@ -5206,7 +5216,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_COUNTING_MODE_UP * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + @@ -5407,7 +5417,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2 */ -__STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) +__STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + @@ -5476,7 +5486,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_TIMER_F * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -5564,7 +5574,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -5629,7 +5639,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -5694,7 +5704,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Ti * @arg @ref LL_HRTIM_TIMER_F * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -5794,7 +5804,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_FAULT_6 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + @@ -5877,7 +5887,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer); @@ -6000,7 +6010,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -6023,7 +6033,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HR * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -6221,7 +6231,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); @@ -6312,7 +6322,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_EELATCH_DISABLED * @arg @ref LL_HRTIM_EELATCH_ENABLED */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); @@ -6366,7 +6376,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, ui * @arg @ref LL_HRTIM_TRIGHALF_ENABLED * @arg @ref LL_HRTIM_TRIGHALF_DISABLED */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6419,7 +6429,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_GTCMP1_EQUAL * @arg @ref LL_HRTIM_GTCMP1_GREATER */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6472,7 +6482,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_GTCMP3_EQUAL * @arg @ref LL_HRTIM_GTCMP3_GREATER */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) + @@ -6524,7 +6534,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6575,7 +6585,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIM * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6626,7 +6636,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6677,7 +6687,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6730,7 +6740,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6784,7 +6794,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN * @retval None */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6833,7 +6843,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_DCDR_COUNTER * @arg @ref LL_HRTIM_DCDR_OUT1SET */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6880,7 +6890,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_DCDS_CMP2 * @arg @ref LL_HRTIM_DCDS_OUT1RST */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -6944,7 +6954,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_TIMER_F * @retval State of DCDE bit in HRTIM_TIMxCR2 register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + @@ -7000,7 +7010,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_EE_COUNTER_B * @retval Threshold Value between Min_Data=0 and Max_Data=63 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); @@ -7080,7 +7090,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_EVENT_9 * @arg @ref LL_HRTIM_EVENT_10 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); @@ -7141,7 +7151,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); @@ -7243,7 +7253,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_EE_COUNTER_B * @retval State of EEVxCE bit in RTIM_EEFxR3 register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); @@ -7341,7 +7351,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16 */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -7384,7 +7394,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval RisingValue Value between 0 and 0x1FF */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -7431,7 +7441,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_DT_RISING_POSITIVE * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -7474,7 +7484,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval FallingValue Value between 0 and 0x1FF */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -7521,7 +7531,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -7542,7 +7552,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_TIMER_F * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -7720,7 +7730,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + @@ -7782,7 +7792,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875 */ -__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + @@ -7859,7 +7869,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256 */ -__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + @@ -8204,7 +8214,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE * (source = TIMy and destination = TIMx, Compare Unit = CMPz). */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + @@ -8541,7 +8551,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE * (source = TIMy and destination = TIMx, Compare Unit = CMPz). */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + @@ -8648,7 +8658,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -8710,7 +8720,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou * @arg @ref LL_HRTIM_OUT_NO_IDLE * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -8773,7 +8783,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -8840,7 +8850,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -8902,7 +8912,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -8964,7 +8974,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -8995,7 +9005,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + @@ -9065,7 +9075,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + @@ -9224,7 +9234,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u * @arg External event source 3 * @arg External event source 4 */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + @@ -9299,7 +9309,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve * @arg @ref LL_HRTIM_EE_POLARITY_HIGH * @arg @ref LL_HRTIM_EE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + @@ -9377,7 +9387,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + @@ -9441,7 +9451,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + @@ -9521,7 +9531,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event * @arg @ref LL_HRTIM_EE_FILTER_14 * @arg @ref LL_HRTIM_EE_FILTER_15 */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6)); return (READ_BIT(HRTIMx->sCommonRegs.EECR3, @@ -9556,7 +9566,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Pr * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8 */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD)); } @@ -9675,7 +9685,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL * @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); @@ -9754,7 +9764,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa * @arg @ref LL_HRTIM_FLT_POLARITY_LOW * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); @@ -9856,7 +9866,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul * @arg @ref LL_HRTIM_FLT_FILTER_14 * @arg @ref LL_HRTIM_FLT_FILTER_15 */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); @@ -9900,7 +9910,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t P * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8 */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD)); } @@ -10002,7 +10012,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) * @arg @ref LL_HRTIM_FAULT_6 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + @@ -10081,7 +10091,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_FAULT_6 * @retval State of FLTxBLKE bit in HRTIM_FLTINRx register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + @@ -10143,7 +10153,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_FAULT_5 * @arg @ref LL_HRTIM_FAULT_6 */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + @@ -10176,7 +10186,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uin uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); - MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxE[iFault])); + MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxCNT[iFault])); } /** @@ -10197,12 +10207,12 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_FAULT_6 * @retval Threshold This parameter can be a number between Min_Data=0 and Max_Data=15 */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); - return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]); + return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxCNT[iFault]); } /** @@ -10255,22 +10265,22 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t F * @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL * @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); - return READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]); + return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]); } /** * @brief Reset the fault counter for a fault circuitry - * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_ResetCounter\n - * FLTINR3 FLT2RSTM LL_HRTIM_FLT_ResetCounter\n - * FLTINR3 FLT3RSTM LL_HRTIM_FLT_ResetCounter\n - * FLTINR3 FLT4RSTM LL_HRTIM_FLT_ResetCounter\n - * FLTINR4 FLT5RSTM LL_HRTIM_FLT_ResetCounter\n - * FLTINR4 FLT6RSTM LL_HRTIM_FLT_ResetCounter + * @rmtoll FLTINR3 FLT1CRES LL_HRTIM_FLT_ResetCounter\n + * FLTINR3 FLT2CRES LL_HRTIM_FLT_ResetCounter\n + * FLTINR3 FLT3CRES LL_HRTIM_FLT_ResetCounter\n + * FLTINR3 FLT4CRES LL_HRTIM_FLT_ResetCounter\n + * FLTINR4 FLT5CRES LL_HRTIM_FLT_ResetCounter\n + * FLTINR4 FLT6CRES LL_HRTIM_FLT_ResetCounter * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: * @arg @ref LL_HRTIM_FAULT_1 @@ -10337,7 +10347,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode) * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM); } @@ -10393,7 +10403,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t Clo * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK); } @@ -10448,7 +10458,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Pr * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768 */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC); } @@ -10481,7 +10491,7 @@ __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx) { uint32_t temp; /* MISRAC-2012 compliance */ temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); @@ -10633,7 +10643,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig) * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR); } @@ -10660,7 +10670,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t Comp * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR); } @@ -10687,7 +10697,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Perio * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... * The maximum value is 0x0000 FFDF. */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER); } @@ -10720,7 +10730,7 @@ __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of BME bit in HRTIM_BMCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL); } @@ -10756,7 +10766,7 @@ __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx) * @arg @ref LL_HRTIM_BM_STATUS_NORMAL * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT)); } @@ -10786,7 +10796,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL); } @@ -10808,7 +10818,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL); } @@ -10830,7 +10840,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL); } @@ -10852,7 +10862,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL); } @@ -10874,7 +10884,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL); } @@ -10896,7 +10906,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT6 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT6(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT6(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT6) == (HRTIM_ISR_FLT6)) ? 1UL : 0UL); } @@ -10918,7 +10928,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL); } @@ -10940,7 +10950,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY)) ? 1UL : 0UL); } @@ -10962,7 +10972,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of BMPER bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL); } @@ -10984,7 +10994,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYNC bit in HRTIM_MISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL); } @@ -11027,7 +11037,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_F * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11075,7 +11085,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_F * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11122,7 +11132,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11169,7 +11179,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11216,7 +11226,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11263,7 +11273,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11306,7 +11316,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11349,7 +11359,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11392,7 +11402,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11435,7 +11445,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11478,7 +11488,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11521,7 +11531,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11564,7 +11574,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_F * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11607,7 +11617,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_F * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -11652,7 +11662,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); } @@ -11685,7 +11695,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL); } @@ -11718,7 +11728,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL); } @@ -11751,7 +11761,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL); } @@ -11784,7 +11794,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL); } @@ -11817,7 +11827,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT6IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT6(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT6(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6) == (HRTIM_IER_FLT6)) ? 1UL : 0UL); } @@ -11850,7 +11860,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL); } @@ -11883,7 +11893,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY)) ? 1UL : 0UL); } @@ -11916,7 +11926,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL); } @@ -11949,7 +11959,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL); } @@ -12015,7 +12025,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_F * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12085,7 +12095,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_F * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12155,7 +12165,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12225,7 +12235,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12295,7 +12305,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12365,7 +12375,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12429,7 +12439,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12493,7 +12503,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12557,7 +12567,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12621,7 +12631,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12685,7 +12695,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12749,7 +12759,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_F * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12813,7 +12823,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_F * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12877,7 +12887,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_F * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -12922,7 +12932,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL); } @@ -12988,7 +12998,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 * @arg @ref LL_HRTIM_TIMER_F * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13058,7 +13068,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13128,7 +13138,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13198,7 +13208,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13268,7 +13278,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13338,7 +13348,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13402,7 +13412,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13466,7 +13476,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13530,7 +13540,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13594,7 +13604,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13658,7 +13668,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13722,7 +13732,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13786,7 +13796,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_F * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -13850,7 +13860,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 * @arg @ref LL_HRTIM_TIMER_F * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h index f419f796b6..e64ae9288b 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h @@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); } @@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); } @@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); } @@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); } @@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); } @@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) { uint32_t data_reg_addr; @@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); } @@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); } @@ -737,7 +737,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); } @@ -772,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); } @@ -800,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT */ -__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); } @@ -849,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); } @@ -905,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); } @@ -930,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); } @@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); } @@ -952,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); } @@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); } @@ -974,7 +974,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); } @@ -1011,7 +1011,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) * @arg @ref LL_I2C_MODE_SMBUS_DEVICE * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP */ -__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); } @@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); } @@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); } @@ -1150,7 +1150,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); } @@ -1182,7 +1182,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); } @@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); } @@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ (ClockTimeout)) ? 1UL : 0UL); @@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); } @@ -1339,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); } @@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); } @@ -1405,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); } @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); } @@ -1477,7 +1477,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); } @@ -1528,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); } @@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); } @@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); } @@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); } @@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); } @@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); } @@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); } @@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); } @@ -1653,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); } @@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); } @@ -1679,7 +1679,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); } @@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); } @@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); } @@ -1725,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); } @@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); } @@ -1899,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); } @@ -1934,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); } @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); } @@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); } @@ -2063,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans * @arg @ref LL_I2C_REQUEST_WRITE * @arg @ref LL_I2C_REQUEST_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); } @@ -2087,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); } @@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** @@ -2150,7 +2157,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr * @arg @ref LL_I2C_DIRECTION_WRITE * @arg @ref LL_I2C_DIRECTION_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); } @@ -2161,7 +2168,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); } @@ -2191,7 +2198,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); } @@ -2204,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); } @@ -2215,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) { return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); } @@ -2241,8 +2248,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) * @{ */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); -ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_iwdg.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_iwdg.h index 54257f0a43..a4a9d89f45 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_iwdg.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_iwdg.h @@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale * @arg @ref LL_IWDG_PRESCALER_128 * @arg @ref LL_IWDG_PRESCALER_256 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->WINR)); } @@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lptim.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lptim.h index ccdfc9c1b8..7465bccb32 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lptim.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lptim.h @@ -346,14 +346,27 @@ typedef struct * @{ */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM +/** +@endcond + */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions * @{ */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); /** * @} @@ -383,7 +396,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); } @@ -479,7 +492,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); } @@ -494,7 +507,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) * @note autoreload value be strictly greater than the compare value. * @rmtoll ARR ARR LL_LPTIM_SetAutoReload * @param LPTIMx Low-Power Timer instance - * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF * @retval None */ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) @@ -506,9 +519,9 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto * @brief Get actual auto reload value * @rmtoll ARR ARR LL_LPTIM_GetAutoReload * @param LPTIMx Low-Power Timer instance - * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } @@ -535,7 +548,7 @@ __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t Compare * @param LPTIMx Low-Power Timer instance * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP)); } @@ -550,7 +563,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval Counter value */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); } @@ -578,7 +591,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); } @@ -627,7 +640,7 @@ __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Wavefo * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); } @@ -654,7 +667,7 @@ __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polari * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); } @@ -698,7 +711,7 @@ __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Presc * @arg @ref LL_LPTIM_PRESCALER_DIV64 * @arg @ref LL_LPTIM_PRESCALER_DIV128 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); } @@ -783,7 +796,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } @@ -863,7 +876,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour * * (*) Value not defined in all devices. \n */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); } @@ -878,7 +891,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_FILTER_4 * @arg @ref LL_LPTIM_TRIG_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); } @@ -892,7 +905,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); } @@ -928,7 +941,7 @@ __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t Clo * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); } @@ -970,7 +983,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockF * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -985,7 +998,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_CLK_FILTER_4 * @arg @ref LL_LPTIM_CLK_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); } @@ -1023,7 +1036,7 @@ __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t Enc * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -1062,7 +1075,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } @@ -1075,13 +1088,14 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) * @{ */ + /** * @brief Clear the compare match flag (CMPMCF) - * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM + * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); } @@ -1092,18 +1106,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** * @brief Clear the autoreload match flag (ARRMCF) - * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); } @@ -1114,7 +1128,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } @@ -1136,7 +1150,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } @@ -1159,7 +1173,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } @@ -1182,7 +1196,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } @@ -1205,7 +1219,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } @@ -1228,7 +1242,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } @@ -1269,7 +1283,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } @@ -1302,7 +1316,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } @@ -1335,7 +1349,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } @@ -1368,7 +1382,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } @@ -1401,7 +1415,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } @@ -1434,7 +1448,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } @@ -1467,7 +1481,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h index bc962b9c71..e3f996ac17 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h @@ -522,7 +522,7 @@ __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } @@ -555,7 +555,7 @@ __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } @@ -590,7 +590,7 @@ __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); } @@ -625,7 +625,7 @@ __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); } @@ -689,7 +689,7 @@ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } @@ -767,7 +767,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint * @arg @ref LL_LPUART_DIRECTION_TX * @arg @ref LL_LPUART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -801,7 +801,7 @@ __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity * @arg @ref LL_LPUART_PARITY_EVEN * @arg @ref LL_LPUART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -828,7 +828,7 @@ __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t * @arg @ref LL_LPUART_WAKEUP_IDLELINE * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); } @@ -857,7 +857,7 @@ __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t Dat * @arg @ref LL_LPUART_DATAWIDTH_8B * @arg @ref LL_LPUART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); } @@ -890,7 +890,7 @@ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } @@ -937,7 +937,7 @@ __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t Pre * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); } @@ -964,7 +964,7 @@ __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_ * @arg @ref LL_LPUART_STOPBITS_1 * @arg @ref LL_LPUART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); } @@ -1022,7 +1022,7 @@ __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t Swap * @arg @ref LL_LPUART_TXRX_STANDARD * @arg @ref LL_LPUART_TXRX_SWAPPED */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); } @@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); } @@ -1076,7 +1076,7 @@ __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); } @@ -1106,7 +1106,7 @@ __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE */ -__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); } @@ -1137,7 +1137,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint3 * @arg @ref LL_LPUART_BITORDER_LSBFIRST * @arg @ref LL_LPUART_BITORDER_MSBFIRST */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); } @@ -1181,7 +1181,7 @@ __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_ * @param LPUARTx LPUART Instance * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } @@ -1194,7 +1194,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) * @arg @ref LL_LPUART_ADDRESS_DETECT_4B * @arg @ref LL_LPUART_ADDRESS_DETECT_7B */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); } @@ -1271,7 +1271,7 @@ __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t Ha * @arg @ref LL_LPUART_HWCONTROL_CTS * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -1304,7 +1304,7 @@ __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } @@ -1333,7 +1333,7 @@ __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT * @arg @ref LL_LPUART_WAKEUP_ON_RXNE */ -__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); } @@ -1398,7 +1398,8 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri * @arg @ref LL_LPUART_PRESCALER_DIV256 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) { uint32_t lpuartdiv; uint32_t brrresult; @@ -1454,7 +1455,7 @@ __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } @@ -1485,7 +1486,7 @@ __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : c */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } @@ -1508,7 +1509,7 @@ __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32 * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } @@ -1541,7 +1542,7 @@ __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } @@ -1568,7 +1569,7 @@ __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint3 * @arg @ref LL_LPUART_DE_POLARITY_HIGH * @arg @ref LL_LPUART_DE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); } @@ -1587,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } @@ -1598,7 +1599,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } @@ -1609,7 +1610,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } @@ -1620,7 +1621,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } @@ -1631,13 +1632,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not @@ -1645,7 +1645,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } @@ -1656,13 +1656,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUART * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not @@ -1670,7 +1669,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } @@ -1681,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } @@ -1692,7 +1691,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } @@ -1703,7 +1702,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } @@ -1714,7 +1713,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } @@ -1725,7 +1724,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } @@ -1736,7 +1735,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } @@ -1747,7 +1746,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } @@ -1758,7 +1757,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } @@ -1769,7 +1768,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } @@ -1780,7 +1779,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } @@ -1791,7 +1790,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } @@ -1802,7 +1801,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } @@ -1813,7 +1812,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } @@ -1936,8 +1935,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -1961,8 +1959,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -2089,8 +2086,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -2114,8 +2110,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -2237,13 +2232,12 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -2251,7 +2245,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } @@ -2262,13 +2256,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled @@ -2276,7 +2269,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } @@ -2287,7 +2280,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } @@ -2298,7 +2291,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } @@ -2309,7 +2302,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } @@ -2320,7 +2313,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } @@ -2331,7 +2324,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } @@ -2342,7 +2335,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } @@ -2353,7 +2346,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } @@ -2364,7 +2357,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } @@ -2375,7 +2368,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } @@ -2416,7 +2409,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } @@ -2449,7 +2442,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } @@ -2482,7 +2475,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } @@ -2497,7 +2490,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUAR * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) { uint32_t data_reg_addr; @@ -2529,7 +2522,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) { return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); } @@ -2540,7 +2533,7 @@ __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) { return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); } @@ -2620,8 +2613,8 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx); -ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct); +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h index 4c3c71d650..9fef6c1432 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h @@ -360,19 +360,19 @@ typedef struct /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection * @{ */ -#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ -#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ -#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ #if defined(RCC_CCIPR2_I2C4SEL) -#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ -#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ -#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ #endif /* RCC_CCIPR2_I2C4SEL */ /** * @} @@ -444,13 +444,13 @@ typedef struct /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection * @{ */ -#define LL_RCC_ADC12_CLKSOURCE_NONE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U)) /*!< No clock used as ADC12 clock source */ -#define LL_RCC_ADC12_CLKSOURCE_PLL ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< PLL clock used as ADC12 clock source */ -#define LL_RCC_ADC12_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< SYSCLK clock used as ADC12 clock source */ +#define LL_RCC_ADC12_CLKSOURCE_NONE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U)) /*!< No clock used as ADC12 clock source */ +#define LL_RCC_ADC12_CLKSOURCE_PLL (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< PLL clock used as ADC12 clock source */ +#define LL_RCC_ADC12_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< SYSCLK clock used as ADC12 clock source */ #if defined(RCC_CCIPR_ADC345SEL) -#define LL_RCC_ADC345_CLKSOURCE_NONE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U)) /*!< No clock used as ADC345 clock source */ -#define LL_RCC_ADC345_CLKSOURCE_PLL ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_0 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */ -#define LL_RCC_ADC345_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_1 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */ +#define LL_RCC_ADC345_CLKSOURCE_NONE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U)) /*!< No clock used as ADC345 clock source */ +#define LL_RCC_ADC345_CLKSOURCE_PLL (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_0 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */ +#define LL_RCC_ADC345_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_1 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */ #endif /* RCC_CCIPR_ADC345SEL */ /** * @} @@ -501,11 +501,11 @@ typedef struct /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source * @{ */ -#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ -#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ -#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ +#define LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ +#define LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ +#define LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ #if defined(RCC_CCIPR2_I2C4SEL) -#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ +#define LL_RCC_I2C4_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ #endif /* RCC_CCIPR2_I2C4SEL */ /** * @} @@ -565,9 +565,9 @@ typedef struct /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source * @{ */ -#define LL_RCC_ADC12_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos)) /*!< ADC12 Clock source selection */ +#define LL_RCC_ADC12_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos)) /*!< ADC12 Clock source selection */ #if defined(RCC_CCIPR_ADC345SEL_Pos) -#define LL_RCC_ADC345_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL >> RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */ +#define LL_RCC_ADC345_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL >> RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */ #endif /* RCC_CCIPR_ADC345SEL_Pos */ /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rng.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rng.h index 5efe67a412..dce1306618 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rng.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rng.h @@ -38,6 +38,7 @@ extern "C" { */ /* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -174,7 +175,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); } @@ -207,7 +208,7 @@ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); } @@ -226,7 +227,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); } @@ -237,7 +238,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); } @@ -248,7 +249,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); } @@ -259,7 +260,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); } @@ -270,7 +271,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); } @@ -336,7 +337,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); } @@ -355,7 +356,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval Generated 32-bit random value */ -__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_REG(RNGx->DR)); } @@ -370,7 +371,7 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) */ ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rtc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rtc.h index d57f81ace3..7c3099f667 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rtc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rtc.h @@ -1202,7 +1202,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1236,7 +1236,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1271,7 +1271,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1357,7 +1357,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1503,7 +1503,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n @@ -1537,7 +1537,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1584,7 +1584,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n @@ -1626,7 +1626,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n @@ -1689,7 +1689,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h index c842354806..ac10472730 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h @@ -671,10 +671,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. @@ -1987,11 +2002,6 @@ typedef struct ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) -/** - * @} - */ - - /** * @} */ @@ -2032,7 +2042,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } @@ -2065,7 +2075,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval Inverted state of bit (0 or 1). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } @@ -2099,7 +2109,7 @@ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSo * @arg @ref LL_TIM_UPDATESOURCE_REGULAR * @arg @ref LL_TIM_UPDATESOURCE_COUNTER */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); } @@ -2126,7 +2136,7 @@ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulse * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); } @@ -2170,7 +2180,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) { uint32_t counter_mode; @@ -2212,7 +2222,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } @@ -2249,7 +2259,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); } @@ -2278,7 +2288,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) * @param TIMx Timer instance * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CNT)); } @@ -2291,7 +2301,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_COUNTERDIRECTION_UP * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); } @@ -2318,7 +2328,7 @@ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) * @param TIMx Timer instance * @retval Prescaler value between Min_Data=0 and Max_Data=65535 */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->PSC)); } @@ -2350,7 +2360,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload * @param TIMx Timer instance * @retval Auto-reload value */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->ARR)); } @@ -2378,7 +2388,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep * @param TIMx Timer instance * @retval Repetition counter value */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->RCR)); } @@ -2412,7 +2422,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) * @param Counter Counter value * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) { return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); } @@ -2451,7 +2461,7 @@ __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL); } @@ -2492,6 +2502,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); } +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check @@ -2530,7 +2551,7 @@ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAR * @arg @ref LL_TIM_CCDMAREQUEST_CC * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); } @@ -2642,7 +2663,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) { return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } @@ -2728,8 +2749,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) * @retval None @@ -2770,12 +2791,12 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2845,7 +2866,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCPOLARITY_HIGH * @arg @ref LL_TIM_OCPOLARITY_LOW */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); @@ -2918,7 +2939,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCIDLESTATE_LOW * @arg @ref LL_TIM_OCIDLESTATE_HIGH */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); @@ -2995,7 +3016,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3071,7 +3092,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3156,7 +3177,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3294,7 +3315,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -3311,7 +3332,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -3328,7 +3349,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -3345,7 +3366,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -3359,7 +3380,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); } @@ -3373,7 +3394,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR6)); } @@ -3438,7 +3459,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_ * @arg @ref LL_TIM_PWPRSC_X64 * @arg @ref LL_TIM_PWPRSC_X128 */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); } @@ -3467,7 +3488,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWi * @param TIMx Timer instance * @retval Returned value can be between Min_Data=0 and Max_Data=255: */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); } @@ -3567,7 +3588,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_TRC */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3618,7 +3639,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3693,7 +3714,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3750,7 +3771,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_IC_POLARITY_FALLING * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> @@ -3791,7 +3812,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } @@ -3808,7 +3829,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -3825,7 +3846,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -3842,7 +3863,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -3859,7 +3880,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -3906,7 +3927,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } @@ -4049,10 +4070,6 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) * @arg @ref LL_TIM_TS_ITR1 * @arg @ref LL_TIM_TS_ITR2 * @arg @ref LL_TIM_TS_ITR3 - * @arg @ref LL_TIM_TS_TI1F_ED - * @arg @ref LL_TIM_TS_TI1FP1 - * @arg @ref LL_TIM_TS_TI2FP2 - * @arg @ref LL_TIM_TS_ETRF * @arg @ref LL_TIM_TS_ITR4 * @arg @ref LL_TIM_TS_ITR5 * @arg @ref LL_TIM_TS_ITR6 @@ -4061,6 +4078,10 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) * @arg @ref LL_TIM_TS_ITR9 * @arg @ref LL_TIM_TS_ITR10 * @arg @ref LL_TIM_TS_ITR11 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF * @retval None */ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) @@ -4102,7 +4123,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } @@ -4309,7 +4330,7 @@ __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL); } @@ -4340,7 +4361,7 @@ __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t Prel * @arg @ref LL_TIM_SMSPS_TIMUPDATE * @arg @ref LL_TIM_SMSPS_INDEX */ -__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS)); } @@ -4441,18 +4462,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); } -/** - * @brief Re-arm the break input (when it operates in bidirectional mode). - * @note The Break input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); -} - /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -4542,18 +4551,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); } -/** - * @brief Re-arm the break 2 input (when it operates in bidirectional mode). - * @note The Break 2 input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); -} - /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -4608,7 +4605,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } @@ -4651,7 +4648,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } @@ -4711,14 +4708,14 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B * AF1 BKCMP5E LL_TIM_DisableBreakInputSource\n * AF1 BKCMP6E LL_TIM_DisableBreakInputSource\n * AF1 BKCMP7E LL_TIM_DisableBreakInputSource\n - * AF2 BKINE LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP1E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP2E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP3E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP4E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP5E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP6E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP7E LL_TIM_DisableBreakInputSource + * AF2 BK2INE LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP3E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP4E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP5E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP6E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP7E LL_TIM_DisableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN @@ -4751,11 +4748,17 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n * AF1 BKCMP4P LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP5P LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP6P LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP7P LL_TIM_SetBreakInputSourcePolarity\n * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity\n - * AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity + * AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP5P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP6P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP7P LL_TIM_SetBreakInputSourcePolarity * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN @@ -4766,9 +4769,14 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*) * @param Polarity This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_POLARITY_LOW * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, @@ -4811,7 +4819,7 @@ __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); } @@ -4845,7 +4853,7 @@ __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadT * @param TIMx Timer instance * @retval Returned value can be between Min_Data=0 and Max_Data=255: */ -__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); } @@ -4884,7 +4892,7 @@ __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); } @@ -5007,7 +5015,7 @@ __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); } @@ -5040,7 +5048,7 @@ __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexD * @arg @ref LL_TIM_INDEX_UP * @arg @ref LL_TIM_INDEX_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); } @@ -5079,7 +5087,7 @@ __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); } @@ -5118,7 +5126,7 @@ __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t Ind * @arg @ref LL_TIM_INDEX_POSITION_DOWN * @arg @ref LL_TIM_INDEX_POSITION_UP */ -__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS)); } @@ -5391,7 +5399,7 @@ __STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL); } @@ -5455,7 +5463,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } @@ -5477,7 +5485,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } @@ -5499,7 +5507,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } @@ -5521,7 +5529,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } @@ -5543,7 +5551,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } @@ -5565,7 +5573,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); } @@ -5587,7 +5595,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); } @@ -5609,7 +5617,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } @@ -5631,7 +5639,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } @@ -5653,7 +5661,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } @@ -5675,7 +5683,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); } @@ -5698,7 +5706,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } @@ -5721,7 +5729,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } @@ -5744,7 +5752,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } @@ -5767,7 +5775,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } @@ -5789,7 +5797,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); } @@ -5815,7 +5823,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL); } @@ -5841,7 +5849,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL); } @@ -5867,7 +5875,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL); } @@ -5893,7 +5901,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL); } @@ -5932,7 +5940,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } @@ -5965,7 +5973,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } @@ -5998,7 +6006,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } @@ -6031,7 +6039,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } @@ -6064,7 +6072,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } @@ -6097,7 +6105,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } @@ -6130,7 +6138,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } @@ -6163,7 +6171,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } @@ -6202,7 +6210,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL); } @@ -6241,7 +6249,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL); } @@ -6280,7 +6288,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL); } @@ -6319,7 +6327,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL); } @@ -6359,7 +6367,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } @@ -6392,7 +6400,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } @@ -6425,7 +6433,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } @@ -6458,7 +6466,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } @@ -6491,7 +6499,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } @@ -6524,7 +6532,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } @@ -6557,7 +6565,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } @@ -6677,19 +6685,19 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) * @{ */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h index 2dcc33c6e1..2cafeaa4cc 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h @@ -1779,18 +1779,18 @@ __STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx) /** * @brief Read the Rx paysize - * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_ReadRxPaySize + * @rmtoll RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize * @param UCPDx UCPD Instance * @retval RXPaysize. */ __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx) { - return READ_BIT(UCPDx->TX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ); + return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ); } /** * @brief Read data - * @rmtoll TXDR RXDATA LL_UCPD_ReadData + * @rmtoll RXDR RXDATA LL_UCPD_ReadData * @param UCPDx UCPD Instance * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h index 1a61622a79..51058c8b3e 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) /** @defgroup USART_LL USART * @{ @@ -63,6 +63,12 @@ static const uint32_t USART_PRESCALER_TAB[] = */ /* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup USART_LL_Private_Macros USART Private Macros @@ -650,7 +656,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } @@ -689,7 +695,7 @@ __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } @@ -728,7 +734,7 @@ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); } @@ -767,7 +773,7 @@ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); } @@ -838,7 +844,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } @@ -916,7 +922,7 @@ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32 * @arg @ref LL_USART_DIRECTION_TX * @arg @ref LL_USART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -950,7 +956,7 @@ __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) * @arg @ref LL_USART_PARITY_EVEN * @arg @ref LL_USART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -977,7 +983,7 @@ __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Me * @arg @ref LL_USART_WAKEUP_IDLELINE * @arg @ref LL_USART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); } @@ -1008,7 +1014,7 @@ __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataW * @arg @ref LL_USART_DATAWIDTH_8B * @arg @ref LL_USART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); } @@ -1041,7 +1047,7 @@ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } @@ -1068,7 +1074,7 @@ __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t Ov * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); } @@ -1100,7 +1106,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); } @@ -1131,7 +1137,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc * @arg @ref LL_USART_PHASE_1EDGE * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); } @@ -1162,7 +1168,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C * @arg @ref LL_USART_POLARITY_LOW * @arg @ref LL_USART_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); } @@ -1241,7 +1247,7 @@ __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t Presc * @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); } @@ -1280,7 +1286,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); } @@ -1311,7 +1317,7 @@ __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_STOPBITS_1_5 * @arg @ref LL_USART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); } @@ -1372,7 +1378,7 @@ __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapCo * @arg @ref LL_USART_TXRX_STANDARD * @arg @ref LL_USART_TXRX_SWAPPED */ -__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); } @@ -1399,7 +1405,7 @@ __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinI * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); } @@ -1426,7 +1432,7 @@ __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinI * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); } @@ -1455,7 +1461,7 @@ __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE */ -__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); } @@ -1486,7 +1492,7 @@ __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_BITORDER_LSBFIRST * @arg @ref LL_USART_BITORDER_MSBFIRST */ -__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); } @@ -1525,7 +1531,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); } @@ -1560,7 +1566,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME */ -__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); } @@ -1593,7 +1599,7 @@ __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); } @@ -1637,7 +1643,7 @@ __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } @@ -1650,7 +1656,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) * @arg @ref LL_USART_ADDRESS_DETECT_4B * @arg @ref LL_USART_ADDRESS_DETECT_7B */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); } @@ -1739,7 +1745,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard * @arg @ref LL_USART_HWCONTROL_CTS * @arg @ref LL_USART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -1772,7 +1778,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); } @@ -1805,7 +1811,7 @@ __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } @@ -1838,7 +1844,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) * @arg @ref LL_USART_WAKEUP_ON_STARTBIT * @arg @ref LL_USART_WAKEUP_ON_RXNE */ -__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); } @@ -1926,7 +1932,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) { uint32_t usartdiv; @@ -1975,7 +1981,7 @@ __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeo * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF */ -__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); } @@ -1998,7 +2004,7 @@ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t Blo * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); } @@ -2045,7 +2051,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); } @@ -2076,7 +2082,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P * @arg @ref LL_USART_IRDA_POWER_NORMAL * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); } @@ -2105,7 +2111,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P * @param USARTx USART Instance * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -2152,7 +2158,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); } @@ -2191,7 +2197,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); } @@ -2223,7 +2229,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, * @param USARTx USART Instance * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); } @@ -2252,7 +2258,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -2281,7 +2287,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); } @@ -2328,7 +2334,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } @@ -2374,7 +2380,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); } @@ -2416,7 +2422,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); } @@ -2455,7 +2461,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LINBREAK_DETECT_10B * @arg @ref LL_USART_LINBREAK_DETECT_11B */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); } @@ -2494,7 +2500,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); } @@ -2529,7 +2535,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 * @param USARTx USART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } @@ -2556,7 +2562,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } @@ -2595,7 +2601,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } @@ -2626,7 +2632,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_DE_POLARITY_HIGH * @arg @ref LL_USART_DE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); } @@ -2929,7 +2935,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } @@ -2940,7 +2946,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } @@ -2951,7 +2957,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } @@ -2962,7 +2968,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } @@ -2973,13 +2979,12 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not @@ -2989,7 +2994,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } @@ -3000,13 +3005,12 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not @@ -3016,7 +3020,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } @@ -3029,7 +3033,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); } @@ -3042,7 +3046,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } @@ -3055,7 +3059,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } @@ -3066,7 +3070,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); } @@ -3079,7 +3083,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); } @@ -3092,7 +3096,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); } @@ -3105,7 +3109,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); } @@ -3118,7 +3122,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); } @@ -3129,7 +3133,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } @@ -3140,7 +3144,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } @@ -3151,7 +3155,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } @@ -3162,7 +3166,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } @@ -3175,7 +3179,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } @@ -3186,7 +3190,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } @@ -3197,7 +3201,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } @@ -3210,7 +3214,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } @@ -3223,7 +3227,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } @@ -3234,7 +3238,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); } @@ -3247,7 +3251,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } @@ -3260,7 +3264,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } @@ -3461,8 +3465,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3488,8 +3491,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -3678,8 +3680,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3705,8 +3706,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -3892,13 +3892,12 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -3908,7 +3907,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } @@ -3919,13 +3918,12 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled @@ -3935,7 +3933,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } @@ -3946,7 +3944,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } @@ -3957,7 +3955,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } @@ -3968,7 +3966,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); } @@ -3981,7 +3979,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); } @@ -3994,7 +3992,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } @@ -4007,7 +4005,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } @@ -4020,7 +4018,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); } @@ -4031,7 +4029,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } @@ -4044,7 +4042,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } @@ -4057,7 +4055,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } @@ -4070,7 +4068,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } @@ -4083,7 +4081,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); } @@ -4096,7 +4094,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } @@ -4137,7 +4135,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } @@ -4170,7 +4168,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } @@ -4203,7 +4201,7 @@ __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } @@ -4218,7 +4216,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) { uint32_t data_reg_addr; @@ -4250,7 +4248,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) { return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); } @@ -4261,7 +4259,7 @@ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) { return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); } @@ -4369,10 +4367,10 @@ __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h index cc0f467236..adced155eb 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h @@ -42,96 +42,89 @@ extern "C" { * @brief USB Mode definition */ - - typedef enum { - USB_DEVICE_MODE = 0 + USB_DEVICE_MODE = 0 } USB_ModeTypeDef; + /** - * @brief USB Initialization Structure definition + * @brief USB Instance Initialization Structure definition */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; typedef struct { - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type */ + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_LL_EP_Type */ - uint8_t data_pid_start; /*!< Initial data PID - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - uint16_t pmaadress; /*!< PMA Address - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - uint16_t pmaaddr0; /*!< PMA Address0 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - uint16_t pmaaddr1; /*!< PMA Address1 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - uint8_t doublebuffer; /*!< Double buffer enable - This parameter can be 0 or 1 */ + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral - This parameter is added to ensure compatibility across USB peripherals */ + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - uint32_t xfer_len; /*!< Current transfer length */ + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint32_t xfer_len; /*!< Current transfer length */ - uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ - uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ + uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ + uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ } USB_EPTypeDef; - /* Exported constants --------------------------------------------------------*/ /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ */ - - /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ @@ -163,14 +156,21 @@ typedef struct * @} */ + #define BTABLE_ADDRESS 0x000U #define PMA_ACCESS 1U +#ifndef USB_EP_RX_STRX +#define USB_EP_RX_STRX (0x3U << 12) +#endif /* USB_EP_RX_STRX */ + #define EP_ADDR_MSK 0x7U #ifndef USE_USB_DOUBLE_BUFFER #define USE_USB_DOUBLE_BUFFER 1U #endif /* USE_USB_DOUBLE_BUFFER */ + + /** * @} */ @@ -192,26 +192,30 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num); + #if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep); #endif /* defined (HAL_PCD_MODULE_ENABLED) */ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); -uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx); HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, +void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, +void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); /** diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h index 134d863f91..60510db505 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h @@ -158,18 +158,31 @@ typedef struct /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE * @{ */ -#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U /*!< WLCSP81 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP128 0x00000007U /*!< LQFP128 package type */ -#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP32 0x00000009U /*!< LQFP32 package type */ -#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE 0x00000010U /*!< LQFP48 EBIKE package type */ +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */ +#if defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32G471xx) || \ + defined (STM32G473xx) || defined (STM32G483xx) || defined (STM32G474xx) || \ + defined (STM32G484xx) +#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 0x00000002U /*!< LQFP100 \ LQFP80 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100 LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 /*!< For backward compatibility */ +#else +#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ +#endif /* STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx ||STM32G474xx || STM32G484xx */ +#define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U /*!< WLCSP81 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 0x00000007U /*!< LQFP128 \ UFBGA121 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP128 LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 /*!< For backward compatibility */ +#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP32 0x00000009U /*!< LQFP32 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100 0x0000000EU /*!< TFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100 LL_UTILS_PACKAGETYPE_TFBGA100 /*!< For backward compatibility */ +#define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE 0x00000010U /*!< LQFP48 EBIKE package type */ +#if defined (STM32G491xx) || defined (STM32G4A1xx) +#define LL_UTILS_PACKAGETYPE_LQFP80 0x00000011U /*!< LQFP80 package type */ +#endif /* STM32G491xx || STM32G4A1xx */ /** * @} @@ -263,7 +276,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) * @note When a RTOS is used, it is recommended to avoid changing the SysTick * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks + * @param Ticks Frequency of Ticks (Hz) * @retval None */ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_wwdg.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_wwdg.h index 2a09972b85..86d0f31846 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_wwdg.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_wwdg.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } @@ -162,7 +162,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Counter value */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } @@ -203,7 +203,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale * @arg @ref LL_WWDG_PRESCALER_64 * @arg @ref LL_WWDG_PRESCALER_128 */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } @@ -235,7 +235,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Window value */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } @@ -256,7 +256,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } @@ -298,7 +298,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/LICENSE.md b/system/Drivers/STM32G4xx_HAL_Driver/LICENSE.md new file mode 100644 index 0000000000..479c4f6826 --- /dev/null +++ b/system/Drivers/STM32G4xx_HAL_Driver/LICENSE.md @@ -0,0 +1,27 @@ +Copyright 2017 STMicroelectronics. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32G4xx_HAL_Driver/Release_Notes.html index c87e4aed09..c38e0b033e 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32G4xx_HAL_Driver/Release_Notes.html @@ -11,24 +11,21 @@ span.underline{text-decoration: underline;} div.column{display: inline-block; vertical-align: top; width: 50%;} - + +
-
-

Release Notes for STM32G4xx HAL Drivers

Copyright © 2019 STMicroelectronics

- +
-
-

Purpose

The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

The Portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

@@ -43,14 +40,236 @@

Purpose

Update History

- +

Main Changes

Maintenance Release

    -

  • General updates to fix known defects and enhancements implementation

    • -
  • HAL
    • -
  • General updates to fix known defects and enhancements implementation.
    • +
  • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
    • +
  • HAL Generic update +
      +
    • Add implementation of utility APIs HAL_GetUIDw0, HAL_GetUIDw1 and HAL_GetUIDw2.
      • +
    • Allow redefinition of macro UNUSED(x).
      • +
    • Update of HAL_GetTickFreq() brief.
      • +
    • +
  • HAL/LL ADC update +
      +
    • Add “ADC_CHANNEL_0” in IS_ADC_CHANNEL() macro.
      • +
    • Add helper macro to convert data from differential mode.
      • +
    • Remove useless action of conversion trigger change in function LL_ADC_DeInit(); Moreover; this action was not compliant with ADC enable state (cf reference manual).
      • +
    • +
  • HAL/LL TIM update +
      +
    • Manage configuration of the Capture/compare DMA request source: +
        +
      • Add related new exported constants (TIM_CCDMAREQUEST_CC, TIM_CCDMAREQUEST_UPDATE).
        • +
      • Create a new macro __HAL_TIM_SELECT_CCDMAREQUEST() allowing to program the TIMx_CR2.CCDS bitfield.
        • +
      • +
    • Remove useless definition of macro IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION.
      • +
    • Improve driver robustness against wrong period values.
      • +
    • Improve driver robustness against wrong DMA related parameters.
      • +
    • Improve period configuration parameter check.
      • +
    • Minor typo correction in hal_tim header file.
      • +
    • Update __LL_TIM_CALC_PSC() macro to round up the evaluated value when the fractional part of the division is greater than 0.5.
      • +
    • Remove useless check on IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() to fix Break Filter configuration problem with specific TIM instances.
      • +
    • Update LL_TIM_DisableBreakInputSource() and LL_TIM_SetBreakInputSourcePolarity() APIs description.
      • +
    • Remove lock management from callback management functions.
      • +
    • Remove multiple volatile reads or writes in interrupt handler for better performance.
      • +
    • Improve HAL TIM driver’s operational behavior.
      • +
    • Assert check for the right channels.
      • +
    • Fix typo in PWM symmetric mode related constants names.
      • +
    • Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init().
      • +
    • +
  • HAL/LL LPTIM update +
      +
    • Improve LPTIM FSM management consistency.
      • +
    • Apply same naming rules to clear FLAG related functions.
      • +
    • Remove Lock management from callback management functions.
      • +
    • Remove redundant IS_LPTIM_AUTORELOAD macro.
      • +
    • +
  • HAL/LL RCC update +
      +
    • Add uint32_t cast to shift left operands constants defined with ‘U’ suffix in case MISRAC2012-Rule-12.2 violated.
      • +
    • Wait PLL1RDY to be off before clearing PLL1 source.
      • +
    • Set RCC_CRS_HSI48CALIBRATION_DEFAULT to 0x40 to be consistent with REFMAN and LL CRS driver.
      • +
    • Fix wrong RCC_APB1ENR1_WWDG2EN bit referenced in __HAL_RCC_WWDG_CLK_DISABLE() macro.
      • +
    • Modify the comment in PLL configuration.
      • +
    • +
  • HAL CORTEX update +
      +
    • Updated HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
      • +
    • Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().
      • +
    • +
  • HAL DAC update +
      +
    • Fix incorrect word ‘surcharged’ in functions headers.
      • +
    • Updated DAC buffer calibration according to RM.
      • +
    • Fix HAL_GetTick() timeout vulnerability.
      • +
    • +
  • HAL EXTI update +
      +
    • Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine().
      • +
    • Fix the wrong references in the “How to use this driver” section.
      • +
    • +
  • HAL CORDIC update +
      +
    • Fix incorrect word ‘surcharged’ in functions headers.
      • +
    • +
  • HAL FMAC update +
      +
    • Avoid usage of magic numbers.
      • +
    • Fix incorrect word ‘surcharged’ in functions headers.
      • +
    • +
  • HAL/LL HRTIM update +
      +
    • Rework HAL_HRTIM_Get…() getter functions not to change the handle state in case input parameter is out-of-range.
      • +
    • Add a right shift of the read bit field in LL_HRTIM_FLT_GetResetMode() before returning the result.
      • +
    • Fix erroneous fault counter threshold configuration function.
      • +
    • Fix typo in LL_HRTIM_FLT_ResetCounter() API header.
      • +
    • +
  • HAL RTC update +
      +
    • Check if the RTC calendar has been previously initialized before entering Initialization mode.
      • +
    • Optimize the way RSF flag is cleared in HAL_RTC_WaitForSynchro().
      • +
    • Correct misleading note about shadow registers.
      • +
    • +
  • HAL FMC update +
      +
    • Fix Hardfault issues when executing NOR read operations caused by FMC_WRITE_OPERATION_DISABLE.
      • +
    • +
  • HAL CRYP update +
      +
    • Mask arrays are declared as static const.
      • +
    • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment.
      • +
    • Update AES GCM in interrupt mode to avoid Computation Completed IRQ fires before the DINR pointer increment.
      • +
    • +
  • HAL FLASH update +
      +
    • Update the hal_flash_ex.c file to correctly support the PB4_PUPEN Option.
      • +
    • Fix FLASH_PAGE_NB value for STM32G4 category 3 devices.
      • +
    • +
  • HAL CRC update +
      +
    • Add filter in HAL_CRCEx_Polynomial_Set() to exclude even polynomials.
      • +
    • +
  • HAL QSPI update +
      +
    • Update HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() APIs to check on QSPI BUSY flag status before executing the abort procedure.
      • +
    • Fix incorrect word ‘surcharged’ in functions headers.
      • +
    • +
  • HAL SMBUS update +
      +
    • Remove Lock management from callback management functions.
      • +
    • Update HAL SMBUS driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
      • +
    • Update SMBUS_ITErrorHandler to flash TXDR just in case of error.
      • +
    • +
  • HAL UART update +
      +
    • Add a new API HAL_UARTEx_GetRxEventType that could be used to retrieve the type of event that has led the RxEventCallback execution.
      • +
    • Remove of HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs.
      • +
    • Remove __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
      • +
    • Disable the Receiver Timeout Interrupt when data reception is completed.
      • +
    • Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.
      • +
    • Update initialisation sequence for TXINV, RXINV and TXRXSWAP settings.
      • +
    • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to allow user Rx Event Callback registration when a transmit is ongoing.
      • +
    • Avoid RTOF flag to be cleared by a transmit process in polling mode.
      • +
    • +
  • HAL SMARTCARD update +
      +
    • Remove __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
      • +
    • +
  • HAL SPI update +
      +
    • Fix driver to don’t update state in case of error (HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT).
      • +
    • Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of one byte transaction.
      • +
    • Update IT API to enable interrupts after process unlock.
      • +
    • +
  • HAL IRDA update +
      +
    • Remove __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
      • +
    • +
  • HAL FDCAN update +
      +
    • Refine description of IsFilterMatchingFrame and FilterIndex, members of structure FDCAN_RxHeaderTypeDef.
      • +
    • Fix GetIndex issue in HAL_FDCAN_GetRxMessage.
      • +
    • Modify misleading DataLength values.
      • +
    • +
  • HAL SAI update +
      +
    • Avoid using magic numbers.
      • +
    • Fix misalignment between reference manual and HAL SAI driver: remove GCR register.
      • +
    • Improve audio quality (avoid potential glitch).
      • +
    • Fix incorrect word ‘surcharged’.
      • +
    • +
  • HAL USART update +
      +
    • Remove __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
      • +
    • +
  • HAL/LL I2C update +
      +
    • Move polling code of HAL memory interface through interrupt management to prevent timeout issue using HAL MEM interface through FreeRTOS.
      • +
    • Update I2C_IsErrorOccurred to return error if timeout is detected.
      • +
    • Clear the ADDRF flag only when direction is confirmed as changed, to prevent that the ADDRF flag is cleared too early when the restart is received.
      • +
    • Remove Lock management from callback management functions.
      • +
    • Duplicate the test condition after timeout detection to avoid false timeout detection.
      • +
    • Update HAL_I2C_IsDeviceReady() API to support 10_bit addressing mode: Update done on the macro I2C_GENERATE_START.
      • +
    • Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
      • +
    • Update HAL I2C driver to disable all interrupts after end of transaction.
      • +
    • Update HAL_I2C_Init API to clear ADD10 bit in 7 bit addressing mode.
      • +
    • Solve Slave No stretch not functional by using HAL Slave interface.
      • +
    • Update HAL_I2C_Mem_Write_IT API to initialize XferSize at 0.
      • +
    • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice.
      • +
    • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE.
      • +
    • Remove the unusable code in function HAL_I2C_IsDeviceReady.
      • +
    • Update I2C_WaitOnFlagUntilTimeout to handle error case.
      • +
    • Update HAL_I2C_Slave_Transmit to check if the received NACK is the good one.
      • +
    • Update LL_I2C_HandleTranfer function to prevent undefined behavior of volatile usage before updating the CR2 register.
      • +
    • +
  • LL UCPD update +
      +
    • Correct register accessed by LL_UCPD_ReadRxPaySize() function.
      • +
    • +
  • HAL USB update +
      +
    • Add new function HAL_PCD_EP_Abort() to abort current USB endpoint transfer.
      • +
    • PCD: add supporting multi packets transfer on Interrupt endpoint.
      • +
    • PCD: software correction added to avoid unexpected STALL condition during EP0 multi packet OUT transfer.
      • +
    • Set DCD timeout to a minimum of 300ms before starting BCD primary detection process.
      • +
    • hal_pcd.h: add a mask for USB RX bytes count.
      • +
    • +
  • LL UTILS update +
      +
    • Align UTILS_PLLVCO_INPUT_MAX value with documentation.
      • +
    • Update the number of LATENCY to be coherent with the reference manual.
      • +
    • Update package type definitions to be aligned with RM0440.
      • +
    • Fix a condition in LL_SetFlashLatency() API to avoid generation of Rule-10.1_R2 warning.
      • +
    • Add else statement in the end of LL_SetFlashLatency API to avoid Misra-C 2012 Rule-15.7 warnings.
      • +
    • Fix a note about Ticks parameter.
      • +
    • +
+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9 + ST-LINKV2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38 + ST-LINKV2
    • +
  • STM32CubeIDE toolchain (gcc9_2020_q2_update) V1.14.0
    • +
+

Supported Devices

+
    +
  • STM32G431/41xx
    • +
  • STM32G471xx
    • +
  • STM32G473/83xx
    • +
  • STM32G474/84xx
    • +
  • STM32G491/A1xx
    • +
+
+
+
+ +
+

Main Changes

+

Maintenance Release

+
    +

  • General updates to fix known defects and enhancements implementation.

  • HAL/LL ADC update
    • Update HAL_ADC_Start_DMA() API to avoid return error when using Independent instance with multimode activated.
      • @@ -189,13 +408,13 @@

      Maintenance Release

    • Update implementation of “HAL_NAND_Write_Page_16b” and “HAL_NAND_Read_Page_16b” APIs implementation to fix an issue with the page calculation of 8 bits memories.
-

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-LINKV2
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-LINKV2
  • STM32CubeIDE toolchain (gcc9_2020_q2_update) V1.7.0
-

Supported Devices

+

Supported Devices

  • STM32G431/41xx
  • STM32G471xx
    • @@ -208,8 +427,8 @@

    Supported Devices

    -

    Main Changes

    -

    Maintenance Release

    +

    Main Changes

    +

    Maintenance Release

    • General updates to fix known defects and enhancements implementation

    • HAL
      • @@ -313,7 +532,7 @@

      Maintenance Release

    • NOR_CMD_READ_STATUS_REG
    • NOR_CMD_CLEAR_STATUS_REG
    -
  • Updated muliple APIs to treat separetely the different memory types.
    • +
  • Updated multiple APIs to treat separately the different memory types.
  • LL FMC Update
      @@ -383,13 +602,13 @@

      Maintenance Release

  • Added few instructions before reading the RX count register.

    • -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-LINKV2
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-LINKV2
    • STM32CubeIDE toolchain V1.6.0
    -

    Supported Devices

    +

    Supported Devices

    • STM32G431/41xx
    • STM32G471xx
      • @@ -402,8 +621,8 @@

      Supported Devices

      -

      Main Changes

      -

      Maintenance Release

      +

      Main Changes

      +

      Maintenance Release

      • Add support for STM32G491xx and STM32G4A1 part numbers

      • General updates to fix known defects and enhancements implementation

        • @@ -489,7 +708,7 @@

        Maintenance Release

    • HAL/LL RCC update
        -
      • Update Table 1. HCLK clock frequency for STM32G4xx devices to be aligned with referance manual RM0440
        • +
      • Update Table 1. HCLK clock frequency for STM32G4xx devices to be aligned with reference manual RM0440
      • Update peripheral clock to support STM32G491/STM32G4A1 devices:
        • HAL_RCCEx_GetPeriphCLKConfig
          • @@ -533,13 +752,13 @@

          Maintenance Release

        • Correct some word spelling issues
      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.40.1
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29
      • STM32CubeIDE toolchain V1.4.0
      -

      Supported Devices

      +

      Supported Devices

      • STM32G431/41xx
      • STM32G471xx
        • @@ -552,8 +771,8 @@

        Supported Devices

        -

        Main Changes

        -

        Maintenance Release

        +

        Main Changes

        +

        Maintenance Release

        • General updates to fix known defects and enhancements implementation

        • HAL/LL CRYP update @@ -736,13 +955,13 @@

          Maintenance Release

        • API LL_PLL_ConfigSystemClock_HSI() and API LL_PLL_ConfigSystemClock_HSE() updated to set back the AHB prescaler to 1 after it has been temporarily set to 2 to avoid undershoot when configuring PLL at high frequencies.
      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
      • STM32CubeIDE toolchain v1.3.0
      -

      Supported Devices

      +

      Supported Devices

      • STM32G431/41xx
      • STM32G471xx
        • @@ -754,8 +973,8 @@

        Supported Devices

        -

        Main Changes

        -

        Maintenance Release

        +

        Main Changes

        +

        Maintenance Release

        Maintenance release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.

        Contents

        @@ -838,13 +1057,13 @@

        Contents

        -

        Development Toolchains and Compilers

        +

        Development Toolchains and Compilers

        • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
        • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
        • System Workbench STM32 (SW4STM32) toolchain V2.7.2
        -

        Supported Devices

        +

        Supported Devices

        • STM32G431/41xx
        • STM32G471xx
          • @@ -856,16 +1075,16 @@

          Supported Devices

          -

          Main Changes

          +

          Main Changes

          First release

          First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.

          -

          Development Toolchains and Compilers

          +

          Development Toolchains and Compilers

          • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
          • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
          • System Workbench STM32 (SW4STM32) toolchain V2.7.2
          -

          Supported Devices

          +

          Supported Devices

          • STM32G431/41xx
          • STM32G471xx
            • diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c index d1b49718f6..ebe1bdf5ee 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c @@ -48,11 +48,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32G4xx HAL Driver version number V1.2.2 + * @brief STM32G4xx HAL Driver version number V1.2.3 */ #define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ -#define __STM32G4xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ +#define __STM32G4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\ @@ -378,7 +378,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) /** * @brief Returns tick frequency. - * @retval tick period in Hz + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. */ uint32_t HAL_GetTickFreq(void) { @@ -471,6 +472,33 @@ uint32_t HAL_GetDEVID(void) return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); } +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c index d2ebf89402..8930f28822 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c @@ -222,11 +222,11 @@ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions HAL_ADC_RegisterCallback() + Use Functions @ref HAL_ADC_RegisterCallback() to register an interrupt callback. [..] - Function HAL_ADC_RegisterCallback() allows to register following callbacks: + Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback @@ -242,11 +242,11 @@ and a pointer to the user callback function. [..] - Use function HAL_ADC_UnRegisterCallback to reset a callback to the default + Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] - HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback @@ -262,27 +262,27 @@ (+) MspDeInitCallback : ADC Msp DeInit callback [..] - By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET + By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: - examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). + examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when + reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() + If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. + Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, + in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() - or HAL_ADC_Init() function. + using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() + or @ref HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or @@ -314,10 +314,11 @@ * @{ */ -#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\ - ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ - ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ - ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ +#define ADC_CFGR_FIELDS_1 (ADC_CFGR_RES | ADC_CFGR_ALIGN |\ + ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ + ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ + ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL) /*!< ADC_CFGR fields of parameters that can + be updated when no regular conversion is on-going */ /* Timeout values for ADC operations (enable settling time, */ /* disable settling time, ...). */ @@ -395,11 +396,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpCFGR; - uint32_t tmp_adc_reg_is_conversion_on_going; - __IO uint32_t wait_loop_index = 0UL; + uint32_t tmp_cfgr; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; + __IO uint32_t wait_loop_index = 0UL; /* Check ADC handle */ if (hadc == NULL) @@ -517,10 +517,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ - tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - && (tmp_adc_reg_is_conversion_on_going == 0UL) + && (tmp_adc_is_conversion_on_going_regular == 0UL) ) { /* Set ADC state */ @@ -567,15 +567,15 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ - tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - hadc->Init.Overrun | - hadc->Init.DataAlign | - hadc->Init.Resolution | - ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); + tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + hadc->Init.Overrun | + hadc->Init.DataAlign | + hadc->Init.Resolution | + ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); if (hadc->Init.DiscontinuousConvMode == ENABLE) { - tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); + tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); } /* Enable external trigger if trigger selection is different of software */ @@ -585,13 +585,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { - tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) - | hadc->Init.ExternalTrigConvEdge - ); + tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) + | hadc->Init.ExternalTrigConvEdge + ); } /* Update Configuration Register CFGR */ - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr); /* Configuration of sampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); @@ -603,17 +603,16 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* - DMA continuous request Init.DMAContinuousRequests */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { - tmpCFGR = (ADC_CFGR_DFSDM(hadc) | - ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | + ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); if (hadc->Init.GainCompensation != 0UL) { @@ -1223,7 +1222,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1257,7 +1256,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ @@ -1326,7 +1325,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ } else { @@ -1414,7 +1413,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1474,7 +1473,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti { tmp_Flag_End = (ADC_FLAG_EOC); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ } /* Get tick count */ @@ -1547,7 +1546,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti #else /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_EOS) @@ -1575,9 +1574,12 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event - * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) - * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) - * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) + * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on + * all STM32 series) + * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on + * all STM32 series) + * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on + * all STM32 series) * @arg @ref ADC_OVR_EVENT ADC Overrun event * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event * @param Timeout Timeout value in millisecond. @@ -1744,7 +1746,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1778,7 +1780,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ @@ -1920,7 +1922,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ } else { @@ -2003,7 +2005,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui HAL_StatusTypeDef tmp_hal_status; #if defined(ADC_MULTIMODE_SUPPORT) uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2047,7 +2049,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) @@ -2116,7 +2118,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui /* Process unlocked */ __HAL_UNLOCK(hadc); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ } else { @@ -2225,7 +2227,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2296,7 +2298,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2360,7 +2362,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Carry on if continuous mode is disabled */ if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) @@ -2450,7 +2452,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ @@ -2596,7 +2598,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) } } else -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ { /* Multimode not set or feature not available or ADC independent */ if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) @@ -2752,10 +2754,10 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_ChannelConfTypeDef". * @param hadc ADC handle - * @param sConfig Structure of ADC channel assigned to ADC group regular. + * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; @@ -2766,24 +2768,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff)); - assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset)); + assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff)); + assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset)); /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ - assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); + assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ - if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) + if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { - assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel)); + assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel)); } else { - assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel)); + assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel)); } /* Process locked */ @@ -2797,7 +2799,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Set ADC group regular sequence: channel on the selected scan sequence rank */ - LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); + LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ @@ -2811,10 +2813,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf ) { /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ - if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) + if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); @@ -2822,7 +2824,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf else { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); @@ -2832,40 +2834,42 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); + tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); - if (sConfig->OffsetNumber != ADC_OFFSET_NONE) + if (pConfig->OffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ - LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); + LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted); - assert_param(IS_ADC_OFFSET_SIGN(sConfig->OffsetSign)); - assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation)); + assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign)); + assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation)); /* Set ADC selected offset sign & saturation */ - LL_ADC_SetOffsetSign(hadc->Instance, sConfig->OffsetNumber, sConfig->OffsetSign); - LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); + LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign); + LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, + (pConfig->OffsetSaturation == ENABLE) ? + LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } @@ -2878,16 +2882,18 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ - LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); + LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); /* Configuration of differential mode */ - if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) + if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, - (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), - sConfig->SamplingTime); + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( + (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) + + 1UL) & 0x1FUL)), + pConfig->SamplingTime); } } @@ -2898,13 +2904,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ - if (((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) + if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) @@ -2924,7 +2930,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf } } } - else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + else if ((pConfig->Channel == ADC_CHANNEL_VBAT) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { @@ -2932,7 +2939,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } - else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) + else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) @@ -2985,29 +2992,29 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. * @param hadc ADC handle - * @param AnalogWDGConfig Structure of ADC analog watchdog configuration + * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpAWDHighThresholdShifted; - uint32_t tmpAWDLowThresholdShifted; + uint32_t tmp_awd_high_threshold_shifted; + uint32_t tmp_awd_low_threshold_shifted; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); - assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(AnalogWDGConfig->FilteringConfig)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - - if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) + assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode)); + assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig)); + assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode)); + + if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || + (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || + (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) { - assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel)); + assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel)); } /* Verify thresholds range */ @@ -3016,14 +3023,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Case of oversampling enabled: depending on ratio and shift configuration, analog watchdog thresholds can be higher than ADC resolution. Verify if thresholds are within maximum thresholds range. */ - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold)); } else { /* Verify if thresholds are within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold)); } /* Process locked */ @@ -3040,26 +3047,29 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG ) { /* Analog watchdog configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels, on groups regular and-or injected. */ - switch (AnalogWDGConfig->WatchdogMode) + switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, - LL_ADC_GROUP_REGULAR)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR)); break; case ADC_ANALOGWATCHDOG_SINGLE_INJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, - LL_ADC_GROUP_INJECTED)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, + LL_ADC_GROUP_INJECTED)); break; case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, - LL_ADC_GROUP_REGULAR_INJECTED)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR_INJECTED)); break; case ADC_ANALOGWATCHDOG_ALL_REG: @@ -3082,7 +3092,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Set the filtering configuration */ MODIFY_REG(hadc->Instance->TR1, ADC_TR1_AWDFILT, - AnalogWDGConfig->FilteringConfig); + pAnalogWDGConfig->FilteringConfig); /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -3094,7 +3104,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD1(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD1(hadc->Instance); } @@ -3106,35 +3116,38 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { - switch (AnalogWDGConfig->WatchdogMode) + switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: case ADC_ANALOGWATCHDOG_SINGLE_INJEC: case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: /* Update AWD by bitfield to keep the possibility to monitor */ /* several channels by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { - SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); + SET_BIT(hadc->Instance->AWD2CR, + (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); } else { - SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); + SET_BIT(hadc->Instance->AWD3CR, + (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); } break; case ADC_ANALOGWATCHDOG_ALL_REG: case ADC_ANALOGWATCHDOG_ALL_INJEC: case ADC_ANALOGWATCHDOG_ALL_REGINJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, + pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; default: /* ADC_ANALOGWATCHDOG_NONE */ - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); break; } - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Update state, clear previous result related to AWD2 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); @@ -3146,7 +3159,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD2(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD2(hadc->Instance); } @@ -3155,7 +3168,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_DisableIT_AWD2(hadc->Instance); } } - /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ + /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ else { /* Update state, clear previous result related to AWD3 */ @@ -3168,7 +3181,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD3(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD3(hadc->Instance); } @@ -3182,13 +3195,13 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG } /* Analog watchdog thresholds configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0. */ - tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); + tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); } /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ else @@ -3196,13 +3209,13 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 7, the LSB (right bits) */ /* are set to 0. */ - tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); + tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); } /* Set ADC analog watchdog thresholds value of both thresholds high and low */ - LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, - tmpAWDLowThresholdShifted); + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted, + tmp_awd_low_threshold_shifted); /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -3243,7 +3256,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3257,7 +3270,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3422,6 +3435,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; + __IO uint32_t wait_loop_index = 0UL; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ @@ -3445,6 +3459,26 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); + if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) + & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) + { + /* Delay for temperature sensor buffer stabilization time */ + /* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of */ + /* LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US because needed */ + /* in case of ADC enable after a system wake up */ + /* from low power mode. */ + + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c index 316207f49b..06c5ece945 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c @@ -50,9 +50,10 @@ * @{ */ -#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ - ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ - ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ +#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ + ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ + ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can + be updated anytime once the ADC is enabled */ /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: low clock frequency, */ @@ -196,7 +197,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval Calibration value. */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -279,7 +280,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) uint32_t tmp_config_injected_queue; #if defined(ADC_MULTIMODE_SUPPORT) uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -345,7 +346,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ @@ -392,7 +393,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) /* Start ADC group injected conversion */ LL_ADC_INJ_StartConversion(hadc->Instance); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ } else @@ -480,14 +481,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; - uint32_t tmp_Flag_End; + uint32_t tmp_flag_end; uint32_t tmp_adc_inj_is_trigger_source_sw_start; uint32_t tmp_adc_reg_is_trigger_source_sw_start; uint32_t tmp_cfgr; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -495,18 +496,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u /* If end of sequence selected */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { - tmp_Flag_End = ADC_FLAG_JEOS; + tmp_flag_end = ADC_FLAG_JEOS; } else /* end of conversion selected */ { - tmp_Flag_End = ADC_FLAG_JEOC; + tmp_flag_end = ADC_FLAG_JEOC; } /* Get timeout */ tickstart = HAL_GetTick(); /* Wait until End of Conversion or Sequence flag is raised */ - while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + while ((hadc->Instance->ISR & tmp_flag_end) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) @@ -514,7 +515,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* New check to avoid false timeout detection in case of preemption */ - if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + if ((hadc->Instance->ISR & tmp_flag_end) == 0UL) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -550,7 +551,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); @@ -586,7 +587,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u } /* Clear polled flag */ - if (tmp_Flag_End == ADC_FLAG_JEOS) + if (tmp_flag_end == ADC_FLAG_JEOS) { /* Clear end of sequence JEOS flag of injected group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ @@ -624,7 +625,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) uint32_t tmp_config_injected_queue; #if defined(ADC_MULTIMODE_SUPPORT) uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -690,7 +691,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ @@ -758,7 +759,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) /* Start ADC group injected conversion */ LL_ADC_INJ_StartConversion(hadc->Instance); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ } else @@ -861,7 +862,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; - ADC_HandleTypeDef tmphadcSlave; + ADC_HandleTypeDef tmp_hadc_slave; ADC_Common_TypeDef *tmpADC_Common; /* Check the parameters */ @@ -880,13 +881,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t __HAL_LOCK(hadc); /* Temporary handle minimum initialization */ - __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); - ADC_CLEAR_ERRORCODE(&tmphadcSlave); + __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); + ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); /* Set a temporary handle of the ADC slave associated to the ADC master */ - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); - if (tmphadcSlave.Instance == NULL) + if (tmp_hadc_slave.Instance == NULL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -902,7 +903,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t tmp_hal_status = ADC_Enable(hadc); if (tmp_hal_status == HAL_OK) { - tmp_hal_status = ADC_Enable(&tmphadcSlave); + tmp_hal_status = ADC_Enable(&tmp_hadc_slave); } /* Start multimode conversion of ADCs pair */ @@ -981,9 +982,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; - ADC_HandleTypeDef tmphadcSlave; - uint32_t tmphadcSlave_conversion_on_going; - HAL_StatusTypeDef tmphadcSlave_disable_status; + ADC_HandleTypeDef tmp_hadc_slave; + uint32_t tmp_hadc_slave_conversion_on_going; + HAL_StatusTypeDef tmp_hadc_slave_disable_status; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -991,7 +992,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Process locked */ __HAL_LOCK(hadc); - /* 1. Stop potential multimode conversion on going, on regular and injected groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); @@ -999,13 +999,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) if (tmp_hal_status == HAL_OK) { /* Temporary handle minimum initialization */ - __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); - ADC_CLEAR_ERRORCODE(&tmphadcSlave); + __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); + ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); /* Set a temporary handle of the ADC slave associated to the ADC master */ - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); - if (tmphadcSlave.Instance == NULL) + if (tmp_hadc_slave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -1022,17 +1022,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ tickstart = HAL_GetTick(); - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) - || (tmphadcSlave_conversion_on_going == 1UL) + || (tmp_hadc_slave_conversion_on_going == 1UL) ) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) - || (tmphadcSlave_conversion_on_going == 1UL) + || (tmp_hadc_slave_conversion_on_going == 1UL) ) { /* Update ADC state machine to error */ @@ -1045,7 +1045,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) } } - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); } /* Disable the DMA channel (in case of DMA in circular mode or stop */ @@ -1069,9 +1069,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { - tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave); + tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave); if ((ADC_Disable(hadc) == HAL_OK) && - (tmphadcSlave_disable_status == HAL_OK)) + (tmp_hadc_slave_disable_status == HAL_OK)) { tmp_hal_status = HAL_OK; } @@ -1080,7 +1080,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { /* In case of error, attempt to disable ADC master and slave without status assert */ (void) ADC_Disable(hadc); - (void) ADC_Disable(&tmphadcSlave); + (void) ADC_Disable(&tmp_hadc_slave); } /* Set ADC state (ADC master) */ @@ -1101,7 +1101,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc) { const ADC_Common_TypeDef *tmpADC_Common; @@ -1134,7 +1134,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) * both flags JEOC and EOS are raised. * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features - * (feature low power auto-wait, not available on all STM32 families). + * (feature low power auto-wait, not available on all STM32 series). * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() @@ -1148,7 +1148,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr; @@ -1458,7 +1458,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) #if defined(ADC_MULTIMODE_SUPPORT) /** - * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going. + * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected + * conversion is on-going. * @note Multimode is kept enabled after this function. Multimode DMA bits * (MDMA and DMACFG bits of common CCR register) are maintained. To disable * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be @@ -1474,8 +1475,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; - ADC_HandleTypeDef tmphadcSlave; - uint32_t tmphadcSlave_conversion_on_going; + ADC_HandleTypeDef tmp_hadc_slave; + uint32_t tmp_hadc_slave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -1494,13 +1495,13 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); /* Temporary handle minimum initialization */ - __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); - ADC_CLEAR_ERRORCODE(&tmphadcSlave); + __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); + ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); /* Set a temporary handle of the ADC slave associated to the ADC master */ - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); - if (tmphadcSlave.Instance == NULL) + if (tmp_hadc_slave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -1517,17 +1518,17 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ tickstart = HAL_GetTick(); - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) - || (tmphadcSlave_conversion_on_going == 1UL) + || (tmp_hadc_slave_conversion_on_going == 1UL) ) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) - || (tmphadcSlave_conversion_on_going == 1UL) + || (tmp_hadc_slave_conversion_on_going == 1UL) ) { /* Update ADC state machine to error */ @@ -1540,7 +1541,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) } } - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); } /* Disable the DMA channel (in case of DMA in circular mode or stop */ @@ -1570,9 +1571,9 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) tmp_hal_status = ADC_Disable(hadc); if (tmp_hal_status == HAL_OK) { - if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL) + if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL) { - tmp_hal_status = ADC_Disable(&tmphadcSlave); + tmp_hal_status = ADC_Disable(&tmp_hadc_slave); } } } @@ -1651,61 +1652,64 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) * start once the 1st context is set, that is after the first three * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. * @param hadc ADC handle - * @param sConfigInjected Structure of ADC injected group and ADC channel for + * @param pConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, + const ADC_InjectionConfTypeDef *pConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpOffsetShifted; + uint32_t tmp_offset_shifted; uint32_t tmp_config_internal_channel; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0; - uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; + uint32_t tmp_jsqr_context_queue_being_built = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext)); - assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); - assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv)); - assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); - assert_param(IS_ADC_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); + assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext)); + assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge)); + assert_param(IS_ADC_EXTTRIGINJEC(hadc, pConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset)); + assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { - assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); - assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank)); + assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode)); } /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ - assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); + assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) + && (pConfigInjected->InjecOversamplingMode == ENABLE))); /* JDISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE) + && (pConfigInjected->AutoInjectedConv == ENABLE))); /* DISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE))); /* Verification of channel number */ - if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) + if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { - assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel)); } else { - assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel)); } /* Process locked */ @@ -1733,7 +1737,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* by software for alignment over all STM32 devices. */ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || - (sConfigInjected->InjectedNbrOfConversion == 1U)) + (pConfigInjected->InjectedNbrOfConversion == 1U)) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ @@ -1742,28 +1746,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* - external trigger polarity */ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ - if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) + if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ - if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); + tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) + | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | pConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); + tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); } - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); + MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built); /* For debug and informative reasons, hadc handle saves JSQR setting */ - hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; + hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built; } } @@ -1783,7 +1787,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { /* Initialize number of channels that will be configured on the context */ /* being built */ - hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion; + hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion; /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() call, this context will be written in JSQR register at the last call. At this point, the context is merely reset */ @@ -1799,16 +1803,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ - if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); + tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U) + | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | pConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)); + tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)); } } @@ -1816,18 +1820,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Clear the old JSQx bits for the selected rank */ - tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank); + tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank); /* Set the JSQx bits for the selected rank */ - tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); + tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank); /* Decrease channel count */ hadc->InjectionConfig.ChannelCount--; - /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel() + /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel() call, aggregate the setting to those already built during the previous HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */ - hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt; + hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built; /* 4. End of context setting: if this is the last channel set, then write context into register JSQR and make it enter into queue */ @@ -1847,12 +1851,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* If auto-injected mode is disabled: no constraint */ - if (sConfigInjected->AutoInjectedConv == DISABLE) + if (pConfigInjected->AutoInjectedConv == DISABLE) { MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) | - ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode)); + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) | + ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode)); } /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ @@ -1860,7 +1864,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)); + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext)); } } @@ -1881,10 +1885,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { /* If injected group external triggers are disabled (set to injected */ /* software start): no constraint */ - if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) - || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) + || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) { - if (sConfigInjected->AutoInjectedConv == ENABLE) + if (pConfigInjected->AutoInjectedConv == ENABLE) { SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } @@ -1897,7 +1901,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* due to injected group external triggers enabled, error is reported. */ else { - if (sConfigInjected->AutoInjectedConv == ENABLE) + if (pConfigInjected->AutoInjectedConv == ENABLE) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -1910,13 +1914,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I } } - if (sConfigInjected->InjecOversamplingMode == ENABLE) + if (pConfigInjected->InjecOversamplingMode == ENABLE) { - assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); - assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift)); + assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift)); /* JOVSE must be reset in case of triggered regular mode */ - assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); + assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) + == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); /* Configuration of Injected Oversampler: */ /* - Oversampling Ratio */ @@ -1928,8 +1933,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I ADC_CFGR2_OVSR | ADC_CFGR2_OVSS, ADC_CFGR2_JOVSE | - sConfigInjected->InjecOversampling.Ratio | - sConfigInjected->InjecOversampling.RightBitShift + pConfigInjected->InjecOversampling.Ratio | + pConfigInjected->InjecOversampling.RightBitShift ); } else @@ -1939,10 +1944,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I } /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ - if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) + if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); @@ -1950,7 +1955,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I else { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, + pConfigInjected->InjectedSamplingTime); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); @@ -1960,40 +1966,41 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); + tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset); - if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) + if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ - LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, - tmpOffsetShifted); + LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel, + tmp_offset_shifted); /* Set ADC selected offset sign & saturation */ - LL_ADC_SetOffsetSign(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedOffsetSign); - LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, - (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); + LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign); + LL_ADC_SetOffsetSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, + (pConfigInjected->InjectedOffsetSaturation == ENABLE) ? + LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } @@ -2007,16 +2014,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ - LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); + LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff); /* Configuration of differential mode */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ - if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) + if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, - (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) - + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( + (__LL_ADC_CHANNEL_TO_DECIMAL_NB( + (uint32_t)pConfigInjected->InjectedChannel) + + 1UL) & 0x1FUL)), + pConfigInjected->InjectedSamplingTime); } } @@ -2027,14 +2037,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)) + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ - if (((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1) - || (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5)) + if (((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1) + || (pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5)) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) @@ -2047,14 +2057,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL)); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) + * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } } - else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) + else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) @@ -2063,7 +2074,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } - else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) + else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) @@ -2099,35 +2110,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I * @note To move back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). * @param hadc Master ADC handle - * @param multimode Structure of ADC multimode configuration + * @param pMultimode Structure of ADC multimode configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; - ADC_HandleTypeDef tmphadcSlave; - uint32_t tmphadcSlave_conversion_on_going; + ADC_HandleTypeDef tmp_hadc_slave; + uint32_t tmp_hadc_slave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_MULTIMODE(multimode->Mode)); - if (multimode->Mode != ADC_MODE_INDEPENDENT) + assert_param(IS_ADC_MULTIMODE(pMultimode->Mode)); + if (pMultimode->Mode != ADC_MODE_INDEPENDENT) { - assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); /* Temporary handle minimum initialization */ - __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); - ADC_CLEAR_ERRORCODE(&tmphadcSlave); + __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); + ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); - if (tmphadcSlave.Instance == NULL) + if (tmp_hadc_slave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -2143,9 +2154,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - && (tmphadcSlave_conversion_on_going == 0UL)) + && (tmp_hadc_slave_conversion_on_going == 0UL)) { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); @@ -2153,10 +2164,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ - if (multimode->Mode != ADC_MODE_INDEPENDENT) + if (pMultimode->Mode != ADC_MODE_INDEPENDENT) { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, - multimode->DMAAccessMode | + pMultimode->DMAAccessMode | ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); /* Parameters that can be updated only when ADC is disabled: */ @@ -2174,8 +2185,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY, - multimode->Mode | - multimode->TwoSamplingDelay + pMultimode->Mode | + pMultimode->TwoSamplingDelay ); } } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_comp.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_comp.c index 0292e452f3..1dc7f91daf 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_comp.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_comp.c @@ -21,9 +21,9 @@ * ****************************************************************************** @verbatim -================================================================================ + ============================================================================== ##### COMP Peripheral features ##### -================================================================================ + ============================================================================== [..] The STM32G4xx device family integrates seven analog comparators instances: @@ -44,7 +44,7 @@ using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). ##### How to use this driver ##### -================================================================================ + ============================================================================== [..] This driver provides functions to configure and program the comparator instances of STM32G4xx devices. @@ -148,7 +148,6 @@ @endverbatim ****************************************************************************** - */ /* Includes ------------------------------------------------------------------*/ @@ -178,7 +177,7 @@ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define COMP_DELAY_STARTUP_US (5UL) /*!< Delay for COMP startup time */ +#define COMP_DELAY_STARTUP_US (5UL) /*!< Delay for COMP startup time */ /* Delay for COMP voltage scaler stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ @@ -231,11 +230,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -250,7 +249,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); - if(hcomp->State == HAL_COMP_STATE_RESET) + if (hcomp->State == HAL_COMP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; @@ -258,7 +257,6 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); - #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) /* Init the COMP Callback settings */ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ @@ -286,7 +284,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN); /* Set COMP parameters */ - tmp_csr = ( hcomp->Init.InputMinus + tmp_csr = (hcomp->Init.InputMinus | hcomp->Init.InputPlus | hcomp->Init.BlankingSrce | hcomp->Init.Hysteresis @@ -305,14 +303,14 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is required and not already enabled */ if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) && - (comp_voltage_scaler_initialized == 0UL) ) + (comp_voltage_scaler_initialized == 0UL)) { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - while(wait_loop_index != 0UL) + while (wait_loop_index != 0UL) { wait_loop_index--; } @@ -322,13 +320,13 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); /* Manage EXTI settings */ - if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) + if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) { /* Configure EXTI rising edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) { #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_EnableRisingTrig_32_63(exti_line); } @@ -343,7 +341,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) else { #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_DisableRisingTrig_32_63(exti_line); } @@ -357,10 +355,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) } /* Configure EXTI falling edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) { #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_EnableFallingTrig_32_63(exti_line); } @@ -375,7 +373,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) else { #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_DisableFallingTrig_32_63(exti_line); } @@ -390,7 +388,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Clear COMP EXTI pending bit (if any) */ #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_ClearFlag_32_63(exti_line); } @@ -403,10 +401,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) #endif /* COMP7 */ /* Configure EXTI event mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) { #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_EnableEvent_32_63(exti_line); } @@ -421,7 +419,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) else { #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_DisableEvent_32_63(exti_line); } @@ -435,10 +433,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) } /* Configure EXTI interrupt mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) { #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_EnableIT_32_63(exti_line); } @@ -453,7 +451,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) else { #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_DisableIT_32_63(exti_line); } @@ -470,7 +468,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { /* Disable EXTI event mode */ #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_DisableEvent_32_63(exti_line); } @@ -484,7 +482,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Disable EXTI interrupt mode */ #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { LL_EXTI_DisableIT_32_63(exti_line); } @@ -521,11 +519,11 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -604,7 +602,8 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, + pCOMP_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -780,11 +779,11 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -793,7 +792,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - if(hcomp->State == HAL_COMP_STATE_READY) + if (hcomp->State == HAL_COMP_STATE_READY) { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN); @@ -809,7 +808,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* of startup time (few us) is within CPU processing cycles */ /* of following instructions. */ wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL))); - while(wait_loop_index != 0UL) + while (wait_loop_index != 0UL) { wait_loop_index--; } @@ -833,11 +832,11 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -848,7 +847,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */ /* (all states except HAL_COMP_STATE_RESET and except locked status. */ - if(hcomp->State != HAL_COMP_STATE_RESET) + if (hcomp->State != HAL_COMP_STATE_RESET) { /* Disable the selected comparator */ CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN); @@ -878,41 +877,41 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) /* Check COMP EXTI flag */ #if defined(COMP7) - if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) + if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7)) { - if(LL_EXTI_IsActiveFlag_32_63(exti_line) != 0UL) + if (LL_EXTI_IsActiveFlag_32_63(exti_line) != 0UL) { tmp_comp_exti_flag_set = 2UL; } } else { - if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) + if (LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) { tmp_comp_exti_flag_set = 1UL; } } #else - if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) + if (LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) { tmp_comp_exti_flag_set = 1UL; } #endif /* COMP7 */ - if(tmp_comp_exti_flag_set != 0UL) + if (tmp_comp_exti_flag_set != 0UL) { - /* Clear COMP EXTI line pending bit */ + /* Clear COMP EXTI line pending bit */ #if defined(COMP7) - if(tmp_comp_exti_flag_set == 2UL) - { - LL_EXTI_ClearFlag_32_63(exti_line); - } - else - { - LL_EXTI_ClearFlag_0_31(exti_line); - } -#else + if (tmp_comp_exti_flag_set == 2UL) + { + LL_EXTI_ClearFlag_32_63(exti_line); + } + else + { LL_EXTI_ClearFlag_0_31(exti_line); + } +#else + LL_EXTI_ClearFlag_0_31(exti_line); #endif /* COMP7 */ /* COMP trigger user callback */ @@ -955,11 +954,11 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -969,7 +968,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); /* Set HAL COMP handle state */ - switch(hcomp->State) + switch (hcomp->State) { case HAL_COMP_STATE_RESET: hcomp->State = HAL_COMP_STATE_RESET_LOCKED; @@ -981,10 +980,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; break; } - } - if(status == HAL_OK) - { /* Set the lock bit corresponding to selected comparator */ __HAL_COMP_LOCK(hcomp); } @@ -1006,7 +1002,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * @arg COMP_OUTPUT_LEVEL_HIGH * */ -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); @@ -1054,10 +1050,10 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval HAL state */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ - if(hcomp == NULL) + if (hcomp == NULL) { return HAL_COMP_STATE_RESET; } @@ -1074,7 +1070,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval COMP error code */ -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp) { /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cordic.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cordic.c index 6f90b142d4..b5cb44a7e6 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cordic.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cordic.c @@ -159,8 +159,8 @@ /** @defgroup CORDIC_Private_Functions CORDIC Private Functions * @{ */ -static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff); -static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff); +static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff); +static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff); static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); @@ -555,7 +555,7 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H * contains the CORDIC configuration information. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig) +HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -602,12 +602,12 @@ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_Con * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; - int32_t *p_tmp_in_buff = pInBuff; + const int32_t *p_tmp_in_buff = pInBuff; int32_t *p_tmp_out_buff = pOutBuff; /* Check parameters setting */ @@ -696,12 +696,12 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; - int32_t *p_tmp_in_buff = pInBuff; + const int32_t *p_tmp_in_buff = pInBuff; int32_t *p_tmp_out_buff = pOutBuff; /* Check parameters setting */ @@ -789,10 +789,10 @@ HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t * @param NbCalc Number of CORDIC calculation to process. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc) { - int32_t *tmp_pInBuff = pInBuff; + const int32_t *tmp_pInBuff = pInBuff; /* Check parameters setting */ if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U)) @@ -881,13 +881,11 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t * DMA transfer to and from the Peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection) { uint32_t sizeinbuff; uint32_t sizeoutbuff; - uint32_t inputaddr; - uint32_t outputaddr; /* Check the parameters */ assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection)); @@ -960,10 +958,9 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_ sizeoutbuff = NbCalc; } - outputaddr = (uint32_t)pOutBuff; - /* Enable the DMA stream managing CORDIC output data read */ - if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, outputaddr, sizeoutbuff) != HAL_OK) + if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, (uint32_t) pOutBuff, sizeoutbuff) + != HAL_OK) { /* Update the error code */ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA; @@ -995,10 +992,9 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_ sizeinbuff = NbCalc; } - inputaddr = (uint32_t)pInBuff; - /* Enable the DMA stream managing CORDIC input data write */ - if (HAL_DMA_Start_IT(hcordic->hdmaIn, inputaddr, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff) != HAL_OK) + if (HAL_DMA_Start_IT(hcordic->hdmaIn, (uint32_t) pInBuff, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff) + != HAL_OK) { /* Update the error code */ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA; @@ -1137,7 +1133,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic) /*Call registered callback*/ hcordic->CalculateCpltCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_CalculateCpltCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } @@ -1169,7 +1165,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic) * the configuration information for CORDIC module * @retval HAL state */ -HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic) +HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic) { /* Return CORDIC handle state */ return hcordic->State; @@ -1182,7 +1178,7 @@ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic) * @note The returned error is a bit-map combination of possible errors * @retval Error bit-map */ -uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic) +uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic) { /* Return CORDIC error code */ return hcordic->ErrorCode; @@ -1207,7 +1203,7 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic) * @param ppInBuff Pointer to pointer to input buffer. * @retval none */ -static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff) +static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff) { /* First write of input data in the Write Data register */ WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff); @@ -1233,7 +1229,7 @@ static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_ * @param ppOutBuff Pointer to pointer to output buffer. * @retval none */ -static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff) +static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff) { /* First read of output data from the Read Data register */ **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA); @@ -1278,7 +1274,7 @@ static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma) /*Call registered callback*/ hcordic->CalculateCpltCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_CalculateCpltCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } @@ -1307,7 +1303,7 @@ static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma) /*Call registered callback*/ hcordic->CalculateCpltCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_CalculateCpltCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } @@ -1332,7 +1328,7 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma) /*Call registered callback*/ hcordic->ErrorCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_ErrorCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c index c5cc592ccb..86b3af2540 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + CLEAR_REG(hcrc->Instance->IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); @@ -403,7 +403,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t * @param hcrc CRC handle * @retval HAL state */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) { /* Return CRC handle state */ return hcrc->State; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c index f030451dab..fb4cad65b8 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c @@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); - /* check polynomial definition vs polynomial size: - * polynomial length must be aligned with polynomial - * definition. HAL_ERROR is reported if Pol degree is - * larger than that indicated by PolyLength. - * Look for MSB position: msb will contain the degree of - * the second to the largest polynomial member. E.g., for - * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + /* Ensure that the generating polynomial is odd */ + if ((Pol & (uint32_t)(0x1U)) == 0U) { + status = HAL_ERROR; } - - switch (PolyLength) + else { - case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_8B: - if (msb >= HAL_CRC_LENGTH_8B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_16B: - if (msb >= HAL_CRC_LENGTH_16B) - { - status = HAL_ERROR; - } - break; - - case CRC_POLYLENGTH_32B: - /* no polynomial definition vs. polynomial length issue possible */ - break; - default: - status = HAL_ERROR; - break; + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } } if (status == HAL_OK) { diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cryp.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cryp.c index 48bf7f89b7..19bbe46e9c 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cryp.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cryp.c @@ -30,7 +30,8 @@ The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows: (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral + (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE() + or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT()) (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() @@ -58,8 +59,10 @@ (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication algorithms) is in words or bytes. (##) The Header used only in AES GCM and CCM Algorithm for authentication. - (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field. - (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes. + (##) The HeaderSize providing the size of the header buffer in words or bytes, + depending upon HeaderWidthUnit field. + (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) + is in words or bytes. (##) The B0 block is the first authentication block used only in AES CCM mode. (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below). @@ -78,7 +81,7 @@ the CRYP peripheral is configured and processes the buffer in input. At second call, no need to Initialize the CRYP, user have to get current configuration via HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set - new parametres, finally user can start encryption/decryption. + new parameters, finally user can start encryption/decryption. (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. @@ -200,7 +203,7 @@ (##) To perform message payload encryption or decryption AES is configured in CTR mode. (##) For authentication two phases are performed : - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message - only cleartext payload (not the ciphertext payload) is used and no outpout. + only cleartext payload (not the ciphertext payload) is used and no output. (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. *** Callback registration *** @@ -316,7 +319,8 @@ * @{ */ #define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey + is 299 clock cycles.*/ #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/ #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */ @@ -350,7 +354,8 @@ * @{ */ -#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__)) +#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR,\ + AES_CR_GCMPH, (uint32_t)(__PHASE__)) /** * @} @@ -390,12 +395,12 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) -static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output); -static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input); -static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output); -static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input); -static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize); -static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize); +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output); +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input); +static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output); +static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input); +static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize); +static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize); static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ @@ -488,7 +493,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and Algorithm */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /* Reset Error Code field */ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; @@ -511,7 +517,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ @@ -600,7 +606,8 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /*clear error flags*/ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); @@ -733,7 +740,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -954,14 +962,14 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) /* If authentication algorithms on-going, carry out first saving steps before disable the peripheral */ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \ - (hcryp->Init.Algorithm == CRYP_AES_CCM)) + (hcryp->Init.Algorithm == CRYP_AES_CCM)) { - /* Save Suspension registers */ - CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); - /* Save Key */ - CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); - /* Save IV */ - CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); + /* Save Suspension registers */ + CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); + /* Save Key */ + CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); + /* Save IV */ + CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); } /* Disable AES */ __HAL_CRYP_DISABLE(hcryp); @@ -974,7 +982,8 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) hcryp->CrypOutCount_saved = hcryp->CrypOutCount; hcryp->Phase_saved = hcryp->Phase; hcryp->State_saved = hcryp->State; - hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size); + hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \ + (hcryp->Size / 4U) : hcryp->Size); hcryp->SizesSum_saved = hcryp->SizesSum; hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation; hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount; @@ -1032,7 +1041,7 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) hcryp->AutoKeyDerivation = hcryp->AutoKeyDerivation_saved; if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ - (hcryp->Init.Algorithm == CRYP_AES_CTR)) + (hcryp->Init.Algorithm == CRYP_AES_CTR)) { hcryp->Init.pInitVect = hcryp->IV_saved; } @@ -1065,14 +1074,16 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) hcryp->ResumingFlag = 1U; if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) { - if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \ + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) { return HAL_ERROR; } } else { - if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \ + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) { return HAL_ERROR; } @@ -1200,7 +1211,8 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { uint32_t algo; HAL_StatusTypeDef status; @@ -1300,7 +1312,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t algo; @@ -1420,26 +1433,26 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) - if (hcryp->ResumingFlag == 1U) - { - hcryp->ResumingFlag = 0U; - if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) - { - hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; - hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; - } - else - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } - } - else + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) + { + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + } + else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } hcryp->pCrypInBuffPtr = Input; hcryp->pCrypOutBuffPtr = Output; @@ -1530,26 +1543,26 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) - if (hcryp->ResumingFlag == 1U) - { - hcryp->ResumingFlag = 0U; - if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) - { - hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; - hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; - } - else - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } - } - else + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) + { + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + } + else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } hcryp->pCrypInBuffPtr = Input; hcryp->pCrypOutBuffPtr = Output; @@ -1703,7 +1716,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu hcryp->Phase = CRYP_PHASE_PROCESS; /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), \ + (uint32_t)(hcryp->pCrypOutBuffPtr)); status = HAL_OK; break; @@ -1856,49 +1870,51 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { + uint32_t itsource = hcryp->Instance->CR; + uint32_t itflag = hcryp->Instance->SR; /* Check if error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET) + if ((itsource & CRYP_IT_ERRIE) != RESET) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET) + if ((itflag & CRYP_IT_WRERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET) + if ((itflag & CRYP_IT_RDERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; } } - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) - { - if(__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + if ((itflag & CRYP_IT_CCF) != RESET) { - /* Clear computation complete flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) + if ((itsource & CRYP_IT_CCFIE) != RESET) { + /* Clear computation complete flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* if header phase */ - if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + + /* if header phase */ + if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } } - else /* if payload phase */ + else /* AES Algorithm ECB,CBC or CTR*/ { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + CRYP_AES_IT(hcryp); } } - else /* AES Algorithm ECB,CBC or CTR*/ - { - CRYP_AES_IT(hcryp); - } } } -} /** * @brief Return the CRYP error code. @@ -2106,15 +2122,17 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); } else { @@ -2134,7 +2152,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure * @param Timeout Specify Timeout value * @retval HAL status -*/ + */ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint16_t incount; /* Temporary CrypInCount Value */ @@ -2307,8 +2325,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2352,15 +2369,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); } else { @@ -2436,8 +2455,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2503,9 +2521,10 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); @@ -2587,7 +2606,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) This case can only occur for GCM and CCM with a payload length not a multiple of 16 bytes */ if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \ - (((hcryp->Size) % 16U) != 0U))) + (((hcryp->Size) % 16U) != 0U))) { /* Call input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -2677,12 +2696,13 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /*Read the output block from the output FIFO */ for (count = 0U; count < 4U; count++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[count] = hcryp->Instance->DOUTR; } count = 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U)) + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; hcryp->CrypOutCount++; @@ -2690,7 +2710,8 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) } } - if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) + if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) + && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) { /* Disable CRYP (not allowed in GCM)*/ __HAL_CRYP_DISABLE(hcryp); @@ -2887,13 +2908,14 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer*/ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUTR; } - i= 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -2916,19 +2938,20 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) if (hcryp->State == HAL_CRYP_STATE_BUSY) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer*/ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUTR; } - i= 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; i++; } - if (hcryp->CrypOutCount == (hcryp->Size / 4U)) + if (hcryp->CrypOutCount == (hcryp->Size / 4U)) { /* Disable Computation Complete flag and errors interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); @@ -2964,13 +2987,13 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } else @@ -2986,7 +3009,7 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if (hcryp->CrypInCount == (hcryp->Size / 4U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3242,7 +3265,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUTR; } for (index = 0U; index < lastwordsize; index++) @@ -3271,9 +3295,10 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) @@ -3358,8 +3383,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3408,7 +3432,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3499,10 +3523,10 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++ ; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -3526,10 +3550,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) header has already been processed; only process here message payload */ { - - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); @@ -3555,7 +3575,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3566,6 +3586,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); } else /* Size < 16Bytes : first block is the last block*/ { @@ -3614,6 +3637,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); } } @@ -3696,8 +3722,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3842,7 +3867,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -3910,10 +3935,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t for (loopcounter = 0U; loopcounter < 4U; loopcounter++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[loopcounter] = hcryp->Instance->DOUTR; } - for (loopcounter = 0U; loopcounterpCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; hcryp->CrypOutCount++; @@ -3941,9 +3967,10 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -4016,8 +4043,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4070,16 +4096,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) } else if (hcryp->Size >= 16U) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -4164,12 +4190,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; loopcounter++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } - } /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) /*Call registered Input complete callback*/ @@ -4183,14 +4209,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) { /* Write the first input header block in the Input FIFO, the following header data will be fed after interrupt occurrence */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/ } /* end of if (dokeyivconfig == 1U) */ else /* Key and IV have already been configured, @@ -4211,16 +4237,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) } else if (hcryp->Size >= 16U) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -4358,8 +4384,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4405,13 +4430,14 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /***************************** Payload phase *******************************/ - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer*/ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUTR; } - i= 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -4419,15 +4445,15 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) } incount = hcryp->CrypInCount; outcount = hcryp->CrypOutCount; - if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) + if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) { - /* When in CCM with Key and IV configuration skipped, don't disable interruptions */ - if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U))) - { + /* When in CCM with Key and IV configuration skipped, don't disable interruptions */ + if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U))) + { /* Disable computation complete flag and errors interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - } + } /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -4459,40 +4485,40 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) - { - /* Call input transfer complete callback */ + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } } - } else /* Last block of payload < 128bit*/ { /* Compute the number of padding bytes in last block of payload */ @@ -4528,13 +4554,13 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } - /* Call input transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4579,9 +4605,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr npblb = 16U - (uint32_t)hcryp->Size; /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/ - reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE); - if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\ - (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT))) + reg = hcryp->Instance->CR & (AES_CR_CHMOD | AES_CR_MODE); + if ((reg == (CRYP_AES_GCM_GMAC | CRYP_OPERATINGMODE_ENCRYPT)) || \ + (reg == (CRYP_AES_CCM | CRYP_OPERATINGMODE_DECRYPT))) { /* Specify the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); @@ -4636,8 +4662,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4645,7 +4670,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUTR; } for (index = 0U; index < lastwordsize; index++) @@ -4660,13 +4686,13 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr /* Process unlocked */ __HAL_UNLOCK(hcryp); - /* Call Output transfer complete callback */ + /* Call Output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } @@ -4685,9 +4711,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4789,17 +4816,17 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - /* Enter last bytes, padded with zeros */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; - hcryp->Instance->DINR = tmp; - loopcounter++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) @@ -4845,9 +4872,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4874,7 +4902,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry if (headersize_in_bytes >= 16U) { /* Initiate header DMA transfer */ - if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK) + if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), + (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK) { return HAL_ERROR; } @@ -4966,9 +4995,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t mode; uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { @@ -5019,7 +5049,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call the input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -5089,28 +5119,28 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - } + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } } else /* Write last header block (4 words), padded with zeros if needed */ { @@ -5140,10 +5170,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -5207,15 +5237,14 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout hcryp->State = HAL_CRYP_STATE_READY; #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); #else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5231,17 +5260,17 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout * as soon as the suspended processing has to be resumed. * @retval None */ -static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output) +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR3; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR2; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR1; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR0; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR3; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR2; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR1; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR0; } /** @@ -5254,17 +5283,17 @@ static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output) * @note AES must be disabled when reconfiguring the IV values. * @retval None */ -static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input) +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input) { uint32_t ivaddr = (uint32_t)Input; - hcryp->Instance->IVR3 = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->IVR2 = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->IVR1 = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->IVR0 = *(uint32_t*)(ivaddr); + hcryp->Instance->IVR3 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR2 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR1 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR0 = *(uint32_t *)(ivaddr); } /** @@ -5277,52 +5306,52 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input) * as soon as the suspended processing has to be resumed. * @retval None */ -static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output) +static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; __IO uint32_t count = 0U; /* In case of GCM payload phase encryption, check that suspension can be carried out */ - if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U)) + if (READ_BIT(hcryp->Instance->CR, + (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | AES_CR_GCMPH_1 | 0x0U)) { - /* Wait for BUSY flag to be cleared */ - count = 0xFFF; - do + /* Wait for BUSY flag to be cleared */ + count = 0xFFF; + do + { + count-- ; + if (count == 0U) { - count-- ; - if(count == 0U) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - HAL_CRYP_ErrorCallback(hcryp); - return; - } + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + HAL_CRYP_ErrorCallback(hcryp); + return; } - while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)); + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)); } - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP7R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP6R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP5R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP4R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP3R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP2R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP1R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP0R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP7R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP6R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP5R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP4R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP3R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP2R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP1R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP0R; } /** @@ -5335,25 +5364,25 @@ static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Outp * @note AES must be disabled when reconfiguring the suspend registers. * @retval None */ -static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input) +static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input) { uint32_t ivaddr = (uint32_t)Input; - hcryp->Instance->SUSP7R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP6R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP5R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP4R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP3R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP2R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP1R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP0R = *(uint32_t*)(ivaddr); + hcryp->Instance->SUSP7R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP6R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP5R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP4R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP3R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP2R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP1R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP0R = *(uint32_t *)(ivaddr); } /** @@ -5366,37 +5395,37 @@ static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Inp * as soon as the suspended processing has to be resumed. * @retval None */ -static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize) +static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize) { uint32_t keyaddr = (uint32_t)Output; switch (KeySize) { case CRYP_KEYSIZE_256B: - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U); + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U); break; case CRYP_KEYSIZE_128B: - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); break; default: break; @@ -5414,29 +5443,29 @@ static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, * @note AES must be disabled when reconfiguring the Key registers. * @retval None */ -static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize) +static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize) { uint32_t keyaddr = (uint32_t)Input; if (KeySize == CRYP_KEYSIZE_256B) { - hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr); - keyaddr+=4U; + hcryp->Instance->KEYR7 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR6 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR5 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR4 = *(uint32_t *)(keyaddr); + keyaddr += 4U; } - hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr); + hcryp->Instance->KEYR3 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR2 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR1 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR0 = *(uint32_t *)(keyaddr); } /** @@ -5464,7 +5493,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) /* Case of header phase resumption =================================================*/ if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) { - /* Set the phase */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; /* Select header phase */ @@ -5473,24 +5502,24 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; } else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ { /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++) + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5513,18 +5542,18 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U) + if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) @@ -5539,32 +5568,32 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) else /* Last block of payload < 128bit*/ { /* Compute the number of padding bytes in last block of payload */ - npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size); + npblb = (((hcryp->Size / 16U) + 1U) * 16U) - (hcryp->Size); cr_temp = hcryp->Instance->CR; - if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || - (((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + if ((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + (((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) { /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U); + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb) << 20U); } /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) ==0U) + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5588,5 +5617,5 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) */ /** - * @} - */ + * @} + */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cryp_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cryp_ex.c index 7b3ac51978..81df1b7455 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cryp_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cryp_ex.c @@ -71,8 +71,8 @@ */ /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions - * @brief Extended processing functions. - * + * @brief Extended processing functions. + * @verbatim ============================================================================== ##### Extended AES processing functions ##### @@ -161,7 +161,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -267,7 +267,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c index 26d8afc74a..5c00e03be9 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c @@ -291,7 +291,7 @@ and a pointer to the user callback function. Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. @@ -306,9 +306,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + reset to the legacy weak (overridden) functions in the HAL_DAC_Init and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -323,7 +323,7 @@ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** DAC HAL driver macros list *** ============================================= @@ -404,7 +404,7 @@ */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -465,7 +465,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -571,6 +571,14 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { + __IO uint32_t wait_loop_index; + + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -583,7 +591,14 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Ensure minimum wait before using peripheral after enabling it */ - HAL_Delay(1); + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */ + /* bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } if (Channel == DAC_CHANNEL_1) { @@ -631,13 +646,17 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); - /* Ensure minimum wait before enabling peripheral after disabling it */ - HAL_Delay(1); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -666,11 +685,18 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; - uint32_t tmpreg = 0U; + uint32_t tmpreg; + __IO uint32_t wait_loop_index; + + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -707,12 +733,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; - default: - break; } } @@ -741,17 +765,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Get DHR12L2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L2; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R2; break; - default: - break; } } - - /* Enable the DMA channel */ if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ @@ -779,7 +799,15 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Ensure minimum wait before using peripheral after enabling it */ - HAL_Delay(1); + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } } else { @@ -805,6 +833,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -813,8 +847,6 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); - /* Ensure minimum wait before enabling peripheral after disabling it */ - HAL_Delay(1); /* Disable the DMA channel */ @@ -855,10 +887,13 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + uint32_t itsource = hdac->Instance->CR; + uint32_t itflag = hdac->Instance->SR; + + if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) { /* Check underrun flag of DAC channel 1 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -870,7 +905,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); /* Disable the selected DAC channel1 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -882,10 +917,10 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) } - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) + if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) { /* Check underrun flag of DAC channel 2 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -897,7 +932,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); /* Disable the selected DAC channel2 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -933,6 +968,12 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui { __IO uint32_t tmp = 0UL; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_ALIGN(Alignment)); @@ -1057,10 +1098,13 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) * Refer to device datasheet for channels availability. * @retval The selected DAC channel data output value. */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) { uint32_t result; + /* Check the DAC peripheral handle */ + assert_param(hdac != NULL); + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -1097,18 +1141,26 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) * Refer to device datasheet for channels availability. * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpreg1; uint32_t tmpreg2; uint32_t tickstart; uint32_t hclkfreq; uint32_t connectOnChip; + /* Check the DAC peripheral handle and channel configuration struct */ + if ((hdac == NULL) || (sConfig == NULL)) + { + return HAL_ERROR; + } + /* Check the DAC parameters */ assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); assert_param(IS_DAC_TRIGGER(hdac->Instance, sConfig->DAC_Trigger)); - assert_param(IS_DAC_TRIGGER(hdac->Instance, sConfig->DAC_Trigger2)); + assert_param(IS_DAC_TRIGGER2(hdac->Instance, sConfig->DAC_Trigger2)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)); assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); @@ -1147,16 +1199,19 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { - /* Update error code */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); - /* Change the DMA state */ - hdac->State = HAL_DAC_STATE_TIMEOUT; + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } - HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } @@ -1168,16 +1223,19 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { - /* Update error code */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); - /* Change the DMA state */ - hdac->State = HAL_DAC_STATE_TIMEOUT; + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } - HAL_Delay(1U); hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } @@ -1212,6 +1270,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ + + if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) { connectOnChip = 0x00000000UL; @@ -1289,7 +1349,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; /* Modify STMODR register value depending on DAC_Channel */ - MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) + << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -1297,7 +1358,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf __HAL_UNLOCK(hdac); /* Return function status */ - return HAL_OK; + return status; } /** @@ -1326,7 +1387,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * the configuration information for the specified DAC. * @retval HAL state */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac) { /* Return DAC handle state */ return hdac->State; @@ -1339,7 +1400,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) * the configuration information for the specified DAC. * @retval DAC Error Code */ -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac) { return hdac->ErrorCode; } @@ -1362,7 +1423,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief Register a User DAC Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback + * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -1386,6 +1449,12 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call { HAL_StatusTypeDef status = HAL_OK; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + if (pCallback == NULL) { /* Update the error code */ @@ -1393,9 +1462,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdac); - if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) @@ -1466,14 +1532,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } /** * @brief Unregister a User DAC Callback - * DAC Callback is redirected to the weak (surcharged) predefined callback + * DAC Callback is redirected to the weak (overridden) predefined callback + * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1494,8 +1560,11 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hdac); + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } if (hdac->State == HAL_DAC_STATE_READY) { @@ -1581,8 +1650,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ @@ -1668,8 +1735,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ #endif /* HAL_DAC_MODULE_ENABLED */ - /** * @} */ - diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c index ea820c5cf0..e6627be90f 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c @@ -23,7 +23,6 @@ ##### How to use this driver ##### ============================================================================== [..] - *** Dual mode IO operation *** ============================== [..] @@ -45,7 +44,6 @@ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. - *** Signal generation operation *** =================================== [..] @@ -85,6 +83,16 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/* Delay for DAC minimum trimming time. */ +/* Note: minimum time needed between two calibration steps */ +/* The delay below is specified under conditions: */ +/* - DAC channel output buffer enabled */ +/* Literal set to maximum value (refer to device datasheet, */ +/* electrical characteristics, parameter "tTRIM"). */ +/* Unit: us */ +#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -123,6 +131,13 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) { uint32_t tmp_swtrig = 0UL; + __IO uint32_t wait_loop_index; + + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); @@ -137,7 +152,15 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before using peripheral after enabling it */ - HAL_Delay(1); + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) @@ -169,14 +192,18 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); - /* Ensure minimum wait before enabling peripheral after disabling it */ - HAL_Delay(1); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -202,11 +229,18 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, - uint32_t Alignment) +HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, + const uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; uint32_t tmpreg = 0UL; + __IO uint32_t wait_loop_index; + + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -294,7 +328,15 @@ HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Chan __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before using peripheral after enabling it */ - HAL_Delay(1); + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } } else { @@ -319,6 +361,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann { HAL_StatusTypeDef status; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Ensure Channel 2 exists for this particular DAC instance */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); @@ -328,8 +376,6 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); - /* Ensure minimum wait before enabling peripheral after disabling it */ - HAL_Delay(1); /* Disable the DMA channel */ @@ -397,6 +443,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann */ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -450,6 +502,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 */ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -501,6 +559,12 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity, uint32_t ResetData, uint32_t StepData) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_SAWTOOTH_POLARITY(Polarity)); @@ -533,7 +597,9 @@ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32 } /* Enable the sawtooth wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1) << (Channel & 0x10UL), (uint32_t)(DAC_CR_WAVE1_1 | DAC_CR_WAVE1_0) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->CR, + (DAC_CR_WAVE1) << (Channel & 0x10UL), + (uint32_t)(DAC_CR_WAVE1_1 | DAC_CR_WAVE1_0) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -564,6 +630,12 @@ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint3 { HAL_StatusTypeDef status = HAL_OK; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -620,6 +692,12 @@ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32 { HAL_StatusTypeDef status = HAL_OK; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -678,6 +756,12 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Align uint32_t data; uint32_t tmp; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); @@ -788,9 +872,9 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo { HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t tmp; uint32_t trimmingvalue; uint32_t delta; + __IO uint32_t wait_loop_index; /* store/restore channel configuration structure purpose */ uint32_t oldmodeconfiguration; @@ -800,7 +884,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Check the DAC handle allocation */ /* Check if DAC running */ - if (hdac == NULL) + if ((hdac == NULL) || (sConfig == NULL)) { status = HAL_ERROR; } @@ -824,20 +908,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set mode in MCR for calibration */ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); - /* Set DAC Channel1 DHR register to the middle value */ - tmp = (uint32_t)hdac->Instance; - - if (Channel == DAC_CHANNEL_1) - { - tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); - } - else - { - tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R); - } - - *(__IO uint32_t *) tmp = 0x0800UL; - /* Enable the selected DAC channel calibration */ /* i.e. set DAC_CR_CENx bit */ SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); @@ -851,9 +921,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); - /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ - /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1); + /* Wait minimum time needed between two calibration steps (OTRIM) */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ + /* 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) { @@ -873,9 +949,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); - /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ - /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1U); + /* Wait minimum time needed between two calibration steps (OTRIM) */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ + /* 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { @@ -926,8 +1008,8 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue)); - /* Check the DAC handle allocation */ - if (hdac == NULL) + /* Check the DAC handle and channel configuration struct allocation */ + if ((hdac == NULL) || (sConfig == NULL)) { status = HAL_ERROR; } @@ -962,7 +1044,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * @retval Trimming value : range: 0->31 * */ -uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameter */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -996,7 +1078,7 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac) { uint32_t tmp = 0UL; @@ -1097,4 +1179,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) /** * @} */ - diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c index 8666cb5b13..871928c6ef 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c @@ -65,7 +65,7 @@ (++) Provide exiting handle as parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). (++) Provide exiting handle as parameter. (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). @@ -348,7 +348,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; - pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u))))); + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; } } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c index ebc9188424..be0a0a656a 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c @@ -96,7 +96,7 @@ *** Callback registration *** ============================================= - The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 + The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() to register an interrupt callback. @@ -114,7 +114,7 @@ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated - register callbacks : respectively HAL_FDCAN_RegisterTxEventFifoCallback(), + register callbacks: respectively HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback() and HAL_FDCAN_RegisterErrorStatusCallback(). @@ -134,7 +134,7 @@ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated - unregister callbacks : respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(), + unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback() and HAL_FDCAN_UnRegisterErrorStatusCallback(). @@ -249,9 +249,15 @@ static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, */ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FDCAN_Private_Functions_Prototypes + * @{ + */ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, - uint32_t BufferIndex); +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions @@ -327,22 +333,17 @@ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) hfdcan->Lock = HAL_UNLOCKED; /* Reset callbacks to legacy functions */ - hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ - hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ - hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ - hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ - hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak - TxBufferCompleteCallback */ - hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak - TxBufferAbortCallback */ - hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak - HighPriorityMessageCallback */ - hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak - TimestampWraparoundCallback */ - hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak - TimeoutOccurredCallback */ - hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */ - hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */ + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */ + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */ + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */ + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */ + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */ + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */ + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */ + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* TimeoutOccurredCallback */ + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* ErrorCallback */ + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* ErrorStatusCallback */ if (hfdcan->MspInitCallback == NULL) { @@ -582,7 +583,7 @@ __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_MspInit could be implemented in the user file */ } @@ -597,7 +598,7 @@ __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_MspDeInit could be implemented in the user file */ } @@ -1292,7 +1293,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h * contains the filter configuration information * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig) +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig) { uint32_t FilterElementW1; uint32_t FilterElementW2; @@ -1417,7 +1418,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @param Mask Extended ID Mask. - This parameter must be a number between 0 and 0x1FFFFFFF + * This parameter must be a number between 0 and 0x1FFFFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask) @@ -1607,7 +1608,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan) * the configuration information for the specified FDCAN. * @retval Timestamp counter value */ -uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan) { return (uint16_t)(hfdcan->Instance->TSCV); } @@ -1730,7 +1731,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) * the configuration information for the specified FDCAN. * @retval Timeout counter value */ -uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan) { return (uint16_t)(hfdcan->Instance->TOCV); } @@ -2103,8 +2104,8 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) * @param pTxData pointer to a buffer containing the payload of the Tx frame. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, - uint8_t *pTxData) +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData) { uint32_t PutIndex; @@ -2171,7 +2172,7 @@ HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDC * - Any value of @arg FDCAN_Tx_location if Tx request has been submitted. * - 0 if no Tx FIFO/Queue request have been submitted. */ -uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan) { /* Return Last Tx FIFO/Queue Request Buffer */ return hfdcan->LatestTxFifoQRequest; @@ -2223,7 +2224,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R uint32_t *RxAddress; uint8_t *pData; uint32_t ByteCounter; - uint32_t GetIndex; + uint32_t GetIndex = 0; HAL_FDCAN_StateTypeDef state = hfdcan->State; /* Check function parameters */ @@ -2243,8 +2244,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Check that the Rx FIFO 0 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 0 element index */ + GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + /* Calculate Rx FIFO 0 element address */ - GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE)); } } @@ -2260,8 +2273,19 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Check that the Rx FIFO 1 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 1 element index */ + GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); /* Calculate Rx FIFO 1 element address */ - GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE)); } } @@ -2292,7 +2316,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS); /* Retrieve DataLength */ - pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC); + pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); /* Retrieve BitRateSwitch */ pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS); @@ -2311,7 +2335,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R /* Retrieve Rx payload */ pData = (uint8_t *)RxAddress; - for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++) + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++) { pRxData[ByteCounter] = pData[ByteCounter]; } @@ -2393,7 +2417,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS); /* Retrieve DataLength */ - pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC); + pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); /* Retrieve BitRateSwitch */ pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS); @@ -2429,7 +2453,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus) { HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos); @@ -2448,7 +2472,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hf * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus) +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus) { uint32_t StatusReg; @@ -2479,7 +2504,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters) +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters) { uint32_t CountersReg; @@ -2503,10 +2529,10 @@ HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ * @param TxBufferIndex Tx buffer index. * This parameter can be any combination of @arg FDCAN_Tx_location. * @retval Status - * - 0 : No pending transmission request on TxBufferIndex list + * - 0 : No pending transmission request on TxBufferIndex list. * - 1 : Pending transmission request on TxBufferIndex. */ -uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) { /* Check function parameters */ assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex)); @@ -2529,7 +2555,7 @@ uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_ * @arg FDCAN_RX_FIFO1: Rx FIFO 1 * @retval Rx FIFO fill level. */ -uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) { uint32_t FillLevel; @@ -2556,7 +2582,7 @@ uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi * the configuration information for the specified FDCAN. * @retval Tx FIFO free level. */ -uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan) { uint32_t FreeLevel; @@ -2574,7 +2600,7 @@ uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan) * - 0 : Normal FDCAN operation. * - 1 : Restricted Operation Mode active. */ -uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan) { uint32_t OperationMode; @@ -2885,6 +2911,8 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) uint32_t ErrorStatusITs; uint32_t TransmittedBuffers; uint32_t AbortedBuffers; + uint32_t itsource; + uint32_t itflag; TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK; TxEventFifoITs &= hfdcan->Instance->IE; @@ -2896,11 +2924,13 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) Errors &= hfdcan->Instance->IE; ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK; ErrorStatusITs &= hfdcan->Instance->IE; + itsource = hfdcan->Instance->IE; + itflag = hfdcan->Instance->IR; /* High Priority Message interrupt management *******************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET) { /* Clear the High Priority Message flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG); @@ -2916,9 +2946,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Transmission Abort interrupt management **********************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) { /* List of aborted monitored buffers */ AbortedBuffers = hfdcan->Instance->TXBCF; @@ -2983,9 +3013,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Tx FIFO empty interrupt management ***************************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_FIFO_EMPTY) != RESET) { /* Clear the Tx FIFO empty flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY); @@ -3001,9 +3031,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Transmission Complete interrupt management *******************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_COMPLETE) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_COMPLETE) != RESET) { /* List of transmitted monitored buffers */ TransmittedBuffers = hfdcan->Instance->TXBTO; @@ -3023,9 +3053,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Timestamp Wraparound interrupt management ********************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET) { /* Clear the Timestamp Wraparound flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND); @@ -3041,9 +3071,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Timeout Occurred interrupt management ************************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) { /* Clear the Timeout Occurred flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED); @@ -3059,9 +3089,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Message RAM access failure interrupt management **************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) { /* Clear the Message RAM access failure flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE); @@ -3141,7 +3171,7 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) * @brief Tx Event callback. * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. - * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled. + * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts. * @retval None */ @@ -3151,7 +3181,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t UNUSED(hfdcan); UNUSED(TxEventFifoITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file */ } @@ -3160,7 +3190,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t * @brief Rx FIFO 0 callback. * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. - * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled. + * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts. * @retval None */ @@ -3170,7 +3200,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi UNUSED(hfdcan); UNUSED(RxFifo0ITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxFifo0Callback could be implemented in the user file */ } @@ -3179,7 +3209,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi * @brief Rx FIFO 1 callback. * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. - * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled. + * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts. * @retval None */ @@ -3189,7 +3219,7 @@ __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi UNUSED(hfdcan); UNUSED(RxFifo1ITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxFifo1Callback could be implemented in the user file */ } @@ -3205,7 +3235,7 @@ __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file */ } @@ -3224,7 +3254,7 @@ __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint UNUSED(hfdcan); UNUSED(BufferIndexes); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file */ } @@ -3243,7 +3273,7 @@ __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_ UNUSED(hfdcan); UNUSED(BufferIndexes); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file */ } @@ -3259,7 +3289,7 @@ __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file */ } @@ -3275,7 +3305,7 @@ __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file */ } @@ -3291,7 +3321,7 @@ __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file */ } @@ -3307,7 +3337,7 @@ __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorCallback could be implemented in the user file */ } @@ -3326,7 +3356,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t UNUSED(hfdcan); UNUSED(ErrorStatusITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file */ } @@ -3356,7 +3386,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t * the configuration information for the specified FDCAN. * @retval HAL state */ -HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan) +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan) { /* Return FDCAN state */ return hfdcan->State; @@ -3368,7 +3398,7 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan) * the configuration information for the specified FDCAN. * @retval FDCAN Error Code */ -uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan) { /* Return FDCAN error code */ return hfdcan->ErrorCode; @@ -3450,8 +3480,8 @@ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) * @param BufferIndex index of the buffer to be configured. * @retval none */ -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, - uint32_t BufferIndex) +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex) { uint32_t TxElementW1; uint32_t TxElementW2; @@ -3479,7 +3509,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy pTxHeader->TxEventFifoControl | pTxHeader->FDFormat | pTxHeader->BitRateSwitch | - pTxHeader->DataLength); + (pTxHeader->DataLength << 16U)); /* Calculate Tx element address */ TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE)); @@ -3491,7 +3521,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy TxAddress++; /* Write Tx payload to the message RAM */ - for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U) + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U) { *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) | ((uint32_t)pTxData[ByteCounter + 2U] << 16U) | diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c index 261fae7d19..0ddb6b4b84 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c @@ -188,6 +188,17 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint { pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Deactivate the data cache if they are activated to avoid data misbehavior */ + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) + { + /* Disable data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; + } + else + { + pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; + } if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) { /* Program double-word (64-bit) at a specified address */ @@ -218,6 +229,9 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint { CLEAR_BIT(FLASH->CR, prog_bit); } + + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); } /* Process Unlocked */ @@ -251,6 +265,18 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Deactivate the data cache if they are activated to avoid data misbehavior */ + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) + { + /* Disable data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; + } + else + { + pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; + } + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); @@ -328,7 +354,7 @@ void HAL_FLASH_IRQHandler(void) __HAL_FLASH_CLEAR_FLAG(error); /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; + FLASH_FlushCaches(); /* FLASH error interrupt user callback */ procedure = pFlash.ProcedureOnGoing; @@ -384,7 +410,7 @@ void HAL_FLASH_IRQHandler(void) pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; + FLASH_FlushCaches(); /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Page); @@ -393,7 +419,7 @@ void HAL_FLASH_IRQHandler(void) else { /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; + FLASH_FlushCaches(); procedure = pFlash.ProcedureOnGoing; if (procedure == FLASH_PROC_MASS_ERASE) diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c index 8baeef666b..073eb3187b 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c @@ -477,10 +477,14 @@ HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank) } } else -#endif { SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1); } +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Bank); + SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1); +#endif /* FLASH_OPTR_DBANK */ return HAL_OK; } @@ -598,7 +602,10 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) SET_BIT(FLASH->CR, FLASH_CR_BKER); } } -#endif +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Banks); +#endif /* FLASH_OPTR_DBANK */ /* Proceed to erase the page */ MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos)); @@ -790,6 +797,18 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon if (status == HAL_OK) { +#if defined(FLASH_OPTR_PB4_PUPEN) + if ((UserType & OB_USER_PB4_PUPEN) != 0U) + { + /* PB4_PUPEN option byte should be modified */ + assert_param(IS_OB_USER_PB4_PUPEN(UserConfig & FLASH_OPTR_PB4_PUPEN)); + + /* Set value and mask for PB4_PUPEN option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_PB4_PUPEN); + optr_reg_mask |= FLASH_OPTR_PB4_PUPEN; + } +#endif /* FLASH_OPTR_PB4_PUPEN */ + if ((UserType & OB_USER_BOR_LEV) != 0U) { /* BOR level option byte should be modified */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fmac.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fmac.c index f0abb56dc5..db8f2617c4 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fmac.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fmac.c @@ -166,7 +166,7 @@ [..] Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: @@ -182,10 +182,10 @@ [..] By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples GetDataCallback(), OutputDataReadyCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init() + reset to the legacy weak functions in the HAL_FMAC_Init() and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -202,7 +202,7 @@ [..] When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -528,6 +528,8 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac) /** * @brief Register a User FMAC Callback. * @note The User FMAC Callback is to be used instead of the weak predefined callback. + * @note The HAL_FMAC_RegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register + * callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param CallbackID ID of the callback to be registered. @@ -562,7 +564,6 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ return HAL_ERROR; } - __HAL_LOCK(hfmac); if (hfmac->State == HAL_FMAC_STATE_READY) { @@ -643,14 +644,14 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ status = HAL_ERROR; } - __HAL_UNLOCK(hfmac); - return status; } /** * @brief Unregister a FMAC CallBack. * @note The FMAC callback is redirected to the weak predefined callback. + * @note The HAL_FMAC_UnRegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register + * callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module * @param CallbackID ID of the callback to be unregistered. @@ -676,8 +677,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA return HAL_ERROR; } - __HAL_LOCK(hfmac); - if (hfmac->State == HAL_FMAC_STATE_READY) { switch (CallbackID) @@ -760,8 +759,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA status = HAL_ERROR; } - __HAL_UNLOCK(hfmac); - return status; } #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ @@ -1530,7 +1527,7 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) * the configuration information for FMAC module. * @retval HAL_FMAC_StateTypeDef FMAC state */ -HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac) +HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac) { /* Return FMAC state */ return hfmac->State; @@ -1543,7 +1540,7 @@ HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac) * @note The returned error is a bit-map combination of possible errors. * @retval uint32_t Error bit-map based on @ref FMAC_Error_Code */ -uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac) +uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac) { /* Return FMAC error code */ return hfmac->ErrorCode; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_hrtim.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_hrtim.c index 1bb9952ca8..7b0ab49193 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_hrtim.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_hrtim.c @@ -445,22 +445,22 @@ static uint32_t TimerIdxToTimerId[] = * @{ */ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef * pTimerCfg); static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef * pTimerCfg); static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCtlTypeDef * pTimerCtl); + const HRTIM_TimerCtlTypeDef * pTimerCtl); static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, @@ -475,29 +475,29 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef * pOutputCfg); static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Event, - HRTIM_EventCfgTypeDef * pEventCfg); + const HRTIM_EventCfgTypeDef * pEventCfg); static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Event); -static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim, +static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx); -static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim, - DMA_HandleTypeDef * hdma); +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, + const DMA_HandleTypeDef * hdma); static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx); @@ -913,7 +913,7 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -1384,7 +1384,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel, - HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) + const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) { uint32_t CompareUnit = (uint32_t)RESET; HRTIM_OutputCfgTypeDef OutputCfg; @@ -2027,7 +2027,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, - HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg) + const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; uint32_t hrtim_timcr; @@ -2722,7 +2722,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, - HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg) + const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg) { HRTIM_EventCfgTypeDef EventCfg; @@ -3386,7 +3386,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel, - HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg) + const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; HRTIM_EventCfgTypeDef EventCfg; @@ -3826,7 +3826,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, * controller */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, - HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) + const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) { uint32_t hrtim_bmcr; @@ -3907,7 +3907,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Event, - HRTIM_EventCfgTypeDef* pEventCfg) + const HRTIM_EventCfgTypeDef* pEventCfg) { /* Check parameters */ assert_param(IS_HRTIM_EVENT(Event)); @@ -3995,7 +3995,7 @@ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Fault, - HRTIM_FaultCfgTypeDef* pFaultCfg) + const HRTIM_FaultCfgTypeDef* pFaultCfg) { uint32_t hrtim_fltinr1; uint32_t hrtim_fltinr2; @@ -4189,7 +4189,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim, uint32_t Fault, - HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg) + const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Fault)); @@ -4300,7 +4300,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * h */ HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Fault, - HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg) + const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Fault)); @@ -4559,7 +4559,7 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t ADCTrigger, - HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) + const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) { uint32_t hrtim_cr1; uint32_t hrtim_adcur; @@ -4958,7 +4958,7 @@ HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef * pTimerCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -5062,7 +5062,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCtlTypeDef * pTimerCtl) + const HRTIM_TimerCtlTypeDef * pTimerCtl) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -5118,7 +5118,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCtlTypeDef * pTimerCtl) + const HRTIM_TimerCtlTypeDef * pTimerCtl) { assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset)); assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep)); @@ -5185,7 +5185,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrt HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Event, - HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) + const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); @@ -5321,7 +5321,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t EventCounter, - HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg) + const HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg) { uint32_t hrtim_eefr3; @@ -5561,7 +5561,7 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) + const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) { uint32_t hrtim_dtr; @@ -5627,7 +5627,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) + const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) { uint32_t hrtim_chpr; @@ -5653,9 +5653,9 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW); /* Update the HRTIM registers */ - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR, (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | - HRTIM_CHPR_STRPW) , - hrtim_chpr); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR, + (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW), + hrtim_chpr); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5820,7 +5820,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - HRTIM_CompareCfgTypeDef* pCompareCfg) + const HRTIM_CompareCfgTypeDef* pCompareCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -6022,7 +6022,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - HRTIM_CaptureCfgTypeDef* pCaptureCfg) + const HRTIM_CaptureCfgTypeDef* pCaptureCfg) { uint32_t Trigger; uint32_t TimerF_Trigger = (uint32_t)(pCaptureCfg->Trigger >> 32); @@ -6131,7 +6131,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg) + const HRTIM_OutputCfgTypeDef * pOutputCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -7334,7 +7334,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval HAL state */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim) +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) { /* Return HRTIM state */ return hhrtim->State; @@ -7357,7 +7357,7 @@ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim) * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval Captured value */ -uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -7385,11 +7385,6 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, default: { captured_value = 0xFFFFFFFFUL; - - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); break; } @@ -7415,7 +7410,7 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval captured value and direction structure */ -HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(HRTIM_HandleTypeDef * hhrtim, +HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -7442,10 +7437,6 @@ HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(HRTIM_HandleTypeDef * hhrtim, default: captured.Value = 0xFFFFFFFFUL; captured.Dir = 0xFFFFFFFFUL; - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); break; } @@ -7472,7 +7463,7 @@ HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERUPDOWNMODE_UP * @arg HRTIM_TIMERUPDOWNMODE_UPDOWN */ -uint32_t HAL_HRTIM_GetCapturedDir(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -7493,10 +7484,6 @@ uint32_t HAL_HRTIM_GetCapturedDir(HRTIM_HandleTypeDef * hhrtim, break; default: tmp = 0xFFFFFFFFU; - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); break; } @@ -7533,11 +7520,11 @@ uint32_t HAL_HRTIM_GetCapturedDir(HRTIM_HandleTypeDef * hhrtim, * @note Returned output level is taken before the output stage (chopper, * polarity). */ -uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output) { - uint32_t output_level = (uint32_t)RESET; + uint32_t output_level; /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -7583,20 +7570,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim, default: { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); - + output_level = 0xFFFFFFFFUL; break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return (uint32_t)HAL_ERROR; - } - return output_level; } @@ -7627,11 +7605,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval Output state */ -uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output) { - uint32_t output_bit = (uint32_t)RESET; + uint32_t output_bit; uint32_t output_state; /* Check parameters */ @@ -7717,20 +7695,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, default: { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); - + output_bit = 0UL; break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return (uint32_t)HAL_ERROR; - } - if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET) { /* Output is enabled: output in RUN state (whatever output disable status is)*/ @@ -7781,11 +7750,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval Delayed protection status */ -uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output) { - uint32_t delayed_protection_status = (uint32_t)RESET; + uint32_t delayed_protection_status; /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -7835,20 +7804,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim, default: { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); - + delayed_protection_status = 0xFFFFFFFFUL; break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return (uint32_t)HAL_ERROR; - } - return delayed_protection_status; } @@ -7857,7 +7817,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim) +uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) { uint32_t burst_mode_status; @@ -7881,7 +7841,7 @@ uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx) { uint32_t current_pushpull_status; @@ -7910,7 +7870,7 @@ uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval Idle Push Pull Status */ -uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx) { uint32_t idle_pushpull_status; @@ -9106,7 +9066,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @retval None */ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) { uint32_t hrtim_mcr; @@ -9135,8 +9095,8 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, * @retval None */ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx , - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + uint32_t TimerIdx , + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) { uint32_t hrtim_timcr; @@ -9164,7 +9124,7 @@ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, * @retval None */ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef * pTimerCfg) { uint32_t hrtim_mcr; uint32_t hrtim_bmcr; @@ -9243,7 +9203,7 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef * pTimerCfg) { uint32_t hrtim_timcr; uint32_t hrtim_timfltr; @@ -9422,7 +9382,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCtlTypeDef * pTimerCtl) + const HRTIM_TimerCtlTypeDef * pTimerCtl) { uint32_t hrtim_timcr2; @@ -9605,7 +9565,7 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg) + const HRTIM_OutputCfgTypeDef * pOutputCfg) { uint32_t hrtim_outr; uint32_t hrtim_dtr; @@ -9697,7 +9657,7 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Event, - HRTIM_EventCfgTypeDef *pEventCfg) + const HRTIM_EventCfgTypeDef *pEventCfg) { uint32_t hrtim_eecr1; uint32_t hrtim_eecr2; @@ -9963,7 +9923,7 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval Interrupt to enable or disable */ -static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -10073,7 +10033,7 @@ static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval DMA request to enable or disable */ -static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -10162,7 +10122,7 @@ static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, return dma_request; } -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim, +static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx) { DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL; @@ -10218,8 +10178,8 @@ static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * return hdma; } -static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim, - DMA_HandleTypeDef * hdma) +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, + const DMA_HandleTypeDef * hdma) { uint32_t timed_idx = 0xFFFFFFFFU; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c index af526a95e1..59da55da72 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c @@ -400,9 +400,15 @@ * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ /* Macro to get remaining data to transfer on DMA side */ #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -418,6 +424,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAError(DMA_HandleTypeDef *hdma); static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + /* Private functions to handle IT transfer */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); @@ -438,10 +445,14 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Private functions for I2C transfer IRQ handler */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); @@ -597,7 +608,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); @@ -707,6 +723,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) /** * @brief Register a User I2C Callback * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be registered @@ -737,8 +755,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -827,14 +843,14 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } /** * @brief Unregister an I2C Callback * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be unregistered @@ -857,9 +873,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { switch (CallbackID) @@ -947,8 +960,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -971,8 +982,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -987,8 +996,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -1003,9 +1010,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ @@ -1019,8 +1023,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -1118,6 +1120,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1141,18 +1144,39 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferCount = Size; hi2c->XferISR = NULL; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_GENERATE_START_WRITE); + xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); } @@ -1355,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1389,6 +1415,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData return HAL_ERROR; } + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1435,31 +1474,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -1662,7 +1718,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_START_WRITE); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1785,6 +1860,20 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1871,6 +1960,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1903,6 +1993,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t xfermode = I2C_AUTOEND_MODE; } + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + if (hi2c->XferSize > 0U) { if (hi2c->hdmatx != NULL) @@ -1918,8 +2022,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { @@ -1940,7 +2044,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), + xfermode, I2C_GENERATE_START_WRITE); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -1979,7 +2084,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ @@ -2135,11 +2240,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -2183,67 +2288,99 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - if (hi2c->hdmatx != NULL) + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; - /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + hi2c->XferCount--; + hi2c->XferSize--; } - else + + if (hi2c->XferCount != 0U) { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - return HAL_ERROR; - } + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); } return HAL_OK; @@ -2357,6 +2494,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD return HAL_BUSY; } } + /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2647,9 +2785,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2669,41 +2804,38 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ + hi2c->XferSize = 0U; hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2741,9 +2873,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2763,9 +2892,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2774,29 +2900,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2805,11 +2931,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } @@ -2818,6 +2944,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre return HAL_BUSY; } } + /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2833,8 +2960,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2856,9 +2981,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2867,28 +2989,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } if (hi2c->hdmatx != NULL) { @@ -2923,12 +3053,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if (dmaxferstatus == HAL_OK) { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2936,11 +3062,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -2980,8 +3106,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3003,9 +3127,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -3014,25 +3135,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } if (hi2c->hdmarx != NULL) @@ -3068,11 +3199,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if (dmaxferstatus == HAL_OK) { - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3080,11 +3208,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -3213,22 +3341,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - /* Increment Trials */ I2C_Trials++; } while (I2C_Trials < Trials); @@ -3267,6 +3379,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3298,6 +3411,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3319,7 +3447,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 } /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3327,6 +3462,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -3355,6 +3494,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3386,6 +3526,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 xfermode = hi2c->XferOptions; } + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3421,8 +3576,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { @@ -3442,7 +3597,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 if (dmaxferstatus == HAL_OK) { /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -3481,8 +3643,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_WRITE); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3745,11 +3913,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -3773,6 +3941,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3832,7 +4003,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -3869,6 +4041,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3903,7 +4077,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA RX */ @@ -3925,7 +4099,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ if (hi2c->hdmatx != NULL) { /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA TX */ @@ -4010,7 +4184,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4050,6 +4225,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4109,7 +4287,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4146,6 +4325,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4287,7 +4468,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4439,7 +4621,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA * the configuration information for the specified I2C. * @retval None */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ { /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); @@ -4692,7 +4874,7 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval HAL state */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) { /* Return I2C handle state */ return hi2c->State; @@ -4704,7 +4886,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) * the configuration information for I2C module * @retval HAL mode */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) { return hi2c->Mode; } @@ -4715,7 +4897,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval I2C Error Code */ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; } @@ -4778,17 +4960,22 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ + ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) { /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; + if (hi2c->XferCount != 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; - hi2c->XferSize--; - hi2c->XferCount--; + hi2c->XferSize--; + hi2c->XferCount--; + } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) @@ -4879,87 +5066,229 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } /** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param ITFlags Interrupt flags to handle. * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { - uint32_t tmpoptions = hi2c->XferOptions; + uint32_t direction = I2C_GENERATE_START_WRITE; uint32_t tmpITFlags = ITFlags; - /* Process locked */ + /* Process Locked */ __HAL_LOCK(hi2c); - /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, tmpITFlags); - } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hi2c->XferCount == 0U) - { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for - Warning[Pa134]: left and right operands are identical */ - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, tmpITFlags); - } - else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - } + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { - if (hi2c->XferCount > 0U) - { - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; /* Increment Buffer pointer */ hi2c->pBuffPtr++; @@ -5159,6 +5488,154 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -5184,9 +5661,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5785,6 +6261,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ @@ -5801,6 +6278,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } else { /* Do nothing */ @@ -5867,6 +6349,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5994,6 +6527,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ @@ -6021,18 +6555,36 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { @@ -6207,6 +6759,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C slave transmit process complete callback. * @param hdma DMA handle @@ -6235,6 +6788,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C master receive process complete callback. * @param hdma DMA handle @@ -6285,6 +6839,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C slave receive process complete callback. * @param hdma DMA handle @@ -6313,6 +6868,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C communication error callback. * @param hdma DMA handle @@ -6330,6 +6886,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); } + /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). @@ -6354,6 +6911,7 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_TreatErrorCallback(hi2c); } + /** * @brief This function handles I2C Communication Timeout. It waits * until a flag is no longer in the specified status. @@ -6370,18 +6928,27 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } } } } @@ -6412,14 +6979,17 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -6448,14 +7018,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6472,16 +7045,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -6489,19 +7064,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -6515,23 +7085,30 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } } } - return HAL_OK; + return status; } /** @@ -6585,14 +7162,11 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + error_code |= HAL_I2C_ERROR_TIMEOUT; status = HAL_ERROR; + + break; } } } @@ -6696,14 +7270,14 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP)), tmp); + I2C_CR2_START | I2C_CR2_STOP)), tmp); } /** @@ -6717,8 +7291,9 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { @@ -6726,6 +7301,18 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ @@ -6735,39 +7322,46 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); - } - - if (InterruptRequest == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; + tmpisr |= I2C_IT_STOPI; } } + else { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ + /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; } } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_irda.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_irda.c index 31247d35cf..dfaadca34b 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_irda.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_irda.c @@ -142,7 +142,7 @@ [..] Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -159,10 +159,10 @@ [..] By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + reset to the legacy weak functions in the HAL_IRDA_Init() and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -179,7 +179,7 @@ [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim ****************************************************************************** @@ -462,7 +462,9 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /** * @brief Register a User IRDA Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback + * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -491,8 +493,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hirda); if (hirda->gState == HAL_IRDA_STATE_READY) { @@ -577,15 +577,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } /** * @brief Unregister an IRDA callback * IRDA callback is redirected to the weak predefined callback + * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -605,9 +604,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hirda); - if (HAL_IRDA_STATE_READY == hirda->gState) { switch (CallbackID) @@ -693,9 +689,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ @@ -2192,7 +2185,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval HAL state */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ uint32_t temp1; @@ -2209,7 +2202,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval IRDA Error Code */ -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) { return hirda->ErrorCode; } @@ -2433,7 +2426,6 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) hirda->gState = HAL_IRDA_STATE_READY; } - /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_lptim.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_lptim.c index ea4d51886c..a2186a7fef 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_lptim.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_lptim.c @@ -188,7 +188,7 @@ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag); /* Exported functions --------------------------------------------------------*/ @@ -458,7 +458,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -506,7 +506,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -523,7 +523,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -534,7 +534,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -545,7 +545,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF + * This parameter must be a value between 0x0001 and 0xFFFF * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF * @retval HAL status @@ -623,7 +623,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -640,7 +640,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -670,7 +670,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -681,7 +681,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -729,7 +729,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -757,7 +757,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -768,7 +768,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -846,7 +846,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -866,6 +866,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -893,7 +894,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -904,7 +905,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM in Set once mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -952,7 +953,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -980,7 +981,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1069,7 +1070,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1116,7 +1117,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1127,7 +1128,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Encoder interface. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1177,7 +1178,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1208,7 +1209,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1287,7 +1288,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1324,7 +1325,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable "switch to up direction" interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1337,7 +1338,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1385,7 +1386,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1416,7 +1417,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1429,7 +1430,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1494,7 +1495,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1511,12 +1512,13 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1531,7 +1533,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1542,7 +1544,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1582,7 +1584,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1610,7 +1612,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1621,7 +1623,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1681,7 +1683,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1698,12 +1700,13 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1717,7 +1720,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1748,7 +1751,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Counter value. */ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1761,7 +1764,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Autoreload value. */ -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1774,7 +1777,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Compare value. */ -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -2069,9 +2072,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2142,9 +2142,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } @@ -2170,9 +2167,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2254,9 +2248,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -2284,7 +2275,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti * @param hlptim LPTIM handle * @retval HAL state */ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim) { /* Return LPTIM handle state */ return hlptim->State; @@ -2331,7 +2322,7 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) * @param flag The lptim flag * @retval HAL status */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag) { HAL_StatusTypeDef result = HAL_OK; uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_nand.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_nand.c index ec30b3e808..99591335ec 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_nand.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_nand.c @@ -77,15 +77,15 @@ and a pointer to the user callback function. Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_NAND_Init + reset to the legacy weak (overridden) functions in the HAL_NAND_Init and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -100,7 +100,7 @@ When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -515,8 +515,8 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; @@ -673,8 +673,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; @@ -841,8 +841,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; @@ -850,7 +850,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; - uint8_t *buff = pBuffer; + const uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -994,8 +994,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; @@ -1003,7 +1003,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; - uint16_t *buff = pBuffer; + const uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1158,8 +1158,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumSpareAreaToRead) +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; @@ -1323,7 +1323,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; @@ -1488,8 +1488,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; @@ -1498,7 +1498,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; - uint8_t *buff = pBuffer; + const uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1651,8 +1651,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; @@ -1661,7 +1661,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; - uint16_t *buff = pBuffer; + const uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1812,7 +1812,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A * @param pAddress pointer to NAND address structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress) { uint32_t deviceaddress; @@ -1868,7 +1868,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address */ -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { uint32_t status = NAND_VALID_ADDRESS; @@ -1899,7 +1899,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /** * @brief Register a User NAND Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hnand : NAND handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1919,9 +1919,6 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hnand); - if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) @@ -1963,14 +1960,12 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnand); return status; } /** * @brief Unregister a User NAND Callback - * NAND Callback is redirected to the weak (surcharged) predefined callback + * NAND Callback is redirected to the weak predefined callback * @param hnand : NAND handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1983,9 +1978,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hnand); - if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) @@ -2027,8 +2019,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnand); return status; } #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ @@ -2179,7 +2169,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, * the configuration information for NAND module. * @retval HAL state */ -HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand) { return hnand->State; } @@ -2190,7 +2180,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) * the configuration information for NAND module. * @retval NAND status */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand) { uint32_t data; uint32_t deviceaddress; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_nor.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_nor.c index 08c0ac4fde..56a4105694 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_nor.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_nor.c @@ -74,15 +74,15 @@ and a pointer to the user callback function. Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_NOR_Init + reset to the legacy weak (overridden) functions in the HAL_NOR_Init and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -97,7 +97,7 @@ When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -106,7 +106,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" -#if defined(FMC_BANK1) +#if defined(FMC_BANK1) /** @addtogroup STM32G4xx_HAL_Driver * @{ @@ -127,6 +127,11 @@ */ /* Constants to define address to set to write a command */ +#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA +#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA +#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA + #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA @@ -230,6 +235,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe FMC_NORSRAM_TimingTypeDef *ExtTiming) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR handle parameter */ if (hnor == NULL) @@ -263,7 +269,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); /* Initialize NOR extended mode timing Interface */ - (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); + (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, + hnor->Init.NSBank, hnor->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); @@ -299,11 +306,32 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe deviceaddress = NOR_MEMORY_ADRESS4; } - /* Get the value of the command set */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE) + { + (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); - return HAL_NOR_ReturnToReadMode(hnor); + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; + } + else + { + /* Get the value of the command set */ + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } + + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + + status = HAL_NOR_ReturnToReadMode(hnor); + } + + return status; } /** @@ -426,7 +454,11 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -455,9 +487,22 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /* Send read ID command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_AUTO_SELECT); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_AUTO_SELECT); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -513,7 +558,11 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -587,7 +636,11 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -616,9 +669,22 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -697,9 +763,21 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /* Send program data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_PROGRAM); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -756,7 +834,11 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -785,9 +867,22 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -880,10 +975,20 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + } + else + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + } /* Write Buffer Load Command */ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); @@ -983,14 +1088,26 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Send block erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + } NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) @@ -1068,15 +1185,28 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /* Send NOR chip erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), + NOR_CMD_DATA_CHIP_ERASE); + } } else { @@ -1116,7 +1246,11 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1143,8 +1277,15 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR } /* Send read CFI query command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } /* read the NOR CFI information */ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); @@ -1168,7 +1309,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /** * @brief Register a User NOR Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hnor : NOR handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1188,9 +1329,6 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hnor); - state = hnor->State; if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { @@ -1214,14 +1352,12 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnor); return status; } /** * @brief Unregister a User NOR Callback - * NOR Callback is redirected to the weak (surcharged) predefined callback + * NOR Callback is redirected to the weak predefined callback * @param hnor : NOR handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1234,9 +1370,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hnor); - state = hnor->State; if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { @@ -1260,8 +1393,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnor); return status; } #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ @@ -1378,7 +1509,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) * the configuration information for NOR module. * @retval NOR controller state */ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor) { return hnor->State; } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c index f5013aa11f..8e93289f8b 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c @@ -37,7 +37,7 @@ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral + (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -178,7 +178,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; hpcd->IN_ep[i].num = i; - hpcd->IN_ep[i].tx_fifo_num = i; /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; hpcd->IN_ep[i].maxpacket = 0U; @@ -294,7 +293,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function @@ -398,7 +397,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister an USB PCD Callback - * USB PCD callabck is redirected to the weak predefined callback + * USB PCD callback is redirected to the weak predefined callback * @param hpcd USB PCD handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -408,7 +407,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status @@ -1408,11 +1407,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->maxpacket = ep_mps; ep->type = ep_type; - if (ep->is_in != 0U) - { - /* Assign a Tx FIFO */ - ep->tx_fifo_num = ep->num; - } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) { @@ -1446,7 +1440,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; ep->is_in = 0U; } - ep->num = ep_addr & EP_ADDR_MSK; + ep->num = ep_addr & EP_ADDR_MSK; __HAL_LOCK(hpcd); (void)USB_DeactivateEndpoint(hpcd->Instance, ep); @@ -1476,14 +1470,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0U; ep->num = ep_addr & EP_ADDR_MSK; - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep); - } + (void)USB_EPStartXfer(hpcd->Instance, ep); return HAL_OK; } @@ -1494,7 +1481,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u * @param ep_addr endpoint address * @retval Data Size */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) { return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; } @@ -1521,14 +1508,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->is_in = 1U; ep->num = ep_addr & EP_ADDR_MSK; - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep); - } + (void)USB_EPStartXfer(hpcd->Instance, ep); return HAL_OK; } @@ -1607,6 +1587,32 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) return HAL_OK; } +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + HAL_StatusTypeDef ret; + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_EPStopXfer(hpcd->Instance, ep); + + return ret; +} + /** * @brief Flush an endpoint * @param hpcd PCD handle @@ -1615,9 +1621,18 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(ep_addr); + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -1666,7 +1681,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval HAL state */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) { return hpcd->State; } @@ -1699,6 +1714,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) uint16_t TxPctSize; uint8_t epindex; +#if (USE_USB_DOUBLE_BUFFER != 1U) + count = 0U; +#endif /* USE_USB_DOUBLE_BUFFER */ + /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { @@ -1786,7 +1805,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U) + wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); @@ -1868,7 +1889,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - (void) USB_EPStartXfer(hpcd->Instance, ep); + (void)USB_EPStartXfer(hpcd->Instance, ep); } } @@ -1879,7 +1900,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - if (ep->type != EP_TYPE_BULK) + if (ep->type == EP_TYPE_ISOC) { ep->xfer_len = 0U; @@ -1906,7 +1927,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - /* Manage Bulk Single Buffer Transaction */ + /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { /* multi-packet on the NON control IN endpoint */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c index 88bb610472..cb53de6936 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c @@ -161,23 +161,8 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) USB_TypeDef *USBx = hpcd->Instance; uint32_t tickstart = HAL_GetTick(); - /* Wait Detect flag or a timeout is happen */ - while ((USBx->BCDR & USB_BCDR_DCDET) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > 1000U) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - return; - } - } - - HAL_Delay(200U); + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); /* Data Pin Contact ? Check Detect flag */ if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) @@ -237,11 +222,24 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Battery Charging capability discovery finished Start Enumeration */ (void)HAL_PCDEx_DeActivateBCD(hpcd); + + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); #else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_qspi.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_qspi.c index 166199ba9f..de89b25e25 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_qspi.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_qspi.c @@ -122,7 +122,7 @@ ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and flushes the fifo : (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. @@ -162,7 +162,7 @@ and a pointer to the user callback function. Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. (+) FifoThresholdCallback : callback when the fifo threshold is reached. @@ -178,9 +178,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + reset to the legacy weak (overridden) functions in the HAL_QSPI_Init and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -195,7 +195,7 @@ When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** Workarounds linked to Silicon Limitation *** ==================================================== @@ -285,7 +285,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initialize the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and initialize the associated handle. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -386,7 +386,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -427,7 +427,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Initialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -442,7 +442,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -481,7 +481,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -767,9 +767,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @param cmd : structure that contains the command configuration information - * @param Timeout : Timeout duration + * @param Timeout Timeout duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -857,8 +857,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -956,9 +956,9 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1039,9 +1039,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1125,8 +1125,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1185,8 +1185,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1249,8 +1249,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1393,8 +1393,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer. + * @param hqspi QSPI handle + * @param pData pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1541,10 +1541,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @param Timeout Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1642,9 +1642,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1746,9 +1746,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the memory mapped configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1835,7 +1835,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1850,7 +1850,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1865,7 +1865,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1880,7 +1880,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1895,7 +1895,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1910,7 +1910,7 @@ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1925,7 +1925,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1940,7 +1940,7 @@ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1955,7 +1955,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1970,7 +1970,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -1985,9 +1985,9 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) /** * @brief Register a User QSPI Callback - * To be used instead of the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be registered + * To be used to override the weak predefined callback + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2001,7 +2001,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID - * @param pCallback : pointer to the Callback function + * @param pCallback pointer to the Callback function * @retval status */ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) @@ -2099,9 +2099,9 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI /** * @brief Unregister a User QSPI Callback - * QSPI Callback is redirected to the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be unregistered + * QSPI Callback is redirected to the weak predefined callback + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2228,10 +2228,10 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS /** * @brief Return the QSPI handle state. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL state */ -HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) +HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi) { /* Return QSPI handle state */ return hqspi->State; @@ -2239,17 +2239,17 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval QSPI Error Code */ -uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) +uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi) { return hqspi->ErrorCode; } /** * @brief Abort the current transmission. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2276,25 +2276,33 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) } } - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if (status == HAL_OK) - { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + if (status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - /* Wait until BUSY flag is reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - } + /* Wait until BUSY flag is reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + } - if (status == HAL_OK) - { - /* Reset functional mode configuration to indirect write mode by default */ - CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + if (status == HAL_OK) + { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + } + else + { /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2305,7 +2313,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2346,22 +2354,30 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } else { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } + else + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + } } } return status; } /** @brief Set QSPI timeout. - * @param hqspi : QSPI handle. - * @param Timeout : Timeout for the QSPI memory access. + * @param hqspi QSPI handle. + * @param Timeout Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2370,8 +2386,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi : QSPI handle. - * @param Threshold : Threshold of the Fifo (value between 1 and 16). + * @param hqspi QSPI handle. + * @param Threshold Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2403,17 +2419,17 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi : QSPI handle. + * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ -uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) +uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi) { return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); } /** @brief Set FlashID. - * @param hqspi : QSPI handle. - * @param FlashID : Index of the flash memory to be accessed. + * @param hqspi QSPI handle. + * @param FlashID Index of the flash memory to be accessed. * This parameter can be a value of @ref QSPI_Flash_Select. * @note The FlashID is ignored when dual flash mode is enabled. * @retval HAL status @@ -2462,7 +2478,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI /** * @brief DMA QSPI receive process complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -2476,7 +2492,7 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) @@ -2490,7 +2506,7 @@ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI receive process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2506,7 +2522,7 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2522,7 +2538,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) @@ -2543,7 +2559,7 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI abort complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) @@ -2582,11 +2598,11 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) /** * @brief Wait for a flag state until timeout. - * @param hqspi : QSPI handle - * @param Flag : Flag checked - * @param State : Value of the flag expected - * @param Tickstart : Tick start value - * @param Timeout : Duration of the timeout + * @param hqspi QSPI handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Tickstart Tick start value + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2612,9 +2628,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information - * @param FunctionalMode : functional mode to configured + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param FunctionalMode functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c index 98dc54f2fe..f163c2c6ff 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c @@ -632,7 +632,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) @@ -672,10 +672,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - /* Disable all PLL outputs to save power if no PLLs on */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); - __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); - /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -687,6 +683,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_TIMEOUT; } } + + /* Unselect PLL clock source and disable outputs to save power */ + RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); } } else @@ -978,7 +977,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rng.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rng.c index 5814ebd74f..169d5aca42 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rng.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rng.c @@ -52,7 +52,7 @@ [..] Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -66,10 +66,10 @@ [..] By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak (overridden) functions: example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -86,7 +86,7 @@ [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -312,8 +312,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -367,14 +365,12 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } /** * @brief Unregister an RNG Callback - * RNG callabck is redirected to the weak predefined callback + * RNG callback is redirected to the weak predefined callback * @param hrng RNG handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -387,8 +383,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -442,8 +436,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -664,15 +656,16 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; /* RNG clock error interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } - else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; @@ -703,7 +696,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) } /* Check RNG data ready interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) { /* Generate random number once, so disable the IT */ __HAL_RNG_DISABLE_IT(hrng); @@ -735,7 +728,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval random value */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) { return (hrng->RandomNumber); } @@ -802,7 +795,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval HAL state */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) { return hrng->State; } @@ -812,7 +805,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code */ -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ return hrng->ErrorCode; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc.c index ea37e80136..0c48d27450 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc.c @@ -372,24 +372,28 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); - /* Set RTC_CR register */ - SET_BIT(hrtc->Instance->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + if (status == HAL_OK) + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(hrtc->Instance->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); - /* Configure the RTC PRER */ - WRITE_REG(hrtc->Instance->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + /* Configure the RTC PRER */ + WRITE_REG(hrtc->Instance->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } if (status == HAL_OK) { @@ -397,10 +401,15 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; + } if (status == HAL_OK) { @@ -1794,8 +1803,8 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { uint32_t tickstart; - /* Clear RSF flag */ - CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_RSF); + /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ + hrtc->Instance->ICSR = ((uint32_t)(RTC_RSF_MASK & RTC_ICSR_RESERVED_MASK)); tickstart = HAL_GetTick(); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sai.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sai.c index 684d778379..befbd56e1a 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sai.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sai.c @@ -170,7 +170,7 @@ [..] Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. [..] @@ -185,10 +185,10 @@ [..] By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + reset to the legacy weak functions in the HAL_SAI_Init and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -205,7 +205,7 @@ [..] When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim */ @@ -243,6 +243,8 @@ typedef enum */ #define SAI_DEFAULT_TIMEOUT 4U #define SAI_LONG_TIMEOUT 1000U +#define SAI_SPDIF_FRAME_LENGTH 64U +#define SAI_AC97_FRAME_LENGTH 256U /** * @} */ @@ -366,7 +368,6 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco */ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) { - uint32_t tmpregisterGCR; uint32_t ckstr_bits; uint32_t syncen_bits; @@ -460,22 +461,6 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /* SAI Block Synchro Configuration -----------------------------------------*/ /* This setting must be done with both audio block (A & B) disabled */ - switch (hsai->Init.SynchroExt) - { - case SAI_SYNCEXT_DISABLE : - tmpregisterGCR = 0; - break; - case SAI_SYNCEXT_OUTBLOCKA_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_0; - break; - case SAI_SYNCEXT_OUTBLOCKB_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_1; - break; - default : - tmpregisterGCR = 0; - break; - } - switch (hsai->Init.Synchro) { case SAI_ASYNCHRONOUS : @@ -484,23 +469,11 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) case SAI_SYNCHRONOUS : syncen_bits = SAI_xCR1_SYNCEN_0; break; - case SAI_SYNCHRONOUS_EXT_SAI1 : - syncen_bits = SAI_xCR1_SYNCEN_1; - break; - case SAI_SYNCHRONOUS_EXT_SAI2 : - syncen_bits = SAI_xCR1_SYNCEN_1; - tmpregisterGCR |= SAI_GCR_SYNCIN_0; - break; default : syncen_bits = 0; break; } - if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) - { - SAI1->GCR = tmpregisterGCR; - } - if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) { uint32_t freq = 0; @@ -525,12 +498,12 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) { /* For SPDIF protocol, frame length is set by hardware to 64 */ - tmpframelength = 64U; + tmpframelength = SAI_SPDIF_FRAME_LENGTH; } else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL) { /* For AC97 protocol, frame length is set by hardware to 256 */ - tmpframelength = 256U; + tmpframelength = SAI_AC97_FRAME_LENGTH; } else { @@ -1368,6 +1341,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -1387,12 +1366,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) (void) HAL_DMA_Abort(hsai->hdmarx); } - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1418,6 +1391,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Check SAI DMA is enabled or not */ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { @@ -1445,12 +1424,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -2078,7 +2051,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval HAL state */ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai) { return hsai->State; } @@ -2089,7 +2062,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) * the configuration information for the specified SAI Block. * @retval SAI Error Code */ -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai) { return hsai->ErrorCode; } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sai_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sai_ex.c index 93246e8050..78e90b6823 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sai_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sai_ex.c @@ -73,7 +73,8 @@ * @param pdmMicDelay Microphone delays configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) { HAL_StatusTypeDef status = HAL_OK; uint32_t offset; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_smartcard.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_smartcard.c index 1007ab8503..53aa44248b 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_smartcard.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_smartcard.c @@ -136,7 +136,7 @@ [..] Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -153,10 +153,10 @@ [..] By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + reset to the legacy weak functions in the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -173,7 +173,7 @@ [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -467,7 +467,10 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /** * @brief Register a User SMARTCARD Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback + * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -497,8 +500,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmartcard); if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { @@ -584,15 +585,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } /** * @brief Unregister an SMARTCARD callback * SMARTCARD callback is redirected to the weak predefined callback + * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -613,9 +614,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmartcard); - if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) { switch (CallbackID) @@ -701,9 +699,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -2276,7 +2271,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle state */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ uint32_t temp1; @@ -2293,7 +2288,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle Error Code */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard) { return hsmartcard->ErrorCode; } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_smbus.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_smbus.c index 0be8b47764..18f8657d59 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_smbus.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_smbus.c @@ -584,6 +584,9 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /** * @brief Register a User SMBUS Callback * To be used instead of the weak predefined callback + * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be registered @@ -613,9 +616,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -691,14 +691,15 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } /** * @brief Unregister an SMBUS Callback * SMBUS callback is redirected to the weak predefined callback + * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be unregistered @@ -719,9 +720,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -797,8 +795,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -822,8 +818,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); if (HAL_SMBUS_STATE_READY == hsmbus->State) { @@ -838,8 +832,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -854,9 +846,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ @@ -870,8 +859,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -939,6 +926,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; + uint32_t sizetoxfer; /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -971,11 +959,35 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint hsmbus->XferSize = Size; } + sizetoxfer = hsmbus->XferSize; + if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || + (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) + { + if (hsmbus->pBuffPtr != NULL) + { + /* Preload TX register */ + /* Write data to TXDR */ + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + hsmbus->XferCount--; + hsmbus->XferSize--; + } + else + { + return HAL_ERROR; + } + } + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + if ((sizetoxfer < hsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } @@ -990,7 +1002,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ @@ -1000,7 +1012,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } @@ -1009,8 +1021,15 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { - hsmbus->XferSize--; - hsmbus->XferCount--; + if (hsmbus->XferSize > 0U) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } } } @@ -1826,7 +1845,7 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval HAL state */ -uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus) { /* Return SMBUS handle state */ return hsmbus->State; @@ -1838,7 +1857,7 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval SMBUS Error Code */ -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus) { return hsmbus->ErrorCode; } @@ -2600,8 +2619,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c index 86b9ae36ac..cd330e6530 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c @@ -908,6 +908,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -957,6 +958,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -986,9 +988,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error: - hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); return errorcode; @@ -1013,6 +1018,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1026,12 +1037,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1109,6 +1114,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1132,6 +1138,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1226,9 +1233,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1349,6 +1359,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { @@ -1387,6 +1411,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1407,6 +1432,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ } } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) @@ -1469,6 +1507,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1538,8 +1577,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + else + { + hspi->State = HAL_SPI_STATE_READY; + } + error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1559,8 +1606,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); if ((pData == NULL) || (Size == 0U)) { @@ -1574,6 +1619,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1613,10 +1661,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1624,8 +1668,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } -error : + /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1641,6 +1689,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1648,14 +1703,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); } - /* Process Locked */ - __HAL_LOCK(hspi); - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -1663,6 +1710,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1715,9 +1765,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current process unlock */ @@ -1729,9 +1776,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1753,9 +1803,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; @@ -1773,6 +1820,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p goto error; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1829,8 +1879,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1839,9 +1887,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1945,7 +1996,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1985,6 +2035,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1999,12 +2055,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -2090,7 +2140,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -2258,7 +2307,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -2280,7 +2328,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c index c1776f7105..dfc1dd7ab9 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c @@ -76,7 +76,7 @@ * the configuration information for the specified SPI module. * @retval HAL status */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) { __IO uint32_t tmpreg; uint8_t count = 0U; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sram.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sram.c index 2b7a647198..a1425a9dcb 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sram.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sram.c @@ -83,15 +83,15 @@ and a pointer to the user callback function. Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init + reset to the legacy weak (overridden) functions in the HAL_SRAM_Init and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -106,7 +106,7 @@ When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -133,9 +133,15 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); static void SRAM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ @@ -731,7 +737,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /** * @brief Register a User SRAM Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -751,9 +757,6 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsram); - state = hsram->State; if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) { @@ -777,14 +780,12 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsram); return status; } /** * @brief Unregister a User SRAM Callback - * SRAM Callback is redirected to the weak (surcharged) predefined callback + * SRAM Callback is redirected to the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -799,9 +800,6 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hsram); - state = hsram->State; if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { @@ -847,14 +845,12 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsram); return status; } /** * @brief Register a User SRAM Callback for DMA transfers - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1018,7 +1014,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) * the configuration information for SRAM module. * @retval HAL state */ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) { return hsram->State; } @@ -1031,6 +1027,10 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) * @} */ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ + /** * @brief DMA SRAM process complete callback. * @param hdma : DMA handle @@ -1097,6 +1097,10 @@ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } +/** + * @} + */ + /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c index c0460d4989..722543765b 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c @@ -217,11 +217,11 @@ all interrupt callbacks are set to the corresponding weak functions: /** @addtogroup TIM_Private_Functions * @{ */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); @@ -237,7 +237,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); + const TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ @@ -290,6 +290,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -537,7 +538,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; @@ -551,7 +552,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else if (htim->State == HAL_TIM_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -673,6 +674,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -898,7 +900,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) @@ -990,7 +992,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1062,13 +1064,14 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) @@ -1077,7 +1080,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1230,7 +1233,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1340,6 +1343,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1565,7 +1569,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) @@ -1657,7 +1661,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1729,13 +1733,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) @@ -1744,7 +1749,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1896,7 +1901,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -2006,6 +2011,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -2139,7 +2145,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) @@ -2187,7 +2193,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); @@ -2223,7 +2229,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) @@ -2311,7 +2317,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -2387,7 +2393,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Set the TIM channel state */ @@ -2399,7 +2405,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -2542,7 +2548,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Disable the Input Capture channel */ @@ -2655,6 +2661,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -3032,7 +3039,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; @@ -3058,6 +3065,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) { @@ -3567,7 +3575,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData1 == NULL) && (Length > 0U)) + if ((pData1 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3592,7 +3600,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData2 == NULL) && (Length > 0U)) + if ((pData2 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3621,7 +3629,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) { return HAL_ERROR; } @@ -3837,13 +3845,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3871,11 +3882,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3901,11 +3912,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3931,11 +3942,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3961,11 +3972,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3974,11 +3985,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else @@ -3987,9 +3999,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break2 input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4000,11 +4012,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -4013,11 +4025,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM commutation event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else @@ -4026,11 +4038,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Encoder index event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET) + if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET) + if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->EncoderIndexCallback(htim); #else @@ -4039,11 +4051,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Direction change event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET) + if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET) + if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->DirectionChangeCallback(htim); #else @@ -4052,11 +4064,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Index error event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET) + if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET) + if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IndexErrorCallback(htim); #else @@ -4065,11 +4077,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Transition error event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET) + if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET) + if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TransitionErrorCallback(htim); #else @@ -4118,7 +4130,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4216,7 +4228,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4318,7 +4330,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4623,7 +4635,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status; @@ -4684,7 +4697,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; @@ -5345,7 +5358,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -5396,10 +5409,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { /* Clear the OCREF clear selection bit */ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - - /* Clear TIM1_AF2_OCRSEL (reset value) */ - MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); } + + /* Set the clear input source */ + MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); break; } @@ -5546,7 +5559,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -5746,7 +5759,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5787,7 +5800,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5829,7 +5842,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; @@ -6112,8 +6125,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call { return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { @@ -6325,9 +6336,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } @@ -6375,9 +6383,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(htim); - if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) @@ -6634,9 +6639,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -6665,7 +6667,7 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @param htim TIM Base handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6675,7 +6677,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Output Compare handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6685,7 +6687,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6695,7 +6697,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) * @param htim TIM IC handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6705,7 +6707,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM OPM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6715,7 +6717,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Encoder Interface handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6725,7 +6727,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval Active channel */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) { return htim->Channel; } @@ -6743,7 +6745,7 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -6760,7 +6762,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, ui * @param htim TIM handle * @retval DMA burst state */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -7103,7 +7105,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) * @param Structure TIM Base configuration structure * @retval None */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; @@ -7143,6 +7145,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } } /** @@ -7151,17 +7160,18 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7226,17 +7236,18 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7265,7 +7276,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7302,17 +7312,18 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7376,17 +7387,18 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7454,17 +7466,18 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) + const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7507,17 +7520,18 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) + const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7561,7 +7575,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -7716,9 +7730,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) @@ -7806,9 +7820,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; @@ -7845,9 +7859,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; @@ -7889,9 +7903,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; @@ -7937,9 +7951,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; @@ -7967,10 +7981,6 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input * @arg TIM_TS_ITR4: Internal Trigger 4 (*) * @arg TIM_TS_ITR5: Internal Trigger 5 * @arg TIM_TS_ITR6: Internal Trigger 6 @@ -7979,6 +7989,10 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_TS_ITR9: Internal Trigger 9 (*) * @arg TIM_TS_ITR10: Internal Trigger 10 * @arg TIM_TS_ITR11: Internal Trigger 11 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input * * (*) Value not defined in all devices. * diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c index 04d982f30a..e029030371 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c @@ -154,7 +154,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; @@ -170,6 +170,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -520,7 +521,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -871,7 +872,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -904,7 +905,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -919,7 +921,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1147,17 +1149,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1401,7 +1392,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1434,7 +1425,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1449,7 +1441,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -2186,7 +2178,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) + const TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -2259,7 +2251,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; @@ -2274,6 +2266,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); @@ -2290,15 +2283,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - - /* Set BREAK AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -2306,20 +2291,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - - /* Set BREAK2 AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } /* Set TIMx_BDTR */ @@ -2342,8 +2320,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; @@ -2679,7 +2656,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO * @arg TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to COMP3 output - + * * For TIM4 this parameter can be one of the following values: * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output @@ -2877,7 +2854,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B uint32_t tmpbdtr; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -2894,7 +2871,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } - case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -2926,13 +2902,13 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B * @note Break input is automatically armed as soon as MOE bit is set. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -3344,7 +3320,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3358,7 +3334,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3373,7 +3349,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3388,7 +3364,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break2 detection callback in non blocking mode + * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ @@ -3486,7 +3462,7 @@ __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) * @param htim TIM Hall Sensor handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -3502,7 +3478,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval TIM Complementary channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -3648,6 +3624,11 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } else { /* nothing to do */ @@ -3679,13 +3660,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha { uint32_t tmp; - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ } /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c index fadbcc8d1b..2ca90c8118 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c @@ -107,7 +107,7 @@ [..] Use function HAL_UART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -131,10 +131,10 @@ [..] By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + reset to the legacy weak functions in the HAL_UART_Init() and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -151,7 +151,7 @@ [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -197,8 +197,8 @@ /** @addtogroup UART_Private_Functions * @{ */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); @@ -348,15 +348,17 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In asynchronous mode, the following bits must be kept cleared: @@ -413,15 +415,17 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In half-duplex mode, the following bits must be kept cleared: @@ -499,15 +503,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In LIN mode, the following bits must be kept cleared: @@ -583,15 +589,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In multiprocessor mode, the following bits must be kept cleared: @@ -656,6 +664,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -695,7 +704,10 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /** * @brief Register a User UART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -727,8 +739,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ return HAL_ERROR; } - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_READY) { switch (CallbackID) @@ -818,14 +828,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } /** * @brief Unregister an UART Callback * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -848,8 +859,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - __HAL_LOCK(huart); - if (HAL_UART_STATE_READY == huart->gState) { switch (CallbackID) @@ -941,8 +950,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } @@ -964,10 +971,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = pCallback; } @@ -978,9 +982,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -994,10 +995,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ } @@ -1008,8 +1006,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); return status; } @@ -1132,8 +1128,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; @@ -1155,12 +1149,13 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD pdata16bits = NULL; } - __HAL_UNLOCK(huart); - while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { + + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1178,6 +1173,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } @@ -1222,8 +1219,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1250,13 +1245,13 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* as long as data have to be received */ while (huart->RxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { + huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1303,8 +1298,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1326,8 +1319,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t huart->TxISR = UART_TxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } @@ -1343,8 +1334,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t huart->TxISR = UART_TxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } @@ -1377,8 +1366,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1420,8 +1407,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1449,8 +1434,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; @@ -1460,8 +1443,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - __HAL_UNLOCK(huart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -1496,8 +1477,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1529,8 +1508,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef rxstate = huart->RxState; - __HAL_LOCK(huart); - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { @@ -1548,8 +1525,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1560,8 +1535,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ @@ -1583,8 +1556,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -2441,6 +2412,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); @@ -2474,6 +2450,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxISR = NULL; ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); @@ -2958,7 +2939,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval HAL state */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { uint32_t temp1; uint32_t temp2; @@ -2974,7 +2955,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval UART Error Code */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { return huart->ErrorCode; } @@ -3242,6 +3223,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { @@ -3263,13 +3251,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { @@ -3327,6 +3308,13 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3338,6 +3326,15 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3347,6 +3344,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -3374,35 +3372,39 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); return HAL_TIMEOUT; } - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; huart->ErrorCode = HAL_UART_ERROR_RTO; /* Process Unlocked */ @@ -3456,8 +3458,6 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) { @@ -3477,8 +3477,6 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) { @@ -3531,15 +3529,12 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; return HAL_ERROR; } } - __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) @@ -3684,6 +3679,10 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } } + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3718,6 +3717,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4178,6 +4181,19 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4193,6 +4209,7 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4257,6 +4274,19 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4272,6 +4302,7 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4387,6 +4418,19 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4402,6 +4446,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4537,6 +4582,19 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4552,6 +4610,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c index cfe058f237..30fd990608 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c @@ -211,15 +211,17 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ @@ -724,11 +726,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -752,8 +753,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* Initialize output number of received elements */ *RxLen = 0U; @@ -770,6 +769,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p /* If Set, and data has already been received, this means Idle Event is valid : End reception */ if (*RxLen > 0U) { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; huart->RxState = HAL_UART_STATE_READY; return HAL_OK; @@ -835,7 +835,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) @@ -845,29 +845,24 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; - status = UART_Start_Receive_IT(huart, pData, Size); + (void)UART_Start_Receive_IT(huart, pData, Size); - /* Check Rx process has been successfully started */ - if (status == HAL_OK) + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; } return status; @@ -907,10 +902,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_DMA(huart, pData, Size); @@ -940,6 +934,36 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ } } +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_usart.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_usart.c index 3a828aee8a..96617bc656 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_usart.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_usart.c @@ -91,7 +91,7 @@ [..] Use function HAL_USART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -109,10 +109,10 @@ [..] By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_USART_Init() + reset to the legacy weak functions in the HAL_USART_Init() and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -129,7 +129,7 @@ [..] When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -406,7 +406,9 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /** * @brief Register a User USART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -436,8 +438,6 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(husart); if (husart->State == HAL_USART_STATE_READY) { @@ -526,15 +526,14 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } /** * @brief Unregister an USART Callback * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -555,9 +554,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(husart); - if (HAL_USART_STATE_READY == husart->State) { switch (CallbackID) @@ -645,9 +641,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -748,7 +741,8 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout) { const uint8_t *ptxdata8bits; const uint16_t *ptxdata16bits; @@ -1233,7 +1227,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ if (husart->Init.Parity != USART_PARITY_NONE) { - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); } SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); } @@ -2485,7 +2479,7 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART handle state */ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) { return husart->State; } @@ -2496,7 +2490,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART handle Error Code */ -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) { return husart->ErrorCode; } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_wwdg.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_wwdg.c index 62f1f411bf..56e18a7dc1 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_wwdg.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_wwdg.c @@ -122,7 +122,6 @@ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt @endverbatim - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c index b8baf56566..d49741c837 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G4xx_LL_Driver * @{ @@ -313,7 +313,7 @@ ) \ ) \ ) -#endif +#endif /* STM32G4xx */ #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ @@ -553,7 +553,7 @@ ) \ ) \ ) -#endif +#endif /* STM32G4xx */ #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ @@ -654,7 +654,7 @@ * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); @@ -676,7 +676,7 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) /* Release reset of ADC clock (core clock) */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345); } -#endif +#endif /* ADC345_COMMON */ return SUCCESS; } @@ -691,25 +691,25 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) * must be disabled. * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are initialized * - ERROR: ADC common registers are not initialized */ -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); + assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock)); #if defined(ADC_MULTIMODE_SUPPORT) - assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); - if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode)); + if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { - assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); - assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); + assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer)); + assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay)); } #endif /* ADC_MULTIMODE_SUPPORT */ @@ -730,7 +730,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* - Set ADC multimode DMA transfer */ /* - Set ADC multimode: delay between 2 sampling phases */ #if defined(ADC_MULTIMODE_SUPPORT) - if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE @@ -739,10 +739,10 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni | ADC_CCR_MDMA | ADC_CCR_DELAY , - ADC_CommonInitStruct->CommonClock - | ADC_CommonInitStruct->Multimode - | ADC_CommonInitStruct->MultiDMATransfer - | ADC_CommonInitStruct->MultiTwoSamplingDelay + pADC_CommonInitStruct->CommonClock + | pADC_CommonInitStruct->Multimode + | pADC_CommonInitStruct->MultiDMATransfer + | pADC_CommonInitStruct->MultiTwoSamplingDelay ); } else @@ -754,13 +754,13 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni | ADC_CCR_MDMA | ADC_CCR_DELAY , - ADC_CommonInitStruct->CommonClock + pADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } #else - LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); -#endif + LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock); +#endif /* ADC_MULTIMODE_SUPPORT */ } else { @@ -774,22 +774,22 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /** * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { - /* Set ADC_CommonInitStruct fields to default values */ + /* Set pADC_CommonInitStruct fields to default values */ /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ - ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; #if defined(ADC_MULTIMODE_SUPPORT) /* Set fields of ADC multimode */ - ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; - ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; - ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE; + pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; + pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; + pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE; #endif /* ADC_MULTIMODE_SUPPORT */ } @@ -823,11 +823,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Disable ADC instance if not already disabled. */ if (LL_ADC_IsEnabled(ADCx) == 1UL) { - /* Set ADC group regular trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - /* Stop potential ADC conversion on going on ADC group regular. */ if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) { @@ -837,11 +832,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) } } - /* Set ADC group injected trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); - /* Stop potential ADC conversion on going on ADC group injected. */ if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) { @@ -1015,13 +1005,17 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Note: bits in access mode read only, no direct reset applicable */ /* Reset register OFR1 */ - CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS); + CLEAR_BIT(ADCx->OFR1, + ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS); /* Reset register OFR2 */ - CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS); + CLEAR_BIT(ADCx->OFR2, + ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS); /* Reset register OFR3 */ - CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS); + CLEAR_BIT(ADCx->OFR3, + ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS); /* Reset register OFR4 */ - CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS); + CLEAR_BIT(ADCx->OFR4, + ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS); /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* Note: bits in access mode read only, no direct reset applicable */ @@ -1062,14 +1056,14 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) * @brief Initialize some features of ADC instance. * @note These parameters have an impact on ADC scope: ADC instance. * Affects both group regular and group injected (availability - * of ADC group injected depends on STM32 families). + * of ADC group injected depends on STM32 series). * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Instance . * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -1086,21 +1080,21 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance - * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); - assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); - assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); + assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment)); + assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ @@ -1116,9 +1110,9 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) | ADC_CFGR_ALIGN | ADC_CFGR_AUTDLY , - ADC_InitStruct->Resolution - | ADC_InitStruct->DataAlignment - | ADC_InitStruct->LowPowerMode + pADC_InitStruct->Resolution + | pADC_InitStruct->DataAlignment + | pADC_InitStruct->LowPowerMode ); } @@ -1133,17 +1127,17 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /** * @brief Set each @ref LL_ADC_InitTypeDef field to default value. - * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) { - /* Set ADC_InitStruct fields to default values */ + /* Set pADC_InitStruct fields to default values */ /* Set fields of ADC instance */ - ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; - ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; - ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; + pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; } @@ -1157,7 +1151,7 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -1174,31 +1168,31 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, pADC_RegInitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength)); + if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { - assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont)); /* ADC group regular continuous mode and discontinuous mode */ /* can not be enabled simultenaeously */ - assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) - || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } - assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); - assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); - assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer)); + assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ @@ -1215,7 +1209,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* - Set ADC group regular overrun behavior */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTSEL @@ -1227,11 +1221,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD , - ADC_REG_InitStruct->TriggerSource - | ADC_REG_InitStruct->SequencerDiscont - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - | ADC_REG_InitStruct->Overrun + pADC_RegInitStruct->TriggerSource + | pADC_RegInitStruct->SequencerDiscont + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun ); } else @@ -1246,16 +1240,16 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD , - ADC_REG_InitStruct->TriggerSource + pADC_RegInitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - | ADC_REG_InitStruct->Overrun + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun ); } /* Set ADC group regular sequencer length and scan direction */ - LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); + LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength); } else { @@ -1267,22 +1261,22 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /** * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { - /* Set ADC_REG_InitStruct fields to default values */ + /* Set pADC_RegInitStruct fields to default values */ /* Set fields of ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; - ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; - ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; - ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; - ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; - ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; + pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; + pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; } /** @@ -1295,7 +1289,7 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -1318,24 +1312,24 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) * To set several features of ADC group injected, use * function @ref LL_ADC_INJ_ConfigQueueContext(). * @param ADCx ADC instance - * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, pADC_InjInitStruct->TriggerSource)); + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength)); + if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { - assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont)); } - assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); + assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ @@ -1350,14 +1344,14 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* from ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO , - ADC_INJ_InitStruct->SequencerDiscont - | ADC_INJ_InitStruct->TrigAuto + pADC_InjInitStruct->SequencerDiscont + | pADC_InjInitStruct->TrigAuto ); } else @@ -1367,7 +1361,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I | ADC_CFGR_JAUTO , LL_ADC_REG_SEQ_DISCONT_DISABLE - | ADC_INJ_InitStruct->TrigAuto + | pADC_InjInitStruct->TrigAuto ); } @@ -1376,8 +1370,8 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I | ADC_JSQR_JEXTEN | ADC_JSQR_JL , - ADC_INJ_InitStruct->TriggerSource - | ADC_INJ_InitStruct->SequencerLength + pADC_InjInitStruct->TriggerSource + | pADC_InjInitStruct->SequencerLength ); } else @@ -1390,18 +1384,18 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /** * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. - * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct) { - /* Set ADC_INJ_InitStruct fields to default values */ + /* Set pADC_InjInitStruct fields to default values */ /* Set fields of ADC group injected */ - ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; - ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; - ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; - ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; + pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; + pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; + pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; + pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; } /** diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_comp.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_comp.c index 0fbcf2fc14..103e753eef 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_comp.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_comp.c @@ -15,6 +15,7 @@ * ****************************************************************************** */ + #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ @@ -53,73 +54,73 @@ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ - ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ + (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ ) #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) || \ - (((__COMP_INSTANCE__) == COMP1) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ - ) || \ - (((__COMP_INSTANCE__) == COMP2) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ - ) || \ - (((__COMP_INSTANCE__) == COMP3) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ - ) || \ - (((__COMP_INSTANCE__) == COMP4) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ - ) || \ - (((__COMP_INSTANCE__) == COMP5) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1)) \ - ) || \ - (((__COMP_INSTANCE__) == COMP6) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH2)) \ - ) || \ - (((__COMP_INSTANCE__) == COMP7) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1)) \ - )) +#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) || \ + (((__COMP_INSTANCE__) == COMP1) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP2) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP3) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP4) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP5) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP6) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH2)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP7) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1)) \ + )) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) || \ - (((__COMP_INSTANCE__) == COMP1) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ - ) || \ - (((__COMP_INSTANCE__) == COMP2) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ - ) || \ - (((__COMP_INSTANCE__) == COMP3) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ - ) || \ - (((__COMP_INSTANCE__) == COMP4) && \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ - ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ - )) +#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) || \ + (((__COMP_INSTANCE__) == COMP1) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP2) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP3) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP4) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ + )) #endif #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \ - ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \ + (((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_10MV) \ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_20MV) \ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_30MV) \ @@ -130,129 +131,129 @@ ) #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \ - ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \ + (((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \ ) #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ - || \ - (((__INSTANCE__) == COMP3) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ - || \ - (((__INSTANCE__) == COMP4) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ - || \ - (((__INSTANCE__) == COMP5) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5))) \ - || \ - (((__INSTANCE__) == COMP6) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6))) \ - || \ - (((__INSTANCE__) == COMP7) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7))) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \ - ) + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ + || \ + (((__INSTANCE__) == COMP3) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ + || \ + (((__INSTANCE__) == COMP4) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ + || \ + (((__INSTANCE__) == COMP5) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5))) \ + || \ + (((__INSTANCE__) == COMP6) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6))) \ + || \ + (((__INSTANCE__) == COMP7) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7))) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \ + ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ - || \ - (((__INSTANCE__) == COMP3) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ - || \ - (((__INSTANCE__) == COMP4) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \ - ) + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ + || \ + (((__INSTANCE__) == COMP3) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ + || \ + (((__INSTANCE__) == COMP4) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \ + ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ - || \ - (((__INSTANCE__) == COMP3) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ - || \ - (((__INSTANCE__) == COMP4) && \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ - ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \ - ) + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ + || \ + (((__INSTANCE__) == COMP3) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ + || \ + (((__INSTANCE__) == COMP4) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \ + ) #endif /** * @} @@ -318,7 +319,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) * - SUCCESS: COMP registers are initialized * - ERROR: COMP registers are not initialized */ -ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct) +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_cordic.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_cordic.c index ff1e3864fc..5bc2fb6464 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_cordic.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_cordic.c @@ -58,7 +58,7 @@ * - SUCCESS: CORDIC registers are de-initialized * - ERROR: CORDIC registers are not de-initialized */ -ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx) +ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_crc.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_crc.c index c41c713d61..e83c92b458 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_crc.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_crc.c @@ -59,7 +59,7 @@ * - SUCCESS: CRC registers are de-initialized * - ERROR: CRC registers are not de-initialized */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dac.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dac.c index c9da11526e..0b21f6102c 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dac.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dac.c @@ -46,23 +46,23 @@ * @{ */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ - (((__DACX__) == DAC2) ? \ +#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ + (((__DACX__) == DAC2) ? \ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ - : \ + : \ (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ - || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)) \ + || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)) \ ) #else -#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ +#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ ) -#endif +#endif /* #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_DAC_TRIGGER_SOURCE(__DACX__, __TRIGGER_SOURCE__) \ - ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ @@ -77,7 +77,7 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG5) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG6) \ || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ + : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ || (((__DACX__) == DAC1) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO1))\ || (((__DACX__) == DAC2) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO2))\ || (((__DACX__) == DAC3) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO3))\ @@ -85,7 +85,7 @@ ) #else #define IS_LL_DAC_TRIGGER_SOURCE(__DACX__, __TRIGGER_SOURCE__) \ - ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ @@ -94,13 +94,13 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ + : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ ) -#endif +#endif /* STM32G474xx || STM32G484xx */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_DAC_TRIGGER_SOURCE2(__DACX__, __TRIGGER_SOURCE__) \ - ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ @@ -115,11 +115,11 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6) \ || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ + : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ ) #else #define IS_LL_DAC_TRIGGER_SOURCE2(__DACX__, __TRIGGER_SOURCE__) \ - ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ @@ -128,64 +128,65 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ + : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ ) -#endif +#endif /* STM32G474xx || STM32G484xx */ #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ - ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH) \ ) -#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ - ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ - ) \ - ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ - ) \ - ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH) \ - && (((__WAVE_AUTO_GENERATION_CONFIG__) & ~(DAC_STR1_STINCDATA1|DAC_STR1_STDIR1|DAC_STR1_STRSTDATA1)) \ - == 0UL) \ - ) \ + +#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ + ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ + ) \ + ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + ) \ + ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) & ~(DAC_STR1_STINCDATA1|DAC_STR1_STDIR1|DAC_STR1_STRSTDATA1)) \ + == 0UL) \ + ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ - ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \ - ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \ - || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ + (((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \ + || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ ) #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \ - ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \ - || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ + (((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \ + || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ ) /** @@ -212,7 +213,7 @@ * - SUCCESS: DAC registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) +ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx) { /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); @@ -226,7 +227,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) /* Release reset of DAC clock */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_DAC1); } -#endif +#endif /* DAC1 */ #ifdef DAC2 if (DACx == DAC2) { @@ -236,7 +237,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) /* Release reset of DAC clock */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_DAC2); } -#endif +#endif /* DAC2 */ #ifdef DAC3 if (DACx == DAC3) { @@ -246,7 +247,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) /* Release reset of DAC clock */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_DAC3); } -#endif +#endif /* DAC3 */ #ifdef DAC4 if (DACx == DAC4) { @@ -256,7 +257,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) /* Release reset of DAC clock */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_DAC4); } -#endif +#endif /* DAC4 */ return SUCCESS; } @@ -289,7 +290,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) * - SUCCESS: DAC registers are initialized * - ERROR: DAC registers are not initialized */ -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; @@ -327,6 +328,7 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), DAC_InitStruct->WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); + MODIFY_REG(DACx->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), ( @@ -334,7 +336,10 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType | ((DAC_InitStruct->TriggerSource2 >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos) ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); - WRITE_REG(*(__DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0)), + + WRITE_REG(*(__DAC_PTR_REG_OFFSET(DACx->STR1, + (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & + DAC_REG_STRX_REGOFFSET_MASK_POSBIT0)), DAC_InitStruct->WaveAutoGenerationConfig); } else @@ -423,4 +428,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmac.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmac.c index 551d1b5a3a..4c523c0bdc 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmac.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmac.c @@ -90,7 +90,7 @@ ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx) * - SUCCESS: FMAC registers are de-initialized * - ERROR: FMAC registers are not de-initialized */ -ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx) +ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmc.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmc.c index c0c231581b..2a6a2f601c 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmc.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmc.c @@ -58,7 +58,8 @@ /** @addtogroup STM32G4xx_HAL_Driver * @{ */ -#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) \ + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_i2c.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_i2c.c index 93bea7277f..8c165f93e9 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_i2c.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_i2c.c @@ -83,7 +83,7 @@ * - SUCCESS: I2C registers are de-initialized * - ERROR: I2C registers are not de-initialized */ -ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) { ErrorStatus status = SUCCESS; @@ -141,7 +141,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) * - SUCCESS: I2C registers are initialized * - ERROR: Not applicable */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct) { /* Check the I2C Instance I2Cx */ assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_lptim.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_lptim.c index 3e1531d760..211681b98f 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_lptim.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_lptim.c @@ -92,7 +92,7 @@ * - SUCCESS: LPTIMx registers are de-initialized * - ERROR: invalid LPTIMx instance */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx) +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx) { ErrorStatus result = SUCCESS; @@ -137,7 +137,7 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) * - SUCCESS: LPTIMx instance has been initialized * - ERROR: LPTIMx instance hasn't been initialized */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { ErrorStatus result = SUCCESS; /* Check the parameters */ @@ -259,8 +259,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_lpuart.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_lpuart.c index caab3fac69..56937edbbc 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_lpuart.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_lpuart.c @@ -44,6 +44,9 @@ * @{ */ +/* Definition of default baudrate value used for LPUART initialisation */ +#define LPUART_DEFAULT_BAUDRATE (9600U) + /** * @} */ @@ -126,7 +129,7 @@ * - SUCCESS: LPUART registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx) { ErrorStatus status = SUCCESS; @@ -164,7 +167,7 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content * - ERROR: Problem occurred during LPUART Registers initialization */ -ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct) +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk; @@ -253,7 +256,7 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) { /* Set LPUART_InitStruct fields to default values */ LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; - LPUART_InitStruct->BaudRate = 9600U; + LPUART_InitStruct->BaudRate = LPUART_DEFAULT_BAUDRATE; LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_rng.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_rng.c index 9a2053f95f..9fdfa6e5de 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_rng.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_rng.c @@ -68,7 +68,7 @@ * - SUCCESS: RNG registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c index 679b22089a..7ef1d51daf 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c @@ -66,8 +66,8 @@ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \ || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \ || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT)) @@ -197,16 +197,16 @@ /** @defgroup TIM_LL_Private_Functions TIM Private Functions * @{ */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); /** * @} */ @@ -227,7 +227,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: invalid TIMx instance */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) { ErrorStatus result = SUCCESS; @@ -331,7 +331,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) { uint32_t tmpcr1; @@ -412,7 +412,7 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) { ErrorStatus result = ERROR; @@ -473,7 +473,7 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) { ErrorStatus result = ERROR; @@ -527,7 +527,7 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -620,7 +620,7 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { uint32_t tmpcr2; uint32_t tmpccmr1; @@ -734,7 +734,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; @@ -746,6 +746,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -758,14 +760,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); - if (IS_TIM_ADVANCED_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(TIMx)) { @@ -806,7 +802,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -817,8 +813,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -846,8 +840,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -885,7 +881,7 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -896,8 +892,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -925,8 +919,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -964,7 +960,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -975,8 +971,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -1004,8 +998,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -1043,7 +1039,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -1054,8 +1050,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1083,8 +1077,10 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); @@ -1122,7 +1118,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; @@ -1183,7 +1179,7 @@ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; @@ -1243,7 +1239,7 @@ static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); @@ -1276,7 +1272,7 @@ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); @@ -1309,7 +1305,7 @@ static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); @@ -1342,7 +1338,7 @@ static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); @@ -1359,7 +1355,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usart.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usart.c index acd26f922c..a3d3964624 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usart.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usart.c @@ -31,7 +31,7 @@ * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) /** @addtogroup USART_LL * @{ @@ -40,6 +40,17 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for USART initialisation */ +#define USART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @addtogroup USART_LL_Private_Macros * @{ @@ -125,7 +136,7 @@ * - SUCCESS: USART registers are de-initialized * - ERROR: USART registers are not de-initialized */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) { ErrorStatus status = SUCCESS; @@ -198,7 +209,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * - SUCCESS: USART registers are initialized according to USART_InitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; @@ -318,7 +329,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) { /* Set USART_InitStruct fields to default values */ USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; - USART_InitStruct->BaudRate = 9600U; + USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; USART_InitStruct->StopBits = LL_USART_STOPBITS_1; USART_InitStruct->Parity = LL_USART_PARITY_NONE ; @@ -341,7 +352,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c index 5c598266f0..61a3edb098 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c @@ -27,7 +27,7 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. (#) Call USB_CoreInit() API to initialize the USB Core peripheral. @@ -172,6 +172,47 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) return HAL_OK; } +/** + * @brief USB_FlushTxFifo : Flush a Tx FIFO + * @param USBx : Selected device + * @param num : FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(num); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + + #if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint @@ -242,8 +283,16 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + if (ep->num == 0U) + { + /* Configure VALID status for EP0 */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + else + { + /* Configure NAK status for OUT Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); + } } } #if (USE_USB_DOUBLE_BUFFER == 1U) @@ -628,6 +677,51 @@ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) return HAL_OK; } + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + /* IN endpoint */ + if (ep->is_in == 1U) + { + if (ep->doublebuffer == 0U) + { + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + } + } + else /* OUT endpoint */ + { + if (ep->doublebuffer == 0U) + { + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); + } + else + { + /* Configure RX Endpoint to disabled state */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } + } + + return HAL_OK; +} #endif /* defined (HAL_PCD_MODULE_ENABLED) */ /** @@ -696,9 +790,9 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) /** * @brief USB_ReadInterrupts return the global USB interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Global Interrupt status */ -uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) { uint32_t tmpreg; @@ -738,24 +832,22 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) * @param wNBytes no. of bytes to be copied. * @retval None */ -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; uint32_t BaseAddr = (uint32_t)USBx; - uint32_t i; - uint32_t temp1; - uint32_t temp2; + uint32_t count; + uint16_t WrVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); - for (i = n; i != 0U; i--) + for (count = n; count != 0U; count--) { - temp1 = *pBuf; - pBuf++; - temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8)); - *pdwVal = (uint16_t)temp2; + WrVal = pBuf[0]; + WrVal |= (uint16_t)pBuf[1] << 8; + *pdwVal = (WrVal & 0xFFFFU); pdwVal++; #if PMA_ACCESS > 1U @@ -763,6 +855,7 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui #endif /* PMA_ACCESS */ pBuf++; + pBuf++; } } @@ -774,24 +867,24 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui * @param wNBytes no. of bytes to be copied. * @retval None */ -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { uint32_t n = (uint32_t)wNBytes >> 1; uint32_t BaseAddr = (uint32_t)USBx; - uint32_t i; - uint32_t temp; + uint32_t count; + uint32_t RdVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); - for (i = n; i != 0U; i--) + for (count = n; count != 0U; count--) { - temp = *(__IO uint16_t *)pdwVal; + RdVal = *(__IO uint16_t *)pdwVal; pdwVal++; - *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); pBuf++; - *pBuf = (uint8_t)((temp >> 8) & 0xFFU); + *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU); pBuf++; #if PMA_ACCESS > 1U @@ -801,8 +894,8 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uin if ((wNBytes % 2U) != 0U) { - temp = *pdwVal; - *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + RdVal = *pdwVal; + *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); } } diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c index 296f701aeb..d971b05d71 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c +++ b/system/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c @@ -46,7 +46,7 @@ /* Defines used for PLL range */ #define UTILS_PLLVCO_INPUT_MIN 2660000U /*!< Frequency min for PLLVCO input, in Hz */ -#define UTILS_PLLVCO_INPUT_MAX 8000000U /*!< Frequency max for PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */ #define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */ #define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */ @@ -55,18 +55,21 @@ #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */ /* Defines used for FLASH latency according to HCLK Frequency */ -#define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ -#define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ -#define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ -#define UTILS_SCALE1_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ -#define UTILS_SCALE1_LATENCY5_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ -#define UTILS_SCALE1_LATENCY6_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 */ -#define UTILS_SCALE1_LATENCY7_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 */ -#define UTILS_SCALE1_LATENCY8_FREQ 160000000U /*!< HCLK frequency to set FLASH latency 8 in power scale 1 */ -#define UTILS_SCALE1_LATENCY9_FREQ 170000000U /*!< HCLK frequency to set FLASH latency 9 in power scale 1 */ -#define UTILS_SCALE2_LATENCY1_FREQ 8000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ -#define UTILS_SCALE2_LATENCY2_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ -#define UTILS_SCALE2_LATENCY3_FREQ 26000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ +#define UTILS_SCALE1_LATENCY1_BOOST_FREQ 34000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_BOOST_FREQ 68000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define UTILS_SCALE1_LATENCY3_BOOST_FREQ 102000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ +#define UTILS_SCALE1_LATENCY4_BOOST_FREQ 136000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE1_LATENCY5_BOOST_FREQ 170000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ + +#define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 normal mode */ +#define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 normal mode */ +#define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 normal mode */ +#define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 normal mode */ +#define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 normal mode */ + +#define UTILS_SCALE2_LATENCY1_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE2_LATENCY2_FREQ 24000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ +#define UTILS_SCALE2_LATENCY3_FREQ 26000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ /** * @} */ @@ -223,31 +226,22 @@ void LL_mDelay(uint32_t Delay) Depending on the device voltage range, the maximum frequency should be adapted accordingly: - (++) Table 1. HCLK clock frequency for STM32G4xx devices - (++) +--------------------------------------------------------+ - (++) | Latency | HCLK clock frequency (MHz) | - (++) | |--------------------------------------| - (++) | | voltage range 1 | voltage range 2 | - (++) | | 1.2 V | 1.0 V | - (++) |-----------------|-------------------|------------------| - (++) |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | - (++) |-----------------|-------------------|------------------| - (++) |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | - (++) |-----------------|-------------------|------------------| - (++) |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | - (++) |-----------------|-------------------|------------------| - (++) |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | - (++) |-----------------|-------------------|------------------| - (++) |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | - (++) |-----------------|-------------------|------------------| - (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | - (++) |-----------------|-------------------|------------------| - (++) |6WS(7 CPU cycles)| 120 < HCLK <= 140 | 16 < HCLK <= 26 | - (++) |-----------------|-------------------|------------------| - (++) |7WS(8 CPU cycles)| 140 < HCLK <= 160 | 16 < HCLK <= 26 | - (++) |-----------------|-------------------|------------------| - (++) |8WS(9 CPU cycles)| 160 < HCLK <= 170 | 16 < HCLK <= 26 | - (++) +--------------------------------------------------------+ + +----------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |----------------------------------------------------------| + | | voltage range 1 | voltage range 1 | voltage range 2 | + | | boost mode 1.28 V | normal mode 1.2 V | 1.0 V | + |-----------------|-------------------|-------------------|------------------| + |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK <= 12 | + |-----------------|-------------------|-------------------|------------------| + |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK <= 24 | + |-----------------|-------------------|-------------------|------------------| + |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | HCLK <= 26 | + |-----------------|-------------------|-------------------|------------------| + |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | - | + |-----------------|-------------------|-------------------|------------------| + |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | - | + +----------------------------------------------------------------------------+ @endinternal @@ -279,80 +273,95 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency) uint32_t timeout; uint32_t getlatency; ErrorStatus status = SUCCESS; + uint32_t regulatorstatus = LL_PWR_GetRegulVoltageScaling(); + uint32_t regulatorbooststatus = LL_PWR_IsEnabledRange1BoostMode(); uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ /* Frequency cannot be equal to 0 or greater than max clock */ - if((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY9_FREQ)) + if((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY5_BOOST_FREQ)) { status = ERROR; } else { - if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + if((regulatorstatus == LL_PWR_REGU_VOLTAGE_SCALE1) && (regulatorbooststatus == 1U)) { - if(HCLKFrequency > UTILS_SCALE1_LATENCY8_FREQ) + if(HCLKFrequency > UTILS_SCALE1_LATENCY4_BOOST_FREQ) { - /* 160 < HCLK <= 170 => 8WS (9 CPU cycles) */ - latency = LL_FLASH_LATENCY_8; + /* 136 < HCLK <= 170 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; } - else if(HCLKFrequency > UTILS_SCALE1_LATENCY7_FREQ) + else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_BOOST_FREQ) { - /* 140 < HCLK <= 160 => 7WS (8 CPU cycles) */ - latency = LL_FLASH_LATENCY_7; + /* 102 < HCLK <= 136 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; } - else if(HCLKFrequency > UTILS_SCALE1_LATENCY6_FREQ) + else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_BOOST_FREQ) { - /* 120 < HCLK <= 140 => 6WS (7 CPU cycles) */ - latency = LL_FLASH_LATENCY_6; + /* 68 < HCLK <= 102 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; } - else if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ) + else { - /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ - latency = LL_FLASH_LATENCY_5; + if(HCLKFrequency > UTILS_SCALE1_LATENCY1_BOOST_FREQ) + { + /* 34 < HCLK <= 68 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ } - else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ) + } + /* SCALE1 normal mode*/ + else if(regulatorstatus == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ) { - /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ + /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ latency = LL_FLASH_LATENCY_4; } else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ) { - /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ + /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ latency = LL_FLASH_LATENCY_3; } else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ) { - /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */ + /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ latency = LL_FLASH_LATENCY_2; } else { if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) { - /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ + /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ } } - else /* SCALE2 */ + /* SCALE2 */ + else if(regulatorstatus == LL_PWR_REGU_VOLTAGE_SCALE2) { if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ) { - /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ + /* 24 < HCLK <= 26 => 2WS (3 CPU cycles) */ latency = LL_FLASH_LATENCY_2; } else { if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ) { - /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ + /* 12 < HCLK <= 24 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 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system/Drivers/STM32G4xx_HAL_Driver/_htmresc/mini-st.css rename to system/Drivers/STM32G4xx_HAL_Driver/_htmresc/mini-st_2020.css index 3caf11c32e..c03463bd58 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/_htmresc/mini-st.css +++ b/system/Drivers/STM32G4xx_HAL_Driver/_htmresc/mini-st_2020.css @@ -1,39 +1,39 @@ @charset "UTF-8"; /* - Flavor name: Default (mini-default) - Author: Angelos Chalaris (chalarangelo@gmail.com) - Maintainers: Angelos Chalaris - mini.css version: v3.0.0-alpha.3 + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 */ /* Browsers resets and base typography. */ /* Core module CSS variable definitions */ :root { - --fore-color: #111; - --secondary-fore-color: #444; - --back-color: #f8f8f8; - --secondary-back-color: #f0f0f0; - --blockquote-color: #f57c00; - --pre-color: #1565c0; - --border-color: #aaa; - --secondary-border-color: #ddd; - --heading-ratio: 1.19; + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; --universal-margin: 0.5rem; - --universal-padding: 0.125rem; - --universal-border-radius: 0.125rem; - --a-link-color: #0277bd; - --a-visited-color: #01579b; } + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } html { - font-size: 14px; } + font-size: 13.5px; } a, b, del, em, i, ins, q, span, strong, u { font-size: 1em; } html, * { - font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; - line-height: 1.4; + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; -webkit-text-size-adjust: 100%; } * { @@ -42,7 +42,10 @@ html, * { body { margin: 0; color: var(--fore-color); - background: var(--back-color); } + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } details { display: block; } @@ -62,9 +65,9 @@ img { height: auto; } h1, h2, h3, h4, h5, h6 { - line-height: 1.2; + line-height: 1.25; margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 500; } + font-weight: 400; } h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { color: var(--secondary-fore-color); display: block; @@ -74,21 +77,15 @@ h1 { font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); - background: var(--mark-back-color); - font-weight: 600; - padding: 0.1em 0.5em 0.2em 0.5em; - color: var(--mark-fore-color); } - + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } h3 { - font-size: calc(1rem * var(--heading-ratio)); - padding-left: calc(2 * var(--universal-margin)); - /* background: var(--border-color); */ - } + font-size: calc(1rem * var(--heading-ratio) ); } h4 { - font-size: 1rem;); - padding-left: calc(4 * var(--universal-margin)); } + font-size: calc(1rem * var(--heading-ratio)); } h5 { font-size: 1rem; } @@ -101,7 +98,7 @@ p { ol, ul { margin: var(--universal-margin); - padding-left: calc(6 * var(--universal-margin)); } + padding-left: calc(3 * var(--universal-margin)); } b, strong { font-weight: 700; } @@ -111,7 +108,7 @@ hr { border: 0; line-height: 1.25em; margin: var(--universal-margin); - height: 0.0625rem; + height: 0.0714285714rem; background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } blockquote { @@ -121,16 +118,16 @@ blockquote { color: var(--secondary-fore-color); margin: var(--universal-margin); padding: calc(3 * var(--universal-padding)); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.375rem solid var(--blockquote-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } blockquote:before { position: absolute; top: calc(0rem - var(--universal-padding)); left: 0; font-family: sans-serif; - font-size: 3rem; - font-weight: 700; + font-size: 2rem; + font-weight: 800; content: "\201c"; color: var(--blockquote-color); } blockquote[cite]:after { @@ -160,8 +157,8 @@ pre { background: var(--secondary-back-color); padding: calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.25rem solid var(--pre-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } sup, sub, code, kbd { @@ -204,7 +201,8 @@ a { box-sizing: border-box; display: flex; flex: 0 1 auto; - flex-flow: row wrap; } + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } .col-sm, [class^='col-sm-'], @@ -565,9 +563,9 @@ a { order: 999; } } /* Card component CSS variable definitions */ :root { - --card-back-color: #f8f8f8; - --card-fore-color: #111; - --card-border-color: #ddd; } + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } .card { display: flex; @@ -578,7 +576,7 @@ a { width: 100%; background: var(--card-back-color); color: var(--card-fore-color); - border: 0.0625rem solid var(--card-border-color); + border: 0.0714285714rem solid var(--card-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); overflow: hidden; } @@ -592,7 +590,7 @@ a { margin: 0; border: 0; border-radius: 0; - border-bottom: 0.0625rem solid var(--card-border-color); + border-bottom: 0.0714285714rem solid var(--card-border-color); padding: var(--universal-padding); width: 100%; } .card > .sectione.media { @@ -617,17 +615,18 @@ a { width: auto; } .card.warning { -/* --card-back-color: #ffca28; */ --card-back-color: #e5b8b7; - --card-border-color: #e8b825; } + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } .card.error { - --card-back-color: #b71c1c; - --card-fore-color: #f8f8f8; - --card-border-color: #a71a1a; } + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } .card > .sectione.dark { - --card-back-color: #e0e0e0; } + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } .card > .sectione.double-padded { padding: calc(1.5 * var(--universal-padding)); } @@ -637,12 +636,12 @@ a { */ /* Input_control module CSS variable definitions */ :root { - --form-back-color: #f0f0f0; - --form-fore-color: #111; - --form-border-color: #ddd; - --input-back-color: #f8f8f8; - --input-fore-color: #111; - --input-border-color: #ddd; + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; --input-focus-color: #0288d1; --input-invalid-color: #d32f2f; --button-back-color: #e2e2e2; @@ -655,13 +654,13 @@ a { form { background: var(--form-back-color); color: var(--form-fore-color); - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); padding: calc(2 * var(--universal-padding)) var(--universal-padding); } fieldset { - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 4); padding: var(--universal-padding); } @@ -671,7 +670,7 @@ legend { display: table; max-width: 100%; white-space: normal; - font-weight: 700; + font-weight: 500; padding: calc(var(--universal-padding) / 2); } label { @@ -716,7 +715,7 @@ input:not([type]), [type="text"], [type="email"], [type="number"], [type="search box-sizing: border-box; background: var(--input-back-color); color: var(--input-fore-color); - border: 0.0625rem solid var(--input-border-color); + border: 0.0714285714rem solid var(--input-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 2); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } @@ -763,8 +762,8 @@ option { [type="radio"]:checked:before { border-radius: 100%; content: ''; - top: calc(0.0625rem + var(--universal-padding) / 2); - left: calc(0.0625rem + var(--universal-padding) / 2); + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); background: var(--input-fore-color); width: 0.5rem; height: 0.5rem; } @@ -793,7 +792,7 @@ a[role="button"], label[role="button"], [role="button"] { display: inline-block; background: var(--button-back-color); color: var(--button-fore-color); - border: 0.0625rem solid var(--button-border-color); + border: 0.0714285714rem solid var(--button-border-color); border-radius: var(--universal-border-radius); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); @@ -814,7 +813,7 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d .button-group { display: flex; - border: 0.0625rem solid var(--button-group-border-color); + border: 0.0714285714rem solid var(--button-group-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { @@ -826,13 +825,13 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d border-radius: 0; box-shadow: none; } .button-group > :not(:first-child) { - border-left: 0.0625rem solid var(--button-group-border-color); } + border-left: 0.0714285714rem solid var(--button-group-border-color); } @media screen and (max-width: 499px) { .button-group { flex-direction: column; } .button-group > :not(:first-child) { border: 0; - border-top: 0.0625rem solid var(--button-group-border-color); } } + border-top: 0.0714285714rem solid var(--button-group-border-color); } } /* Custom elements for forms and input elements. @@ -874,29 +873,29 @@ button.large, [type="button"].large, [type="submit"].large, [type="reset"].large */ /* Navigation module CSS variable definitions */ :root { - --header-back-color: #f8f8f8; - --header-hover-back-color: #f0f0f0; - --header-fore-color: #444; - --header-border-color: #ddd; - --nav-back-color: #f8f8f8; - --nav-hover-back-color: #f0f0f0; - --nav-fore-color: #444; - --nav-border-color: #ddd; - --nav-link-color: #0277bd; - --footer-fore-color: #444; - --footer-back-color: #f8f8f8; - --footer-border-color: #ddd; - --footer-link-color: #0277bd; - --drawer-back-color: #f8f8f8; - --drawer-hover-back-color: #f0f0f0; - --drawer-border-color: #ddd; - --drawer-close-color: #444; } + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } header { - height: 3.1875rem; + height: 2.75rem; background: var(--header-back-color); color: var(--header-fore-color); - border-bottom: 0.0625rem solid var(--header-border-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); padding: calc(var(--universal-padding) / 4) 0; white-space: nowrap; overflow-x: auto; @@ -927,7 +926,7 @@ header { nav { background: var(--nav-back-color); color: var(--nav-fore-color); - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } nav * { @@ -946,10 +945,10 @@ nav { nav .sublink-1:before { position: absolute; left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } nav .sublink-2 { position: relative; @@ -957,16 +956,16 @@ nav { nav .sublink-2:before { position: absolute; left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } footer { background: var(--footer-back-color); color: var(--footer-fore-color); - border-top: 0.0625rem solid var(--footer-border-color); + border-top: 0.0714285714rem solid var(--footer-border-color); padding: calc(2 * var(--universal-padding)) var(--universal-padding); font-size: 0.875rem; } footer a, footer a:visited { @@ -1013,7 +1012,7 @@ footer.sticky { height: 100vh; overflow-y: auto; background: var(--drawer-back-color); - border: 0.0625rem solid var(--drawer-border-color); + border: 0.0714285714rem solid var(--drawer-border-color); border-radius: 0; margin: 0; z-index: 1110; @@ -1060,38 +1059,36 @@ footer.sticky { */ /* Table module CSS variable definitions. */ :root { - --table-border-color: #aaa; - --table-border-separator-color: #666; - --table-head-back-color: #e6e6e6; - --table-head-fore-color: #111; - --table-body-back-color: #f8f8f8; - --table-body-fore-color: #111; - --table-body-alt-back-color: #eee; } + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } table { border-collapse: separate; border-spacing: 0; - : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + margin: 0; display: flex; flex: 0 1 auto; flex-flow: row wrap; padding: var(--universal-padding); - padding-top: 0; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + padding-top: 0; } table caption { - font-size: 1.25 * rem; + font-size: 1rem; margin: calc(2 * var(--universal-margin)) 0; max-width: 100%; - flex: 0 0 100%; - text-align: left;} + flex: 0 0 100%; } table thead, table tbody { display: flex; flex-flow: row wrap; - border: 0.0625rem solid var(--table-border-color); } + border: 0.0714285714rem solid var(--table-border-color); } table thead { z-index: 999; border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0625rem solid var(--table-border-separator-color); } + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } table tbody { border-top: 0; margin-top: calc(0 - var(--universal-margin)); @@ -1109,11 +1106,11 @@ table { table td { background: var(--table-body-back-color); color: var(--table-body-fore-color); - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table:not(.horizontal) { overflow: auto; - max-height: 850px; } + max-height: 100%; } table:not(.horizontal) thead, table:not(.horizontal) tbody { max-width: 100%; flex: 0 0 100%; } @@ -1134,32 +1131,33 @@ table.horizontal { border: 0; } table.horizontal thead, table.horizontal tbody { border: 0; + flex: .2 0 0; flex-flow: row nowrap; } table.horizontal tbody { overflow: auto; justify-content: space-between; - flex: 1 0 0; - margin-left: calc( 4 * var(--universal-margin)); + flex: .8 0 0; + margin-left: 0; padding-bottom: calc(var(--universal-padding) / 4); } table.horizontal tr { flex-direction: column; flex: 1 0 auto; } table.horizontal th, table.horizontal td { - width: 100%; + width: auto; border: 0; - border-bottom: 0.0625rem solid var(--table-border-color); } + border-bottom: 0.0714285714rem solid var(--table-border-color); } table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { border-top: 0; } table.horizontal th { text-align: right; - border-left: 0.0625rem solid var(--table-border-color); - border-right: 0.0625rem solid var(--table-border-separator-color); } + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } table.horizontal thead tr:first-child { padding-left: 0; } table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td { - border-right: 0.0625rem solid var(--table-border-color); } + border-right: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td:first-child { border-top-right-radius: 0.25rem; } table.horizontal tbody tr:last-child td:last-child { @@ -1191,12 +1189,12 @@ table.horizontal { display: table-row-group; } table tr, table.horizontal tr { display: block; - border: 0.0625rem solid var(--table-border-color); + border: 0.0714285714rem solid var(--table-border-color); border-radius: var(--universal-border-radius); - background: #fafafa; + background: #ffffff; padding: var(--universal-padding); margin: var(--universal-margin); - margin-bottom: calc(2 * var(--universal-margin)); } + margin-bottom: calc(1 * var(--universal-margin)); } table th, table td, table.horizontal th, table.horizontal td { width: auto; } table td, table.horizontal td { @@ -1211,9 +1209,6 @@ table.horizontal { border-top: 0; } table tbody tr:last-child td, table.horizontal tbody tr:last-child td { border-right: 0; } } -:root { - --table-body-alt-back-color: #eee; } - table tr:nth-of-type(2n) > td { background: var(--table-body-alt-back-color); } @@ -1234,8 +1229,8 @@ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focu */ /* Contextual module CSS variable definitions */ :root { - --mark-back-color: #0277bd; - --mark-fore-color: #fafafa; } + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } mark { background: var(--mark-back-color); @@ -1243,11 +1238,11 @@ mark { font-size: 0.95em; line-height: 1em; border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } mark.inline-block { display: inline-block; font-size: 1em; - line-height: 1.5; + line-height: 1.4; padding: calc(var(--universal-padding) / 2) var(--universal-padding); } :root { @@ -1314,8 +1309,8 @@ mark { :root { --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #444; - --modal-close-hover-color: #f0f0f0; } + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } [type="checkbox"].modal { height: 1px; @@ -1368,13 +1363,14 @@ mark { z-index: 1211; } :root { - --collapse-label-back-color: #e8e8e8; - --collapse-label-fore-color: #212121; - --collapse-label-hover-back-color: #f0f0f0; - --collapse-selected-label-back-color: #ececec; - --collapse-border-color: #ddd; - --collapse-content-back-color: #fafafa; - --collapse-selected-label-border-color: #0277bd; } + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } .collapse { width: calc(100% - 2 * var(--universal-margin)); @@ -1395,13 +1391,13 @@ mark { .collapse > label { flex-grow: 1; display: inline-block; - height: 1.5rem; + height: 1.25rem; cursor: pointer; - transition: background 0.3s; + transition: background 0.2s; color: var(--collapse-label-fore-color); background: var(--collapse-label-back-color); - border: 0.0625rem solid var(--collapse-border-color); - padding: calc(1.5 * var(--universal-padding)); } + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } .collapse > label:hover, .collapse > label:focus { background: var(--collapse-label-hover-back-color); } .collapse > label + div { @@ -1418,7 +1414,7 @@ mark { max-height: 1px; } .collapse > :checked + label { background: var(--collapse-selected-label-back-color); - border-bottom-color: var(--collapse-selected-label-border-color); } + border-color: var(--collapse-selected-label-border-color); } .collapse > :checked + label + div { box-sizing: border-box; position: relative; @@ -1427,13 +1423,13 @@ mark { overflow: auto; margin: 0; background: var(--collapse-content-back-color); - border: 0.0625rem solid var(--collapse-border-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); border-top: 0; padding: var(--universal-padding); clip: auto; -webkit-clip-path: inset(0%); clip-path: inset(0%); - max-height: 850px; } + max-height: 100%; } .collapse > label:not(:first-of-type) { border-top: 0; } .collapse > label:first-of-type { @@ -1450,11 +1446,8 @@ mark { /* Custom elements for contextual background elements, toasts and tooltips. */ -mark.secondary { - --mark-back-color: #d32f2f; } - mark.tertiary { - --mark-back-color: #308732; } + --mark-back-color: #3cb4e6; } mark.tag { padding: calc(var(--universal-padding)/2) var(--universal-padding); @@ -1463,9 +1456,9 @@ mark.tag { /* Definitions for progress elements and spinners. */ -/* Progess module CSS variable definitions */ +/* Progress module CSS variable definitions */ :root { - --progress-back-color: #ddd; + --progress-back-color: #3cb4e6; --progress-fore-color: #555; } progress { @@ -1558,45 +1551,45 @@ span[class^='icon-'] { filter: invert(100%); } span.icon-alert { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } span.icon-bookmark { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-calendar { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-credit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-edit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } span.icon-link { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } span.icon-help { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } span.icon-home { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-info { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } span.icon-lock { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } span.icon-mail { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-location { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' 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16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-search { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } span.icon-settings { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' 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fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-share { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } span.icon-cart { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } span.icon-upload { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } /* Definitions for utilities and helper classes. @@ -1604,7 +1597,7 @@ span.icon-user { /* Utility module CSS variable definitions */ :root { --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } .hidden { display: none !important; } @@ -1622,7 +1615,7 @@ span.icon-user { overflow: hidden !important; } .bordered { - border: 0.0625rem solid var(--generic-border-color) !important; } + border: 0.0714285714rem solid var(--generic-border-color) !important; } .rounded { border-radius: var(--universal-border-radius) !important; } @@ -1697,4 +1690,14 @@ span.icon-user { clip-path: inset(100%) !important; overflow: hidden !important; } } -/*# sourceMappingURL=mini-default.css.map */ +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/system/Drivers/STM32G4xx_HAL_Driver/_htmresc/st_logo.png b/system/Drivers/STM32G4xx_HAL_Driver/_htmresc/st_logo.png deleted file mode 100644 index 8b80057fd3a454a97de1c9d732b7fede82c83227..0000000000000000000000000000000000000000 GIT binary patch literal 0 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-8,7 +8,7 @@ * STM32F4: 1.8.2 * STM32F7: 1.3.0 * STM32G0: 1.4.6 - * STM32G4: 1.2.2 + * STM32G4: 1.2.3 * STM32H5: 1.1.0 * STM32H7: 1.11.1 * STM32L0: 1.10.6 From 4d19f086aa994bf2166cadd661c53f345f5e71f9 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 2 Jan 2024 15:36:21 +0100 Subject: [PATCH 67/83] system(G4): update STM32G4xx CMSIS Drivers to v1.2.3 Included in STM32CubeG4 FW v1.5.2 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32G4xx/Include/stm32g431xx.h | 28 +- .../Device/ST/STM32G4xx/Include/stm32g441xx.h | 28 +- .../Device/ST/STM32G4xx/Include/stm32g471xx.h | 28 +- .../Device/ST/STM32G4xx/Include/stm32g473xx.h | 30 +- .../Device/ST/STM32G4xx/Include/stm32g474xx.h | 38 +- .../Device/ST/STM32G4xx/Include/stm32g483xx.h | 30 +- .../Device/ST/STM32G4xx/Include/stm32g484xx.h | 38 +- .../Device/ST/STM32G4xx/Include/stm32g491xx.h | 28 +- .../Device/ST/STM32G4xx/Include/stm32g4a1xx.h | 28 +- .../Device/ST/STM32G4xx/Include/stm32g4xx.h | 4 +- .../Device/ST/STM32G4xx/Include/stm32gbk1cb.h | 28 +- .../CMSIS/Device/ST/STM32G4xx/License.md | 83 ++++ .../Device/ST/STM32G4xx/Release_Notes.html | 140 ++++--- .../Templates/gcc/startup_stm32g431xx.s | 9 +- .../Templates/gcc/startup_stm32g441xx.s | 8 +- .../Templates/gcc/startup_stm32g471xx.s | 8 +- .../Templates/gcc/startup_stm32g473xx.s | 8 +- .../Templates/gcc/startup_stm32g474xx.s | 8 +- .../Templates/gcc/startup_stm32g483xx.s | 9 +- .../Templates/gcc/startup_stm32g484xx.s | 8 +- .../Templates/gcc/startup_stm32g491xx.s | 8 +- .../Templates/gcc/startup_stm32g4a1xx.s | 8 +- .../Templates/gcc/startup_stm32gbk1cb.s | 9 +- .../Device/ST/STM32G4xx/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../{mini-st.css => mini-st_2020.css} | 363 +++++++++--------- .../Device/ST/STM32G4xx/_htmresc/st_logo.png | Bin 18616 -> 0 bytes .../ST/STM32G4xx/_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 28 files changed, 499 insertions(+), 480 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32G4xx/License.md create mode 100644 system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/favicon.png rename system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/{mini-st.css => mini-st_2020.css} (77%) delete mode 100644 system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/st_logo.png create mode 100644 system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/st_logo_2020.png diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h index 7be3c23282..4d47482925 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h @@ -699,8 +699,7 @@ typedef struct typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1216,7 +1215,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1362,7 +1361,7 @@ typedef struct #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4063,7 +4062,7 @@ typedef struct /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*! - + +
            -
            -

            Release Notes for STM32G4xx CMSIS

            Copyright © 2019 STMicroelectronics

            - +
            -
            -

            Purpose

            This driver provides the CMSIS device for the stm32g4xx products. This covers following series :

              @@ -41,14 +38,14 @@

              Purpose

              Various template file are provided to easily build an application. They can be adapted to fit applications requirements.

              • Templates/system_stm32g4xx.c contains the initialization code referred as SystemInit.
                • -
              • Startup files are provided as example for IAR©, KEIL© and SW4STM32©.
                • -
              • Linker files are provided as example for IAR©, KEIL© and SW4STM32©.
                • +
              • Startup files are provided as example for IAR©, KEIL© and STM32CubeIDE©.
                • +
              • Linker files are provided as example for IAR©, KEIL© and STM32CubeIDE©.

            Update History

            - +

            Main Changes

            Maintenance release

            @@ -57,6 +54,59 @@

            Maintenance release

          Contents

          + + + + + + + + + + + + + + + + + + + + + + + +
          Fixed bugs list
          +
          Headline
          - Fix misalignment between reference manual and CMSIS driver: remove GCR register.
          - Add missing __IRQn and __IRQHandler aliases, TIM7_DAC and COMP4_5_6 for STM32G491xx and STM32G4A1xx devices.
          - Update to call SystemInit first in startup/Reset_Handler, so GCC code is similar to IAR/Keil.
          - Change the value of RAM end region in stm32g491xx IAR linker files.
          - Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.
          +

          Known Limitations

          +

          Development Toolchains and Compilers

          +
            +
          • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9 + ST-Link
            • +
          • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38 + ST-Link
            • +
          • CubeIDE toolchain V1.14.0
            • +
          +

          Supported Devices and boards

          +
            +
          • STM32G431xx, STM32G441xx devices
            • +
          • STM32G471xx devices
            • +
          • STM32G473xx, STM32G483xx devices
            • +
          • STM32G474xx, STM32G484xx devices
            • +
          • STM32G491xx, STM32G4A1xx devices
            • +
          +

          Note: in the section above, main changes are highlighted in bold since previous release.

          +
          +
          +
          + +
          +

          Main Changes

          +

          Maintenance release

          +
            +
          • General updates to fix known defects and enhancements implementation.
            • +
          +

          Contents

          + @@ -88,16 +138,14 @@

          Contents

          Additional features
          -

          : Fixed bugs list
          -

          -

          Known Limitations

          -

          Development Toolchains and Compilers

          +

          Known Limitations

          +

          Development Toolchains and Compilers

          • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-Link
          • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-Link
          • CubeIDE toolchain V1.6.0
          -

          Supported Devices and boards

          +

          Supported Devices and boards

          • STM32G431xx, STM32G441xx devices
          • STM32G471xx devices
            • @@ -111,12 +159,12 @@

            Supported Devices and boards

            -

            Main Changes

            -

            Maintenance release

            +

            Main Changes

            +

            Maintenance release

            • General updates to fix known defects and enhancements implementation
            -

            Contents

            +

            Contents

            @@ -134,16 +182,14 @@

            Contents

            Additional features
            -

            : Fixed bugs list
            -

            -

            Known Limitations

            -

            Development Toolchains and Compilers

            +

            Known Limitations

            +

            Development Toolchains and Compilers

            • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-Link
            • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-Link
            • CubeIDE toolchain V1.6.0
            -

            Supported Devices and boards

            +

            Supported Devices and boards

            • STM32G431xx, STM32G441xx devices
            • STM32G471xx devices
              • @@ -157,13 +203,13 @@

              Supported Devices and boards

              -

              Main Changes

              -

              Maintenance release

              +

              Main Changes

              +

              Maintenance release

              • Add support for STM32G491xx and STM32G4A1 devices
              • General updates to fix known defects and enhancements implementation
              -

              Contents

              +

              Contents

              @@ -187,16 +233,14 @@

              Contents

              Additional features
              -

              : Fixed bugs list
              -

              -

              Known Limitations

              -

              Development Toolchains and Compilers

              +

              Known Limitations

              +

              Development Toolchains and Compilers

              • IAR Embedded Workbench for ARM (EWARM) toolchain V8.40.1
              • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
              • STM32CubeIDE toolchain V1.3.0
              -

              Supported Devices and boards

              +

              Supported Devices and boards

              • STM32G431xx, STM32G441xx devices
              • STM32G471xx devices
                • @@ -210,10 +254,10 @@

                Supported Devices and boards

                -

                Main Changes

                -

                Maintenance release

                +

                Main Changes

                +

                Maintenance release

                General updates to fix known defects and enhancements implementation

                -

                Contents

                +

                Contents

                @@ -238,21 +282,21 @@

                Contents

                - +
                Additional features
                Update STM32G473/483 startup files to support FDCAN2/3 intancesUpdate STM32G473/483 startup files to support FDCAN2/3 instances
                Remove IS_TIM_SYNCHRO_INSTANCE macro from device header files
                -

                Known Limitations

                -

                Development Toolchains and Compilers

                +

                Known Limitations

                +

                Development Toolchains and Compilers

                • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
                • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
                • STM32CubeIDE toolchain V1.3.0
                -

                Supported Devices and boards

                +

                Supported Devices and boards

                • STM32G431xx, STM32G441xx devices
                • STM32G471xx devices
                  • @@ -265,10 +309,10 @@

                  Supported Devices and boards

                  -

                  Main Changes

                  -

                  Maintenance release

                  +

                  Main Changes

                  +

                  Maintenance release

                  Maintenance release of CMSIS Devices drivers supporting STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, STM32G483xx, STM32G474xx and STM32G484xx devices

                  -

                  Contents

                  +

                  Contents

                  @@ -309,14 +353,14 @@

                  Contents

                  Additional features
                  -

                  Known Limitations

                  -

                  Development Toolchains and Compilers

                  +

                  Known Limitations

                  +

                  Development Toolchains and Compilers

                  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
                  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
                  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
                  -

                  Supported Devices and boards

                  +

                  Supported Devices and boards

                  • STM32G431xx, STM32G441xx devices
                  • STM32G471xx devices
                    • @@ -329,12 +373,12 @@

                    Supported Devices and boards

                    -

                    Main Changes

                    +

                    Main Changes

                    First release

                    First official release for STM32G4xx devices

                    -

                    Contents

                    +

                    Contents

                    CMSIS devices files for STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, STM32G474xx and STM32G484xx.

                    -

                    Known Limitations

                    +

                    Known Limitations

                    @@ -347,13 +391,13 @@

                    Known Limitations

                    -

                    Development Toolchains and Compilers

                    +

                    Development Toolchains and Compilers

                    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
                    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
                    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
                    -

                    Supported Devices and boards

                    +

                    Supported Devices and boards

                    • STM32G431xx, STM32G441xx devices
                    • STM32G471xx devices
                      • diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s index 33974285c9..b0d76a8f11 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s @@ -62,6 +62,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -92,9 +95,6 @@ FillZerobss: LoopFillZerobss: cmp r2, r4 bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +249,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s index 11c3af123a..4951636e6b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s @@ -62,6 +62,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s index b9aa6de6ee..8dfaf51f10 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s @@ -62,6 +62,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s index 3d7d8d69e5..40351c2f5e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s @@ -62,6 +62,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s index a6add31bd0..e7a2c61fcd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s @@ -62,6 +62,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s index 8690d346da..ffae6523fa 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s @@ -62,6 +62,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit + /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +129,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +251,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s index 9ec0f3cfde..f24aeb38be 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s @@ -61,6 +61,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -92,8 +95,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -126,7 +127,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -249,6 +249,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g491xx.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g491xx.s index 64fbb7d2ac..72c8cb22bc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g491xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g491xx.s @@ -62,6 +62,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g4a1xx.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g4a1xx.s index 31794d3d60..8d7d32812f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g4a1xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g4a1xx.s @@ -62,6 +62,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s index 778cb460eb..df603e6ccd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s @@ -61,6 +61,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit @@ -89,8 +92,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit + /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -123,7 +125,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -246,6 +247,8 @@ g_pfnVectors: .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + 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a/system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/mini-st.css b/system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/mini-st_2020.css similarity index 77% rename from system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/mini-st.css rename to system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/mini-st_2020.css index 8cf99b5551..db8b406aa4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/mini-st.css +++ b/system/Drivers/CMSIS/Device/ST/STM32G4xx/_htmresc/mini-st_2020.css @@ -1,39 +1,39 @@ @charset "UTF-8"; /* - Flavor name: Default (mini-default) - Author: Angelos Chalaris (chalarangelo@gmail.com) - Maintainers: Angelos Chalaris - mini.css version: v3.0.0-alpha.3 + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 */ /* Browsers resets and base typography. */ /* Core module CSS variable definitions */ :root { - --fore-color: #111; - --secondary-fore-color: #444; - --back-color: #f8f8f8; - --secondary-back-color: #f0f0f0; - --blockquote-color: #f57c00; - --pre-color: #1565c0; - --border-color: #aaa; - --secondary-border-color: #ddd; - --heading-ratio: 1.19; + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; --universal-margin: 0.5rem; - --universal-padding: 0.125rem; - --universal-border-radius: 0.125rem; - --a-link-color: #0277bd; - --a-visited-color: #01579b; } + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } html { - font-size: 14px; } + font-size: 13.5px; } a, b, del, em, i, ins, q, span, strong, u { font-size: 1em; } html, * { - font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; - line-height: 1.4; + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; -webkit-text-size-adjust: 100%; } * { @@ -42,7 +42,10 @@ html, * { body { margin: 0; color: var(--fore-color); - background: var(--back-color); } + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } details { display: block; } @@ -62,9 +65,9 @@ img { height: auto; } h1, h2, h3, h4, h5, h6 { - line-height: 1.2; + line-height: 1.25; margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 500; } + font-weight: 400; } h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { color: var(--secondary-fore-color); display: block; @@ -74,21 +77,15 @@ h1 { font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); - background: var(--mark-back-color); - font-weight: 600; - padding: 0.1em 0.5em 0.2em 0.5em; - color: var(--mark-fore-color); } - + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } h3 { - font-size: calc(1rem * var(--heading-ratio)); - padding-left: calc(2 * var(--universal-margin)); - /* background: var(--border-color); */ - } + font-size: calc(1rem * var(--heading-ratio) ); } h4 { - font-size: 1rem;); - padding-left: calc(4 * var(--universal-margin)); } + font-size: calc(1rem * var(--heading-ratio)); } h5 { font-size: 1rem; } @@ -101,7 +98,7 @@ p { ol, ul { margin: var(--universal-margin); - padding-left: calc(6 * var(--universal-margin)); } + padding-left: calc(3 * var(--universal-margin)); } b, strong { font-weight: 700; } @@ -111,7 +108,7 @@ hr { border: 0; line-height: 1.25em; margin: var(--universal-margin); - height: 0.0625rem; + height: 0.0714285714rem; background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } blockquote { @@ -121,16 +118,16 @@ blockquote { color: var(--secondary-fore-color); margin: var(--universal-margin); padding: calc(3 * var(--universal-padding)); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.375rem solid var(--blockquote-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } blockquote:before { position: absolute; top: calc(0rem - var(--universal-padding)); left: 0; font-family: sans-serif; - font-size: 3rem; - font-weight: 700; + font-size: 2rem; + font-weight: 800; content: "\201c"; color: var(--blockquote-color); } blockquote[cite]:after { @@ -160,8 +157,8 @@ pre { background: var(--secondary-back-color); padding: calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.25rem solid var(--pre-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } sup, sub, code, kbd { @@ -204,7 +201,8 @@ a { box-sizing: border-box; display: flex; flex: 0 1 auto; - flex-flow: row wrap; } + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } .col-sm, [class^='col-sm-'], @@ -565,9 +563,9 @@ a { order: 999; } } /* Card component CSS variable definitions */ :root { - --card-back-color: #f8f8f8; - --card-fore-color: #111; - --card-border-color: #ddd; } + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } .card { display: flex; @@ -578,7 +576,7 @@ a { width: 100%; background: var(--card-back-color); color: var(--card-fore-color); - border: 0.0625rem solid var(--card-border-color); + border: 0.0714285714rem solid var(--card-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); overflow: hidden; } @@ -592,7 +590,7 @@ a { margin: 0; border: 0; border-radius: 0; - border-bottom: 0.0625rem solid var(--card-border-color); + border-bottom: 0.0714285714rem solid var(--card-border-color); padding: var(--universal-padding); width: 100%; } .card > .sectione.media { @@ -617,17 +615,18 @@ a { width: auto; } .card.warning { -/* --card-back-color: #ffca28; */ --card-back-color: #e5b8b7; - --card-border-color: #e8b825; } + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } .card.error { - --card-back-color: #b71c1c; - --card-fore-color: #f8f8f8; - --card-border-color: #a71a1a; } + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } .card > .sectione.dark { - --card-back-color: #e0e0e0; } + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } .card > .sectione.double-padded { padding: calc(1.5 * var(--universal-padding)); } @@ -637,12 +636,12 @@ a { */ /* Input_control module CSS variable definitions */ :root { - --form-back-color: #f0f0f0; - --form-fore-color: #111; - --form-border-color: #ddd; - --input-back-color: #f8f8f8; - --input-fore-color: #111; - --input-border-color: #ddd; + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; --input-focus-color: #0288d1; --input-invalid-color: #d32f2f; --button-back-color: #e2e2e2; @@ -655,13 +654,13 @@ a { form { background: var(--form-back-color); color: var(--form-fore-color); - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); padding: calc(2 * var(--universal-padding)) var(--universal-padding); } fieldset { - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 4); padding: var(--universal-padding); } @@ -671,7 +670,7 @@ legend { display: table; max-width: 100%; white-space: normal; - font-weight: 700; + font-weight: 500; padding: calc(var(--universal-padding) / 2); } label { @@ -716,7 +715,7 @@ input:not([type]), [type="text"], [type="email"], [type="number"], [type="search box-sizing: border-box; background: var(--input-back-color); color: var(--input-fore-color); - border: 0.0625rem solid var(--input-border-color); + border: 0.0714285714rem solid var(--input-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 2); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } @@ -763,8 +762,8 @@ option { [type="radio"]:checked:before { border-radius: 100%; content: ''; - top: calc(0.0625rem + var(--universal-padding) / 2); - left: calc(0.0625rem + var(--universal-padding) / 2); + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); background: var(--input-fore-color); width: 0.5rem; height: 0.5rem; } @@ -793,7 +792,7 @@ a[role="button"], label[role="button"], [role="button"] { display: inline-block; background: var(--button-back-color); color: var(--button-fore-color); - border: 0.0625rem solid var(--button-border-color); + border: 0.0714285714rem solid var(--button-border-color); border-radius: var(--universal-border-radius); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); @@ -814,7 +813,7 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d .button-group { display: flex; - border: 0.0625rem solid var(--button-group-border-color); + border: 0.0714285714rem solid var(--button-group-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { @@ -826,13 +825,13 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d border-radius: 0; box-shadow: none; } .button-group > :not(:first-child) { - border-left: 0.0625rem solid var(--button-group-border-color); } + border-left: 0.0714285714rem solid var(--button-group-border-color); } @media screen and (max-width: 499px) { .button-group { flex-direction: column; } .button-group > :not(:first-child) { border: 0; - border-top: 0.0625rem solid var(--button-group-border-color); } } + border-top: 0.0714285714rem solid var(--button-group-border-color); } } /* Custom elements for forms and input elements. @@ -874,29 +873,29 @@ button.large, [type="button"].large, [type="submit"].large, [type="reset"].large */ /* Navigation module CSS variable definitions */ :root { - --header-back-color: #f8f8f8; - --header-hover-back-color: #f0f0f0; - --header-fore-color: #444; - --header-border-color: #ddd; - --nav-back-color: #f8f8f8; - --nav-hover-back-color: #f0f0f0; - --nav-fore-color: #444; - --nav-border-color: #ddd; - --nav-link-color: #0277bd; - --footer-fore-color: #444; - --footer-back-color: #f8f8f8; - --footer-border-color: #ddd; - --footer-link-color: #0277bd; - --drawer-back-color: #f8f8f8; - --drawer-hover-back-color: #f0f0f0; - --drawer-border-color: #ddd; - --drawer-close-color: #444; } + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } header { - height: 3.1875rem; + height: 2.75rem; background: var(--header-back-color); color: var(--header-fore-color); - border-bottom: 0.0625rem solid var(--header-border-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); padding: calc(var(--universal-padding) / 4) 0; white-space: nowrap; overflow-x: auto; @@ -927,7 +926,7 @@ header { nav { background: var(--nav-back-color); color: var(--nav-fore-color); - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } nav * { @@ -946,10 +945,10 @@ nav { nav .sublink-1:before { position: absolute; left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } nav .sublink-2 { position: relative; @@ -957,16 +956,16 @@ nav { nav .sublink-2:before { position: absolute; left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } footer { background: var(--footer-back-color); color: var(--footer-fore-color); - border-top: 0.0625rem solid var(--footer-border-color); + border-top: 0.0714285714rem solid var(--footer-border-color); padding: calc(2 * var(--universal-padding)) var(--universal-padding); font-size: 0.875rem; } footer a, footer a:visited { @@ -1013,7 +1012,7 @@ footer.sticky { height: 100vh; overflow-y: auto; background: var(--drawer-back-color); - border: 0.0625rem solid var(--drawer-border-color); + border: 0.0714285714rem solid var(--drawer-border-color); border-radius: 0; margin: 0; z-index: 1110; @@ -1060,38 +1059,36 @@ footer.sticky { */ /* Table module CSS variable definitions. */ :root { - --table-border-color: #aaa; - --table-border-separator-color: #666; - --table-head-back-color: #e6e6e6; - --table-head-fore-color: #111; - --table-body-back-color: #f8f8f8; - --table-body-fore-color: #111; - --table-body-alt-back-color: #eee; } + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } table { border-collapse: separate; border-spacing: 0; - : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + margin: 0; display: flex; flex: 0 1 auto; flex-flow: row wrap; padding: var(--universal-padding); - padding-top: 0; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + padding-top: 0; } table caption { - font-size: 1.25 * rem; + font-size: 1rem; margin: calc(2 * var(--universal-margin)) 0; max-width: 100%; - flex: 0 0 100%; - text-align: left;} + flex: 0 0 100%; } table thead, table tbody { display: flex; flex-flow: row wrap; - border: 0.0625rem solid var(--table-border-color); } + border: 0.0714285714rem solid var(--table-border-color); } table thead { z-index: 999; border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0625rem solid var(--table-border-separator-color); } + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } table tbody { border-top: 0; margin-top: calc(0 - var(--universal-margin)); @@ -1109,11 +1106,11 @@ table { table td { background: var(--table-body-back-color); color: var(--table-body-fore-color); - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table:not(.horizontal) { overflow: auto; - max-height: 850px; } + max-height: 100%; } table:not(.horizontal) thead, table:not(.horizontal) tbody { max-width: 100%; flex: 0 0 100%; } @@ -1134,32 +1131,33 @@ table.horizontal { border: 0; } table.horizontal thead, table.horizontal tbody { border: 0; + flex: .2 0 0; flex-flow: row nowrap; } table.horizontal tbody { overflow: auto; justify-content: space-between; - flex: 1 0 0; - margin-left: calc( 4 * var(--universal-margin)); + flex: .8 0 0; + margin-left: 0; padding-bottom: calc(var(--universal-padding) / 4); } table.horizontal tr { flex-direction: column; flex: 1 0 auto; } table.horizontal th, table.horizontal td { - width: 100%; + width: auto; border: 0; - border-bottom: 0.0625rem solid var(--table-border-color); } + border-bottom: 0.0714285714rem solid var(--table-border-color); } table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { border-top: 0; } table.horizontal th { text-align: right; - border-left: 0.0625rem solid var(--table-border-color); - border-right: 0.0625rem solid var(--table-border-separator-color); } + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } table.horizontal thead tr:first-child { padding-left: 0; } table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td { - border-right: 0.0625rem solid var(--table-border-color); } + border-right: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td:first-child { border-top-right-radius: 0.25rem; } table.horizontal tbody tr:last-child td:last-child { @@ -1191,12 +1189,12 @@ table.horizontal { display: table-row-group; } table tr, table.horizontal tr { display: block; - border: 0.0625rem solid var(--table-border-color); + border: 0.0714285714rem solid var(--table-border-color); border-radius: var(--universal-border-radius); - background: #fafafa; + background: #ffffff; padding: var(--universal-padding); margin: var(--universal-margin); - margin-bottom: calc(2 * var(--universal-margin)); } + margin-bottom: calc(1 * var(--universal-margin)); } table th, table td, table.horizontal th, table.horizontal td { width: auto; } table td, table.horizontal td { @@ -1211,9 +1209,6 @@ table.horizontal { border-top: 0; } table tbody tr:last-child td, table.horizontal tbody tr:last-child td { border-right: 0; } } -:root { - --table-body-alt-back-color: #eee; } - table tr:nth-of-type(2n) > td { background: var(--table-body-alt-back-color); } @@ -1234,8 +1229,8 @@ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focu */ /* Contextual module CSS variable definitions */ :root { - --mark-back-color: #0277bd; - --mark-fore-color: #fafafa; } + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } mark { background: var(--mark-back-color); @@ -1243,11 +1238,11 @@ mark { font-size: 0.95em; line-height: 1em; border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } mark.inline-block { display: inline-block; font-size: 1em; - line-height: 1.5; + line-height: 1.4; padding: calc(var(--universal-padding) / 2) var(--universal-padding); } :root { @@ -1314,8 +1309,8 @@ mark { :root { --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #444; - --modal-close-hover-color: #f0f0f0; } + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } [type="checkbox"].modal { height: 1px; @@ -1368,13 +1363,14 @@ mark { z-index: 1211; } :root { - --collapse-label-back-color: #e8e8e8; - --collapse-label-fore-color: #212121; - --collapse-label-hover-back-color: #f0f0f0; - --collapse-selected-label-back-color: #ececec; - --collapse-border-color: #ddd; - --collapse-content-back-color: #fafafa; - --collapse-selected-label-border-color: #0277bd; } + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } .collapse { width: calc(100% - 2 * var(--universal-margin)); @@ -1395,13 +1391,13 @@ mark { .collapse > label { flex-grow: 1; display: inline-block; - height: 1.5rem; + height: 1.25rem; cursor: pointer; - transition: background 0.3s; + transition: background 0.2s; color: var(--collapse-label-fore-color); background: var(--collapse-label-back-color); - border: 0.0625rem solid var(--collapse-border-color); - padding: calc(1.5 * var(--universal-padding)); } + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } .collapse > label:hover, .collapse > label:focus { background: var(--collapse-label-hover-back-color); } .collapse > label + div { @@ -1418,7 +1414,7 @@ mark { max-height: 1px; } .collapse > :checked + label { background: var(--collapse-selected-label-back-color); - border-bottom-color: var(--collapse-selected-label-border-color); } + border-color: var(--collapse-selected-label-border-color); } .collapse > :checked + label + div { box-sizing: border-box; position: relative; @@ -1427,13 +1423,13 @@ mark { overflow: auto; margin: 0; background: var(--collapse-content-back-color); - border: 0.0625rem solid var(--collapse-border-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); border-top: 0; padding: var(--universal-padding); clip: auto; -webkit-clip-path: inset(0%); clip-path: inset(0%); - max-height: 850px; } + max-height: 100%; } .collapse > label:not(:first-of-type) { border-top: 0; } .collapse > label:first-of-type { @@ -1450,11 +1446,8 @@ mark { /* Custom elements for contextual background elements, toasts and tooltips. */ -mark.secondary { - --mark-back-color: #d32f2f; } - mark.tertiary { - --mark-back-color: #308732; } + --mark-back-color: #3cb4e6; } mark.tag { padding: calc(var(--universal-padding)/2) var(--universal-padding); @@ -1465,7 +1458,7 @@ mark.tag { */ /* Progress module CSS variable definitions */ :root { - --progress-back-color: #ddd; + --progress-back-color: #3cb4e6; --progress-fore-color: #555; } progress { @@ -1558,45 +1551,53 @@ span[class^='icon-'] { filter: invert(100%); } span.icon-alert { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } span.icon-bookmark { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-calendar { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-credit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-edit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } span.icon-link { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } span.icon-help { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } span.icon-home { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-info { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } span.icon-lock { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } span.icon-mail { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-location { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-phone { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-rss { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-search { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } span.icon-settings { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-share { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } span.icon-cart { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } span.icon-upload { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } /* Definitions for utilities and helper classes. @@ -1604,7 +1605,7 @@ span.icon-user { /* Utility module CSS variable definitions */ :root { --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } .hidden { display: none !important; } @@ -1622,7 +1623,7 @@ span.icon-user { overflow: hidden !important; } .bordered { - border: 0.0625rem solid var(--generic-border-color) !important; } + border: 0.0714285714rem solid var(--generic-border-color) !important; } .rounded { border-radius: var(--universal-border-radius) !important; } @@ -1697,4 +1698,14 @@ span.icon-user { clip-path: inset(100%) !important; overflow: hidden !important; } } -/*# sourceMappingURL=mini-default.css.map */ +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git 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zw7ER9v~DyrC*R$do9aEw5r@B)YzHOLB^-c9Eu9D!sFmI8^VljVKE89{zY_8PTSF+J b^}%0^qYmp2WD(pA|JtZ4>nPPKybJpu3@X?! literal 0 HcmV?d00001 diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 6a5af926c1..c196d1b070 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -8,7 +8,7 @@ * STM32F4: 2.6.9 * STM32F7: 1.2.8 * STM32G0: 1.4.4 - * STM32G4: 1.2.2 + * STM32G4: 1.2.3 * STM32H5: 1.1.0 * STM32H7: 1.10.3 * STM32L0: 1.9.3 From 72f8bd29dab09ea2833733e4791b0181ae1705bc Mon Sep 17 00:00:00 2001 From: Simran <23563486+Khelicon@users.noreply.github.com> Date: Thu, 4 Jan 2024 04:24:08 -0500 Subject: [PATCH 68/83] Update README.md (#2238) doc(README); update AGAFIA board URL Co-authored-by: Frederic Pillon --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 516b847f7c..4b4e410562 100644 --- a/README.md +++ b/README.md @@ -417,7 +417,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32G030C6
                      STM32G030C8 | Generic Board | *2.2.0* | | :green_heart: | STM32G030F6
                      STM32G030F6 | Generic Board | *2.2.0* | | :green_heart: | STM32G030K8 | Aurora One | *2.0.0* | -| :green_heart: | STM32G071CB | [AGAFIA SG0](https://www.sigmaic.com/store/p7/agafia-sgo.html) | *2.3.0* | +| :green_heart: | STM32G071CB | [AGAFIA SG0](https://www.sigmaic.com) | *2.3.0* | | :green_heart: | STM32G030J6 | Generic Board | *2.4.0* | | | :green_heart: | STM32G030K6
                      STM32G030K8 | Generic Board | *2.0.0* | | | :green_heart: | STM32G031C4
                      STM32G031C6
                      STM32G031C8 | Generic Board | *2.4.0* | | From 8cf5250c40f72cfd7fa83d65553f185e349b813e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 4 Jan 2024 11:01:02 +0100 Subject: [PATCH 69/83] fix(stm32variant): wrong regex for db release Signed-off-by: Frederic Pillon --- CI/update/stm32variant.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index b245fc3719..596ece9add 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -2621,7 +2621,7 @@ def manage_repo(): db_release = item.attributes["Release"].value # Process DB release -release_regex = r".*(\d+.\d+.\d+)$" +release_regex = r".*(\d+\.\d+\.\d+)$" release_match = re.match(release_regex, db_release) if release_match: db_release = release_match.group(1) From 84f54a075a91313c611cd6d26a6d078c086e5047 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 4 Jan 2024 14:09:49 +0100 Subject: [PATCH 70/83] variants: update generated files to STM32_open_pin_data v6.0.100 Signed-off-by: Frederic Pillon --- boards.txt | 14 +- .../PeripheralPins.c | 2 +- .../STM32C0xx/C011J(4-6)M/PeripheralPins.c | 2 +- .../C031C(4-6)(T-U)/PeripheralPins.c | 2 +- .../STM32C0xx/C031G(4-6)U/PeripheralPins.c | 2 +- .../C031K(4-6)(T-U)/PeripheralPins.c | 2 +- variants/STM32F0xx/F030C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030C8T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030CCT/PeripheralPins.c | 2 +- variants/STM32F0xx/F030F4P/PeripheralPins.c | 2 +- variants/STM32F0xx/F030K6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030R8T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030RCT/PeripheralPins.c | 2 +- .../STM32F0xx/F031C(4-6)T/PeripheralPins.c | 2 +- .../F031E6Y_F038E6Y/PeripheralPins.c | 2 +- .../STM32F0xx/F031F(4-6)P/PeripheralPins.c | 2 +- .../STM32F0xx/F031G(4-6)U/PeripheralPins.c | 2 +- .../STM32F0xx/F031K(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F031K6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F038C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F038F6P/PeripheralPins.c | 2 +- variants/STM32F0xx/F038G6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F038K6U/PeripheralPins.c | 2 +- .../F042C(4-6)(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F042F(4-6)P/PeripheralPins.c | 2 +- .../STM32F0xx/F042G(4-6)U/PeripheralPins.c | 2 +- .../STM32F0xx/F042K(4-6)T/PeripheralPins.c | 2 +- .../STM32F0xx/F042K(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F042T6Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F048C6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F048G6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F048T6Y/PeripheralPins.c | 2 +- .../STM32F0xx/F051C4(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F051C6(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F051C8(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F051K(6-8)T/PeripheralPins.c | 2 +- .../STM32F0xx/F051K(6-8)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K4T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K4U/PeripheralPins.c | 2 +- variants/STM32F0xx/F051R4T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051R6T/PeripheralPins.c | 2 +- .../STM32F0xx/F051R8(H-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F051T8Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F058C8U/PeripheralPins.c | 2 +- .../STM32F0xx/F058R8(H-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F058T8Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F070C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F070CBT/PeripheralPins.c | 2 +- variants/STM32F0xx/F070F6P/PeripheralPins.c | 2 +- variants/STM32F0xx/F070RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32F0xx/F071RBT/PeripheralPins.c | 2 +- .../F071V(8-B)(H-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F072R8T_F072RB(H-I-T)/PeripheralPins.c | 2 +- .../F072V(8-B)(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c | 2 +- .../STM32F0xx/F078RB(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F078VB(H-T)/PeripheralPins.c | 2 +- .../F091C(B-C)(T-U)/PeripheralPins.c | 2 +- .../F091RBT_F091RC(H-T-Y)/PeripheralPins.c | 2 +- .../F091VBT_F091VC(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F098CC(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c | 2 +- .../STM32F0xx/F098VC(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F100C(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100C(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(4-6)H/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(8-B)H/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100V(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100V(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101C(4-6)T/PeripheralPins.c | 2 +- .../F101C(8-B)(T-U)/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(F-G)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101RBH/PeripheralPins.c | 2 +- .../STM32F1xx/F101T(4-6)U/PeripheralPins.c | 2 +- .../STM32F1xx/F101T(8-B)U/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(F-G)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101Z(F-G)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102C(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102C(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102R(8-B)T/PeripheralPins.c | 2 +- .../F103C4T_F103C6(T-U)/PeripheralPins.c | 2 +- .../F103C8T_F103CB(T-U)/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(4-6)H/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(8-B)H/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(F-G)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103T(4-6)U/PeripheralPins.c | 2 +- .../STM32F1xx/F103T(8-B)U/PeripheralPins.c | 2 +- .../F103V(C-D-E)(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F103V(F-G)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F103Z(C-D-E)(H-T)/PeripheralPins.c | 2 +- .../F103Z(F-G)(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F105R(8-B-C)T/PeripheralPins.c | 2 +- .../F105V(8-B)(H-T)_F105VCT/PeripheralPins.c | 2 +- .../STM32F1xx/F107R(B-C)T/PeripheralPins.c | 2 +- .../F107VBT_F107VC(H-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F301C6T_F301C8(T-Y)/PeripheralPins.c | 2 +- .../STM32F3xx/F301K(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F301K(6-8)U/PeripheralPins.c | 2 +- .../STM32F3xx/F301R(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302C(B-C)T/PeripheralPins.c | 2 +- .../F302C6T_F302C8(T-Y)/PeripheralPins.c | 2 +- .../STM32F3xx/F302K(6-8)U/PeripheralPins.c | 2 +- .../STM32F3xx/F302R(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302R(B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302R(D-E)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302V(B-C)T/PeripheralPins.c | 2 +- .../F302V(D-E)(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F302VCY/PeripheralPins.c | 2 +- .../STM32F3xx/F302Z(D-E)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32F3xx/F303C(B-C)T/PeripheralPins.c | 2 +- .../F303C8Y_F334C8Y/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F303R(6-8)T_F334R(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F303R(B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F303R(D-E)T/PeripheralPins.c | 2 +- .../STM32F3xx/F303V(B-C)T/PeripheralPins.c | 2 +- .../F303V(D-E)(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F303VCY/PeripheralPins.c | 2 +- variants/STM32F3xx/F303VEY/PeripheralPins.c | 2 +- .../STM32F3xx/F303Z(D-E)T/PeripheralPins.c | 2 +- .../STM32F3xx/F318C8(T-Y)/PeripheralPins.c | 2 +- variants/STM32F3xx/F318K8U/PeripheralPins.c | 2 +- variants/STM32F3xx/F328C8T/PeripheralPins.c | 2 +- variants/STM32F3xx/F358CCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F358RCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F358VCT/PeripheralPins.c | 2 +- .../STM32F3xx/F373C(8-B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F373R(8-B-C)T/PeripheralPins.c | 2 +- .../F373V(8-B-C)(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F378CCT/PeripheralPins.c | 2 +- .../STM32F3xx/F378RC(T-Y)/PeripheralPins.c | 2 +- .../STM32F3xx/F378VC(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F398VET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F401R(B-C-D-E)T/PeripheralPins.c | 2 +- .../F401V(B-C-D-E)H/PeripheralPins.c | 2 +- .../F401V(B-C-D-E)T/PeripheralPins.c | 2 +- .../F405O(E-G)Y_F415OGY/PeripheralPins.c | 2 +- .../F405RGT_F415RGT/PeripheralPins.c | 2 +- .../F405VGT_F415VGT/PeripheralPins.c | 2 +- .../F405ZGT_F415ZGT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F407V(E-G)T_F417V(E-G)T/PeripheralPins.c | 2 +- .../F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c | 2 +- .../STM32F4xx/F410C(8-B)T/PeripheralPins.c | 2 +- .../STM32F4xx/F410C(8-B)U/PeripheralPins.c | 2 +- .../F410R(8-B)(I-T)/PeripheralPins.c | 2 +- .../STM32F4xx/F410T(8-B)Y/PeripheralPins.c | 2 +- .../F411C(C-E)(U-Y)/PeripheralPins.c | 2 +- .../STM32F4xx/F411R(C-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F411V(C-E)H/PeripheralPins.c | 2 +- .../STM32F4xx/F411V(C-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F412C(E-G)U/PeripheralPins.c | 2 +- .../F412R(E-G)(T-Y)x(P)/PeripheralPins.c | 2 +- .../STM32F4xx/F412V(E-G)H/PeripheralPins.c | 2 +- .../STM32F4xx/F412V(E-G)T/PeripheralPins.c | 2 +- .../F412Z(E-G)(J-T)/PeripheralPins.c | 2 +- .../F413C(G-H)U_F423CHU/PeripheralPins.c | 2 +- .../F413M(G-H)Y_F423MHY/PeripheralPins.c | 2 +- .../F413R(G-H)T_F423RHT/PeripheralPins.c | 2 +- .../F413V(G-H)H_F423VHH/PeripheralPins.c | 2 +- .../F413V(G-H)T_F423VHT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32F4xx/F446M(C-E)Y/PeripheralPins.c | 2 +- .../STM32F4xx/F446R(C-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F446V(C-E)T/PeripheralPins.c | 2 +- .../F446Z(C-E)(H-J-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F722Z(C-E)T_F732ZET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F769I(G-I)T_F779IIT/PeripheralPins.c | 2 +- .../STM32G0xx/G030C(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G030F6P/PeripheralPins.c | 2 +- variants/STM32G0xx/G030J6M/PeripheralPins.c | 2 +- .../STM32G0xx/G030K(6-8)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G031J(4-6)M_G041J6M/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32G0xx/G050C(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G050F6P/PeripheralPins.c | 2 +- .../STM32G0xx/G050K(6-8)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G051G(6-8)U_G061G(6-8)U/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32G0xx/G070CBT/PeripheralPins.c | 2 +- variants/STM32G0xx/G070KBT/PeripheralPins.c | 2 +- variants/STM32G0xx/G070RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G071EBY_G081EBY/PeripheralPins.c | 2 +- .../G071G(6-8-B)U_G081GBU/PeripheralPins.c | 2 +- .../G071G(8-B)UxN_G081GBUxN/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0CET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0KET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0RET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0VET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G0B1NEY_G0C1NEY/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G431C(6-8-B)T_G441CBT/PeripheralPins.c | 2 +- .../G431C(6-8-B)U_G441CBU/PeripheralPins.c | 2 +- .../G431CBY_G441CBY/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G431M(6-8-B)T_G441MBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G431V(6-8-B)T_G441VBT/PeripheralPins.c | 2 +- .../STM32G4xx/G471C(C-E)T/PeripheralPins.c | 2 +- .../STM32G4xx/G471C(C-E)U/PeripheralPins.c | 2 +- .../STM32G4xx/G471M(C-E)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G471MEY/PeripheralPins.c | 2 +- .../STM32G4xx/G471Q(C-E)T/PeripheralPins.c | 2 +- .../STM32G4xx/G471R(C-E)T/PeripheralPins.c | 2 +- .../G471V(C-E)(H-I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G491C(C-E)T_G4A1CET/PeripheralPins.c | 2 +- .../G491C(C-E)U_G4A1CEU/PeripheralPins.c | 2 +- .../G491K(C-E)U_G4A1KEU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G491V(C-E)T_G4A1VET/PeripheralPins.c | 2 +- .../STM32H5xx/H503CB(T-U)/PeripheralPins.c | 2 +- variants/STM32H5xx/H503EBY/PeripheralPins.c | 2 +- variants/STM32H5xx/H503KBU/PeripheralPins.c | 2 +- variants/STM32H5xx/H503RBT/PeripheralPins.c | 2 +- .../STM32H5xx/H562A(G-I)I/PeripheralPins.c | 2 +- .../H562I(G-I)(K-T)/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)V/PeripheralPins.c | 2 +- .../STM32H5xx/H562V(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562Z(G-I)T/PeripheralPins.c | 2 +- variants/STM32H5xx/H563A(G-I)I/CMakeLists.txt | 31 - .../PeripheralPins.c | 3 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 12 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 variants/STM32H5xx/H563AIIxQ/CMakeLists.txt | 31 - .../PeripheralPins.c | 4 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 10 +- .../generic_clock.c | 2 +- .../variant_generic.cpp | 2 +- .../variant_generic.h | 0 .../STM32H5xx/H563I(G-I)(K-T)/CMakeLists.txt | 31 - .../PeripheralPins.c | 3 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 24 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 variants/STM32H5xx/H563IIKxQ/CMakeLists.txt | 31 - variants/STM32H5xx/H563IIKxQ/generic_clock.c | 90 -- .../STM32H5xx/H563IIKxQ/variant_generic.cpp | 183 ---- .../PeripheralPins.c | 4 +- .../PeripheralPins_STM32H573I_DK.c | 0 .../PinNamesVar.h | 0 .../boards_entry.txt | 10 +- .../generic_clock.c | 2 +- .../ldscript.ld | 0 .../variant_STM32H573I_DK.cpp | 0 .../variant_STM32H573I_DK.h | 0 .../variant_generic.cpp | 2 +- .../variant_generic.h | 0 variants/STM32H5xx/H563IITxQ/CMakeLists.txt | 31 - .../STM32H5xx/H563IITxQ/variant_generic.cpp | 180 ---- .../PeripheralPins.c | 4 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 10 +- .../generic_clock.c | 2 +- .../variant_generic.cpp | 2 +- .../variant_generic.h | 0 variants/STM32H5xx/H563MIYxQ/CMakeLists.txt | 31 - .../STM32H5xx/H563MIYxQ/variant_generic.cpp | 97 -- .../PeripheralPins.c | 4 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 10 +- .../generic_clock.c | 2 +- .../variant_generic.cpp | 2 +- .../variant_generic.h | 0 variants/STM32H5xx/H563R(G-I)T/CMakeLists.txt | 31 - .../PeripheralPins.c | 3 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 12 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 variants/STM32H5xx/H563R(G-I)V/CMakeLists.txt | 31 - .../PeripheralPins.c | 3 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 12 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 variants/STM32H5xx/H563V(G-I)T/CMakeLists.txt | 31 - .../PeripheralPins.c | 3 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 12 +- .../generic_clock.c | 3 +- .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 .../H563VITxQ_H573VITxQ/PeripheralPins.c | 2 +- variants/STM32H5xx/H563Z(G-I)T/CMakeLists.txt | 32 - .../PeripheralPins.c | 3 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 12 +- .../generic_clock.c | 3 +- .../ldscript.ld | 0 .../variant_NUCLEO_H563ZI.cpp | 0 .../variant_NUCLEO_H563ZI.h | 0 .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 .../H563ZITxQ_H573ZITxQ/PeripheralPins.c | 2 +- variants/STM32H5xx/H573AII/CMakeLists.txt | 31 - variants/STM32H5xx/H573AII/PeripheralPins.c | 829 ----------------- variants/STM32H5xx/H573AII/PinNamesVar.h | 98 -- variants/STM32H5xx/H573AII/boards_entry.txt | 13 - variants/STM32H5xx/H573AII/generic_clock.c | 27 - .../STM32H5xx/H573AII/variant_generic.cpp | 180 ---- variants/STM32H5xx/H573AII/variant_generic.h | 328 ------- variants/STM32H5xx/H573AIIxQ/CMakeLists.txt | 31 - variants/STM32H5xx/H573AIIxQ/PeripheralPins.c | 818 ----------------- variants/STM32H5xx/H573AIIxQ/PinNamesVar.h | 99 --- variants/STM32H5xx/H573AIIxQ/boards_entry.txt | 13 - variants/STM32H5xx/H573AIIxQ/generic_clock.c | 27 - .../STM32H5xx/H573AIIxQ/variant_generic.cpp | 178 ---- .../STM32H5xx/H573AIIxQ/variant_generic.h | 327 ------- variants/STM32H5xx/H573II(K-T)/CMakeLists.txt | 31 - .../STM32H5xx/H573II(K-T)/PeripheralPins.c | 838 ------------------ variants/STM32H5xx/H573II(K-T)/PinNamesVar.h | 100 --- .../STM32H5xx/H573II(K-T)/boards_entry.txt | 21 - .../STM32H5xx/H573II(K-T)/generic_clock.c | 27 - .../STM32H5xx/H573II(K-T)/variant_generic.cpp | 184 ---- .../STM32H5xx/H573II(K-T)/variant_generic.h | 334 ------- variants/STM32H5xx/H573IIKxQ/CMakeLists.txt | 33 - variants/STM32H5xx/H573IIKxQ/PeripheralPins.c | 836 ----------------- variants/STM32H5xx/H573IIKxQ/PinNamesVar.h | 100 --- variants/STM32H5xx/H573IIKxQ/boards_entry.txt | 13 - variants/STM32H5xx/H573IIKxQ/ldscript.ld | 185 ---- .../STM32H5xx/H573IIKxQ/variant_generic.h | 333 ------- variants/STM32H5xx/H573IITxQ/CMakeLists.txt | 31 - variants/STM32H5xx/H573IITxQ/PeripheralPins.c | 830 ----------------- variants/STM32H5xx/H573IITxQ/PinNamesVar.h | 99 --- variants/STM32H5xx/H573IITxQ/boards_entry.txt | 13 - variants/STM32H5xx/H573IITxQ/generic_clock.c | 27 - .../STM32H5xx/H573IITxQ/variant_generic.h | 329 ------- variants/STM32H5xx/H573MIYxQ/CMakeLists.txt | 31 - variants/STM32H5xx/H573MIYxQ/PeripheralPins.c | 605 ------------- variants/STM32H5xx/H573MIYxQ/PinNamesVar.h | 84 -- variants/STM32H5xx/H573MIYxQ/boards_entry.txt | 13 - variants/STM32H5xx/H573MIYxQ/generic_clock.c | 27 - .../STM32H5xx/H573MIYxQ/variant_generic.h | 238 ----- variants/STM32H5xx/H573RIT/CMakeLists.txt | 31 - variants/STM32H5xx/H573RIT/PeripheralPins.c | 578 ------------ variants/STM32H5xx/H573RIT/PinNamesVar.h | 84 -- variants/STM32H5xx/H573RIT/boards_entry.txt | 13 - variants/STM32H5xx/H573RIT/generic_clock.c | 27 - .../STM32H5xx/H573RIT/variant_generic.cpp | 89 -- variants/STM32H5xx/H573RIT/variant_generic.h | 230 ----- variants/STM32H5xx/H573RIV/CMakeLists.txt | 31 - variants/STM32H5xx/H573RIV/PeripheralPins.c | 612 ------------- variants/STM32H5xx/H573RIV/PinNamesVar.h | 85 -- variants/STM32H5xx/H573RIV/boards_entry.txt | 13 - variants/STM32H5xx/H573RIV/generic_clock.c | 27 - .../STM32H5xx/H573RIV/variant_generic.cpp | 93 -- variants/STM32H5xx/H573RIV/variant_generic.h | 232 ----- variants/STM32H5xx/H573VIT/CMakeLists.txt | 31 - variants/STM32H5xx/H573VIT/PeripheralPins.c | 683 -------------- variants/STM32H5xx/H573VIT/PinNamesVar.h | 85 -- variants/STM32H5xx/H573VIT/boards_entry.txt | 13 - variants/STM32H5xx/H573VIT/generic_clock.c | 27 - .../STM32H5xx/H573VIT/variant_generic.cpp | 120 --- variants/STM32H5xx/H573VIT/variant_generic.h | 259 ------ variants/STM32H5xx/H573ZIT/CMakeLists.txt | 31 - variants/STM32H5xx/H573ZIT/PeripheralPins.c | 774 ---------------- variants/STM32H5xx/H573ZIT/PinNamesVar.h | 88 -- variants/STM32H5xx/H573ZIT/boards_entry.txt | 13 - variants/STM32H5xx/H573ZIT/generic_clock.c | 89 -- variants/STM32H5xx/H573ZIT/ldscript.ld | 185 ---- .../STM32H5xx/H573ZIT/variant_generic.cpp | 156 ---- variants/STM32H5xx/H573ZIT/variant_generic.h | 294 ------ .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H725R(E-G)V_H735RGV/PeripheralPins.c | 2 +- .../H725V(E-G)H_H735VGH/PeripheralPins.c | 2 +- .../H725V(E-G)T_H735VGT/PeripheralPins.c | 2 +- .../H725VGY_H735VGY/PeripheralPins.c | 2 +- .../H725Z(E-G)T_H735ZGT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H745B(G-I)T_H755BIT/PeripheralPins.c | 2 +- .../H745I(G-I)K_H755IIK/PeripheralPins.c | 2 +- .../H745I(G-I)T_H755IIT/PeripheralPins.c | 2 +- .../H745Z(G-I)T_H755ZIT/PeripheralPins.c | 2 +- .../H747B(G-I)T_H757BIT/PeripheralPins.c | 2 +- .../H747ZIY_H757ZIY/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c | 2 +- .../H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c | 2 +- .../H7A3N(G-I)H_H7B3NIH/PeripheralPins.c | 2 +- .../H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c | 2 +- .../H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c | 2 +- variants/STM32L0xx/L010C6T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L0xx/L010K8T/PeripheralPins.c | 2 +- variants/STM32L0xx/L010R8T/PeripheralPins.c | 2 +- variants/STM32L0xx/L010RBT/PeripheralPins.c | 2 +- .../L011D(3-4)P_L021D4P/PeripheralPins.c | 2 +- .../STM32L0xx/L011E(3-4)Y/PeripheralPins.c | 2 +- .../L011F(3-4)U_L021F4U/PeripheralPins.c | 2 +- .../L011G(3-4)U_L021G4U/PeripheralPins.c | 2 +- .../L011K(3-4)U_L021K4U/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L031E(4-6)Y_L041E6Y/PeripheralPins.c | 2 +- .../L031F(4-6)P_L041F6P/PeripheralPins.c | 2 +- .../L031G(4-6)U_L041G6U/PeripheralPins.c | 2 +- .../L031G6UxS_L041G6UxS/PeripheralPins.c | 2 +- .../L031K(4-6)T_L041K6T/PeripheralPins.c | 2 +- .../L031K(4-6)U_L041K6U/PeripheralPins.c | 2 +- .../L051C(6-8)(T-U)/PeripheralPins.c | 2 +- .../STM32L0xx/L051K(6-8)T/PeripheralPins.c | 2 +- .../STM32L0xx/L051K(6-8)U/PeripheralPins.c | 2 +- .../STM32L0xx/L051R(6-8)H/PeripheralPins.c | 2 +- .../STM32L0xx/L051R(6-8)T/PeripheralPins.c | 2 +- .../STM32L0xx/L051T(6-8)Y/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L052K(6-8)T_L062K8T/PeripheralPins.c | 2 +- .../L052K(6-8)U_L062K8U/PeripheralPins.c | 2 +- .../L052R(6-8)H_L053R(6-8)H/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L052T6Y_L052T8(F-Y)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L0xx/L071C(B-Z)Y/PeripheralPins.c | 2 +- .../L071K(8-B-Z)U_L081KZU/PeripheralPins.c | 2 +- .../L071K(B-Z)T_L081KZT/PeripheralPins.c | 2 +- .../STM32L0xx/L071R(B-Z)H/PeripheralPins.c | 2 +- .../STM32L0xx/L071R(B-Z)T/PeripheralPins.c | 2 +- .../L071V(8-B-Z)(I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c | 2 +- .../L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L1xx/L100RCT/PeripheralPins.c | 2 +- .../L151CC(T-U)_L152CC(T-U)/PeripheralPins.c | 2 +- .../L151QCH_L152QCH_L162QCH/PeripheralPins.c | 2 +- .../L151QDH_L152QDH_L162QDH/PeripheralPins.c | 2 +- .../L151QEH_L152QEH/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L151RET_L152RET_L162RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L151VDT_L152VDT_L162VDT/PeripheralPins.c | 2 +- .../L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c | 2 +- .../L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c | 2 +- .../L151ZET_L152ZET_L162ZET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L4xx/L412CB(T-U)xP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L4xx/L412RB(I-T)xP/PeripheralPins.c | 2 +- .../L412T(8-B)Y_L422TBY/PeripheralPins.c | 2 +- variants/STM32L4xx/L412TBYxP/PeripheralPins.c | 2 +- .../L431C(B-C)(T-U)/PeripheralPins.c | 2 +- .../STM32L4xx/L431C(B-C)Y/PeripheralPins.c | 2 +- .../STM32L4xx/L431K(B-C)U/PeripheralPins.c | 2 +- .../L431R(B-C)(I-T-Y)/PeripheralPins.c | 2 +- .../STM32L4xx/L431VC(I-T)/PeripheralPins.c | 2 +- .../L432K(B-C)U_L442KCU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L433RCTxP/PeripheralPins.c | 2 +- .../L433VC(I-T)_L443VC(I-T)/PeripheralPins.c | 2 +- .../L451CCU_L451CE(T-U)/PeripheralPins.c | 2 +- .../L451R(C-E)(I-T-Y)/PeripheralPins.c | 2 +- .../L451V(C-E)(I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L452RETxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L4xx/L471Q(E-G)I/PeripheralPins.c | 2 +- .../STM32L4xx/L471R(E-G)T/PeripheralPins.c | 2 +- .../STM32L4xx/L471V(E-G)T/PeripheralPins.c | 2 +- .../L471Z(E-G)(J-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L476JGYxP/PeripheralPins.c | 2 +- .../STM32L4xx/L476M(E-G)Y/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L476VGYxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L476ZGTxP/PeripheralPins.c | 2 +- .../L496A(E-G)I_L4A6AGI/PeripheralPins.c | 2 +- .../L496AGIxP_L4A6AGIxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L496QGIxP_L4A6QGIxP/PeripheralPins.c | 2 +- .../L496R(E-G)T_L4A6RGT/PeripheralPins.c | 2 +- variants/STM32L4xx/L496RGTxP/PeripheralPins.c | 2 +- .../L496V(E-G)T_L4A6VGT/PeripheralPins.c | 2 +- .../L496VGTxP_L4A6VGTxP/PeripheralPins.c | 2 +- .../L496VGY_L4A6VGY/PeripheralPins.c | 2 +- .../L496VGYxP_L4A6VGYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496WGYxP/PeripheralPins.c | 2 +- .../L496Z(E-G)T_L4A6ZGT/PeripheralPins.c | 2 +- .../L496ZGTxP_L4A6ZGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c | 2 +- .../L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c | 2 +- .../L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c | 2 +- .../L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c | 2 +- .../L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c | 2 +- .../L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c | 2 +- .../L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c | 2 +- .../L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c | 2 +- .../L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c | 2 +- .../L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c | 2 +- .../L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c | 2 +- .../L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c | 2 +- .../L4R9A(G-I)I_L4S9AII/PeripheralPins.c | 2 +- .../L4R9V(G-I)T_L4S9VIT/PeripheralPins.c | 2 +- .../L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c | 2 +- .../L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c | 2 +- variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L552MEYxP_L562MEYxP/PeripheralPins.c | 2 +- .../L552MEYxQ_L562MEYxQ/PeripheralPins.c | 2 +- .../L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c | 2 +- .../L552QEI_L562QEI/PeripheralPins.c | 2 +- .../L552QEIxP_L562QEIxP/PeripheralPins.c | 2 +- .../L552R(C-E)T_L562RET/PeripheralPins.c | 2 +- .../L552RETxP_L562RETxP/PeripheralPins.c | 2 +- .../L552RETxQ_L562RETxQ/PeripheralPins.c | 2 +- .../L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c | 2 +- .../L552VET_L562VET/PeripheralPins.c | 2 +- .../L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c | 2 +- .../L552ZET_L562ZET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535JEYxQ_U545JEYxQ/PeripheralPins.c | 2 +- .../U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c | 2 +- .../U535R(B-C-E)I_U545REI/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535R(B-C-E)T_U545RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535V(C-E)I_U545VEI/PeripheralPins.c | 2 +- .../U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c | 2 +- .../U535V(C-E)T_U545VET/PeripheralPins.c | 2 +- .../U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c | 2 +- .../U575A(G-I)I_U585AII/PeripheralPins.c | 2 +- .../U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c | 2 +- .../U575Q(G-I)I_U585QII/PeripheralPins.c | 2 +- .../U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c | 2 +- .../U575R(G-I)T_U585RIT/PeripheralPins.c | 2 +- .../U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c | 2 +- .../U575V(G-I)T_U585VIT/PeripheralPins.c | 2 +- .../U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c | 2 +- .../U575Z(G-I)T_U585ZIT/PeripheralPins.c | 2 +- .../U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c | 2 +- .../U595A(I-J)H_U5A5AJH/PeripheralPins.c | 2 +- .../U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c | 2 +- .../U595Q(I-J)I_U5A5QJI/PeripheralPins.c | 2 +- .../PeripheralPins.c | 4 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 14 +- .../generic_clock.c | 2 +- .../variant_generic.cpp | 2 +- .../variant_generic.h | 0 .../U595Q(I-J)IxQ_U5A5QJIxQ/CMakeLists.txt | 31 - .../U595R(I-J)T_U5A5RJT/PeripheralPins.c | 2 +- .../U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595Z(I-J)T_U5A5ZJT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c | 2 +- .../U599BJYxQ_U5A9BJYxQ/PeripheralPins.c | 2 +- .../U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c | 2 +- .../U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c | 2 +- .../U5F7V(I-J)T_U5G7VJT/PeripheralPins.c | 3 +- .../U5F7V(I-J)T_U5G7VJT/PinNamesVar.h | 7 +- .../U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c | 3 +- .../U5F7V(I-J)TxQ_U5G7VJTxQ/PinNamesVar.h | 7 +- .../U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c | 3 +- .../U5F9BJYxQ_U5G9BJYxQ/PinNamesVar.h | 7 +- .../U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c | 3 +- .../U5F9NJHxQ_U5G9NJHxQ/PinNamesVar.h | 7 +- .../U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c | 3 +- .../U5F9V(I-J)TxQ_U5G9VJTxQ/PinNamesVar.h | 7 +- .../U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c | 3 +- .../U5F9Z(I-J)JxQ_U5G9ZJJxQ/PinNamesVar.h | 7 +- .../U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c | 3 +- .../U5F9Z(I-J)TxQ_U5G9ZJTxQ/PinNamesVar.h | 7 +- variants/STM32WBxx/WB10CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCUxE/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCY/PeripheralPins.c | 2 +- variants/STM32WBxx/WB1MMCH/PeripheralPins.c | 2 +- .../WB30CEUxA_WB50CGU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32WBxx/WB5MMGH/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32WLxx/WL5MOCH/PeripheralPins.c | 2 +- 716 files changed, 781 insertions(+), 14871 deletions(-) delete mode 100644 variants/STM32H5xx/H563A(G-I)I/CMakeLists.txt rename variants/STM32H5xx/{H563A(G-I)I => H563A(G-I)I_H573AII}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H563A(G-I)I => H563A(G-I)I_H573AII}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563A(G-I)I => H563A(G-I)I_H573AII}/boards_entry.txt (70%) rename variants/STM32H5xx/{H563A(G-I)I => H563A(G-I)I_H573AII}/generic_clock.c (94%) rename variants/STM32H5xx/{H563A(G-I)I => H563A(G-I)I_H573AII}/variant_generic.cpp (98%) rename variants/STM32H5xx/{H563A(G-I)I => H563A(G-I)I_H573AII}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H563AIIxQ/CMakeLists.txt rename variants/STM32H5xx/{H563AIIxQ => H563AIIxQ_H573AIIxQ}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H563AIIxQ => H563AIIxQ_H573AIIxQ}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563AIIxQ => H563AIIxQ_H573AIIxQ}/boards_entry.txt (59%) rename variants/STM32H5xx/{H563IITxQ => H563AIIxQ_H573AIIxQ}/generic_clock.c (91%) rename variants/STM32H5xx/{H563AIIxQ => H563AIIxQ_H573AIIxQ}/variant_generic.cpp (97%) rename variants/STM32H5xx/{H563AIIxQ => H563AIIxQ_H573AIIxQ}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H563I(G-I)(K-T)/CMakeLists.txt rename variants/STM32H5xx/{H563I(G-I)(K-T) => H563I(G-I)(K-T)_H573II(K-T)}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H563I(G-I)(K-T) => H563I(G-I)(K-T)_H573II(K-T)}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563I(G-I)(K-T) => H563I(G-I)(K-T)_H573II(K-T)}/boards_entry.txt (66%) rename variants/STM32H5xx/{H563I(G-I)(K-T) => H563I(G-I)(K-T)_H573II(K-T)}/generic_clock.c (91%) rename variants/STM32H5xx/{H563I(G-I)(K-T) => H563I(G-I)(K-T)_H573II(K-T)}/variant_generic.cpp (97%) rename variants/STM32H5xx/{H563I(G-I)(K-T) => H563I(G-I)(K-T)_H573II(K-T)}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H563IIKxQ/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H563IIKxQ/generic_clock.c delete mode 100644 variants/STM32H5xx/H563IIKxQ/variant_generic.cpp rename variants/STM32H5xx/{H563IIKxQ => H563IIKxQ_H573IIKxQ}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H573IIKxQ => H563IIKxQ_H573IIKxQ}/PeripheralPins_STM32H573I_DK.c (100%) rename variants/STM32H5xx/{H563IIKxQ => H563IIKxQ_H573IIKxQ}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563IIKxQ => H563IIKxQ_H573IIKxQ}/boards_entry.txt (59%) rename variants/STM32H5xx/{H573IIKxQ => H563IIKxQ_H573IIKxQ}/generic_clock.c (97%) rename variants/STM32H5xx/{H563IIKxQ => H563IIKxQ_H573IIKxQ}/ldscript.ld (100%) rename variants/STM32H5xx/{H573IIKxQ => H563IIKxQ_H573IIKxQ}/variant_STM32H573I_DK.cpp (100%) rename variants/STM32H5xx/{H573IIKxQ => H563IIKxQ_H573IIKxQ}/variant_STM32H573I_DK.h (100%) rename variants/STM32H5xx/{H573IIKxQ => H563IIKxQ_H573IIKxQ}/variant_generic.cpp (97%) rename variants/STM32H5xx/{H563IIKxQ => H563IIKxQ_H573IIKxQ}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H563IITxQ/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H563IITxQ/variant_generic.cpp rename variants/STM32H5xx/{H563IITxQ => H563IITxQ_H573IITxQ}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H563IITxQ => H563IITxQ_H573IITxQ}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563IITxQ => H563IITxQ_H573IITxQ}/boards_entry.txt (59%) rename variants/STM32H5xx/{H563AIIxQ => H563IITxQ_H573IITxQ}/generic_clock.c (91%) rename variants/STM32H5xx/{H573IITxQ => H563IITxQ_H573IITxQ}/variant_generic.cpp (97%) rename variants/STM32H5xx/{H563IITxQ => H563IITxQ_H573IITxQ}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H563MIYxQ/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H563MIYxQ/variant_generic.cpp rename variants/STM32H5xx/{H563MIYxQ => H563MIYxQ_H573MIYxQ}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H563MIYxQ => H563MIYxQ_H573MIYxQ}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563MIYxQ => H563MIYxQ_H573MIYxQ}/boards_entry.txt (59%) rename variants/STM32H5xx/{H563MIYxQ => H563MIYxQ_H573MIYxQ}/generic_clock.c (91%) rename variants/STM32H5xx/{H573MIYxQ => H563MIYxQ_H573MIYxQ}/variant_generic.cpp (96%) rename variants/STM32H5xx/{H563MIYxQ => H563MIYxQ_H573MIYxQ}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H563R(G-I)T/CMakeLists.txt rename variants/STM32H5xx/{H563R(G-I)T => H563R(G-I)T_H573RIT}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H563R(G-I)T => H563R(G-I)T_H573RIT}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563R(G-I)T => H563R(G-I)T_H573RIT}/boards_entry.txt (70%) rename variants/STM32H5xx/{H563R(G-I)T => H563R(G-I)T_H573RIT}/generic_clock.c (94%) rename variants/STM32H5xx/{H563R(G-I)T => H563R(G-I)T_H573RIT}/variant_generic.cpp (97%) rename variants/STM32H5xx/{H563R(G-I)T => H563R(G-I)T_H573RIT}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H563R(G-I)V/CMakeLists.txt rename variants/STM32H5xx/{H563R(G-I)V => H563R(G-I)V_H573RIV}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H563R(G-I)V => H563R(G-I)V_H573RIV}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563R(G-I)V => H563R(G-I)V_H573RIV}/boards_entry.txt (70%) rename variants/STM32H5xx/{H563R(G-I)V => H563R(G-I)V_H573RIV}/generic_clock.c (94%) rename variants/STM32H5xx/{H563R(G-I)V => H563R(G-I)V_H573RIV}/variant_generic.cpp (97%) rename variants/STM32H5xx/{H563R(G-I)V => H563R(G-I)V_H573RIV}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H563V(G-I)T/CMakeLists.txt rename variants/STM32H5xx/{H563V(G-I)T => H563V(G-I)T_H573VIT}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H563V(G-I)T => H563V(G-I)T_H573VIT}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563V(G-I)T => H563V(G-I)T_H573VIT}/boards_entry.txt (70%) rename variants/STM32H5xx/{H563V(G-I)T => H563V(G-I)T_H573VIT}/generic_clock.c (94%) rename variants/STM32H5xx/{H563V(G-I)T => H563V(G-I)T_H573VIT}/variant_generic.cpp (97%) rename variants/STM32H5xx/{H563V(G-I)T => H563V(G-I)T_H573VIT}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H563Z(G-I)T/CMakeLists.txt rename variants/STM32H5xx/{H563Z(G-I)T => H563Z(G-I)T_H573ZIT}/PeripheralPins.c (99%) rename variants/STM32H5xx/{H563Z(G-I)T => H563Z(G-I)T_H573ZIT}/PinNamesVar.h (100%) rename variants/STM32H5xx/{H563Z(G-I)T => H563Z(G-I)T_H573ZIT}/boards_entry.txt (70%) rename variants/STM32H5xx/{H563Z(G-I)T => H563Z(G-I)T_H573ZIT}/generic_clock.c (98%) rename variants/STM32H5xx/{H563Z(G-I)T => H563Z(G-I)T_H573ZIT}/ldscript.ld (100%) rename variants/STM32H5xx/{H563Z(G-I)T => H563Z(G-I)T_H573ZIT}/variant_NUCLEO_H563ZI.cpp (100%) rename variants/STM32H5xx/{H563Z(G-I)T => H563Z(G-I)T_H573ZIT}/variant_NUCLEO_H563ZI.h (100%) rename variants/STM32H5xx/{H563Z(G-I)T => H563Z(G-I)T_H573ZIT}/variant_generic.cpp (98%) rename variants/STM32H5xx/{H563Z(G-I)T => H563Z(G-I)T_H573ZIT}/variant_generic.h (100%) delete mode 100644 variants/STM32H5xx/H573AII/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573AII/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573AII/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573AII/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573AII/generic_clock.c delete mode 100644 variants/STM32H5xx/H573AII/variant_generic.cpp delete mode 100644 variants/STM32H5xx/H573AII/variant_generic.h delete mode 100644 variants/STM32H5xx/H573AIIxQ/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573AIIxQ/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573AIIxQ/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573AIIxQ/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573AIIxQ/generic_clock.c delete mode 100644 variants/STM32H5xx/H573AIIxQ/variant_generic.cpp delete mode 100644 variants/STM32H5xx/H573AIIxQ/variant_generic.h delete mode 100644 variants/STM32H5xx/H573II(K-T)/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573II(K-T)/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573II(K-T)/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573II(K-T)/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573II(K-T)/generic_clock.c delete mode 100644 variants/STM32H5xx/H573II(K-T)/variant_generic.cpp delete mode 100644 variants/STM32H5xx/H573II(K-T)/variant_generic.h delete mode 100644 variants/STM32H5xx/H573IIKxQ/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573IIKxQ/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573IIKxQ/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573IIKxQ/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573IIKxQ/ldscript.ld delete mode 100644 variants/STM32H5xx/H573IIKxQ/variant_generic.h delete mode 100644 variants/STM32H5xx/H573IITxQ/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573IITxQ/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573IITxQ/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573IITxQ/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573IITxQ/generic_clock.c delete mode 100644 variants/STM32H5xx/H573IITxQ/variant_generic.h delete mode 100644 variants/STM32H5xx/H573MIYxQ/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573MIYxQ/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573MIYxQ/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573MIYxQ/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573MIYxQ/generic_clock.c delete mode 100644 variants/STM32H5xx/H573MIYxQ/variant_generic.h delete mode 100644 variants/STM32H5xx/H573RIT/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573RIT/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573RIT/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573RIT/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573RIT/generic_clock.c delete mode 100644 variants/STM32H5xx/H573RIT/variant_generic.cpp delete mode 100644 variants/STM32H5xx/H573RIT/variant_generic.h delete mode 100644 variants/STM32H5xx/H573RIV/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573RIV/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573RIV/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573RIV/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573RIV/generic_clock.c delete mode 100644 variants/STM32H5xx/H573RIV/variant_generic.cpp delete mode 100644 variants/STM32H5xx/H573RIV/variant_generic.h delete mode 100644 variants/STM32H5xx/H573VIT/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573VIT/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573VIT/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573VIT/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573VIT/generic_clock.c delete mode 100644 variants/STM32H5xx/H573VIT/variant_generic.cpp delete mode 100644 variants/STM32H5xx/H573VIT/variant_generic.h delete mode 100644 variants/STM32H5xx/H573ZIT/CMakeLists.txt delete mode 100644 variants/STM32H5xx/H573ZIT/PeripheralPins.c delete mode 100644 variants/STM32H5xx/H573ZIT/PinNamesVar.h delete mode 100644 variants/STM32H5xx/H573ZIT/boards_entry.txt delete mode 100644 variants/STM32H5xx/H573ZIT/generic_clock.c delete mode 100644 variants/STM32H5xx/H573ZIT/ldscript.ld delete mode 100644 variants/STM32H5xx/H573ZIT/variant_generic.cpp delete mode 100644 variants/STM32H5xx/H573ZIT/variant_generic.h rename variants/STM32U5xx/{U595Q(I-J)IxQ_U5A5QJIxQ => U595Q(I-J)IxQ_U5A5Q(I-J)IxQ}/PeripheralPins.c (99%) rename variants/STM32U5xx/{U595Q(I-J)IxQ_U5A5QJIxQ => U595Q(I-J)IxQ_U5A5Q(I-J)IxQ}/PinNamesVar.h (100%) rename variants/STM32U5xx/{U595Q(I-J)IxQ_U5A5QJIxQ => U595Q(I-J)IxQ_U5A5Q(I-J)IxQ}/boards_entry.txt (74%) rename variants/STM32U5xx/{U595Q(I-J)IxQ_U5A5QJIxQ => U595Q(I-J)IxQ_U5A5Q(I-J)IxQ}/generic_clock.c (92%) rename variants/STM32U5xx/{U595Q(I-J)IxQ_U5A5QJIxQ => U595Q(I-J)IxQ_U5A5Q(I-J)IxQ}/variant_generic.cpp (97%) rename variants/STM32U5xx/{U595Q(I-J)IxQ_U5A5QJIxQ => U595Q(I-J)IxQ_U5A5Q(I-J)IxQ}/variant_generic.h (100%) delete mode 100644 variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/CMakeLists.txt diff --git a/boards.txt b/boards.txt index 23e9d17871..ef0d7200fe 100644 --- a/boards.txt +++ b/boards.txt @@ -154,7 +154,7 @@ Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.float-abi=-mfloat-abi=hard Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.board=NUCLEO_H563ZI Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.series=STM32H5xx Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.product_line=STM32H563xx -Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.variant=STM32H5xx/H563Z(G-I)T +Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT # NUCLEO H723ZG board Nucleo_144.menu.pnum.NUCLEO_H723ZG=Nucleo H723ZG @@ -1044,7 +1044,7 @@ Disco.menu.pnum.STM32H573I_DK.build.float-abi=-mfloat-abi=hard Disco.menu.pnum.STM32H573I_DK.build.board=STM32H573I_DK Disco.menu.pnum.STM32H573I_DK.build.series=STM32H5xx Disco.menu.pnum.STM32H573I_DK.build.product_line=STM32H573xx -Disco.menu.pnum.STM32H573I_DK.build.variant=STM32H5xx/H573IIKxQ +Disco.menu.pnum.STM32H573I_DK.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ Disco.menu.pnum.STM32H573I_DK.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS # STM32H747I-DISCO @@ -7377,7 +7377,7 @@ GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IIKXQ.build.board=GENERIC_H563IIKXQ GenH5.menu.pnum.GENERIC_H563IIKXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IIKXQ.build.variant=STM32H5xx/H563IIKxQ +GenH5.menu.pnum.GENERIC_H563IIKXQ.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ # Generic H563ZGTx GenH5.menu.pnum.GENERIC_H563ZGTX=Generic H563ZGTx @@ -7385,7 +7385,7 @@ GenH5.menu.pnum.GENERIC_H563ZGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563ZGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563ZGTX.build.board=GENERIC_H563ZGTX GenH5.menu.pnum.GENERIC_H563ZGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563ZGTX.build.variant=STM32H5xx/H563Z(G-I)T +GenH5.menu.pnum.GENERIC_H563ZGTX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT # Generic H563ZITx GenH5.menu.pnum.GENERIC_H563ZITX=Generic H563ZITx @@ -7393,7 +7393,7 @@ GenH5.menu.pnum.GENERIC_H563ZITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563ZITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563ZITX.build.board=GENERIC_H563ZITX GenH5.menu.pnum.GENERIC_H563ZITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563ZITX.build.variant=STM32H5xx/H563Z(G-I)T +GenH5.menu.pnum.GENERIC_H563ZITX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT # Generic H573IIKxQ GenH5.menu.pnum.GENERIC_H573IIKXQ=Generic H573IIKxQ @@ -7401,7 +7401,7 @@ GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H573IIKXQ.build.board=GENERIC_H573IIKXQ GenH5.menu.pnum.GENERIC_H573IIKXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IIKXQ.build.variant=STM32H5xx/H573IIKxQ +GenH5.menu.pnum.GENERIC_H573IIKXQ.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ # Generic H573ZITx GenH5.menu.pnum.GENERIC_H573ZITX=Generic H573ZITx @@ -7409,7 +7409,7 @@ GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H573ZITX.build.board=GENERIC_H573ZITX GenH5.menu.pnum.GENERIC_H573ZITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573ZITX.build.variant=STM32H5xx/H573ZIT +GenH5.menu.pnum.GENERIC_H573ZITX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT # Upload menu GenH5.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c index 6f1b6f2517..e7c6f59deb 100644 --- a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c +++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C011D6Yx.xml, STM32C011F(4-6)Px.xml * STM32C011F(4-6)Ux.xml, STM32C031F(4-6)Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c index 03409f11a1..e833b49336 100644 --- a/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c +++ b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C011J(4-6)Mx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c index 3365ea3bab..d26b281535 100644 --- a/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031C(4-6)Tx.xml, STM32C031C(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c b/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c index cfb93dd604..935eead862 100644 --- a/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c +++ b/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031G(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c index 8bfeac644d..34072bfc95 100644 --- a/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031K(4-6)Tx.xml, STM32C031K(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030C6T/PeripheralPins.c b/variants/STM32F0xx/F030C6T/PeripheralPins.c index 14771b63f0..92d0f3a4bc 100644 --- a/variants/STM32F0xx/F030C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F030C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030C6Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030C8T/PeripheralPins.c b/variants/STM32F0xx/F030C8T/PeripheralPins.c index a6dcb0c134..8eef567840 100644 --- a/variants/STM32F0xx/F030C8T/PeripheralPins.c +++ b/variants/STM32F0xx/F030C8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030C8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030CCT/PeripheralPins.c b/variants/STM32F0xx/F030CCT/PeripheralPins.c index beb4767bb3..6078f61e86 100644 --- a/variants/STM32F0xx/F030CCT/PeripheralPins.c +++ b/variants/STM32F0xx/F030CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030CCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030F4P/PeripheralPins.c b/variants/STM32F0xx/F030F4P/PeripheralPins.c index 7bdd232de2..cf8a9708e5 100644 --- a/variants/STM32F0xx/F030F4P/PeripheralPins.c +++ b/variants/STM32F0xx/F030F4P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030F4Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030K6T/PeripheralPins.c b/variants/STM32F0xx/F030K6T/PeripheralPins.c index 1633a69951..45b8444ec6 100644 --- a/variants/STM32F0xx/F030K6T/PeripheralPins.c +++ b/variants/STM32F0xx/F030K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030K6Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030R8T/PeripheralPins.c b/variants/STM32F0xx/F030R8T/PeripheralPins.c index 07e2d7103c..64abdf84db 100644 --- a/variants/STM32F0xx/F030R8T/PeripheralPins.c +++ b/variants/STM32F0xx/F030R8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030R8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030RCT/PeripheralPins.c b/variants/STM32F0xx/F030RCT/PeripheralPins.c index 1eaf727529..9891ac540d 100644 --- a/variants/STM32F0xx/F030RCT/PeripheralPins.c +++ b/variants/STM32F0xx/F030RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030RCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c b/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c index 31614b7059..c8a19d15ac 100644 --- a/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c +++ b/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031C(4-6)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c b/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c index b75eeb91b7..78a5265486 100644 --- a/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031E6Yx.xml, STM32F038E6Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c b/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c index 3f6c64ec70..881297b028 100644 --- a/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c +++ b/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031F(4-6)Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c index a9e34287ab..97eee17591 100644 --- a/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031G(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c index 56c5a81333..7dbfbcafc3 100644 --- a/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031K(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031K6T/PeripheralPins.c b/variants/STM32F0xx/F031K6T/PeripheralPins.c index 5ae9cc89bc..91177eec8f 100644 --- a/variants/STM32F0xx/F031K6T/PeripheralPins.c +++ b/variants/STM32F0xx/F031K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031K6Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038C6T/PeripheralPins.c b/variants/STM32F0xx/F038C6T/PeripheralPins.c index d431d69d41..ed1b96cdfb 100644 --- a/variants/STM32F0xx/F038C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F038C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038C6Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038F6P/PeripheralPins.c b/variants/STM32F0xx/F038F6P/PeripheralPins.c index 000f9a42b8..65d788dde8 100644 --- a/variants/STM32F0xx/F038F6P/PeripheralPins.c +++ b/variants/STM32F0xx/F038F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038F6Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038G6U/PeripheralPins.c b/variants/STM32F0xx/F038G6U/PeripheralPins.c index a2c825c044..28984b2e5f 100644 --- a/variants/STM32F0xx/F038G6U/PeripheralPins.c +++ b/variants/STM32F0xx/F038G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038G6Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038K6U/PeripheralPins.c b/variants/STM32F0xx/F038K6U/PeripheralPins.c index 0c5b211ff1..35d8682d4a 100644 --- a/variants/STM32F0xx/F038K6U/PeripheralPins.c +++ b/variants/STM32F0xx/F038K6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038K6Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c b/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c index 66f4ad4bb5..5da77ff765 100644 --- a/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042C(4-6)Tx.xml, STM32F042C(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c b/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c index 68325bf232..c1e3efecdc 100644 --- a/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c +++ b/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042F4Px.xml, STM32F042F6Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c index 17e67d85f9..6cae9c1c4c 100644 --- a/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042G(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c b/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c index cc89b0e10e..4e15eadcb8 100644 --- a/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c +++ b/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042K(4-6)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c index 75da4c42f6..8112ffefac 100644 --- a/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042K(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042T6Y/PeripheralPins.c b/variants/STM32F0xx/F042T6Y/PeripheralPins.c index 3cebb0b0e4..72a8c7bad8 100644 --- a/variants/STM32F0xx/F042T6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F042T6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042T6Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048C6U/PeripheralPins.c b/variants/STM32F0xx/F048C6U/PeripheralPins.c index 37e0673513..b20e5231fe 100644 --- a/variants/STM32F0xx/F048C6U/PeripheralPins.c +++ b/variants/STM32F0xx/F048C6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048C6Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048G6U/PeripheralPins.c b/variants/STM32F0xx/F048G6U/PeripheralPins.c index de6400ea73..fb5d5c1aa1 100644 --- a/variants/STM32F0xx/F048G6U/PeripheralPins.c +++ b/variants/STM32F0xx/F048G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048G6Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048T6Y/PeripheralPins.c b/variants/STM32F0xx/F048T6Y/PeripheralPins.c index f8d19aa848..ed54461c58 100644 --- a/variants/STM32F0xx/F048T6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F048T6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048T6Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c index 2da514c7fc..2141a8a39a 100644 --- a/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C4Tx.xml, STM32F051C4Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c index 24b2235b97..5df2f34bdc 100644 --- a/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C6Tx.xml, STM32F051C6Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c index 39b013dbb0..bf265a37b6 100644 --- a/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C8Tx.xml, STM32F051C8Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c b/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c index 769b9fc98f..ba36deb76e 100644 --- a/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c +++ b/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K6Tx.xml, STM32F051K8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c b/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c index 37220eb149..07c40223f6 100644 --- a/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c +++ b/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K6Ux.xml, STM32F051K8Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K4T/PeripheralPins.c b/variants/STM32F0xx/F051K4T/PeripheralPins.c index 152856a9b4..f671e58efa 100644 --- a/variants/STM32F0xx/F051K4T/PeripheralPins.c +++ b/variants/STM32F0xx/F051K4T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K4Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K4U/PeripheralPins.c b/variants/STM32F0xx/F051K4U/PeripheralPins.c index 99fb3dc101..2c36d0f233 100644 --- a/variants/STM32F0xx/F051K4U/PeripheralPins.c +++ b/variants/STM32F0xx/F051K4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K4Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R4T/PeripheralPins.c b/variants/STM32F0xx/F051R4T/PeripheralPins.c index 39f803679a..75d1314453 100644 --- a/variants/STM32F0xx/F051R4T/PeripheralPins.c +++ b/variants/STM32F0xx/F051R4T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R4Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R6T/PeripheralPins.c b/variants/STM32F0xx/F051R6T/PeripheralPins.c index 1514ef5dc0..51788a3da9 100644 --- a/variants/STM32F0xx/F051R6T/PeripheralPins.c +++ b/variants/STM32F0xx/F051R6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R6Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c b/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c index 92e7a27df3..7cac625d74 100644 --- a/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R8Hx.xml, STM32F051R8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051T8Y/PeripheralPins.c b/variants/STM32F0xx/F051T8Y/PeripheralPins.c index d8cefc2509..d12ef6237a 100644 --- a/variants/STM32F0xx/F051T8Y/PeripheralPins.c +++ b/variants/STM32F0xx/F051T8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051T8Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058C8U/PeripheralPins.c b/variants/STM32F0xx/F058C8U/PeripheralPins.c index 04410872e7..0050815622 100644 --- a/variants/STM32F0xx/F058C8U/PeripheralPins.c +++ b/variants/STM32F0xx/F058C8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058C8Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c b/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c index 1276b35aeb..e9b0deb046 100644 --- a/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058R8Hx.xml, STM32F058R8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058T8Y/PeripheralPins.c b/variants/STM32F0xx/F058T8Y/PeripheralPins.c index a23e2594e9..dc1ae65c1a 100644 --- a/variants/STM32F0xx/F058T8Y/PeripheralPins.c +++ b/variants/STM32F0xx/F058T8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058T8Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070C6T/PeripheralPins.c b/variants/STM32F0xx/F070C6T/PeripheralPins.c index 4d8e6e1b9b..f99f6da9cf 100644 --- a/variants/STM32F0xx/F070C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F070C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070C6Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070CBT/PeripheralPins.c b/variants/STM32F0xx/F070CBT/PeripheralPins.c index 916a8da040..7a9a05085e 100644 --- a/variants/STM32F0xx/F070CBT/PeripheralPins.c +++ b/variants/STM32F0xx/F070CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070CBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070F6P/PeripheralPins.c b/variants/STM32F0xx/F070F6P/PeripheralPins.c index ff1f7ad3e6..36f44fcde5 100644 --- a/variants/STM32F0xx/F070F6P/PeripheralPins.c +++ b/variants/STM32F0xx/F070F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070F6Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070RBT/PeripheralPins.c b/variants/STM32F0xx/F070RBT/PeripheralPins.c index 9d635bb9b7..7e64baff50 100644 --- a/variants/STM32F0xx/F070RBT/PeripheralPins.c +++ b/variants/STM32F0xx/F070RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070RBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c index 3c02de3ca6..df9f8a855f 100644 --- a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F071C(8-B)Tx.xml, STM32F071C(8-B)Ux.xml * STM32F071CBYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071RBT/PeripheralPins.c b/variants/STM32F0xx/F071RBT/PeripheralPins.c index 9befd147e7..e47b79c90d 100644 --- a/variants/STM32F0xx/F071RBT/PeripheralPins.c +++ b/variants/STM32F0xx/F071RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F071RBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c b/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c index 350748d04c..1c28b8e523 100644 --- a/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F071V(8-B)Hx.xml, STM32F071V(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c index 1a3382feed..c415cfbabf 100644 --- a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F072C(8-B)Tx.xml, STM32F072C(8-B)Ux.xml * STM32F072CBYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c index 87b1b88829..b1b8b405a5 100644 --- a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F072R(8-B)Tx.xml, STM32F072RBHx.xml * STM32F072RBIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c b/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c index e3923e5ce2..d9ea4b30e9 100644 --- a/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F072V(8-B)Hx.xml, STM32F072V(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c index ee3c26a4a9..40699020e2 100644 --- a/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F078CBTx.xml, STM32F078CBUx.xml * STM32F078CBYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c b/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c index 379c667193..f151d4d093 100644 --- a/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F078RBHx.xml, STM32F078RBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c b/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c index f7aeea5c59..9d3d851324 100644 --- a/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F078VBHx.xml, STM32F078VBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c b/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c index 359e17abde..144703c3ec 100644 --- a/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F091C(B-C)Tx.xml, STM32F091C(B-C)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c index 49e8745010..ed66ec9f34 100644 --- a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F091R(B-C)Tx.xml, STM32F091RCHx.xml * STM32F091RCYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c b/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c index e99df7237a..eee75ad156 100644 --- a/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F091V(B-C)Tx.xml, STM32F091VCHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c b/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c index f8a292ae19..2af89d54de 100644 --- a/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F098CCTx.xml, STM32F098CCUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c b/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c index b25151232a..0971147b6c 100644 --- a/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F098RCHx.xml, STM32F098RCTx.xml * STM32F098RCYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c b/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c index 9a897c0efd..4d7483aa90 100644 --- a/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F098VCHx.xml, STM32F098VCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c index 7942b754a4..2808bf6166 100644 --- a/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100C(4-6)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c index 3834dbf779..7e68d975d7 100644 --- a/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100C(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c b/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c index 895d581a27..654629e276 100644 --- a/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(4-6)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c index d5727f9236..dee8b78849 100644 --- a/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(4-6)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c b/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c index c3ad1ce122..00bc68a99a 100644 --- a/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(8-B)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c index b372736689..1241ba3976 100644 --- a/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c index 119219c9d7..831165bfa6 100644 --- a/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(C-D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c index 86d0855013..002a2cb5f5 100644 --- a/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100V(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c index 3c0acedd71..b8acce54c6 100644 --- a/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100V(C-D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c index 6dd352fe19..86f3371d27 100644 --- a/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c index b526327474..19546e80b9 100644 --- a/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101C(4-6)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c b/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c index e7327ae934..3b1efd7101 100644 --- a/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101C(8-B)Tx.xml, STM32F101C(8-B)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c index 5778286c9f..3e3726ac76 100644 --- a/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(4-6)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c index 09cf306e36..d109dc18cf 100644 --- a/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c index cf0f90860f..1ecb0a5e4a 100644 --- a/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(C-D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c index ffd957f44f..13f4cf62f9 100644 --- a/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(F-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101RBH/PeripheralPins.c b/variants/STM32F1xx/F101RBH/PeripheralPins.c index 5b4c9f3eb0..98b8e8eb5d 100644 --- a/variants/STM32F1xx/F101RBH/PeripheralPins.c +++ b/variants/STM32F1xx/F101RBH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101RBHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c b/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c index 54974823a2..ae5ebe6b15 100644 --- a/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c +++ b/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101T(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c b/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c index 01cddc4ee0..42d184fdc5 100644 --- a/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c +++ b/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101T(8-B)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c index 692fa3402c..132d1eecc5 100644 --- a/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c index fabc08acc8..325736e92c 100644 --- a/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(C-D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c index f30eba6908..27f0136440 100644 --- a/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(F-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c index 6cfbeb8b6a..188fa4c309 100644 --- a/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c index 4c31e0f95f..3bb15b83cd 100644 --- a/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101Z(F-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c index 210bb05c72..a2d7d3d8ba 100644 --- a/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102C(4-6)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c index 30b60713d1..44983508db 100644 --- a/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102C(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c index 94e86a13ca..4ee1948ee6 100644 --- a/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102R(4-6)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c index 28b6299877..f3f2d5e7db 100644 --- a/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102R(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c index 955013cd5d..89e4b9304e 100644 --- a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103C(4-6)Tx.xml, STM32F103C6Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c index e1c11277a3..6daee26203 100644 --- a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103C(8-B)Tx.xml, STM32F103CBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c b/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c index fe5e012b0e..14c074dce0 100644 --- a/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(4-6)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c index 8c0a974e81..a1611e675a 100644 --- a/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(4-6)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c b/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c index 92cbf80b4d..7466801597 100644 --- a/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(8-B)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c index 22dd2b66d3..cbc5f33b0a 100644 --- a/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c index ab4dd47cd6..581b5771d2 100644 --- a/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(C-D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c b/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c index 6f112d8624..5041d69c0f 100644 --- a/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(C-D-E)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c index 44732640be..674907bae7 100644 --- a/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(F-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c b/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c index bbfdca15fc..29791385a9 100644 --- a/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c +++ b/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103T(4-6)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c b/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c index 7a29e53e1e..0a6c39e14a 100644 --- a/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c +++ b/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103T(8-B)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c index 4c714f7255..7c500cc148 100644 --- a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103V(C-D-E)Hx.xml, STM32F103V(C-D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c index 35c56659df..89bee65405 100644 --- a/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103V(F-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c index dc1448f6f9..37fe8244a2 100644 --- a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F103V(8-B)Hx.xml, STM32F103V(8-B)Tx.xml * STM32F103VBIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c index 79efa80fd9..1796d71d52 100644 --- a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103Z(C-D-E)Hx.xml, STM32F103Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c index fe74bdb399..990646e372 100644 --- a/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103Z(F-G)Hx.xml, STM32F103Z(F-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c b/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c index 57b72ce605..9af6486d92 100644 --- a/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F105R(8-B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c index d6b2dfa617..5e25d59dcc 100644 --- a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c +++ b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F105V(8-B)Hx.xml, STM32F105V(8-B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c b/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c index a1a5a750dd..e6313e0f0d 100644 --- a/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c +++ b/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F107R(B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c index 9c0eccb262..6089699ad2 100644 --- a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F107V(B-C)Tx.xml, STM32F107VCHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c index cfe1fb17f5..62de7770db 100644 --- a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F205R(B-C-E-F-G)Tx.xml, STM32F205R(E-G)Yx.xml * STM32F205RGEx.xml, STM32F215R(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c index 83562d18ac..ebf4b8f0f7 100644 --- a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F205V(B-C-E-F-G)Tx.xml, STM32F215V(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c index 79ee28a40a..12c8b04368 100644 --- a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F205Z(C-E-F-G)Tx.xml, STM32F215Z(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c index 877bcba280..1d926c3f7f 100644 --- a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F207I(C-E-F-G)Hx.xml, STM32F207I(C-E-F-G)Tx.xml * STM32F217I(E-G)Hx.xml, STM32F217I(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c index f262fe4483..8a16f3fad2 100644 --- a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F207V(C-E-F-G)Tx.xml, STM32F217V(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c index 5c41d116dc..5e37451c9a 100644 --- a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F207Z(C-E-F-G)Tx.xml, STM32F217Z(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c index 7373fd6018..78b22cb73d 100644 --- a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301C(6-8)Tx.xml, STM32F301C8Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c index 2a49652235..f02388e0a1 100644 --- a/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301K(6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c b/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c index 5c4939744e..fcaacea165 100644 --- a/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301K(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c index c6baee8ba1..b4cab8ca1d 100644 --- a/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301R(6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c index 424c5fd152..078592e1b6 100644 --- a/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302C(B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c index 45613ac5cf..f6b5f986a8 100644 --- a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302C(6-8)Tx.xml, STM32F302C8Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c b/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c index 4586035405..d73621a6e4 100644 --- a/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302K(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c index 923967210c..c2b67bd3fe 100644 --- a/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c index ac49485197..6dd6b6a946 100644 --- a/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c index c477d20db6..f13a89484f 100644 --- a/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c index c9f26036ce..9e6d791385 100644 --- a/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302V(B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c index c0bb434633..c56e717f0a 100644 --- a/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302V(D-E)Hx.xml, STM32F302V(D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302VCY/PeripheralPins.c b/variants/STM32F3xx/F302VCY/PeripheralPins.c index 625c36b890..a5f13082e2 100644 --- a/variants/STM32F3xx/F302VCY/PeripheralPins.c +++ b/variants/STM32F3xx/F302VCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302VCYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c index 4652d71fc5..0450593add 100644 --- a/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302Z(D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c index d408311425..d3a86f9e4e 100644 --- a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C(6-8)Tx.xml, STM32F334C(4-6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c index e2eea9dba5..9e7e81eed0 100644 --- a/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C(B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c b/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c index f093463ca0..0bb590927b 100644 --- a/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c +++ b/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C8Yx.xml, STM32F334C8Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c index a220c16d2d..4ab2f1c413 100644 --- a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303K(6-8)Tx.xml, STM32F334K(4-6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c index 980f0804cb..8b80edaab5 100644 --- a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303K(6-8)Ux.xml, STM32F334K(4-6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c index 77d5f0e2e9..31a5182ffa 100644 --- a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(6-8)Tx.xml, STM32F334R(6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c index 4d50fb621f..dfe6824a1e 100644 --- a/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c index 12bb91f0e8..381f77b47c 100644 --- a/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c index 56bab00ad2..f458475a75 100644 --- a/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303V(B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c index b4ab3ac97e..4957273c31 100644 --- a/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303V(D-E)Hx.xml, STM32F303V(D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303VCY/PeripheralPins.c b/variants/STM32F3xx/F303VCY/PeripheralPins.c index aab6db5743..d2edd346d4 100644 --- a/variants/STM32F3xx/F303VCY/PeripheralPins.c +++ b/variants/STM32F3xx/F303VCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303VCYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303VEY/PeripheralPins.c b/variants/STM32F3xx/F303VEY/PeripheralPins.c index ff62950763..b60a9ab7e9 100644 --- a/variants/STM32F3xx/F303VEY/PeripheralPins.c +++ b/variants/STM32F3xx/F303VEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303VEYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c index 7ee8392283..fb1675cbe2 100644 --- a/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303Z(D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c index 3012e15d54..90d5f05cdc 100644 --- a/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F318C8Tx.xml, STM32F318C8Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F318K8U/PeripheralPins.c b/variants/STM32F3xx/F318K8U/PeripheralPins.c index 6faa6bc2b7..4f9267a5f7 100644 --- a/variants/STM32F3xx/F318K8U/PeripheralPins.c +++ b/variants/STM32F3xx/F318K8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F318K8Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F328C8T/PeripheralPins.c b/variants/STM32F3xx/F328C8T/PeripheralPins.c index 9074f15be5..ce24c88bed 100644 --- a/variants/STM32F3xx/F328C8T/PeripheralPins.c +++ b/variants/STM32F3xx/F328C8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F328C8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358CCT/PeripheralPins.c b/variants/STM32F3xx/F358CCT/PeripheralPins.c index d31dfd6a9e..015c3bd060 100644 --- a/variants/STM32F3xx/F358CCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358CCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358RCT/PeripheralPins.c b/variants/STM32F3xx/F358RCT/PeripheralPins.c index d6b1e8c966..17812a597e 100644 --- a/variants/STM32F3xx/F358RCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358RCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358VCT/PeripheralPins.c b/variants/STM32F3xx/F358VCT/PeripheralPins.c index a613fcedcb..2c350a9bfa 100644 --- a/variants/STM32F3xx/F358VCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358VCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358VCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c b/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c index 150423aa99..d39876d61d 100644 --- a/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373C(8-B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c b/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c index 8629629dde..04e62c51d2 100644 --- a/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373R(8-B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c index 9be63a86c2..947c5b440b 100644 --- a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373V(8-B-C)Hx.xml, STM32F373V(8-B-C)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378CCT/PeripheralPins.c b/variants/STM32F3xx/F378CCT/PeripheralPins.c index e12a751c4f..74043b4a87 100644 --- a/variants/STM32F3xx/F378CCT/PeripheralPins.c +++ b/variants/STM32F3xx/F378CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378CCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c index 1496b8acaf..75f5a16711 100644 --- a/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378RCTx.xml, STM32F378RCYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c b/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c index 305ea0bf3e..0c863f090b 100644 --- a/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378VCHx.xml, STM32F378VCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F398VET/PeripheralPins.c b/variants/STM32F3xx/F398VET/PeripheralPins.c index fb25e1aa71..9baa6bf6f2 100644 --- a/variants/STM32F3xx/F398VET/PeripheralPins.c +++ b/variants/STM32F3xx/F398VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F398VETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c index d360f2f6c3..e7fa58fc1c 100644 --- a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F401C(B-C)Ux.xml, STM32F401C(B-C)Yx.xml * STM32F401C(D-E)Ux.xml, STM32F401C(D-E)Yx.xml * STM32F401CCFx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c b/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c index 0e586998e1..d20e42ffd4 100644 --- a/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401R(B-C)Tx.xml, STM32F401R(D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c b/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c index 9cb9c003a5..b4a92edf88 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c +++ b/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401V(B-C)Hx.xml, STM32F401V(D-E)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c b/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c index a64e052d50..a991a28602 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401V(B-C)Tx.xml, STM32F401V(D-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c index 9cef5981d7..5730a13147 100644 --- a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c +++ b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405O(E-G)Yx.xml, STM32F415OGYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c b/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c index 18eccae764..6f79e02e78 100644 --- a/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405RGTx.xml, STM32F415RGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c b/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c index 88bb4c305d..c0b808e3e1 100644 --- a/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405VGTx.xml, STM32F415VGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c b/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c index 096c9818ee..2239f0ee94 100644 --- a/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405ZGTx.xml, STM32F415ZGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c index 84dc64d455..abe8329661 100644 --- a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F407I(E-G)Hx.xml, STM32F407I(E-G)Tx.xml * STM32F417I(E-G)Hx.xml, STM32F417I(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c index beb3a66870..8ff791f1ac 100644 --- a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F407V(E-G)Tx.xml, STM32F417V(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c index 8316f9d0f5..a84b110f5f 100644 --- a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F407Z(E-G)Tx.xml, STM32F417Z(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c b/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c index 7fc3e7b6a3..219cc34de5 100644 --- a/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c +++ b/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410C(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c b/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c index 13fd03726d..6189bf967c 100644 --- a/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c +++ b/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410C(8-B)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c b/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c index 84115d1cc0..2261975f33 100644 --- a/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410R(8-B)Ix.xml, STM32F410R(8-B)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c b/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c index 6ddbbbc2bb..1349e1cc81 100644 --- a/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c +++ b/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410T(8-B)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c b/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c index 15015155e2..f0bdf42d78 100644 --- a/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411C(C-E)Ux.xml, STM32F411C(C-E)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c index 7a1ce27f21..f91da86f9c 100644 --- a/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411R(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c b/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c index 1fe43dd382..46bd476f31 100644 --- a/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c +++ b/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411V(C-E)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c index 9b7547923f..c9530c77a2 100644 --- a/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411V(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c b/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c index 81a85bcbc3..7a32960538 100644 --- a/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c +++ b/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412C(E-G)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c index 99bfe4afe0..2f8e0feb2c 100644 --- a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c +++ b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F412R(E-G)Tx.xml, STM32F412R(E-G)Yx.xml * STM32F412R(E-G)YxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c b/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c index 9a7b9029b2..78b4dca9b4 100644 --- a/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c +++ b/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412V(E-G)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c index 3885c608b2..d24750f4f3 100644 --- a/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412V(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c b/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c index 25d6e825d9..41f2acf721 100644 --- a/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412Z(E-G)Jx.xml, STM32F412Z(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c index 3fa39e1f3e..4d8d1553a1 100644 --- a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c +++ b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413C(G-H)Ux.xml, STM32F423CHUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c index d195c4481d..e1644b9092 100644 --- a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c +++ b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413M(G-H)Yx.xml, STM32F423MHYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c index b1e49b0dfa..8def1e2da2 100644 --- a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c +++ b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413R(G-H)Tx.xml, STM32F423RHTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c index ca687a9eaf..31dcf845cd 100644 --- a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c +++ b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413V(G-H)Hx.xml, STM32F423VHHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c index 61bf97aaef..faf091bc28 100644 --- a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c +++ b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413V(G-H)Tx.xml, STM32F423VHTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c index ac94e763d7..d2879b9256 100644 --- a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F413Z(G-H)Jx.xml, STM32F413Z(G-H)Tx.xml * STM32F423ZHJx.xml, STM32F423ZHTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c index 5ab0d79850..c9e783aba0 100644 --- a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c +++ b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F427A(G-I)Hx.xml, STM32F429A(G-I)Hx.xml * STM32F437AIHx.xml, STM32F439AIHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c index dd92062b85..64088fd9f7 100644 --- a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32F429IITx.xml, STM32F437I(G-I)Hx.xml * STM32F437I(G-I)Tx.xml, STM32F439I(G-I)Hx.xml * STM32F439I(G-I)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c index 1366699baa..24bc1053a6 100644 --- a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F427V(G-I)Tx.xml, STM32F429V(E-G)Tx.xml * STM32F429VITx.xml, STM32F437V(G-I)Tx.xml * STM32F439V(G-I)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c index decbf60ad6..598db59558 100644 --- a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F429ZGYx.xml, STM32F429ZITx.xml * STM32F429ZIYx.xml, STM32F437Z(G-I)Tx.xml * STM32F439Z(G-I)Tx.xml, STM32F439Z(G-I)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c index 5c865e5b16..b593b5a640 100644 --- a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c +++ b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F429B(E-G-I)Tx.xml, STM32F429N(E-G)Hx.xml * STM32F429NIHx.xml, STM32F439B(G-I)Tx.xml * STM32F439N(G-I)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c b/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c index cbf3d7218f..2272942709 100644 --- a/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c +++ b/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446M(C-E)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c index 6549260b5e..abd501afa4 100644 --- a/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446R(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c index 39a3033de8..85e692f4d2 100644 --- a/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446V(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c index 1f7e57ff53..e49a0a9487 100644 --- a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F446Z(C-E)Hx.xml, STM32F446Z(C-E)Jx.xml * STM32F446Z(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c index fd4126d7dc..db9f60303f 100644 --- a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469A(E-G-I)Hx.xml, STM32F469A(E-G-I)Yx.xml * STM32F479A(G-I)Hx.xml, STM32F479A(G-I)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c index 29fbf20449..4c37c32835 100644 --- a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c +++ b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F469B(E-G-I)Tx.xml, STM32F469N(E-G)Hx.xml * STM32F469NIHx.xml, STM32F479B(G-I)Tx.xml * STM32F479N(G-I)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c index bba3cabaf3..c0de65db02 100644 --- a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F469I(E-G)Tx.xml, STM32F469I(E-G-I)Hx.xml * STM32F469IITx.xml, STM32F479I(G-I)Hx.xml * STM32F479I(G-I)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c index b132f7b181..26ad2525e2 100644 --- a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469V(E-G)Tx.xml, STM32F469VITx.xml * STM32F479V(G-I)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c index 490380acc3..60cd693033 100644 --- a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469Z(E-G)Tx.xml, STM32F469ZITx.xml * STM32F479Z(G-I)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c index e829192090..4713a56677 100644 --- a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722I(C-E)Kx.xml, STM32F722I(C-E)Tx.xml * STM32F732IEKx.xml, STM32F732IETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c index 20d38f9f4e..544277fc8d 100644 --- a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c +++ b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722R(C-E)Tx.xml, STM32F730R8Tx.xml * STM32F732RETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c index 9833d9d131..ba26b35ec1 100644 --- a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c +++ b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722V(C-E)Tx.xml, STM32F730V8Tx.xml * STM32F732VETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c index 6b3cf1cc34..dd17df34d3 100644 --- a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c +++ b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F722Z(C-E)Tx.xml, STM32F732ZETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c index 1b6793c8d0..a8b4d1720f 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F723I(C-E)Kx.xml, STM32F723I(C-E)Tx.xml * STM32F730I8Kx.xml, STM32F733IEKx.xml * STM32F733IETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c index ec849b71da..bf97ea0d4f 100644 --- a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c +++ b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F723V(C-E)Tx.xml, STM32F723V(C-E)Yx.xml * STM32F733VETx.xml, STM32F733VEYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c index 90774cdded..a4553ee51a 100644 --- a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F723Z(C-E)Ix.xml, STM32F723Z(C-E)Tx.xml * STM32F730Z8Tx.xml, STM32F733ZEIx.xml * STM32F733ZETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c index 81e52b19fb..dbacd6d754 100644 --- a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746I(E-G)Kx.xml, STM32F746IETx.xml * STM32F746IGTx.xml, STM32F756IGKx.xml * STM32F756IGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c index 8d7c73ccfe..81b389e0c1 100644 --- a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746V(E-G)Hx.xml, STM32F746VETx.xml * STM32F746VGTx.xml, STM32F750V8Tx.xml * STM32F756VGHx.xml, STM32F756VGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c index 275c404b6c..f2f5e746ff 100644 --- a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c +++ b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746ZETx.xml, STM32F746ZGTx.xml * STM32F750Z8Tx.xml, STM32F756ZGTx.xml * STM32F756ZGYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c index 1762b98027..fb16bc7c39 100644 --- a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c +++ b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F746B(E-G)Tx.xml, STM32F746NEHx.xml * STM32F746NGHx.xml, STM32F750N8Hx.xml * STM32F756BGTx.xml, STM32F756NGHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c index c696f864ed..43d0ffa286 100644 --- a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c +++ b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F765B(G-I)Tx.xml, STM32F765N(G-I)Hx.xml * STM32F767B(G-I)Tx.xml, STM32F767N(G-I)Hx.xml * STM32F777BITx.xml, STM32F777NIHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c index 96b074f394..cb3966354d 100644 --- a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F765I(G-I)Kx.xml, STM32F765I(G-I)Tx.xml * STM32F767I(G-I)Kx.xml, STM32F767I(G-I)Tx.xml * STM32F777IIKx.xml, STM32F777IITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c index ca2bc1cfd1..e944ee8b8f 100644 --- a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F767VGHx.xml, STM32F767VGTx.xml * STM32F767VIHx.xml, STM32F767VITx.xml * STM32F777VIHx.xml, STM32F777VITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c index 2532f744fc..ec632d7eac 100644 --- a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c +++ b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F765Z(G-I)Tx.xml, STM32F767ZGTx.xml * STM32F767ZITx.xml, STM32F777ZITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c index 9f3edd43a5..ce152290dc 100644 --- a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c +++ b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F768AIYx.xml, STM32F769A(G-I)Yx.xml * STM32F778AIYx.xml, STM32F779AIYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c index 95c684d7c1..2f82c77fe5 100644 --- a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c +++ b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F769B(G-I)Tx.xml, STM32F769NGHx.xml * STM32F769NIHx.xml, STM32F779BITx.xml * STM32F779NIHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c index 34be7b28f6..33bd249101 100644 --- a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c +++ b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F769IGTx.xml, STM32F769IITx.xml * STM32F779IITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c index 455a657128..3031d022bf 100644 --- a/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030C(6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030F6P/PeripheralPins.c b/variants/STM32G0xx/G030F6P/PeripheralPins.c index 3e61dd204e..b138bec697 100644 --- a/variants/STM32G0xx/G030F6P/PeripheralPins.c +++ b/variants/STM32G0xx/G030F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030F6Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030J6M/PeripheralPins.c b/variants/STM32G0xx/G030J6M/PeripheralPins.c index 87610bfdc3..c0dc885dfb 100644 --- a/variants/STM32G0xx/G030J6M/PeripheralPins.c +++ b/variants/STM32G0xx/G030J6M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030J6Mx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c index 08a59a495e..8c778ef1a5 100644 --- a/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030K(6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c index dda988e052..d2e82d40db 100644 --- a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031C(4-6-8)Tx.xml, STM32G031C(4-6-8)Ux.xml * STM32G041C(6-8)Tx.xml, STM32G041C(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c index 60c9d482b0..703619c0ba 100644 --- a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c +++ b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031F(4-6-8)Px.xml, STM32G031Y8Yx.xml * STM32G041F(6-8)Px.xml, STM32G041Y8Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c index 1a47fac065..81284dfcb5 100644 --- a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c +++ b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G031G(4-6-8)Ux.xml, STM32G041G(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c index 051b2b827e..d4ee772552 100644 --- a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c +++ b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G031J(4-6)Mx.xml, STM32G041J6Mx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c index a125147bec..fcc02b6ab6 100644 --- a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031K(4-6-8)Tx.xml, STM32G031K(4-6-8)Ux.xml * STM32G041K(6-8)Tx.xml, STM32G041K(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c index e99298fec7..c3e90fbd07 100644 --- a/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050C6Tx.xml, STM32G050C8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050F6P/PeripheralPins.c b/variants/STM32G0xx/G050F6P/PeripheralPins.c index 45c72dae04..e948247431 100644 --- a/variants/STM32G0xx/G050F6P/PeripheralPins.c +++ b/variants/STM32G0xx/G050F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050F6Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c index 968b0a6ceb..e5abe58e0b 100644 --- a/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050K6Tx.xml, STM32G050K8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c index 1f2448a1b7..54e790d815 100644 --- a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051C(6-8)Tx.xml, STM32G051C(6-8)Ux.xml * STM32G061C(6-8)Tx.xml, STM32G061C(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c index 4df5f7516e..29176f1463 100644 --- a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c +++ b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051F(6-8)Px.xml, STM32G051F8Yx.xml * STM32G061F(6-8)Px.xml, STM32G061F8Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c index f593a55b18..23e4b6aa27 100644 --- a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c +++ b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G051G(6-8)Ux.xml, STM32G061G(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c index a62767f7c0..46312ec40a 100644 --- a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051K(6-8)Tx.xml, STM32G051K(6-8)Ux.xml * STM32G061K(6-8)Tx.xml, STM32G061K(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070CBT/PeripheralPins.c b/variants/STM32G0xx/G070CBT/PeripheralPins.c index 92295c63dd..d8d4ce06ab 100644 --- a/variants/STM32G0xx/G070CBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070CBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070KBT/PeripheralPins.c b/variants/STM32G0xx/G070KBT/PeripheralPins.c index 58a97ffe17..6eb15c6384 100644 --- a/variants/STM32G0xx/G070KBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070KBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070KBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070RBT/PeripheralPins.c b/variants/STM32G0xx/G070RBT/PeripheralPins.c index b742b6ddde..cd2814f365 100644 --- a/variants/STM32G0xx/G070RBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070RBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c index 9894f53112..8528d10422 100644 --- a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071C(6-8-B)Tx.xml, STM32G071C(6-8-B)Ux.xml * STM32G081CBTx.xml, STM32G081CBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c b/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c index dead2fcea8..803c7be88c 100644 --- a/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c +++ b/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071EBYx.xml, STM32G081EBYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c index b80e459a69..edd852c362 100644 --- a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c +++ b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071G(6-8-B)Ux.xml, STM32G081GBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c index fa458b5e05..7750563592 100644 --- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c +++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071G(8-B)UxN.xml, STM32G081GBUxN.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c index 543a91d29f..a0e017c65a 100644 --- a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071K(6-8-B)Tx.xml, STM32G071K(6-8-B)Ux.xml * STM32G081KBTx.xml, STM32G081KBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c index 3dc451b403..b69629cb93 100644 --- a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071K(8-B)TxN.xml, STM32G071K(8-B)UxN.xml * STM32G081KBTxN.xml, STM32G081KBUxN.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c index 75f64df49e..a3c36a53e8 100644 --- a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c +++ b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071R(6-8-B)Tx.xml, STM32G071RBIx.xml * STM32G081RBIx.xml, STM32G081RBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0CET/PeripheralPins.c b/variants/STM32G0xx/G0B0CET/PeripheralPins.c index a090980bb5..4b08387223 100644 --- a/variants/STM32G0xx/G0B0CET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0CET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0CETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0KET/PeripheralPins.c b/variants/STM32G0xx/G0B0KET/PeripheralPins.c index b0b300c67f..6c427cf261 100644 --- a/variants/STM32G0xx/G0B0KET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0KET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0KETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0RET/PeripheralPins.c b/variants/STM32G0xx/G0B0RET/PeripheralPins.c index 0783e0c92f..89f99a163d 100644 --- a/variants/STM32G0xx/G0B0RET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0RET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0RETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0VET/PeripheralPins.c b/variants/STM32G0xx/G0B0VET/PeripheralPins.c index 2a0adb1bdb..0a0c6e1106 100644 --- a/variants/STM32G0xx/G0B0VET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0VETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c index b7f9df5e39..b627b7fd06 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1C(B-C-E)Tx.xml, STM32G0B1C(B-C-E)Ux.xml * STM32G0C1C(C-E)Tx.xml, STM32G0C1C(C-E)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c index d3832384e1..12d46eacfb 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1C(B-C-E)TxN.xml, STM32G0B1C(B-C-E)UxN.xml * STM32G0C1C(C-E)TxN.xml, STM32G0C1C(C-E)UxN.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c index dfd011969e..d0b75fade4 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1K(B-C-E)Tx.xml, STM32G0B1K(B-C-E)Ux.xml * STM32G0C1K(C-E)Tx.xml, STM32G0C1K(C-E)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c index 202aae31be..8a4383a6b5 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1K(B-C-E)TxN.xml, STM32G0B1K(B-C-E)UxN.xml * STM32G0C1K(C-E)TxN.xml, STM32G0C1K(C-E)UxN.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c index c6c1a1b40c..c54e4c0f7a 100644 --- a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1M(B-C-E)Tx.xml, STM32G0C1M(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c index 0d003985bc..849f7d555e 100644 --- a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1NEYx.xml, STM32G0C1NEYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c index 34b85bbc64..6f2e460193 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1R(B-C-E)IxN.xml, STM32G0B1R(B-C-E)TxN.xml * STM32G0C1R(C-E)IxN.xml, STM32G0C1R(C-E)TxN.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c index 1443c84777..c7bbe382eb 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1R(B-C-E)Tx.xml, STM32G0C1R(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c index 391610de81..ecb5a246fd 100644 --- a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1V(B-C-E)Ix.xml, STM32G0B1V(B-C-E)Tx.xml * STM32G0C1V(C-E)Ix.xml, STM32G0C1V(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c index 1697068d61..a0fdf7f4db 100644 --- a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431C(6-8-B)Tx.xml, STM32G441CBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c index 682776afcd..bc472e1413 100644 --- a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c +++ b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431C(6-8-B)Ux.xml, STM32G441CBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c b/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c index c58bd4151b..6496f317c2 100644 --- a/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c +++ b/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431CBYx.xml, STM32G441CBYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c index fb8bb5e54c..5114eaa456 100644 --- a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c +++ b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G431K(6-8-B)Tx.xml, STM32G431K(6-8-B)Ux.xml * STM32G441KBTx.xml, STM32G441KBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c index 4e45a514d4..27c0d0466c 100644 --- a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431M(6-8-B)Tx.xml, STM32G441MBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)/PeripheralPins.c b/variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)/PeripheralPins.c index 694e7ba12b..6828758598 100644 --- a/variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G431R(6-8-B)Ix.xml, STM32G431R(6-8-B)Tx.xml * STM32G441RBIx.xml, STM32G441RBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c index 5ba15dbe84..28bfaa24f0 100644 --- a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431V(6-8-B)Tx.xml, STM32G441VBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c index 5fe4b4eec1..2257578d54 100644 --- a/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471C(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c b/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c index 44651f4e4e..94e632ced1 100644 --- a/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c +++ b/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471C(C-E)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c index e9074031cb..fc2fdd3133 100644 --- a/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471M(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471MEY/PeripheralPins.c b/variants/STM32G4xx/G471MEY/PeripheralPins.c index 4ca2e2d236..0d9a276dde 100644 --- a/variants/STM32G4xx/G471MEY/PeripheralPins.c +++ b/variants/STM32G4xx/G471MEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471MEYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c index a30a381197..5e89203f30 100644 --- a/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471Q(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c index 0ff346c759..8ddbf8f865 100644 --- a/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471R(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c b/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c index 892d1a449d..ad08e6b654 100644 --- a/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G471V(C-E)Hx.xml, STM32G471V(C-E)Ix.xml * STM32G471V(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c index 5f49537123..785d4a6902 100644 --- a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c +++ b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473C(B-C-E)Tx.xml, STM32G474C(B-C-E)Tx.xml * STM32G483CETx.xml, STM32G484CETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c index 946db51ab7..8925805808 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473C(B-C-E)Ux.xml, STM32G474C(B-C-E)Ux.xml * STM32G483CEUx.xml, STM32G484CEUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c index a036baea07..3d73d02409 100644 --- a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c +++ b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473M(B-C-E)Tx.xml, STM32G474M(B-C-E)Tx.xml * STM32G483METx.xml, STM32G484METx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c index 5f48af95a6..5d067cd448 100644 --- a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c +++ b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473MEYx.xml, STM32G474MEYx.xml * STM32G483MEYx.xml, STM32G484MEYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c index 42b247f28a..750b9642eb 100644 --- a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c +++ b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473P(B-C-E)Ix.xml, STM32G474P(B-C-E)Ix.xml * STM32G483PEIx.xml, STM32G484PEIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c b/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c index bd3ab4f054..a9e77f8236 100644 --- a/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c +++ b/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473Q(B-C-E)Tx.xml, STM32G474Q(B-C-E)Tx.xml * STM32G483QETx.xml, STM32G484QETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c b/variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c index 97c62a7e5b..402df8396e 100644 --- a/variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c +++ b/variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473R(B-C-E)Tx.xml, STM32G474R(B-C-E)Tx.xml * STM32G483RETx.xml, STM32G484RETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c index 58e11d78e3..f16ceef1be 100644 --- a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32G474V(B-C-E)Hx.xml, STM32G474V(B-C-E)Tx.xml * STM32G483VEHx.xml, STM32G483VETx.xml * STM32G484VEHx.xml, STM32G484VETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c index fee7d2bc04..016ff160ad 100644 --- a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c +++ b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491C(C-E)Tx.xml, STM32G4A1CETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c b/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c index c1e262a92b..f0e0781c74 100644 --- a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c +++ b/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491C(C-E)Ux.xml, STM32G4A1CEUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c index 21a0523a52..12cc13ad5a 100644 --- a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c +++ b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491K(C-E)Ux.xml, STM32G4A1KEUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c index 559a0065e3..444ab74eb7 100644 --- a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G491M(C-E)Sx.xml, STM32G491M(C-E)Tx.xml * STM32G4A1MESx.xml, STM32G4A1METx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)/PeripheralPins.c b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)/PeripheralPins.c index beb504a9f1..d6c4206b07 100644 --- a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)/PeripheralPins.c +++ b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G491R(C-E)Ix.xml, STM32G491R(C-E)Tx.xml * STM32G491REYx.xml, STM32G4A1REIx.xml * STM32G4A1RETx.xml, STM32G4A1REYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c index 192089fd0e..a917b0015c 100644 --- a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c +++ b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491V(C-E)Tx.xml, STM32G4A1VETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c index f6bc0386ae..23bf51b0e2 100644 --- a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c +++ b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503CBTx.xml, STM32H503CBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503EBY/PeripheralPins.c b/variants/STM32H5xx/H503EBY/PeripheralPins.c index 5afaedf6f3..8237f2f1c1 100644 --- a/variants/STM32H5xx/H503EBY/PeripheralPins.c +++ b/variants/STM32H5xx/H503EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503EBYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503KBU/PeripheralPins.c b/variants/STM32H5xx/H503KBU/PeripheralPins.c index 25cab80aa4..4f17b58eda 100644 --- a/variants/STM32H5xx/H503KBU/PeripheralPins.c +++ b/variants/STM32H5xx/H503KBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503KBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503RBT/PeripheralPins.c b/variants/STM32H5xx/H503RBT/PeripheralPins.c index 1e36de03c6..5cd984d790 100644 --- a/variants/STM32H5xx/H503RBT/PeripheralPins.c +++ b/variants/STM32H5xx/H503RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503RBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c index 532cc28305..84de66853c 100644 --- a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c +++ b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562AGIx.xml, STM32H562AIIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c index cd29035a1f..f3dd1f2df9 100644 --- a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H562IGKx.xml, STM32H562IGTx.xml * STM32H562IIKx.xml, STM32H562IITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c index abdd5e6de5..4b2c91c25b 100644 --- a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGTx.xml, STM32H562RITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c index d5b567e1a7..bdb471f39d 100644 --- a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGVx.xml, STM32H562RIVx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c index 2f936e3a7a..21459abe93 100644 --- a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562VGTx.xml, STM32H562VITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c index 522dea4447..bc2c2a3718 100644 --- a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562ZGTx.xml, STM32H562ZITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563A(G-I)I/CMakeLists.txt b/variants/STM32H5xx/H563A(G-I)I/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H563A(G-I)I/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563A(G-I)I/PeripheralPins.c b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563A(G-I)I/PeripheralPins.c rename to variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c index 27dd73dcd4..cd0b480efc 100644 --- a/variants/STM32H5xx/H563A(G-I)I/PeripheralPins.c +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c @@ -12,7 +12,8 @@ */ /* * Automatically generated from STM32H563AGIx.xml, STM32H563AIIx.xml - * CubeMX DB release 6.0.90 + * STM32H573AIIx.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563A(G-I)I/PinNamesVar.h b/variants/STM32H5xx/H563A(G-I)I_H573AII/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563A(G-I)I/PinNamesVar.h rename to variants/STM32H5xx/H563A(G-I)I_H573AII/PinNamesVar.h diff --git a/variants/STM32H5xx/H563A(G-I)I/boards_entry.txt b/variants/STM32H5xx/H563A(G-I)I_H573AII/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563A(G-I)I/boards_entry.txt rename to variants/STM32H5xx/H563A(G-I)I_H573AII/boards_entry.txt index 65884e8614..a6d0f8a4b3 100644 --- a/variants/STM32H5xx/H563A(G-I)I/boards_entry.txt +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563AGIX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563AGIX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563AGIX.build.board=GENERIC_H563AGIX GenH5.menu.pnum.GENERIC_H563AGIX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563AGIX.build.variant=STM32H5xx/H563A(G-I)I +GenH5.menu.pnum.GENERIC_H563AGIX.build.variant=STM32H5xx/H563A(G-I)I_H573AII # Generic H563AIIx GenH5.menu.pnum.GENERIC_H563AIIX=Generic H563AIIx @@ -17,5 +17,13 @@ GenH5.menu.pnum.GENERIC_H563AIIX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563AIIX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563AIIX.build.board=GENERIC_H563AIIX GenH5.menu.pnum.GENERIC_H563AIIX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563AIIX.build.variant=STM32H5xx/H563A(G-I)I +GenH5.menu.pnum.GENERIC_H563AIIX.build.variant=STM32H5xx/H563A(G-I)I_H573AII + +# Generic H573AIIx +GenH5.menu.pnum.GENERIC_H573AIIX=Generic H573AIIx +GenH5.menu.pnum.GENERIC_H573AIIX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573AIIX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573AIIX.build.board=GENERIC_H573AIIX +GenH5.menu.pnum.GENERIC_H573AIIX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573AIIX.build.variant=STM32H5xx/H563A(G-I)I_H573AII diff --git a/variants/STM32H5xx/H563A(G-I)I/generic_clock.c b/variants/STM32H5xx/H563A(G-I)I_H573AII/generic_clock.c similarity index 94% rename from variants/STM32H5xx/H563A(G-I)I/generic_clock.c rename to variants/STM32H5xx/H563A(G-I)I_H573AII/generic_clock.c index a70d6bdff6..5bee13d537 100644 --- a/variants/STM32H5xx/H563A(G-I)I/generic_clock.c +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/generic_clock.c @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563AGIX) || defined(ARDUINO_GENERIC_H563AIIX) +#if defined(ARDUINO_GENERIC_H563AGIX) || defined(ARDUINO_GENERIC_H563AIIX) ||\ + defined(ARDUINO_GENERIC_H573AIIX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563A(G-I)I/variant_generic.cpp b/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.cpp similarity index 98% rename from variants/STM32H5xx/H563A(G-I)I/variant_generic.cpp rename to variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.cpp index e87b94786a..493eed1506 100644 --- a/variants/STM32H5xx/H563A(G-I)I/variant_generic.cpp +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.cpp @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563AGIX) || defined(ARDUINO_GENERIC_H563AIIX) +#if defined(ARDUINO_GENERIC_H563AGIX) || defined(ARDUINO_GENERIC_H563AIIX) ||\ + defined(ARDUINO_GENERIC_H573AIIX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563A(G-I)I/variant_generic.h b/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563A(G-I)I/variant_generic.h rename to variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.h diff --git a/variants/STM32H5xx/H563AIIxQ/CMakeLists.txt b/variants/STM32H5xx/H563AIIxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H563AIIxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563AIIxQ/PeripheralPins.c b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563AIIxQ/PeripheralPins.c rename to variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c index daa191ba12..d0f602895e 100644 --- a/variants/STM32H5xx/H563AIIxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563AIIxQ.xml - * CubeMX DB release 6.0.90 + * Automatically generated from STM32H563AIIxQ.xml, STM32H573AIIxQ.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563AIIxQ/PinNamesVar.h b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563AIIxQ/PinNamesVar.h rename to variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PinNamesVar.h diff --git a/variants/STM32H5xx/H563AIIxQ/boards_entry.txt b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/boards_entry.txt similarity index 59% rename from variants/STM32H5xx/H563AIIxQ/boards_entry.txt rename to variants/STM32H5xx/H563AIIxQ_H573AIIxQ/boards_entry.txt index 9797c155d5..1e9e8114db 100644 --- a/variants/STM32H5xx/H563AIIxQ/boards_entry.txt +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/boards_entry.txt @@ -9,5 +9,13 @@ GenH5.menu.pnum.GENERIC_H563AIIXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563AIIXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563AIIXQ.build.board=GENERIC_H563AIIXQ GenH5.menu.pnum.GENERIC_H563AIIXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563AIIXQ.build.variant=STM32H5xx/H563AIIxQ +GenH5.menu.pnum.GENERIC_H563AIIXQ.build.variant=STM32H5xx/H563AIIxQ_H573AIIxQ + +# Generic H573AIIxQ +GenH5.menu.pnum.GENERIC_H573AIIXQ=Generic H573AIIxQ +GenH5.menu.pnum.GENERIC_H573AIIXQ.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573AIIXQ.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573AIIXQ.build.board=GENERIC_H573AIIXQ +GenH5.menu.pnum.GENERIC_H573AIIXQ.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573AIIXQ.build.variant=STM32H5xx/H563AIIxQ_H573AIIxQ diff --git a/variants/STM32H5xx/H563IITxQ/generic_clock.c b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/generic_clock.c similarity index 91% rename from variants/STM32H5xx/H563IITxQ/generic_clock.c rename to variants/STM32H5xx/H563AIIxQ_H573AIIxQ/generic_clock.c index c7322cb46f..c2db916941 100644 --- a/variants/STM32H5xx/H563IITxQ/generic_clock.c +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/generic_clock.c @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563IITXQ) +#if defined(ARDUINO_GENERIC_H563AIIXQ) || defined(ARDUINO_GENERIC_H573AIIXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563AIIxQ/variant_generic.cpp b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563AIIxQ/variant_generic.cpp rename to variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.cpp index 880f7ce59c..83bb5a4b95 100644 --- a/variants/STM32H5xx/H563AIIxQ/variant_generic.cpp +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563AIIXQ) +#if defined(ARDUINO_GENERIC_H563AIIXQ) || defined(ARDUINO_GENERIC_H573AIIXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563AIIxQ/variant_generic.h b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563AIIxQ/variant_generic.h rename to variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.h diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)/CMakeLists.txt b/variants/STM32H5xx/H563I(G-I)(K-T)/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H563I(G-I)(K-T)/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)/PeripheralPins.c b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563I(G-I)(K-T)/PeripheralPins.c rename to variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c index 1877ad1f9b..921f4b3d82 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c @@ -13,7 +13,8 @@ /* * Automatically generated from STM32H563IGKx.xml, STM32H563IGTx.xml * STM32H563IIKx.xml, STM32H563IITx.xml - * CubeMX DB release 6.0.90 + * STM32H573IIKx.xml, STM32H573IITx.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)/PinNamesVar.h b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563I(G-I)(K-T)/PinNamesVar.h rename to variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PinNamesVar.h diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)/boards_entry.txt b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/boards_entry.txt similarity index 66% rename from variants/STM32H5xx/H563I(G-I)(K-T)/boards_entry.txt rename to variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/boards_entry.txt index e54004a38d..796d2d201a 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)/boards_entry.txt +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563IGKX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563IGKX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IGKX.build.board=GENERIC_H563IGKX GenH5.menu.pnum.GENERIC_H563IGKX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IGKX.build.variant=STM32H5xx/H563I(G-I)(K-T) +GenH5.menu.pnum.GENERIC_H563IGKX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) # Generic H563IGTx GenH5.menu.pnum.GENERIC_H563IGTX=Generic H563IGTx @@ -17,7 +17,7 @@ GenH5.menu.pnum.GENERIC_H563IGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563IGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IGTX.build.board=GENERIC_H563IGTX GenH5.menu.pnum.GENERIC_H563IGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IGTX.build.variant=STM32H5xx/H563I(G-I)(K-T) +GenH5.menu.pnum.GENERIC_H563IGTX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) # Generic H563IIKx GenH5.menu.pnum.GENERIC_H563IIKX=Generic H563IIKx @@ -25,7 +25,7 @@ GenH5.menu.pnum.GENERIC_H563IIKX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IIKX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IIKX.build.board=GENERIC_H563IIKX GenH5.menu.pnum.GENERIC_H563IIKX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IIKX.build.variant=STM32H5xx/H563I(G-I)(K-T) +GenH5.menu.pnum.GENERIC_H563IIKX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) # Generic H563IITx GenH5.menu.pnum.GENERIC_H563IITX=Generic H563IITx @@ -33,5 +33,21 @@ GenH5.menu.pnum.GENERIC_H563IITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IITX.build.board=GENERIC_H563IITX GenH5.menu.pnum.GENERIC_H563IITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IITX.build.variant=STM32H5xx/H563I(G-I)(K-T) +GenH5.menu.pnum.GENERIC_H563IITX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) + +# Generic H573IIKx +GenH5.menu.pnum.GENERIC_H573IIKX=Generic H573IIKx +GenH5.menu.pnum.GENERIC_H573IIKX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573IIKX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573IIKX.build.board=GENERIC_H573IIKX +GenH5.menu.pnum.GENERIC_H573IIKX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573IIKX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) + +# Generic H573IITx +GenH5.menu.pnum.GENERIC_H573IITX=Generic H573IITx +GenH5.menu.pnum.GENERIC_H573IITX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573IITX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573IITX.build.board=GENERIC_H573IITX +GenH5.menu.pnum.GENERIC_H573IITX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573IITX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)/generic_clock.c b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/generic_clock.c similarity index 91% rename from variants/STM32H5xx/H563I(G-I)(K-T)/generic_clock.c rename to variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/generic_clock.c index 00fee101c2..941ef32ee7 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)/generic_clock.c +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/generic_clock.c @@ -11,7 +11,8 @@ ******************************************************************************* */ #if defined(ARDUINO_GENERIC_H563IGKX) || defined(ARDUINO_GENERIC_H563IGTX) ||\ - defined(ARDUINO_GENERIC_H563IIKX) || defined(ARDUINO_GENERIC_H563IITX) + defined(ARDUINO_GENERIC_H563IIKX) || defined(ARDUINO_GENERIC_H563IITX) ||\ + defined(ARDUINO_GENERIC_H573IIKX) || defined(ARDUINO_GENERIC_H573IITX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.cpp b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.cpp rename to variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.cpp index 6c09ffed3a..6e4b482a27 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.cpp +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.cpp @@ -11,7 +11,8 @@ ******************************************************************************* */ #if defined(ARDUINO_GENERIC_H563IGKX) || defined(ARDUINO_GENERIC_H563IGTX) ||\ - defined(ARDUINO_GENERIC_H563IIKX) || defined(ARDUINO_GENERIC_H563IITX) + defined(ARDUINO_GENERIC_H563IIKX) || defined(ARDUINO_GENERIC_H563IITX) ||\ + defined(ARDUINO_GENERIC_H573IIKX) || defined(ARDUINO_GENERIC_H573IITX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.h b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.h rename to variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.h diff --git a/variants/STM32H5xx/H563IIKxQ/CMakeLists.txt b/variants/STM32H5xx/H563IIKxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H563IIKxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563IIKxQ/generic_clock.c b/variants/STM32H5xx/H563IIKxQ/generic_clock.c deleted file mode 100644 index 68a5da81e2..0000000000 --- a/variants/STM32H5xx/H563IIKxQ/generic_clock.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H563IIKXQ) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - - /** Configure the main internal regulator output voltage - */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); - - while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI - | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; - RCC_OscInitStruct.CSIState = RCC_CSI_ON; - RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 4; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; - RCC_OscInitStruct.PLL.PLLFRACN = 0; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - Error_Handler(); - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 - | RCC_CLOCKTYPE_PCLK3; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - Error_Handler(); - } - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 - | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; - PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { - Error_Handler(); - } -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H563IIKxQ/variant_generic.cpp b/variants/STM32H5xx/H563IIKxQ/variant_generic.cpp deleted file mode 100644 index 58977c2352..0000000000 --- a/variants/STM32H5xx/H563IIKxQ/variant_generic.cpp +++ /dev/null @@ -1,183 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H563IIKXQ) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_9, // D25 - PB_10, // D26 - PB_11, // D27 - PB_12, // D28 - PB_13, // D29 - PB_14, // D30 - PB_15, // D31 - PC_0, // D32/A10 - PC_1, // D33/A11 - PC_2, // D34/A12 - PC_3, // D35/A13 - PC_4, // D36/A14 - PC_5, // D37/A15 - PC_6, // D38 - PC_7, // D39 - PC_8, // D40 - PC_9, // D41 - PC_10, // D42 - PC_11, // D43 - PC_12, // D44 - PC_13, // D45 - PC_14, // D46 - PC_15, // D47 - PD_0, // D48 - PD_1, // D49 - PD_2, // D50 - PD_3, // D51 - PD_4, // D52 - PD_5, // D53 - PD_6, // D54 - PD_7, // D55 - PD_8, // D56 - PD_9, // D57 - PD_10, // D58 - PD_11, // D59 - PD_12, // D60 - PD_13, // D61 - PD_14, // D62 - PD_15, // D63 - PE_0, // D64 - PE_1, // D65 - PE_2, // D66 - PE_3, // D67 - PE_4, // D68 - PE_5, // D69 - PE_6, // D70 - PE_7, // D71 - PE_8, // D72 - PE_9, // D73 - PE_10, // D74 - PE_11, // D75 - PE_12, // D76 - PE_13, // D77 - PE_14, // D78 - PE_15, // D79 - PF_0, // D80 - PF_1, // D81 - PF_2, // D82 - PF_3, // D83 - PF_4, // D84 - PF_5, // D85 - PF_6, // D86 - PF_7, // D87 - PF_8, // D88 - PF_9, // D89 - PF_10, // D90 - PF_11, // D91/A16 - PF_12, // D92/A17 - PF_13, // D93/A18 - PF_14, // D94/A19 - PF_15, // D95 - PG_0, // D96 - PG_1, // D97 - PG_2, // D98 - PG_3, // D99 - PG_4, // D100 - PG_5, // D101 - PG_6, // D102 - PG_7, // D103 - PG_8, // D104 - PG_9, // D105 - PG_10, // D106 - PG_11, // D107 - PG_12, // D108 - PG_13, // D109 - PG_14, // D110 - PG_15, // D111 - PH_0, // D112 - PH_1, // D113 - PH_2, // D114 - PH_3, // D115 - PH_4, // D116 - PH_5, // D117 - PH_6, // D118 - PH_7, // D119 - PH_8, // D120 - PH_9, // D121 - PH_10, // D122 - PH_11, // D123 - PH_12, // D124 - PH_13, // D125 - PH_14, // D126 - PH_15, // D127 - PI_1, // D128 - PI_2, // D129 - PI_3, // D130 - PI_4, // D131 - PI_5, // D132 - PI_6, // D133 - PI_7, // D134 - PI_8, // D135 - PI_9, // D136 - PI_10, // D137 - PI_11 // D138 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 32, // A10, PC0 - 33, // A11, PC1 - 34, // A12, PC2 - 35, // A13, PC3 - 36, // A14, PC4 - 37, // A15, PC5 - 91, // A16, PF11 - 92, // A17, PF12 - 93, // A18, PF13 - 94 // A19, PF14 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H563IIKxQ/PeripheralPins.c b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563IIKxQ/PeripheralPins.c rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c index 8781fb9713..e721763c88 100644 --- a/variants/STM32H5xx/H563IIKxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563IIKxQ.xml - * CubeMX DB release 6.0.90 + * Automatically generated from STM32H563IIKxQ.xml, STM32H573IIKxQ.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H573IIKxQ/PeripheralPins_STM32H573I_DK.c b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins_STM32H573I_DK.c similarity index 100% rename from variants/STM32H5xx/H573IIKxQ/PeripheralPins_STM32H573I_DK.c rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins_STM32H573I_DK.c diff --git a/variants/STM32H5xx/H563IIKxQ/PinNamesVar.h b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563IIKxQ/PinNamesVar.h rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PinNamesVar.h diff --git a/variants/STM32H5xx/H563IIKxQ/boards_entry.txt b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/boards_entry.txt similarity index 59% rename from variants/STM32H5xx/H563IIKxQ/boards_entry.txt rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/boards_entry.txt index 8783be74c9..4bba114ae0 100644 --- a/variants/STM32H5xx/H563IIKxQ/boards_entry.txt +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/boards_entry.txt @@ -9,5 +9,13 @@ GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IIKXQ.build.board=GENERIC_H563IIKXQ GenH5.menu.pnum.GENERIC_H563IIKXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IIKXQ.build.variant=STM32H5xx/H563IIKxQ +GenH5.menu.pnum.GENERIC_H563IIKXQ.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ + +# Generic H573IIKxQ +GenH5.menu.pnum.GENERIC_H573IIKXQ=Generic H573IIKxQ +GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573IIKXQ.build.board=GENERIC_H573IIKXQ +GenH5.menu.pnum.GENERIC_H573IIKXQ.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573IIKXQ.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ diff --git a/variants/STM32H5xx/H573IIKxQ/generic_clock.c b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c similarity index 97% rename from variants/STM32H5xx/H573IIKxQ/generic_clock.c rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c index 2f63be49ff..708820d6df 100644 --- a/variants/STM32H5xx/H573IIKxQ/generic_clock.c +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H573IIKXQ) +#if defined(ARDUINO_GENERIC_H563IIKXQ) || defined(ARDUINO_GENERIC_H573IIKXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563IIKxQ/ldscript.ld b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/ldscript.ld similarity index 100% rename from variants/STM32H5xx/H563IIKxQ/ldscript.ld rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/ldscript.ld diff --git a/variants/STM32H5xx/H573IIKxQ/variant_STM32H573I_DK.cpp b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp similarity index 100% rename from variants/STM32H5xx/H573IIKxQ/variant_STM32H573I_DK.cpp rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp diff --git a/variants/STM32H5xx/H573IIKxQ/variant_STM32H573I_DK.h b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.h similarity index 100% rename from variants/STM32H5xx/H573IIKxQ/variant_STM32H573I_DK.h rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.h diff --git a/variants/STM32H5xx/H573IIKxQ/variant_generic.cpp b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H573IIKxQ/variant_generic.cpp rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.cpp index fc373d83ca..3c7f322f5d 100644 --- a/variants/STM32H5xx/H573IIKxQ/variant_generic.cpp +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H573IIKXQ) +#if defined(ARDUINO_GENERIC_H563IIKXQ) || defined(ARDUINO_GENERIC_H573IIKXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563IIKxQ/variant_generic.h b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563IIKxQ/variant_generic.h rename to variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.h diff --git a/variants/STM32H5xx/H563IITxQ/CMakeLists.txt b/variants/STM32H5xx/H563IITxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H563IITxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563IITxQ/variant_generic.cpp b/variants/STM32H5xx/H563IITxQ/variant_generic.cpp deleted file mode 100644 index 6e4b701bd8..0000000000 --- a/variants/STM32H5xx/H563IITxQ/variant_generic.cpp +++ /dev/null @@ -1,180 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H563IITXQ) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_9, // D25 - PB_10, // D26 - PB_11, // D27 - PB_12, // D28 - PB_13, // D29 - PB_14, // D30 - PB_15, // D31 - PC_0, // D32/A10 - PC_1, // D33/A11 - PC_2, // D34/A12 - PC_3, // D35/A13 - PC_4, // D36/A14 - PC_5, // D37/A15 - PC_6, // D38 - PC_7, // D39 - PC_8, // D40 - PC_9, // D41 - PC_10, // D42 - PC_11, // D43 - PC_12, // D44 - PC_13, // D45 - PC_14, // D46 - PC_15, // D47 - PD_0, // D48 - PD_1, // D49 - PD_2, // D50 - PD_3, // D51 - PD_4, // D52 - PD_5, // D53 - PD_6, // D54 - PD_7, // D55 - PD_8, // D56 - PD_9, // D57 - PD_10, // D58 - PD_11, // D59 - PD_12, // D60 - PD_13, // D61 - PD_14, // D62 - PD_15, // D63 - PE_0, // D64 - PE_1, // D65 - PE_2, // D66 - PE_3, // D67 - PE_4, // D68 - PE_5, // D69 - PE_6, // D70 - PE_7, // D71 - PE_8, // D72 - PE_9, // D73 - PE_10, // D74 - PE_11, // D75 - PE_12, // D76 - PE_13, // D77 - PE_14, // D78 - PE_15, // D79 - PF_0, // D80 - PF_1, // D81 - PF_2, // D82 - PF_3, // D83 - PF_4, // D84 - PF_5, // D85 - PF_6, // D86 - PF_7, // D87 - PF_8, // D88 - PF_9, // D89 - PF_11, // D90/A16 - PF_12, // D91/A17 - PF_13, // D92/A18 - PF_14, // D93/A19 - PF_15, // D94 - PG_0, // D95 - PG_1, // D96 - PG_2, // D97 - PG_3, // D98 - PG_4, // D99 - PG_5, // D100 - PG_6, // D101 - PG_7, // D102 - PG_8, // D103 - PG_9, // D104 - PG_10, // D105 - PG_11, // D106 - PG_12, // D107 - PG_13, // D108 - PG_14, // D109 - PG_15, // D110 - PH_0, // D111 - PH_1, // D112 - PH_2, // D113 - PH_3, // D114 - PH_6, // D115 - PH_7, // D116 - PH_9, // D117 - PH_10, // D118 - PH_11, // D119 - PH_12, // D120 - PH_13, // D121 - PH_14, // D122 - PH_15, // D123 - PI_0, // D124 - PI_1, // D125 - PI_2, // D126 - PI_3, // D127 - PI_4, // D128 - PI_5, // D129 - PI_6, // D130 - PI_7, // D131 - PI_8, // D132 - PI_9, // D133 - PI_10, // D134 - PI_11 // D135 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 32, // A10, PC0 - 33, // A11, PC1 - 34, // A12, PC2 - 35, // A13, PC3 - 36, // A14, PC4 - 37, // A15, PC5 - 90, // A16, PF11 - 91, // A17, PF12 - 92, // A18, PF13 - 93 // A19, PF14 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H563IITxQ/PeripheralPins.c b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563IITxQ/PeripheralPins.c rename to variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c index bff5fbcc78..22ca02f65b 100644 --- a/variants/STM32H5xx/H563IITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563IITxQ.xml - * CubeMX DB release 6.0.90 + * Automatically generated from STM32H563IITxQ.xml, STM32H573IITxQ.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563IITxQ/PinNamesVar.h b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563IITxQ/PinNamesVar.h rename to variants/STM32H5xx/H563IITxQ_H573IITxQ/PinNamesVar.h diff --git a/variants/STM32H5xx/H563IITxQ/boards_entry.txt b/variants/STM32H5xx/H563IITxQ_H573IITxQ/boards_entry.txt similarity index 59% rename from variants/STM32H5xx/H563IITxQ/boards_entry.txt rename to variants/STM32H5xx/H563IITxQ_H573IITxQ/boards_entry.txt index 97a0ea5b98..f6d0d1569c 100644 --- a/variants/STM32H5xx/H563IITxQ/boards_entry.txt +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/boards_entry.txt @@ -9,5 +9,13 @@ GenH5.menu.pnum.GENERIC_H563IITXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IITXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IITXQ.build.board=GENERIC_H563IITXQ GenH5.menu.pnum.GENERIC_H563IITXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IITXQ.build.variant=STM32H5xx/H563IITxQ +GenH5.menu.pnum.GENERIC_H563IITXQ.build.variant=STM32H5xx/H563IITxQ_H573IITxQ + +# Generic H573IITxQ +GenH5.menu.pnum.GENERIC_H573IITXQ=Generic H573IITxQ +GenH5.menu.pnum.GENERIC_H573IITXQ.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573IITXQ.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573IITXQ.build.board=GENERIC_H573IITXQ +GenH5.menu.pnum.GENERIC_H573IITXQ.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573IITXQ.build.variant=STM32H5xx/H563IITxQ_H573IITxQ diff --git a/variants/STM32H5xx/H563AIIxQ/generic_clock.c b/variants/STM32H5xx/H563IITxQ_H573IITxQ/generic_clock.c similarity index 91% rename from variants/STM32H5xx/H563AIIxQ/generic_clock.c rename to variants/STM32H5xx/H563IITxQ_H573IITxQ/generic_clock.c index 8659be2dce..7719cc5de0 100644 --- a/variants/STM32H5xx/H563AIIxQ/generic_clock.c +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/generic_clock.c @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563AIIXQ) +#if defined(ARDUINO_GENERIC_H563IITXQ) || defined(ARDUINO_GENERIC_H573IITXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H573IITxQ/variant_generic.cpp b/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H573IITxQ/variant_generic.cpp rename to variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.cpp index 2c34bbc623..d723d86caa 100644 --- a/variants/STM32H5xx/H573IITxQ/variant_generic.cpp +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H573IITXQ) +#if defined(ARDUINO_GENERIC_H563IITXQ) || defined(ARDUINO_GENERIC_H573IITXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563IITxQ/variant_generic.h b/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563IITxQ/variant_generic.h rename to variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.h diff --git a/variants/STM32H5xx/H563MIYxQ/CMakeLists.txt b/variants/STM32H5xx/H563MIYxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H563MIYxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563MIYxQ/variant_generic.cpp b/variants/STM32H5xx/H563MIYxQ/variant_generic.cpp deleted file mode 100644 index 8691ee0278..0000000000 --- a/variants/STM32H5xx/H563MIYxQ/variant_generic.cpp +++ /dev/null @@ -1,97 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H563MIYXQ) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_10, // D25 - PB_12, // D26 - PB_13, // D27 - PB_14, // D28 - PB_15, // D29 - PC_0, // D30/A10 - PC_1, // D31/A11 - PC_2, // D32/A12 - PC_3, // D33/A13 - PC_4, // D34/A14 - PC_5, // D35/A15 - PC_6, // D36 - PC_7, // D37 - PC_8, // D38 - PC_9, // D39 - PC_10, // D40 - PC_11, // D41 - PC_12, // D42 - PC_13, // D43 - PC_14, // D44 - PC_15, // D45 - PD_0, // D46 - PD_1, // D47 - PD_2, // D48 - PD_14, // D49 - PD_15, // D50 - PE_7, // D51 - PE_8, // D52 - PE_9, // D53 - PE_10, // D54 - PH_0, // D55 - PH_1 // D56 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 30, // A10, PC0 - 31, // A11, PC1 - 32, // A12, PC2 - 33, // A13, PC3 - 34, // A14, PC4 - 35 // A15, PC5 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H563MIYxQ/PeripheralPins.c b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563MIYxQ/PeripheralPins.c rename to variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c index 4f39380c58..eb57d1a9d0 100644 --- a/variants/STM32H5xx/H563MIYxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563MIYxQ.xml - * CubeMX DB release 6.0.90 + * Automatically generated from STM32H563MIYxQ.xml, STM32H573MIYxQ.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563MIYxQ/PinNamesVar.h b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563MIYxQ/PinNamesVar.h rename to variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h diff --git a/variants/STM32H5xx/H563MIYxQ/boards_entry.txt b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/boards_entry.txt similarity index 59% rename from variants/STM32H5xx/H563MIYxQ/boards_entry.txt rename to variants/STM32H5xx/H563MIYxQ_H573MIYxQ/boards_entry.txt index 21ec764406..b6a151fc07 100644 --- a/variants/STM32H5xx/H563MIYxQ/boards_entry.txt +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/boards_entry.txt @@ -9,5 +9,13 @@ GenH5.menu.pnum.GENERIC_H563MIYXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563MIYXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563MIYXQ.build.board=GENERIC_H563MIYXQ GenH5.menu.pnum.GENERIC_H563MIYXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563MIYXQ.build.variant=STM32H5xx/H563MIYxQ +GenH5.menu.pnum.GENERIC_H563MIYXQ.build.variant=STM32H5xx/H563MIYxQ_H573MIYxQ + +# Generic H573MIYxQ +GenH5.menu.pnum.GENERIC_H573MIYXQ=Generic H573MIYxQ +GenH5.menu.pnum.GENERIC_H573MIYXQ.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573MIYXQ.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573MIYXQ.build.board=GENERIC_H573MIYXQ +GenH5.menu.pnum.GENERIC_H573MIYXQ.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573MIYXQ.build.variant=STM32H5xx/H563MIYxQ_H573MIYxQ diff --git a/variants/STM32H5xx/H563MIYxQ/generic_clock.c b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/generic_clock.c similarity index 91% rename from variants/STM32H5xx/H563MIYxQ/generic_clock.c rename to variants/STM32H5xx/H563MIYxQ_H573MIYxQ/generic_clock.c index 01bd75bd49..273a5c2e75 100644 --- a/variants/STM32H5xx/H563MIYxQ/generic_clock.c +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/generic_clock.c @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563MIYXQ) +#if defined(ARDUINO_GENERIC_H563MIYXQ) || defined(ARDUINO_GENERIC_H573MIYXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H573MIYxQ/variant_generic.cpp b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.cpp similarity index 96% rename from variants/STM32H5xx/H573MIYxQ/variant_generic.cpp rename to variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.cpp index 0f52f3f205..ff92840911 100644 --- a/variants/STM32H5xx/H573MIYxQ/variant_generic.cpp +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H573MIYXQ) +#if defined(ARDUINO_GENERIC_H563MIYXQ) || defined(ARDUINO_GENERIC_H573MIYXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563MIYxQ/variant_generic.h b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563MIYxQ/variant_generic.h rename to variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.h diff --git a/variants/STM32H5xx/H563R(G-I)T/CMakeLists.txt b/variants/STM32H5xx/H563R(G-I)T/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H563R(G-I)T/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563R(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563R(G-I)T/PeripheralPins.c rename to variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c index f1ed25238e..9d232a66f6 100644 --- a/variants/STM32H5xx/H563R(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c @@ -12,7 +12,8 @@ */ /* * Automatically generated from STM32H563RGTx.xml, STM32H563RITx.xml - * CubeMX DB release 6.0.90 + * STM32H573RITx.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563R(G-I)T/PinNamesVar.h b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563R(G-I)T/PinNamesVar.h rename to variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h diff --git a/variants/STM32H5xx/H563R(G-I)T/boards_entry.txt b/variants/STM32H5xx/H563R(G-I)T_H573RIT/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563R(G-I)T/boards_entry.txt rename to variants/STM32H5xx/H563R(G-I)T_H573RIT/boards_entry.txt index f7f0eb2ff5..ac5a9663f4 100644 --- a/variants/STM32H5xx/H563R(G-I)T/boards_entry.txt +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563RGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563RGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563RGTX.build.board=GENERIC_H563RGTX GenH5.menu.pnum.GENERIC_H563RGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563RGTX.build.variant=STM32H5xx/H563R(G-I)T +GenH5.menu.pnum.GENERIC_H563RGTX.build.variant=STM32H5xx/H563R(G-I)T_H573RIT # Generic H563RITx GenH5.menu.pnum.GENERIC_H563RITX=Generic H563RITx @@ -17,5 +17,13 @@ GenH5.menu.pnum.GENERIC_H563RITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563RITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563RITX.build.board=GENERIC_H563RITX GenH5.menu.pnum.GENERIC_H563RITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563RITX.build.variant=STM32H5xx/H563R(G-I)T +GenH5.menu.pnum.GENERIC_H563RITX.build.variant=STM32H5xx/H563R(G-I)T_H573RIT + +# Generic H573RITx +GenH5.menu.pnum.GENERIC_H573RITX=Generic H573RITx +GenH5.menu.pnum.GENERIC_H573RITX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573RITX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573RITX.build.board=GENERIC_H573RITX +GenH5.menu.pnum.GENERIC_H573RITX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573RITX.build.variant=STM32H5xx/H563R(G-I)T_H573RIT diff --git a/variants/STM32H5xx/H563R(G-I)T/generic_clock.c b/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c similarity index 94% rename from variants/STM32H5xx/H563R(G-I)T/generic_clock.c rename to variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c index 42890297f9..f68f7375d1 100644 --- a/variants/STM32H5xx/H563R(G-I)T/generic_clock.c +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563RGTX) || defined(ARDUINO_GENERIC_H563RITX) +#if defined(ARDUINO_GENERIC_H563RGTX) || defined(ARDUINO_GENERIC_H563RITX) ||\ + defined(ARDUINO_GENERIC_H573RITX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563R(G-I)T/variant_generic.cpp b/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563R(G-I)T/variant_generic.cpp rename to variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.cpp index 1bcad42048..366177811b 100644 --- a/variants/STM32H5xx/H563R(G-I)T/variant_generic.cpp +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.cpp @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563RGTX) || defined(ARDUINO_GENERIC_H563RITX) +#if defined(ARDUINO_GENERIC_H563RGTX) || defined(ARDUINO_GENERIC_H563RITX) ||\ + defined(ARDUINO_GENERIC_H573RITX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563R(G-I)T/variant_generic.h b/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563R(G-I)T/variant_generic.h rename to variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.h diff --git a/variants/STM32H5xx/H563R(G-I)V/CMakeLists.txt b/variants/STM32H5xx/H563R(G-I)V/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H563R(G-I)V/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563R(G-I)V/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563R(G-I)V/PeripheralPins.c rename to variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c index e6f0f32818..e2cde3d7fa 100644 --- a/variants/STM32H5xx/H563R(G-I)V/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c @@ -12,7 +12,8 @@ */ /* * Automatically generated from STM32H563RGVx.xml, STM32H563RIVx.xml - * CubeMX DB release 6.0.90 + * STM32H573RIVx.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563R(G-I)V/PinNamesVar.h b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563R(G-I)V/PinNamesVar.h rename to variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h diff --git a/variants/STM32H5xx/H563R(G-I)V/boards_entry.txt b/variants/STM32H5xx/H563R(G-I)V_H573RIV/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563R(G-I)V/boards_entry.txt rename to variants/STM32H5xx/H563R(G-I)V_H573RIV/boards_entry.txt index 11cbf3b8d3..bc69ec98dd 100644 --- a/variants/STM32H5xx/H563R(G-I)V/boards_entry.txt +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563RGVX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563RGVX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563RGVX.build.board=GENERIC_H563RGVX GenH5.menu.pnum.GENERIC_H563RGVX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563RGVX.build.variant=STM32H5xx/H563R(G-I)V +GenH5.menu.pnum.GENERIC_H563RGVX.build.variant=STM32H5xx/H563R(G-I)V_H573RIV # Generic H563RIVx GenH5.menu.pnum.GENERIC_H563RIVX=Generic H563RIVx @@ -17,5 +17,13 @@ GenH5.menu.pnum.GENERIC_H563RIVX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563RIVX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563RIVX.build.board=GENERIC_H563RIVX GenH5.menu.pnum.GENERIC_H563RIVX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563RIVX.build.variant=STM32H5xx/H563R(G-I)V +GenH5.menu.pnum.GENERIC_H563RIVX.build.variant=STM32H5xx/H563R(G-I)V_H573RIV + +# Generic H573RIVx +GenH5.menu.pnum.GENERIC_H573RIVX=Generic H573RIVx +GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573RIVX.build.board=GENERIC_H573RIVX +GenH5.menu.pnum.GENERIC_H573RIVX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573RIVX.build.variant=STM32H5xx/H563R(G-I)V_H573RIV diff --git a/variants/STM32H5xx/H563R(G-I)V/generic_clock.c b/variants/STM32H5xx/H563R(G-I)V_H573RIV/generic_clock.c similarity index 94% rename from variants/STM32H5xx/H563R(G-I)V/generic_clock.c rename to variants/STM32H5xx/H563R(G-I)V_H573RIV/generic_clock.c index cf925e7f1a..7af96324c1 100644 --- a/variants/STM32H5xx/H563R(G-I)V/generic_clock.c +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/generic_clock.c @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563RGVX) || defined(ARDUINO_GENERIC_H563RIVX) +#if defined(ARDUINO_GENERIC_H563RGVX) || defined(ARDUINO_GENERIC_H563RIVX) ||\ + defined(ARDUINO_GENERIC_H573RIVX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563R(G-I)V/variant_generic.cpp b/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563R(G-I)V/variant_generic.cpp rename to variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.cpp index 29051985d9..77c0f3dfc5 100644 --- a/variants/STM32H5xx/H563R(G-I)V/variant_generic.cpp +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.cpp @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563RGVX) || defined(ARDUINO_GENERIC_H563RIVX) +#if defined(ARDUINO_GENERIC_H563RGVX) || defined(ARDUINO_GENERIC_H563RIVX) ||\ + defined(ARDUINO_GENERIC_H573RIVX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563R(G-I)V/variant_generic.h b/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563R(G-I)V/variant_generic.h rename to variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.h diff --git a/variants/STM32H5xx/H563V(G-I)T/CMakeLists.txt b/variants/STM32H5xx/H563V(G-I)T/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H563V(G-I)T/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563V(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563V(G-I)T/PeripheralPins.c rename to variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c index b567ba3517..9f862af7db 100644 --- a/variants/STM32H5xx/H563V(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c @@ -12,7 +12,8 @@ */ /* * Automatically generated from STM32H563VGTx.xml, STM32H563VITx.xml - * CubeMX DB release 6.0.90 + * STM32H573VITx.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563V(G-I)T/PinNamesVar.h b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563V(G-I)T/PinNamesVar.h rename to variants/STM32H5xx/H563V(G-I)T_H573VIT/PinNamesVar.h diff --git a/variants/STM32H5xx/H563V(G-I)T/boards_entry.txt b/variants/STM32H5xx/H563V(G-I)T_H573VIT/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563V(G-I)T/boards_entry.txt rename to variants/STM32H5xx/H563V(G-I)T_H573VIT/boards_entry.txt index 9675a61afd..c5410e37ae 100644 --- a/variants/STM32H5xx/H563V(G-I)T/boards_entry.txt +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563VGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563VGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563VGTX.build.board=GENERIC_H563VGTX GenH5.menu.pnum.GENERIC_H563VGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563VGTX.build.variant=STM32H5xx/H563V(G-I)T +GenH5.menu.pnum.GENERIC_H563VGTX.build.variant=STM32H5xx/H563V(G-I)T_H573VIT # Generic H563VITx GenH5.menu.pnum.GENERIC_H563VITX=Generic H563VITx @@ -17,5 +17,13 @@ GenH5.menu.pnum.GENERIC_H563VITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563VITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563VITX.build.board=GENERIC_H563VITX GenH5.menu.pnum.GENERIC_H563VITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563VITX.build.variant=STM32H5xx/H563V(G-I)T +GenH5.menu.pnum.GENERIC_H563VITX.build.variant=STM32H5xx/H563V(G-I)T_H573VIT + +# Generic H573VITx +GenH5.menu.pnum.GENERIC_H573VITX=Generic H573VITx +GenH5.menu.pnum.GENERIC_H573VITX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573VITX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573VITX.build.board=GENERIC_H573VITX +GenH5.menu.pnum.GENERIC_H573VITX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573VITX.build.variant=STM32H5xx/H563V(G-I)T_H573VIT diff --git a/variants/STM32H5xx/H563V(G-I)T/generic_clock.c b/variants/STM32H5xx/H563V(G-I)T_H573VIT/generic_clock.c similarity index 94% rename from variants/STM32H5xx/H563V(G-I)T/generic_clock.c rename to variants/STM32H5xx/H563V(G-I)T_H573VIT/generic_clock.c index 3e9b12c850..bb368dae15 100644 --- a/variants/STM32H5xx/H563V(G-I)T/generic_clock.c +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/generic_clock.c @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563VGTX) || defined(ARDUINO_GENERIC_H563VITX) +#if defined(ARDUINO_GENERIC_H563VGTX) || defined(ARDUINO_GENERIC_H563VITX) ||\ + defined(ARDUINO_GENERIC_H573VITX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563V(G-I)T/variant_generic.cpp b/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563V(G-I)T/variant_generic.cpp rename to variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.cpp index eacd6f1846..87bd517067 100644 --- a/variants/STM32H5xx/H563V(G-I)T/variant_generic.cpp +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.cpp @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563VGTX) || defined(ARDUINO_GENERIC_H563VITX) +#if defined(ARDUINO_GENERIC_H563VGTX) || defined(ARDUINO_GENERIC_H563VITX) ||\ + defined(ARDUINO_GENERIC_H573VITX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563V(G-I)T/variant_generic.h b/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563V(G-I)T/variant_generic.h rename to variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.h diff --git a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c index 07669a16c0..ecc7e86ec6 100644 --- a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563VITxQ.xml, STM32H573VITxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563Z(G-I)T/CMakeLists.txt b/variants/STM32H5xx/H563Z(G-I)T/CMakeLists.txt deleted file mode 100644 index b30dd9bd31..0000000000 --- a/variants/STM32H5xx/H563Z(G-I)T/CMakeLists.txt +++ /dev/null @@ -1,32 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp - variant_NUCLEO_H563ZI.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H563Z(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563Z(G-I)T/PeripheralPins.c rename to variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c index 188db7d196..02090103b2 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c @@ -12,7 +12,8 @@ */ /* * Automatically generated from STM32H563ZGTx.xml, STM32H563ZITx.xml - * CubeMX DB release 6.0.90 + * STM32H573ZITx.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563Z(G-I)T/PinNamesVar.h b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T/PinNamesVar.h rename to variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PinNamesVar.h diff --git a/variants/STM32H5xx/H563Z(G-I)T/boards_entry.txt b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563Z(G-I)T/boards_entry.txt rename to variants/STM32H5xx/H563Z(G-I)T_H573ZIT/boards_entry.txt index 7229d74d12..d6797dc89a 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/boards_entry.txt +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563ZGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563ZGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563ZGTX.build.board=GENERIC_H563ZGTX GenH5.menu.pnum.GENERIC_H563ZGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563ZGTX.build.variant=STM32H5xx/H563Z(G-I)T +GenH5.menu.pnum.GENERIC_H563ZGTX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT # Generic H563ZITx GenH5.menu.pnum.GENERIC_H563ZITX=Generic H563ZITx @@ -17,5 +17,13 @@ GenH5.menu.pnum.GENERIC_H563ZITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563ZITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563ZITX.build.board=GENERIC_H563ZITX GenH5.menu.pnum.GENERIC_H563ZITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563ZITX.build.variant=STM32H5xx/H563Z(G-I)T +GenH5.menu.pnum.GENERIC_H563ZITX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT + +# Generic H573ZITx +GenH5.menu.pnum.GENERIC_H573ZITX=Generic H573ZITx +GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573ZITX.build.board=GENERIC_H573ZITX +GenH5.menu.pnum.GENERIC_H573ZITX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573ZITX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT diff --git a/variants/STM32H5xx/H563Z(G-I)T/generic_clock.c b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c similarity index 98% rename from variants/STM32H5xx/H563Z(G-I)T/generic_clock.c rename to variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c index 98da0c36cb..884d196ddf 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/generic_clock.c +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563ZGTX) || defined(ARDUINO_GENERIC_H563ZITX) +#if defined(ARDUINO_GENERIC_H563ZGTX) || defined(ARDUINO_GENERIC_H563ZITX) ||\ + defined(ARDUINO_GENERIC_H573ZITX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563Z(G-I)T/ldscript.ld b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/ldscript.ld similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T/ldscript.ld rename to variants/STM32H5xx/H563Z(G-I)T_H573ZIT/ldscript.ld diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp rename to variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.h similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h rename to variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.h diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_generic.cpp b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.cpp similarity index 98% rename from variants/STM32H5xx/H563Z(G-I)T/variant_generic.cpp rename to variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.cpp index 3eeee9322f..01933f196d 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/variant_generic.cpp +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.cpp @@ -10,7 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563ZGTX) || defined(ARDUINO_GENERIC_H563ZITX) +#if defined(ARDUINO_GENERIC_H563ZGTX) || defined(ARDUINO_GENERIC_H563ZITX) ||\ + defined(ARDUINO_GENERIC_H573ZITX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_generic.h b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T/variant_generic.h rename to variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.h diff --git a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c index b82cdc3e5b..2e6f120f32 100644 --- a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563ZITxQ.xml, STM32H573ZITxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H573AII/CMakeLists.txt b/variants/STM32H5xx/H573AII/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H573AII/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573AII/PeripheralPins.c b/variants/STM32H5xx/H573AII/PeripheralPins.c deleted file mode 100644 index b0383fc271..0000000000 --- a/variants/STM32H5xx/H573AII/PeripheralPins.c +++ /dev/null @@ -1,829 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573AIIx.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 - {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 - {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 - {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N - {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PH_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N - {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, - {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS - {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573AII/PinNamesVar.h b/variants/STM32H5xx/H573AII/PinNamesVar.h deleted file mode 100644 index f6532dee66..0000000000 --- a/variants/STM32H5xx/H573AII/PinNamesVar.h +++ /dev/null @@ -1,98 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_9_ALT1 = PB_9 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, -PF_8_ALT1 = PF_8 | ALT1, -PF_9_ALT1 = PF_9 | ALT1, -PG_13_ALT1 = PG_13 | ALT1, -PH_6_ALT1 = PH_6 | ALT1, -PH_6_ALT2 = PH_6 | ALT2, -PH_7_ALT1 = PH_7 | ALT1, -PH_8_ALT1 = PH_8 | ALT1, -PH_10_ALT1 = PH_10 | ALT1, -PH_10_ALT2 = PH_10 | ALT2, -PH_11_ALT1 = PH_11 | ALT1, -PH_11_ALT2 = PH_11 | ALT2, -PH_12_ALT1 = PH_12 | ALT1, -PH_13_ALT1 = PH_13 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = PI_8, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = PD_2, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = PD_3, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573AII/boards_entry.txt b/variants/STM32H5xx/H573AII/boards_entry.txt deleted file mode 100644 index a3cc636d79..0000000000 --- a/variants/STM32H5xx/H573AII/boards_entry.txt +++ /dev/null @@ -1,13 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573AIIx -GenH5.menu.pnum.GENERIC_H573AIIX=Generic H573AIIx -GenH5.menu.pnum.GENERIC_H573AIIX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573AIIX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573AIIX.build.board=GENERIC_H573AIIX -GenH5.menu.pnum.GENERIC_H573AIIX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573AIIX.build.variant=STM32H5xx/H573AII - diff --git a/variants/STM32H5xx/H573AII/generic_clock.c b/variants/STM32H5xx/H573AII/generic_clock.c deleted file mode 100644 index 5f8d6405cc..0000000000 --- a/variants/STM32H5xx/H573AII/generic_clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573AIIX) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573AII/variant_generic.cpp b/variants/STM32H5xx/H573AII/variant_generic.cpp deleted file mode 100644 index e257da6d6f..0000000000 --- a/variants/STM32H5xx/H573AII/variant_generic.cpp +++ /dev/null @@ -1,180 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573AIIX) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_9, // D25 - PB_10, // D26 - PB_11, // D27 - PB_12, // D28 - PB_13, // D29 - PB_14, // D30 - PB_15, // D31 - PC_0, // D32/A10 - PC_1, // D33/A11 - PC_2, // D34/A12 - PC_3, // D35/A13 - PC_4, // D36/A14 - PC_5, // D37/A15 - PC_6, // D38 - PC_7, // D39 - PC_8, // D40 - PC_9, // D41 - PC_10, // D42 - PC_11, // D43 - PC_12, // D44 - PC_13, // D45 - PC_14, // D46 - PC_15, // D47 - PD_0, // D48 - PD_1, // D49 - PD_2, // D50 - PD_3, // D51 - PD_4, // D52 - PD_5, // D53 - PD_6, // D54 - PD_7, // D55 - PD_8, // D56 - PD_9, // D57 - PD_10, // D58 - PD_11, // D59 - PD_12, // D60 - PD_13, // D61 - PD_14, // D62 - PD_15, // D63 - PE_0, // D64 - PE_1, // D65 - PE_2, // D66 - PE_3, // D67 - PE_4, // D68 - PE_5, // D69 - PE_6, // D70 - PE_7, // D71 - PE_8, // D72 - PE_9, // D73 - PE_10, // D74 - PE_11, // D75 - PE_12, // D76 - PE_13, // D77 - PE_14, // D78 - PE_15, // D79 - PF_0, // D80 - PF_1, // D81 - PF_2, // D82 - PF_3, // D83 - PF_4, // D84 - PF_5, // D85 - PF_6, // D86 - PF_7, // D87 - PF_8, // D88 - PF_9, // D89 - PF_10, // D90 - PF_11, // D91/A16 - PF_12, // D92/A17 - PF_13, // D93/A18 - PF_14, // D94/A19 - PF_15, // D95 - PG_0, // D96 - PG_1, // D97 - PG_2, // D98 - PG_3, // D99 - PG_4, // D100 - PG_5, // D101 - PG_6, // D102 - PG_7, // D103 - PG_8, // D104 - PG_9, // D105 - PG_10, // D106 - PG_11, // D107 - PG_12, // D108 - PG_13, // D109 - PG_14, // D110 - PG_15, // D111 - PH_0, // D112 - PH_1, // D113 - PH_2, // D114 - PH_3, // D115 - PH_4, // D116 - PH_5, // D117 - PH_6, // D118 - PH_7, // D119 - PH_8, // D120 - PH_10, // D121 - PH_11, // D122 - PH_12, // D123 - PH_13, // D124 - PH_14, // D125 - PH_15, // D126 - PI_0, // D127 - PI_1, // D128 - PI_2, // D129 - PI_3, // D130 - PI_4, // D131 - PI_6, // D132 - PI_7, // D133 - PI_8, // D134 - PI_11 // D135 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 32, // A10, PC0 - 33, // A11, PC1 - 34, // A12, PC2 - 35, // A13, PC3 - 36, // A14, PC4 - 37, // A15, PC5 - 91, // A16, PF11 - 92, // A17, PF12 - 93, // A18, PF13 - 94 // A19, PF14 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573AII/variant_generic.h b/variants/STM32H5xx/H573AII/variant_generic.h deleted file mode 100644 index 01e8b7bcbf..0000000000 --- a/variants/STM32H5xx/H573AII/variant_generic.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB11 27 -#define PB12 28 -#define PB13 29 -#define PB14 30 -#define PB15 31 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 38 -#define PC7 39 -#define PC8 40 -#define PC9 41 -#define PC10 42 -#define PC11 43 -#define PC12 44 -#define PC13 45 -#define PC14 46 -#define PC15 47 -#define PD0 48 -#define PD1 49 -#define PD2 50 -#define PD3 51 -#define PD4 52 -#define PD5 53 -#define PD6 54 -#define PD7 55 -#define PD8 56 -#define PD9 57 -#define PD10 58 -#define PD11 59 -#define PD12 60 -#define PD13 61 -#define PD14 62 -#define PD15 63 -#define PE0 64 -#define PE1 65 -#define PE2 66 -#define PE3 67 -#define PE4 68 -#define PE5 69 -#define PE6 70 -#define PE7 71 -#define PE8 72 -#define PE9 73 -#define PE10 74 -#define PE11 75 -#define PE12 76 -#define PE13 77 -#define PE14 78 -#define PE15 79 -#define PF0 80 -#define PF1 81 -#define PF2 82 -#define PF3 83 -#define PF4 84 -#define PF5 85 -#define PF6 86 -#define PF7 87 -#define PF8 88 -#define PF9 89 -#define PF10 90 -#define PF11 PIN_A16 -#define PF12 PIN_A17 -#define PF13 PIN_A18 -#define PF14 PIN_A19 -#define PF15 95 -#define PG0 96 -#define PG1 97 -#define PG2 98 -#define PG3 99 -#define PG4 100 -#define PG5 101 -#define PG6 102 -#define PG7 103 -#define PG8 104 -#define PG9 105 -#define PG10 106 -#define PG11 107 -#define PG12 108 -#define PG13 109 -#define PG14 110 -#define PG15 111 -#define PH0 112 -#define PH1 113 -#define PH2 114 -#define PH3 115 -#define PH4 116 -#define PH5 117 -#define PH6 118 -#define PH7 119 -#define PH8 120 -#define PH10 121 -#define PH11 122 -#define PH12 123 -#define PH13 124 -#define PH14 125 -#define PH15 126 -#define PI0 127 -#define PI1 128 -#define PI2 129 -#define PI3 130 -#define PI4 131 -#define PI6 132 -#define PI7 133 -#define PI8 134 -#define PI11 135 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB9_ALT1 (PB9 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) -#define PF8_ALT1 (PF8 | ALT1) -#define PF9_ALT1 (PF9 | ALT1) -#define PG13_ALT1 (PG13 | ALT1) -#define PH6_ALT1 (PH6 | ALT1) -#define PH6_ALT2 (PH6 | ALT2) -#define PH7_ALT1 (PH7 | ALT1) -#define PH8_ALT1 (PH8 | ALT1) -#define PH10_ALT1 (PH10 | ALT1) -#define PH10_ALT2 (PH10 | ALT2) -#define PH11_ALT1 (PH11 | ALT1) -#define PH11_ALT2 (PH11 | ALT2) -#define PH12_ALT1 (PH12 | ALT1) -#define PH13_ALT1 (PH13 | ALT1) - -#define NUM_DIGITAL_PINS 136 -#define NUM_ANALOG_INPUTS 20 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PG10 -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H5xx/H573AIIxQ/CMakeLists.txt b/variants/STM32H5xx/H573AIIxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H573AIIxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573AIIxQ/PeripheralPins.c b/variants/STM32H5xx/H573AIIxQ/PeripheralPins.c deleted file mode 100644 index 0dcf374ca1..0000000000 --- a/variants/STM32H5xx/H573AIIxQ/PeripheralPins.c +++ /dev/null @@ -1,818 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573AIIxQ.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 - {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 - {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 - {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N - {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PH_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PH_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PH_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_9_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N - {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, - {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PH_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PH_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS - {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573AIIxQ/PinNamesVar.h b/variants/STM32H5xx/H573AIIxQ/PinNamesVar.h deleted file mode 100644 index 912e35d030..0000000000 --- a/variants/STM32H5xx/H573AIIxQ/PinNamesVar.h +++ /dev/null @@ -1,99 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_9_ALT1 = PB_9 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, -PF_8_ALT1 = PF_8 | ALT1, -PF_9_ALT1 = PF_9 | ALT1, -PH_6_ALT1 = PH_6 | ALT1, -PH_6_ALT2 = PH_6 | ALT2, -PH_7_ALT1 = PH_7 | ALT1, -PH_8_ALT1 = PH_8 | ALT1, -PH_9_ALT1 = PH_9 | ALT1, -PH_9_ALT2 = PH_9 | ALT2, -PH_10_ALT1 = PH_10 | ALT1, -PH_10_ALT2 = PH_10 | ALT2, -PH_11_ALT1 = PH_11 | ALT1, -PH_11_ALT2 = PH_11 | ALT2, -PH_12_ALT1 = PH_12 | ALT1, -PH_13_ALT1 = PH_13 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = PI_8, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = PD_2, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = PD_3, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573AIIxQ/boards_entry.txt b/variants/STM32H5xx/H573AIIxQ/boards_entry.txt deleted file mode 100644 index 37e8fc73cc..0000000000 --- a/variants/STM32H5xx/H573AIIxQ/boards_entry.txt +++ /dev/null @@ -1,13 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573AIIxQ -GenH5.menu.pnum.GENERIC_H573AIIXQ=Generic H573AIIxQ -GenH5.menu.pnum.GENERIC_H573AIIXQ.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573AIIXQ.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573AIIXQ.build.board=GENERIC_H573AIIXQ -GenH5.menu.pnum.GENERIC_H573AIIXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573AIIXQ.build.variant=STM32H5xx/H573AIIxQ - diff --git a/variants/STM32H5xx/H573AIIxQ/generic_clock.c b/variants/STM32H5xx/H573AIIxQ/generic_clock.c deleted file mode 100644 index fd1d9d9049..0000000000 --- a/variants/STM32H5xx/H573AIIxQ/generic_clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573AIIXQ) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573AIIxQ/variant_generic.cpp b/variants/STM32H5xx/H573AIIxQ/variant_generic.cpp deleted file mode 100644 index ff8922f953..0000000000 --- a/variants/STM32H5xx/H573AIIxQ/variant_generic.cpp +++ /dev/null @@ -1,178 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573AIIXQ) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_9, // D25 - PB_10, // D26 - PB_11, // D27 - PB_12, // D28 - PB_13, // D29 - PB_14, // D30 - PB_15, // D31 - PC_0, // D32/A10 - PC_1, // D33/A11 - PC_2, // D34/A12 - PC_3, // D35/A13 - PC_4, // D36/A14 - PC_5, // D37/A15 - PC_6, // D38 - PC_7, // D39 - PC_8, // D40 - PC_9, // D41 - PC_10, // D42 - PC_11, // D43 - PC_12, // D44 - PC_13, // D45 - PC_14, // D46 - PC_15, // D47 - PD_0, // D48 - PD_1, // D49 - PD_2, // D50 - PD_3, // D51 - PD_4, // D52 - PD_5, // D53 - PD_6, // D54 - PD_7, // D55 - PD_8, // D56 - PD_9, // D57 - PD_10, // D58 - PD_11, // D59 - PD_12, // D60 - PD_13, // D61 - PD_14, // D62 - PD_15, // D63 - PE_0, // D64 - PE_1, // D65 - PE_2, // D66 - PE_3, // D67 - PE_4, // D68 - PE_5, // D69 - PE_6, // D70 - PE_7, // D71 - PE_8, // D72 - PE_9, // D73 - PE_10, // D74 - PE_11, // D75 - PE_12, // D76 - PE_13, // D77 - PE_14, // D78 - PE_15, // D79 - PF_0, // D80 - PF_1, // D81 - PF_2, // D82 - PF_3, // D83 - PF_4, // D84 - PF_5, // D85 - PF_6, // D86 - PF_7, // D87 - PF_8, // D88 - PF_9, // D89 - PF_10, // D90 - PF_11, // D91/A16 - PF_12, // D92/A17 - PF_13, // D93/A18 - PF_14, // D94/A19 - PF_15, // D95 - PG_0, // D96 - PG_1, // D97 - PG_2, // D98 - PG_3, // D99 - PG_4, // D100 - PG_5, // D101 - PG_6, // D102 - PG_7, // D103 - PG_8, // D104 - PG_9, // D105 - PG_10, // D106 - PG_12, // D107 - PG_15, // D108 - PH_0, // D109 - PH_1, // D110 - PH_2, // D111 - PH_3, // D112 - PH_4, // D113 - PH_5, // D114 - PH_6, // D115 - PH_7, // D116 - PH_8, // D117 - PH_9, // D118 - PH_10, // D119 - PH_11, // D120 - PH_12, // D121 - PH_13, // D122 - PH_14, // D123 - PH_15, // D124 - PI_0, // D125 - PI_1, // D126 - PI_2, // D127 - PI_3, // D128 - PI_4, // D129 - PI_5, // D130 - PI_6, // D131 - PI_7, // D132 - PI_8 // D133 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 32, // A10, PC0 - 33, // A11, PC1 - 34, // A12, PC2 - 35, // A13, PC3 - 36, // A14, PC4 - 37, // A15, PC5 - 91, // A16, PF11 - 92, // A17, PF12 - 93, // A18, PF13 - 94 // A19, PF14 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573AIIxQ/variant_generic.h b/variants/STM32H5xx/H573AIIxQ/variant_generic.h deleted file mode 100644 index 79e19270e2..0000000000 --- a/variants/STM32H5xx/H573AIIxQ/variant_generic.h +++ /dev/null @@ -1,327 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB11 27 -#define PB12 28 -#define PB13 29 -#define PB14 30 -#define PB15 31 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 38 -#define PC7 39 -#define PC8 40 -#define PC9 41 -#define PC10 42 -#define PC11 43 -#define PC12 44 -#define PC13 45 -#define PC14 46 -#define PC15 47 -#define PD0 48 -#define PD1 49 -#define PD2 50 -#define PD3 51 -#define PD4 52 -#define PD5 53 -#define PD6 54 -#define PD7 55 -#define PD8 56 -#define PD9 57 -#define PD10 58 -#define PD11 59 -#define PD12 60 -#define PD13 61 -#define PD14 62 -#define PD15 63 -#define PE0 64 -#define PE1 65 -#define PE2 66 -#define PE3 67 -#define PE4 68 -#define PE5 69 -#define PE6 70 -#define PE7 71 -#define PE8 72 -#define PE9 73 -#define PE10 74 -#define PE11 75 -#define PE12 76 -#define PE13 77 -#define PE14 78 -#define PE15 79 -#define PF0 80 -#define PF1 81 -#define PF2 82 -#define PF3 83 -#define PF4 84 -#define PF5 85 -#define PF6 86 -#define PF7 87 -#define PF8 88 -#define PF9 89 -#define PF10 90 -#define PF11 PIN_A16 -#define PF12 PIN_A17 -#define PF13 PIN_A18 -#define PF14 PIN_A19 -#define PF15 95 -#define PG0 96 -#define PG1 97 -#define PG2 98 -#define PG3 99 -#define PG4 100 -#define PG5 101 -#define PG6 102 -#define PG7 103 -#define PG8 104 -#define PG9 105 -#define PG10 106 -#define PG12 107 -#define PG15 108 -#define PH0 109 -#define PH1 110 -#define PH2 111 -#define PH3 112 -#define PH4 113 -#define PH5 114 -#define PH6 115 -#define PH7 116 -#define PH8 117 -#define PH9 118 -#define PH10 119 -#define PH11 120 -#define PH12 121 -#define PH13 122 -#define PH14 123 -#define PH15 124 -#define PI0 125 -#define PI1 126 -#define PI2 127 -#define PI3 128 -#define PI4 129 -#define PI5 130 -#define PI6 131 -#define PI7 132 -#define PI8 133 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB9_ALT1 (PB9 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) -#define PF8_ALT1 (PF8 | ALT1) -#define PF9_ALT1 (PF9 | ALT1) -#define PH6_ALT1 (PH6 | ALT1) -#define PH6_ALT2 (PH6 | ALT2) -#define PH7_ALT1 (PH7 | ALT1) -#define PH8_ALT1 (PH8 | ALT1) -#define PH9_ALT1 (PH9 | ALT1) -#define PH9_ALT2 (PH9 | ALT2) -#define PH10_ALT1 (PH10 | ALT1) -#define PH10_ALT2 (PH10 | ALT2) -#define PH11_ALT1 (PH11 | ALT1) -#define PH11_ALT2 (PH11 | ALT2) -#define PH12_ALT1 (PH12 | ALT1) -#define PH13_ALT1 (PH13 | ALT1) - -#define NUM_DIGITAL_PINS 134 -#define NUM_ANALOG_INPUTS 20 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PG10 -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H5xx/H573II(K-T)/CMakeLists.txt b/variants/STM32H5xx/H573II(K-T)/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H573II(K-T)/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573II(K-T)/PeripheralPins.c b/variants/STM32H5xx/H573II(K-T)/PeripheralPins.c deleted file mode 100644 index c58830e04e..0000000000 --- a/variants/STM32H5xx/H573II(K-T)/PeripheralPins.c +++ /dev/null @@ -1,838 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573IIKx.xml, STM32H573IITx.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 - {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 - {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 - {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N - {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PH_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PH_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PH_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_9_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N - {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PI_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, - {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PH_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PI_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PI_10, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS - {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573II(K-T)/PinNamesVar.h b/variants/STM32H5xx/H573II(K-T)/PinNamesVar.h deleted file mode 100644 index ddf97db984..0000000000 --- a/variants/STM32H5xx/H573II(K-T)/PinNamesVar.h +++ /dev/null @@ -1,100 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_9_ALT1 = PB_9 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, -PF_8_ALT1 = PF_8 | ALT1, -PF_9_ALT1 = PF_9 | ALT1, -PG_13_ALT1 = PG_13 | ALT1, -PH_6_ALT1 = PH_6 | ALT1, -PH_6_ALT2 = PH_6 | ALT2, -PH_7_ALT1 = PH_7 | ALT1, -PH_8_ALT1 = PH_8 | ALT1, -PH_9_ALT1 = PH_9 | ALT1, -PH_9_ALT2 = PH_9 | ALT2, -PH_10_ALT1 = PH_10 | ALT1, -PH_10_ALT2 = PH_10 | ALT2, -PH_11_ALT1 = PH_11 | ALT1, -PH_11_ALT2 = PH_11 | ALT2, -PH_12_ALT1 = PH_12 | ALT1, -PH_13_ALT1 = PH_13 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = PI_8, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = PD_2, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = PD_3, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573II(K-T)/boards_entry.txt b/variants/STM32H5xx/H573II(K-T)/boards_entry.txt deleted file mode 100644 index 48980a45cc..0000000000 --- a/variants/STM32H5xx/H573II(K-T)/boards_entry.txt +++ /dev/null @@ -1,21 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573IIKx -GenH5.menu.pnum.GENERIC_H573IIKX=Generic H573IIKx -GenH5.menu.pnum.GENERIC_H573IIKX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573IIKX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573IIKX.build.board=GENERIC_H573IIKX -GenH5.menu.pnum.GENERIC_H573IIKX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IIKX.build.variant=STM32H5xx/H573II(K-T) - -# Generic H573IITx -GenH5.menu.pnum.GENERIC_H573IITX=Generic H573IITx -GenH5.menu.pnum.GENERIC_H573IITX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573IITX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573IITX.build.board=GENERIC_H573IITX -GenH5.menu.pnum.GENERIC_H573IITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IITX.build.variant=STM32H5xx/H573II(K-T) - diff --git a/variants/STM32H5xx/H573II(K-T)/generic_clock.c b/variants/STM32H5xx/H573II(K-T)/generic_clock.c deleted file mode 100644 index 64ecc3ca7f..0000000000 --- a/variants/STM32H5xx/H573II(K-T)/generic_clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573IIKX) || defined(ARDUINO_GENERIC_H573IITX) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573II(K-T)/variant_generic.cpp b/variants/STM32H5xx/H573II(K-T)/variant_generic.cpp deleted file mode 100644 index 348ecea665..0000000000 --- a/variants/STM32H5xx/H573II(K-T)/variant_generic.cpp +++ /dev/null @@ -1,184 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573IIKX) || defined(ARDUINO_GENERIC_H573IITX) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_9, // D25 - PB_10, // D26 - PB_11, // D27 - PB_12, // D28 - PB_13, // D29 - PB_14, // D30 - PB_15, // D31 - PC_0, // D32/A10 - PC_1, // D33/A11 - PC_2, // D34/A12 - PC_3, // D35/A13 - PC_4, // D36/A14 - PC_5, // D37/A15 - PC_6, // D38 - PC_7, // D39 - PC_8, // D40 - PC_9, // D41 - PC_10, // D42 - PC_11, // D43 - PC_12, // D44 - PC_13, // D45 - PC_14, // D46 - PC_15, // D47 - PD_0, // D48 - PD_1, // D49 - PD_2, // D50 - PD_3, // D51 - PD_4, // D52 - PD_5, // D53 - PD_6, // D54 - PD_7, // D55 - PD_8, // D56 - PD_9, // D57 - PD_10, // D58 - PD_11, // D59 - PD_12, // D60 - PD_13, // D61 - PD_14, // D62 - PD_15, // D63 - PE_0, // D64 - PE_1, // D65 - PE_2, // D66 - PE_3, // D67 - PE_4, // D68 - PE_5, // D69 - PE_6, // D70 - PE_7, // D71 - PE_8, // D72 - PE_9, // D73 - PE_10, // D74 - PE_11, // D75 - PE_12, // D76 - PE_13, // D77 - PE_14, // D78 - PE_15, // D79 - PF_0, // D80 - PF_1, // D81 - PF_2, // D82 - PF_3, // D83 - PF_4, // D84 - PF_5, // D85 - PF_6, // D86 - PF_7, // D87 - PF_8, // D88 - PF_9, // D89 - PF_10, // D90 - PF_11, // D91/A16 - PF_12, // D92/A17 - PF_13, // D93/A18 - PF_14, // D94/A19 - PF_15, // D95 - PG_0, // D96 - PG_1, // D97 - PG_2, // D98 - PG_3, // D99 - PG_4, // D100 - PG_5, // D101 - PG_6, // D102 - PG_7, // D103 - PG_8, // D104 - PG_9, // D105 - PG_10, // D106 - PG_11, // D107 - PG_12, // D108 - PG_13, // D109 - PG_14, // D110 - PG_15, // D111 - PH_0, // D112 - PH_1, // D113 - PH_2, // D114 - PH_3, // D115 - PH_4, // D116 - PH_5, // D117 - PH_6, // D118 - PH_7, // D119 - PH_8, // D120 - PH_9, // D121 - PH_10, // D122 - PH_11, // D123 - PH_12, // D124 - PH_13, // D125 - PH_14, // D126 - PH_15, // D127 - PI_0, // D128 - PI_1, // D129 - PI_2, // D130 - PI_3, // D131 - PI_4, // D132 - PI_5, // D133 - PI_6, // D134 - PI_7, // D135 - PI_8, // D136 - PI_9, // D137 - PI_10, // D138 - PI_11 // D139 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 32, // A10, PC0 - 33, // A11, PC1 - 34, // A12, PC2 - 35, // A13, PC3 - 36, // A14, PC4 - 37, // A15, PC5 - 91, // A16, PF11 - 92, // A17, PF12 - 93, // A18, PF13 - 94 // A19, PF14 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573II(K-T)/variant_generic.h b/variants/STM32H5xx/H573II(K-T)/variant_generic.h deleted file mode 100644 index d8b1e831b5..0000000000 --- a/variants/STM32H5xx/H573II(K-T)/variant_generic.h +++ /dev/null @@ -1,334 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB11 27 -#define PB12 28 -#define PB13 29 -#define PB14 30 -#define PB15 31 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 38 -#define PC7 39 -#define PC8 40 -#define PC9 41 -#define PC10 42 -#define PC11 43 -#define PC12 44 -#define PC13 45 -#define PC14 46 -#define PC15 47 -#define PD0 48 -#define PD1 49 -#define PD2 50 -#define PD3 51 -#define PD4 52 -#define PD5 53 -#define PD6 54 -#define PD7 55 -#define PD8 56 -#define PD9 57 -#define PD10 58 -#define PD11 59 -#define PD12 60 -#define PD13 61 -#define PD14 62 -#define PD15 63 -#define PE0 64 -#define PE1 65 -#define PE2 66 -#define PE3 67 -#define PE4 68 -#define PE5 69 -#define PE6 70 -#define PE7 71 -#define PE8 72 -#define PE9 73 -#define PE10 74 -#define PE11 75 -#define PE12 76 -#define PE13 77 -#define PE14 78 -#define PE15 79 -#define PF0 80 -#define PF1 81 -#define PF2 82 -#define PF3 83 -#define PF4 84 -#define PF5 85 -#define PF6 86 -#define PF7 87 -#define PF8 88 -#define PF9 89 -#define PF10 90 -#define PF11 PIN_A16 -#define PF12 PIN_A17 -#define PF13 PIN_A18 -#define PF14 PIN_A19 -#define PF15 95 -#define PG0 96 -#define PG1 97 -#define PG2 98 -#define PG3 99 -#define PG4 100 -#define PG5 101 -#define PG6 102 -#define PG7 103 -#define PG8 104 -#define PG9 105 -#define PG10 106 -#define PG11 107 -#define PG12 108 -#define PG13 109 -#define PG14 110 -#define PG15 111 -#define PH0 112 -#define PH1 113 -#define PH2 114 -#define PH3 115 -#define PH4 116 -#define PH5 117 -#define PH6 118 -#define PH7 119 -#define PH8 120 -#define PH9 121 -#define PH10 122 -#define PH11 123 -#define PH12 124 -#define PH13 125 -#define PH14 126 -#define PH15 127 -#define PI0 128 -#define PI1 129 -#define PI2 130 -#define PI3 131 -#define PI4 132 -#define PI5 133 -#define PI6 134 -#define PI7 135 -#define PI8 136 -#define PI9 137 -#define PI10 138 -#define PI11 139 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB9_ALT1 (PB9 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) -#define PF8_ALT1 (PF8 | ALT1) -#define PF9_ALT1 (PF9 | ALT1) -#define PG13_ALT1 (PG13 | ALT1) -#define PH6_ALT1 (PH6 | ALT1) -#define PH6_ALT2 (PH6 | ALT2) -#define PH7_ALT1 (PH7 | ALT1) -#define PH8_ALT1 (PH8 | ALT1) -#define PH9_ALT1 (PH9 | ALT1) -#define PH9_ALT2 (PH9 | ALT2) -#define PH10_ALT1 (PH10 | ALT1) -#define PH10_ALT2 (PH10 | ALT2) -#define PH11_ALT1 (PH11 | ALT1) -#define PH11_ALT2 (PH11 | ALT2) -#define PH12_ALT1 (PH12 | ALT1) -#define PH13_ALT1 (PH13 | ALT1) - -#define NUM_DIGITAL_PINS 140 -#define NUM_ANALOG_INPUTS 20 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PG10 -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H5xx/H573IIKxQ/CMakeLists.txt b/variants/STM32H5xx/H573IIKxQ/CMakeLists.txt deleted file mode 100644 index 2a21dc24a7..0000000000 --- a/variants/STM32H5xx/H573IIKxQ/CMakeLists.txt +++ /dev/null @@ -1,33 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - PeripheralPins_STM32H573I_DK.c - variant_generic.cpp - variant_STM32H573I_DK.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573IIKxQ/PeripheralPins.c b/variants/STM32H5xx/H573IIKxQ/PeripheralPins.c deleted file mode 100644 index b2b6217ee9..0000000000 --- a/variants/STM32H5xx/H573IIKxQ/PeripheralPins.c +++ /dev/null @@ -1,836 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573IIKxQ.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 - {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 - {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 - {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N - {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PH_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PH_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PH_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_9_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N - {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PI_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, - {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PH_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PI_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PI_10, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS - {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573IIKxQ/PinNamesVar.h b/variants/STM32H5xx/H573IIKxQ/PinNamesVar.h deleted file mode 100644 index ddf97db984..0000000000 --- a/variants/STM32H5xx/H573IIKxQ/PinNamesVar.h +++ /dev/null @@ -1,100 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_9_ALT1 = PB_9 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, -PF_8_ALT1 = PF_8 | ALT1, -PF_9_ALT1 = PF_9 | ALT1, -PG_13_ALT1 = PG_13 | ALT1, -PH_6_ALT1 = PH_6 | ALT1, -PH_6_ALT2 = PH_6 | ALT2, -PH_7_ALT1 = PH_7 | ALT1, -PH_8_ALT1 = PH_8 | ALT1, -PH_9_ALT1 = PH_9 | ALT1, -PH_9_ALT2 = PH_9 | ALT2, -PH_10_ALT1 = PH_10 | ALT1, -PH_10_ALT2 = PH_10 | ALT2, -PH_11_ALT1 = PH_11 | ALT1, -PH_11_ALT2 = PH_11 | ALT2, -PH_12_ALT1 = PH_12 | ALT1, -PH_13_ALT1 = PH_13 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = PI_8, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = PD_2, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = PD_3, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573IIKxQ/boards_entry.txt b/variants/STM32H5xx/H573IIKxQ/boards_entry.txt deleted file mode 100644 index b5e321c3b8..0000000000 --- a/variants/STM32H5xx/H573IIKxQ/boards_entry.txt +++ /dev/null @@ -1,13 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573IIKxQ -GenH5.menu.pnum.GENERIC_H573IIKXQ=Generic H573IIKxQ -GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573IIKXQ.build.board=GENERIC_H573IIKXQ -GenH5.menu.pnum.GENERIC_H573IIKXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IIKXQ.build.variant=STM32H5xx/H573IIKxQ - diff --git a/variants/STM32H5xx/H573IIKxQ/ldscript.ld b/variants/STM32H5xx/H573IIKxQ/ldscript.ld deleted file mode 100644 index 7ed43755cb..0000000000 --- a/variants/STM32H5xx/H573IIKxQ/ldscript.ld +++ /dev/null @@ -1,185 +0,0 @@ -/* -****************************************************************************** -** -** @file : LinkerScript.ld -** -** @author : Auto-generated by STM32CubeIDE -** -** @brief : Linker script for STM32H573IIKxQ Device from STM32H5 series -** 2048Kbytes FLASH -** 640Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -****************************************************************************** -** @attention -** -** Copyright (c) 2023 STMicroelectronics. -** All rights reserved. -** -** This software is licensed under terms that can be found in the LICENSE file -** in the root directory of this software component. -** If no LICENSE file comes with this software, it is provided AS-IS. -** -****************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE - FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "FLASH" Rom type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data into "FLASH" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data into "FLASH" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >FLASH - - .ARM : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >FLASH - - .preinit_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >FLASH - - .init_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >FLASH - - .fini_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >FLASH - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - *(.RamFunc) /* .RamFunc sections */ - *(.RamFunc*) /* .RamFunc* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM AT> FLASH - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/variants/STM32H5xx/H573IIKxQ/variant_generic.h b/variants/STM32H5xx/H573IIKxQ/variant_generic.h deleted file mode 100644 index 84d49d2c34..0000000000 --- a/variants/STM32H5xx/H573IIKxQ/variant_generic.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB11 27 -#define PB12 28 -#define PB13 29 -#define PB14 30 -#define PB15 31 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 38 -#define PC7 39 -#define PC8 40 -#define PC9 41 -#define PC10 42 -#define PC11 43 -#define PC12 44 -#define PC13 45 -#define PC14 46 -#define PC15 47 -#define PD0 48 -#define PD1 49 -#define PD2 50 -#define PD3 51 -#define PD4 52 -#define PD5 53 -#define PD6 54 -#define PD7 55 -#define PD8 56 -#define PD9 57 -#define PD10 58 -#define PD11 59 -#define PD12 60 -#define PD13 61 -#define PD14 62 -#define PD15 63 -#define PE0 64 -#define PE1 65 -#define PE2 66 -#define PE3 67 -#define PE4 68 -#define PE5 69 -#define PE6 70 -#define PE7 71 -#define PE8 72 -#define PE9 73 -#define PE10 74 -#define PE11 75 -#define PE12 76 -#define PE13 77 -#define PE14 78 -#define PE15 79 -#define PF0 80 -#define PF1 81 -#define PF2 82 -#define PF3 83 -#define PF4 84 -#define PF5 85 -#define PF6 86 -#define PF7 87 -#define PF8 88 -#define PF9 89 -#define PF10 90 -#define PF11 PIN_A16 -#define PF12 PIN_A17 -#define PF13 PIN_A18 -#define PF14 PIN_A19 -#define PF15 95 -#define PG0 96 -#define PG1 97 -#define PG2 98 -#define PG3 99 -#define PG4 100 -#define PG5 101 -#define PG6 102 -#define PG7 103 -#define PG8 104 -#define PG9 105 -#define PG10 106 -#define PG11 107 -#define PG12 108 -#define PG13 109 -#define PG14 110 -#define PG15 111 -#define PH0 112 -#define PH1 113 -#define PH2 114 -#define PH3 115 -#define PH4 116 -#define PH5 117 -#define PH6 118 -#define PH7 119 -#define PH8 120 -#define PH9 121 -#define PH10 122 -#define PH11 123 -#define PH12 124 -#define PH13 125 -#define PH14 126 -#define PH15 127 -#define PI1 128 -#define PI2 129 -#define PI3 130 -#define PI4 131 -#define PI5 132 -#define PI6 133 -#define PI7 134 -#define PI8 135 -#define PI9 136 -#define PI10 137 -#define PI11 138 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB9_ALT1 (PB9 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) -#define PF8_ALT1 (PF8 | ALT1) -#define PF9_ALT1 (PF9 | ALT1) -#define PG13_ALT1 (PG13 | ALT1) -#define PH6_ALT1 (PH6 | ALT1) -#define PH6_ALT2 (PH6 | ALT2) -#define PH7_ALT1 (PH7 | ALT1) -#define PH8_ALT1 (PH8 | ALT1) -#define PH9_ALT1 (PH9 | ALT1) -#define PH9_ALT2 (PH9 | ALT2) -#define PH10_ALT1 (PH10 | ALT1) -#define PH10_ALT2 (PH10 | ALT2) -#define PH11_ALT1 (PH11 | ALT1) -#define PH11_ALT2 (PH11 | ALT2) -#define PH12_ALT1 (PH12 | ALT1) -#define PH13_ALT1 (PH13 | ALT1) - -#define NUM_DIGITAL_PINS 139 -#define NUM_ANALOG_INPUTS 20 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PG10 -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H5xx/H573IITxQ/CMakeLists.txt b/variants/STM32H5xx/H573IITxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H573IITxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573IITxQ/PeripheralPins.c b/variants/STM32H5xx/H573IITxQ/PeripheralPins.c deleted file mode 100644 index 2146cd5ea4..0000000000 --- a/variants/STM32H5xx/H573IITxQ/PeripheralPins.c +++ /dev/null @@ -1,830 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573IITxQ.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 - {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 - {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 - {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N - {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PH_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_9_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N - {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PI_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, - {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PH_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PI_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PI_10, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS - {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573IITxQ/PinNamesVar.h b/variants/STM32H5xx/H573IITxQ/PinNamesVar.h deleted file mode 100644 index e57cfd85f3..0000000000 --- a/variants/STM32H5xx/H573IITxQ/PinNamesVar.h +++ /dev/null @@ -1,99 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_9_ALT1 = PB_9 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, -PF_8_ALT1 = PF_8 | ALT1, -PF_9_ALT1 = PF_9 | ALT1, -PG_13_ALT1 = PG_13 | ALT1, -PH_6_ALT1 = PH_6 | ALT1, -PH_6_ALT2 = PH_6 | ALT2, -PH_7_ALT1 = PH_7 | ALT1, -PH_9_ALT1 = PH_9 | ALT1, -PH_9_ALT2 = PH_9 | ALT2, -PH_10_ALT1 = PH_10 | ALT1, -PH_10_ALT2 = PH_10 | ALT2, -PH_11_ALT1 = PH_11 | ALT1, -PH_11_ALT2 = PH_11 | ALT2, -PH_12_ALT1 = PH_12 | ALT1, -PH_13_ALT1 = PH_13 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = PI_8, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = PD_2, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = PD_3, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573IITxQ/boards_entry.txt b/variants/STM32H5xx/H573IITxQ/boards_entry.txt deleted file mode 100644 index e377e73172..0000000000 --- a/variants/STM32H5xx/H573IITxQ/boards_entry.txt +++ /dev/null @@ -1,13 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573IITxQ -GenH5.menu.pnum.GENERIC_H573IITXQ=Generic H573IITxQ -GenH5.menu.pnum.GENERIC_H573IITXQ.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573IITXQ.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573IITXQ.build.board=GENERIC_H573IITXQ -GenH5.menu.pnum.GENERIC_H573IITXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IITXQ.build.variant=STM32H5xx/H573IITxQ - diff --git a/variants/STM32H5xx/H573IITxQ/generic_clock.c b/variants/STM32H5xx/H573IITxQ/generic_clock.c deleted file mode 100644 index e61cf9c1ce..0000000000 --- a/variants/STM32H5xx/H573IITxQ/generic_clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573IITXQ) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573IITxQ/variant_generic.h b/variants/STM32H5xx/H573IITxQ/variant_generic.h deleted file mode 100644 index 5d9ed6afa9..0000000000 --- a/variants/STM32H5xx/H573IITxQ/variant_generic.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB11 27 -#define PB12 28 -#define PB13 29 -#define PB14 30 -#define PB15 31 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 38 -#define PC7 39 -#define PC8 40 -#define PC9 41 -#define PC10 42 -#define PC11 43 -#define PC12 44 -#define PC13 45 -#define PC14 46 -#define PC15 47 -#define PD0 48 -#define PD1 49 -#define PD2 50 -#define PD3 51 -#define PD4 52 -#define PD5 53 -#define PD6 54 -#define PD7 55 -#define PD8 56 -#define PD9 57 -#define PD10 58 -#define PD11 59 -#define PD12 60 -#define PD13 61 -#define PD14 62 -#define PD15 63 -#define PE0 64 -#define PE1 65 -#define PE2 66 -#define PE3 67 -#define PE4 68 -#define PE5 69 -#define PE6 70 -#define PE7 71 -#define PE8 72 -#define PE9 73 -#define PE10 74 -#define PE11 75 -#define PE12 76 -#define PE13 77 -#define PE14 78 -#define PE15 79 -#define PF0 80 -#define PF1 81 -#define PF2 82 -#define PF3 83 -#define PF4 84 -#define PF5 85 -#define PF6 86 -#define PF7 87 -#define PF8 88 -#define PF9 89 -#define PF11 PIN_A16 -#define PF12 PIN_A17 -#define PF13 PIN_A18 -#define PF14 PIN_A19 -#define PF15 94 -#define PG0 95 -#define PG1 96 -#define PG2 97 -#define PG3 98 -#define PG4 99 -#define PG5 100 -#define PG6 101 -#define PG7 102 -#define PG8 103 -#define PG9 104 -#define PG10 105 -#define PG11 106 -#define PG12 107 -#define PG13 108 -#define PG14 109 -#define PG15 110 -#define PH0 111 -#define PH1 112 -#define PH2 113 -#define PH3 114 -#define PH6 115 -#define PH7 116 -#define PH9 117 -#define PH10 118 -#define PH11 119 -#define PH12 120 -#define PH13 121 -#define PH14 122 -#define PH15 123 -#define PI0 124 -#define PI1 125 -#define PI2 126 -#define PI3 127 -#define PI4 128 -#define PI5 129 -#define PI6 130 -#define PI7 131 -#define PI8 132 -#define PI9 133 -#define PI10 134 -#define PI11 135 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB9_ALT1 (PB9 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) -#define PF8_ALT1 (PF8 | ALT1) -#define PF9_ALT1 (PF9 | ALT1) -#define PG13_ALT1 (PG13 | ALT1) -#define PH6_ALT1 (PH6 | ALT1) -#define PH6_ALT2 (PH6 | ALT2) -#define PH7_ALT1 (PH7 | ALT1) -#define PH9_ALT1 (PH9 | ALT1) -#define PH9_ALT2 (PH9 | ALT2) -#define PH10_ALT1 (PH10 | ALT1) -#define PH10_ALT2 (PH10 | ALT2) -#define PH11_ALT1 (PH11 | ALT1) -#define PH11_ALT2 (PH11 | ALT2) -#define PH12_ALT1 (PH12 | ALT1) -#define PH13_ALT1 (PH13 | ALT1) - -#define NUM_DIGITAL_PINS 136 -#define NUM_ANALOG_INPUTS 20 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PG10 -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H5xx/H573MIYxQ/CMakeLists.txt b/variants/STM32H5xx/H573MIYxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H573MIYxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573MIYxQ/PeripheralPins.c b/variants/STM32H5xx/H573MIYxQ/PeripheralPins.c deleted file mode 100644 index cb329e045e..0000000000 --- a/variants/STM32H5xx/H573MIYxQ/PeripheralPins.c +++ /dev/null @@ -1,605 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573MIYxQ.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573MIYxQ/PinNamesVar.h b/variants/STM32H5xx/H573MIYxQ/PinNamesVar.h deleted file mode 100644 index c06b9e6d50..0000000000 --- a/variants/STM32H5xx/H573MIYxQ/PinNamesVar.h +++ /dev/null @@ -1,84 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = PD_2, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573MIYxQ/boards_entry.txt b/variants/STM32H5xx/H573MIYxQ/boards_entry.txt deleted file mode 100644 index 833c1152b3..0000000000 --- a/variants/STM32H5xx/H573MIYxQ/boards_entry.txt +++ /dev/null @@ -1,13 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573MIYxQ -GenH5.menu.pnum.GENERIC_H573MIYXQ=Generic H573MIYxQ -GenH5.menu.pnum.GENERIC_H573MIYXQ.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573MIYXQ.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573MIYXQ.build.board=GENERIC_H573MIYXQ -GenH5.menu.pnum.GENERIC_H573MIYXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573MIYXQ.build.variant=STM32H5xx/H573MIYxQ - diff --git a/variants/STM32H5xx/H573MIYxQ/generic_clock.c b/variants/STM32H5xx/H573MIYxQ/generic_clock.c deleted file mode 100644 index 0635225e0c..0000000000 --- a/variants/STM32H5xx/H573MIYxQ/generic_clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573MIYXQ) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573MIYxQ/variant_generic.h b/variants/STM32H5xx/H573MIYxQ/variant_generic.h deleted file mode 100644 index 70f49431b0..0000000000 --- a/variants/STM32H5xx/H573MIYxQ/variant_generic.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB10 25 -#define PB12 26 -#define PB13 27 -#define PB14 28 -#define PB15 29 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 36 -#define PC7 37 -#define PC8 38 -#define PC9 39 -#define PC10 40 -#define PC11 41 -#define PC12 42 -#define PC13 43 -#define PC14 44 -#define PC15 45 -#define PD0 46 -#define PD1 47 -#define PD2 48 -#define PD14 49 -#define PD15 50 -#define PE7 51 -#define PE8 52 -#define PE9 53 -#define PE10 54 -#define PH0 55 -#define PH1 56 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) - -#define NUM_DIGITAL_PINS 57 -#define NUM_ANALOG_INPUTS 16 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// SDMMC signals not available -#define SDMMC_CDIR_NA - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H5xx/H573RIT/CMakeLists.txt b/variants/STM32H5xx/H573RIT/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H573RIT/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573RIT/PeripheralPins.c b/variants/STM32H5xx/H573RIT/PeripheralPins.c deleted file mode 100644 index efa34c71a9..0000000000 --- a/variants/STM32H5xx/H573RIT/PeripheralPins.c +++ /dev/null @@ -1,578 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573RITx.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573RIT/PinNamesVar.h b/variants/STM32H5xx/H573RIT/PinNamesVar.h deleted file mode 100644 index c06b9e6d50..0000000000 --- a/variants/STM32H5xx/H573RIT/PinNamesVar.h +++ /dev/null @@ -1,84 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = PD_2, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573RIT/boards_entry.txt b/variants/STM32H5xx/H573RIT/boards_entry.txt deleted file mode 100644 index 70654bdc5d..0000000000 --- a/variants/STM32H5xx/H573RIT/boards_entry.txt +++ /dev/null @@ -1,13 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573RITx -GenH5.menu.pnum.GENERIC_H573RITX=Generic H573RITx -GenH5.menu.pnum.GENERIC_H573RITX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573RITX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573RITX.build.board=GENERIC_H573RITX -GenH5.menu.pnum.GENERIC_H573RITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573RITX.build.variant=STM32H5xx/H573RIT - diff --git a/variants/STM32H5xx/H573RIT/generic_clock.c b/variants/STM32H5xx/H573RIT/generic_clock.c deleted file mode 100644 index a6f79ede55..0000000000 --- a/variants/STM32H5xx/H573RIT/generic_clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573RITX) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573RIT/variant_generic.cpp b/variants/STM32H5xx/H573RIT/variant_generic.cpp deleted file mode 100644 index 6b8a4158f8..0000000000 --- a/variants/STM32H5xx/H573RIT/variant_generic.cpp +++ /dev/null @@ -1,89 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573RITX) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_10, // D25 - PB_12, // D26 - PB_13, // D27 - PB_14, // D28 - PB_15, // D29 - PC_0, // D30/A10 - PC_1, // D31/A11 - PC_2, // D32/A12 - PC_3, // D33/A13 - PC_4, // D34/A14 - PC_5, // D35/A15 - PC_6, // D36 - PC_7, // D37 - PC_8, // D38 - PC_9, // D39 - PC_10, // D40 - PC_11, // D41 - PC_12, // D42 - PC_13, // D43 - PC_14, // D44 - PC_15, // D45 - PD_2, // D46 - PH_0, // D47 - PH_1 // D48 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 30, // A10, PC0 - 31, // A11, PC1 - 32, // A12, PC2 - 33, // A13, PC3 - 34, // A14, PC4 - 35 // A15, PC5 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573RIT/variant_generic.h b/variants/STM32H5xx/H573RIT/variant_generic.h deleted file mode 100644 index 5a73f7757a..0000000000 --- a/variants/STM32H5xx/H573RIT/variant_generic.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB10 25 -#define PB12 26 -#define PB13 27 -#define PB14 28 -#define PB15 29 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 36 -#define PC7 37 -#define PC8 38 -#define PC9 39 -#define PC10 40 -#define PC11 41 -#define PC12 42 -#define PC13 43 -#define PC14 44 -#define PC15 45 -#define PD2 46 -#define PH0 47 -#define PH1 48 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) - -#define NUM_DIGITAL_PINS 49 -#define NUM_ANALOG_INPUTS 16 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// SDMMC signals not available -#define SDMMC_CDIR_NA - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H5xx/H573RIV/CMakeLists.txt b/variants/STM32H5xx/H573RIV/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H573RIV/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573RIV/PeripheralPins.c b/variants/STM32H5xx/H573RIV/PeripheralPins.c deleted file mode 100644 index 8ed83a895c..0000000000 --- a/variants/STM32H5xx/H573RIV/PeripheralPins.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573RIVx.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573RIV/PinNamesVar.h b/variants/STM32H5xx/H573RIV/PinNamesVar.h deleted file mode 100644 index 1ee6296ec3..0000000000 --- a/variants/STM32H5xx/H573RIV/PinNamesVar.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_9_ALT1 = PB_9 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = NC, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = NC, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573RIV/boards_entry.txt b/variants/STM32H5xx/H573RIV/boards_entry.txt deleted file mode 100644 index 2c0c35462f..0000000000 --- a/variants/STM32H5xx/H573RIV/boards_entry.txt +++ /dev/null @@ -1,13 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573RIVx -GenH5.menu.pnum.GENERIC_H573RIVX=Generic H573RIVx -GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573RIVX.build.board=GENERIC_H573RIVX -GenH5.menu.pnum.GENERIC_H573RIVX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573RIVX.build.variant=STM32H5xx/H573RIV - diff --git a/variants/STM32H5xx/H573RIV/generic_clock.c b/variants/STM32H5xx/H573RIV/generic_clock.c deleted file mode 100644 index e4587f4e08..0000000000 --- a/variants/STM32H5xx/H573RIV/generic_clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573RIVX) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573RIV/variant_generic.cpp b/variants/STM32H5xx/H573RIV/variant_generic.cpp deleted file mode 100644 index deaba50874..0000000000 --- a/variants/STM32H5xx/H573RIV/variant_generic.cpp +++ /dev/null @@ -1,93 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573RIVX) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_9, // D25 - PB_10, // D26 - PB_11, // D27 - PB_12, // D28 - PB_13, // D29 - PB_14, // D30 - PB_15, // D31 - PC_0, // D32/A10 - PC_1, // D33/A11 - PC_2, // D34/A12 - PC_3, // D35/A13 - PC_4, // D36/A14 - PC_5, // D37/A15 - PC_6, // D38 - PC_7, // D39 - PC_8, // D40 - PC_9, // D41 - PC_10, // D42 - PC_11, // D43 - PC_12, // D44 - PC_13, // D45 - PC_14, // D46 - PC_15, // D47 - PD_11, // D48 - PD_12, // D49 - PE_0, // D50 - PH_0, // D51 - PH_1 // D52 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 32, // A10, PC0 - 33, // A11, PC1 - 34, // A12, PC2 - 35, // A13, PC3 - 36, // A14, PC4 - 37 // A15, PC5 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573RIV/variant_generic.h b/variants/STM32H5xx/H573RIV/variant_generic.h deleted file mode 100644 index 34c02d73af..0000000000 --- a/variants/STM32H5xx/H573RIV/variant_generic.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB11 27 -#define PB12 28 -#define PB13 29 -#define PB14 30 -#define PB15 31 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 38 -#define PC7 39 -#define PC8 40 -#define PC9 41 -#define PC10 42 -#define PC11 43 -#define PC12 44 -#define PC13 45 -#define PC14 46 -#define PC15 47 -#define PD11 48 -#define PD12 49 -#define PE0 50 -#define PH0 51 -#define PH1 52 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB9_ALT1 (PB9 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) - -#define NUM_DIGITAL_PINS 53 -#define NUM_ANALOG_INPUTS 16 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H5xx/H573VIT/CMakeLists.txt b/variants/STM32H5xx/H573VIT/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H573VIT/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573VIT/PeripheralPins.c b/variants/STM32H5xx/H573VIT/PeripheralPins.c deleted file mode 100644 index 16dc6127d9..0000000000 --- a/variants/STM32H5xx/H573VIT/PeripheralPins.c +++ /dev/null @@ -1,683 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573VITx.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, - {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573VIT/PinNamesVar.h b/variants/STM32H5xx/H573VIT/PinNamesVar.h deleted file mode 100644 index 118d5c80d2..0000000000 --- a/variants/STM32H5xx/H573VIT/PinNamesVar.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_9_ALT1 = PB_9 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = PD_2, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = PD_3, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573VIT/boards_entry.txt b/variants/STM32H5xx/H573VIT/boards_entry.txt deleted file mode 100644 index 3e62eb15a5..0000000000 --- a/variants/STM32H5xx/H573VIT/boards_entry.txt +++ /dev/null @@ -1,13 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573VITx -GenH5.menu.pnum.GENERIC_H573VITX=Generic H573VITx -GenH5.menu.pnum.GENERIC_H573VITX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573VITX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573VITX.build.board=GENERIC_H573VITX -GenH5.menu.pnum.GENERIC_H573VITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573VITX.build.variant=STM32H5xx/H573VIT - diff --git a/variants/STM32H5xx/H573VIT/generic_clock.c b/variants/STM32H5xx/H573VIT/generic_clock.c deleted file mode 100644 index 21ac09faa6..0000000000 --- a/variants/STM32H5xx/H573VIT/generic_clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573VITX) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573VIT/variant_generic.cpp b/variants/STM32H5xx/H573VIT/variant_generic.cpp deleted file mode 100644 index c6a0c12914..0000000000 --- a/variants/STM32H5xx/H573VIT/variant_generic.cpp +++ /dev/null @@ -1,120 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573VITX) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_9, // D25 - PB_10, // D26 - PB_12, // D27 - PB_13, // D28 - PB_14, // D29 - PB_15, // D30 - PC_0, // D31/A10 - PC_1, // D32/A11 - PC_2, // D33/A12 - PC_3, // D34/A13 - PC_4, // D35/A14 - PC_5, // D36/A15 - PC_6, // D37 - PC_7, // D38 - PC_8, // D39 - PC_9, // D40 - PC_10, // D41 - PC_11, // D42 - PC_12, // D43 - PC_13, // D44 - PC_14, // D45 - PC_15, // D46 - PD_0, // D47 - PD_1, // D48 - PD_2, // D49 - PD_3, // D50 - PD_4, // D51 - PD_5, // D52 - PD_6, // D53 - PD_7, // D54 - PD_8, // D55 - PD_9, // D56 - PD_10, // D57 - PD_11, // D58 - PD_12, // D59 - PD_13, // D60 - PD_14, // D61 - PD_15, // D62 - PE_0, // D63 - PE_2, // D64 - PE_3, // D65 - PE_4, // D66 - PE_5, // D67 - PE_6, // D68 - PE_7, // D69 - PE_8, // D70 - PE_9, // D71 - PE_10, // D72 - PE_11, // D73 - PE_12, // D74 - PE_13, // D75 - PE_14, // D76 - PE_15, // D77 - PH_0, // D78 - PH_1 // D79 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 31, // A10, PC0 - 32, // A11, PC1 - 33, // A12, PC2 - 34, // A13, PC3 - 35, // A14, PC4 - 36 // A15, PC5 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573VIT/variant_generic.h b/variants/STM32H5xx/H573VIT/variant_generic.h deleted file mode 100644 index 2ddfafc68c..0000000000 --- a/variants/STM32H5xx/H573VIT/variant_generic.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB12 27 -#define PB13 28 -#define PB14 29 -#define PB15 30 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 37 -#define PC7 38 -#define PC8 39 -#define PC9 40 -#define PC10 41 -#define PC11 42 -#define PC12 43 -#define PC13 44 -#define PC14 45 -#define PC15 46 -#define PD0 47 -#define PD1 48 -#define PD2 49 -#define PD3 50 -#define PD4 51 -#define PD5 52 -#define PD6 53 -#define PD7 54 -#define PD8 55 -#define PD9 56 -#define PD10 57 -#define PD11 58 -#define PD12 59 -#define PD13 60 -#define PD14 61 -#define PD15 62 -#define PE0 63 -#define PE2 64 -#define PE3 65 -#define PE4 66 -#define PE5 67 -#define PE6 68 -#define PE7 69 -#define PE8 70 -#define PE9 71 -#define PE10 72 -#define PE11 73 -#define PE12 74 -#define PE13 75 -#define PE14 76 -#define PE15 77 -#define PH0 78 -#define PH1 79 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB9_ALT1 (PB9 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) - -#define NUM_DIGITAL_PINS 80 -#define NUM_ANALOG_INPUTS 16 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H5xx/H573ZIT/CMakeLists.txt b/variants/STM32H5xx/H573ZIT/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32H5xx/H573ZIT/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32H5xx/H573ZIT/PeripheralPins.c b/variants/STM32H5xx/H573ZIT/PeripheralPins.c deleted file mode 100644 index 5c1e4c5f46..0000000000 --- a/variants/STM32H5xx/H573ZIT/PeripheralPins.c +++ /dev/null @@ -1,774 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -/* - * Automatically generated from STM32H573ZITx.xml - * CubeMX DB release 6.0.90 - */ -#if !defined(CUSTOM_PERIPHERAL_PINS) -#include "Arduino.h" -#include "PeripheralPins.h" - -/* ===== - * Notes: - * - The pins mentioned Px_y_ALTz are alternative possibilities which use other - * HW peripheral instances. You can use them the same way as any other "normal" - * pin (i.e. analogWrite(PA7_ALT1, 128);). - * - * - Commented lines are alternative possibilities which are not used per default. - * If you change them, you will have to know what you do - * ===== - */ - -//*** ADC *** - -#ifdef HAL_ADC_MODULE_ENABLED -WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 - {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 - {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 - {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 - {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 - {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 - {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 - {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 - {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 - {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 - {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 - {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 - {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 - {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 - {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 - {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 - {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 - {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 - {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 - {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 - {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 - {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 - {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 - {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 - {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 - {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 - {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 - {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 - {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 - {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 - {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 - {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 - {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 - {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 - {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 - {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 - {NC, NP, 0} -}; -#endif - -//*** DAC *** - -#ifdef HAL_DAC_MODULE_ENABLED -WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NP, 0} -}; -#endif - -//*** I2C *** - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I2C_MODULE_ENABLED -WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, - {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, - {NC, NP, 0} -}; -#endif - -//*** I3C *** - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SDA[] = { - {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_I3C_MODULE_ENABLED -WEAK const PinMap PinMap_I3C_SCL[] = { - {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, - {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, - {NC, NP, 0} -}; -#endif - -//*** TIM *** - -#ifdef HAL_TIM_MODULE_ENABLED -WEAK const PinMap PinMap_TIM[] = { - {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 - {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 - {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N - {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N - {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N - {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 - {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 - {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N - {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {NC, NP, 0} -}; -#endif - -//*** UART *** - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, - {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, - {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_UART_MODULE_ENABLED -WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, - {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, - {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, - {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, - {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, - {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, - {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {NC, NP, 0} -}; -#endif - -//*** SPI *** - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, - {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SPI_MODULE_ENABLED -WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, - {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, - {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, - {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, - {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, - {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NP, 0} -}; -#endif - -//*** FDCAN *** - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -#ifdef HAL_FDCAN_MODULE_ENABLED -WEAK const PinMap PinMap_CAN_TD[] = { - {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, - {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NP, 0} -}; -#endif - -//*** ETHERNET *** - -#ifdef HAL_ETH_MODULE_ENABLED -WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PB_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 - {NC, NP, 0} -}; -#endif - -//*** OCTOSPI *** - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { - {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 - {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { - {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 - {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 - {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { - {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 - {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { - {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 - {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 - {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { - {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { - {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 - {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 - {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { - {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 - {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 - {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 - {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { - {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 - {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { - {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK - {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK - {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_OSPI_MODULE_ENABLED -WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { - {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS - {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS - {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS - {NC, NP, 0} -}; -#endif - -//*** USB *** - -#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB[] = { - {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} -}; -#endif - -//*** SD *** - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CMD[] = { - {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD - {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD - {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CK[] = { - {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK - {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK - {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA0[] = { - {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 - {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 - {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA1[] = { - {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 - {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 - {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA2[] = { - {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 - {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 - {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA3[] = { - {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 - {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 - {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA4[] = { - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 - {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA5[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 - {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA6[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 - {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_DATA7[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 - {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CKIN[] = { - {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN - {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_CDIR[] = { - {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D0DIR[] = { - {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR - {NC, NP, 0} -}; -#endif - -#ifdef HAL_SD_MODULE_ENABLED -WEAK const PinMap PinMap_SD_D123DIR[] = { - {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR - {NC, NP, 0} -}; -#endif - -#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H573ZIT/PinNamesVar.h b/variants/STM32H5xx/H573ZIT/PinNamesVar.h deleted file mode 100644 index df96a15ce4..0000000000 --- a/variants/STM32H5xx/H573ZIT/PinNamesVar.h +++ /dev/null @@ -1,88 +0,0 @@ -/* Alternate pin name */ -PA_0_ALT1 = PA_0 | ALT1, -PA_1_ALT1 = PA_1 | ALT1, -PA_1_ALT2 = PA_1 | ALT2, -PA_2_ALT1 = PA_2 | ALT1, -PA_2_ALT2 = PA_2 | ALT2, -PA_3_ALT1 = PA_3 | ALT1, -PA_3_ALT2 = PA_3 | ALT2, -PA_4_ALT1 = PA_4 | ALT1, -PA_4_ALT2 = PA_4 | ALT2, -PA_5_ALT1 = PA_5 | ALT1, -PA_6_ALT1 = PA_6 | ALT1, -PA_7_ALT1 = PA_7 | ALT1, -PA_7_ALT2 = PA_7 | ALT2, -PA_7_ALT3 = PA_7 | ALT3, -PA_9_ALT1 = PA_9 | ALT1, -PA_10_ALT1 = PA_10 | ALT1, -PA_11_ALT1 = PA_11 | ALT1, -PA_12_ALT1 = PA_12 | ALT1, -PA_15_ALT1 = PA_15 | ALT1, -PA_15_ALT2 = PA_15 | ALT2, -PB_0_ALT1 = PB_0 | ALT1, -PB_0_ALT2 = PB_0 | ALT2, -PB_1_ALT1 = PB_1 | ALT1, -PB_1_ALT2 = PB_1 | ALT2, -PB_3_ALT1 = PB_3 | ALT1, -PB_3_ALT2 = PB_3 | ALT2, -PB_4_ALT1 = PB_4 | ALT1, -PB_4_ALT2 = PB_4 | ALT2, -PB_5_ALT1 = PB_5 | ALT1, -PB_5_ALT2 = PB_5 | ALT2, -PB_6_ALT1 = PB_6 | ALT1, -PB_6_ALT2 = PB_6 | ALT2, -PB_7_ALT1 = PB_7 | ALT1, -PB_8_ALT1 = PB_8 | ALT1, -PB_9_ALT1 = PB_9 | ALT1, -PB_14_ALT1 = PB_14 | ALT1, -PB_14_ALT2 = PB_14 | ALT2, -PB_15_ALT1 = PB_15 | ALT1, -PB_15_ALT2 = PB_15 | ALT2, -PC_0_ALT1 = PC_0 | ALT1, -PC_1_ALT1 = PC_1 | ALT1, -PC_2_ALT1 = PC_2 | ALT1, -PC_3_ALT1 = PC_3 | ALT1, -PC_4_ALT1 = PC_4 | ALT1, -PC_5_ALT1 = PC_5 | ALT1, -PC_6_ALT1 = PC_6 | ALT1, -PC_7_ALT1 = PC_7 | ALT1, -PC_8_ALT1 = PC_8 | ALT1, -PC_9_ALT1 = PC_9 | ALT1, -PC_10_ALT1 = PC_10 | ALT1, -PC_11_ALT1 = PC_11 | ALT1, -PF_8_ALT1 = PF_8 | ALT1, -PF_9_ALT1 = PF_9 | ALT1, -PG_13_ALT1 = PG_13 | ALT1, - -/* SYS_WKUP */ -#ifdef PWR_WAKEUP_PIN1 - SYS_WKUP1 = PA_0, -#endif -#ifdef PWR_WAKEUP_PIN2 - SYS_WKUP2 = PA_2, -#endif -#ifdef PWR_WAKEUP_PIN3 - SYS_WKUP3 = NC, -#endif -#ifdef PWR_WAKEUP_PIN4 - SYS_WKUP4 = PC_13, -#endif -#ifdef PWR_WAKEUP_PIN5 - SYS_WKUP5 = PB_7, -#endif -#ifdef PWR_WAKEUP_PIN6 - SYS_WKUP6 = PC_1, -#endif -#ifdef PWR_WAKEUP_PIN7 - SYS_WKUP7 = PD_2, -#endif -#ifdef PWR_WAKEUP_PIN8 - SYS_WKUP8 = PD_3, -#endif - -/* USB */ -#ifdef USBCON - USB_DM = PA_11, - USB_DP = PA_12, - USB_SOF = PA_8, -#endif diff --git a/variants/STM32H5xx/H573ZIT/boards_entry.txt b/variants/STM32H5xx/H573ZIT/boards_entry.txt deleted file mode 100644 index 59ac286e27..0000000000 --- a/variants/STM32H5xx/H573ZIT/boards_entry.txt +++ /dev/null @@ -1,13 +0,0 @@ -# This file help to add generic board entry. -# upload.maximum_size and product_line have to be verified -# and changed if needed. -# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 - -# Generic H573ZITx -GenH5.menu.pnum.GENERIC_H573ZITX=Generic H573ZITx -GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573ZITX.build.board=GENERIC_H573ZITX -GenH5.menu.pnum.GENERIC_H573ZITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573ZITX.build.variant=STM32H5xx/H573ZIT - diff --git a/variants/STM32H5xx/H573ZIT/generic_clock.c b/variants/STM32H5xx/H573ZIT/generic_clock.c deleted file mode 100644 index 13ee132a5e..0000000000 --- a/variants/STM32H5xx/H573ZIT/generic_clock.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573ZITX) -#include "pins_arduino.h" - -/** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - - /** Configure the main internal regulator output voltage - */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); - - while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI - | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; - RCC_OscInitStruct.CSIState = RCC_CSI_ON; - RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; - RCC_OscInitStruct.PLL.PLLFRACN = 0; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - Error_Handler(); - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 - | RCC_CLOCKTYPE_PCLK3; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - Error_Handler(); - } - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 - | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; - PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { - Error_Handler(); - } -} - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573ZIT/ldscript.ld b/variants/STM32H5xx/H573ZIT/ldscript.ld deleted file mode 100644 index a1ced4e188..0000000000 --- a/variants/STM32H5xx/H573ZIT/ldscript.ld +++ /dev/null @@ -1,185 +0,0 @@ -/* -****************************************************************************** -** -** @file : LinkerScript.ld -** -** @author : Auto-generated by STM32CubeIDE -** -** @brief : Linker script for STM32H563ZITx Device from STM32H5 series -** 2048Kbytes FLASH -** 640Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -****************************************************************************** -** @attention -** -** Copyright (c) 2023 STMicroelectronics. -** All rights reserved. -** -** This software is licensed under terms that can be found in the LICENSE file -** in the root directory of this software component. -** If no LICENSE file comes with this software, it is provided AS-IS. -** -****************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE - FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "FLASH" Rom type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data into "FLASH" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data into "FLASH" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >FLASH - - .ARM : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >FLASH - - .preinit_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >FLASH - - .init_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >FLASH - - .fini_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >FLASH - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - *(.RamFunc) /* .RamFunc sections */ - *(.RamFunc*) /* .RamFunc* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM AT> FLASH - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/variants/STM32H5xx/H573ZIT/variant_generic.cpp b/variants/STM32H5xx/H573ZIT/variant_generic.cpp deleted file mode 100644 index 922235bc8f..0000000000 --- a/variants/STM32H5xx/H573ZIT/variant_generic.cpp +++ /dev/null @@ -1,156 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#if defined(ARDUINO_GENERIC_H573ZITX) -#include "pins_arduino.h" - -// Digital PinName array -const PinName digitalPin[] = { - PA_0, // D0/A0 - PA_1, // D1/A1 - PA_2, // D2/A2 - PA_3, // D3/A3 - PA_4, // D4/A4 - PA_5, // D5/A5 - PA_6, // D6/A6 - PA_7, // D7/A7 - PA_8, // D8 - PA_9, // D9 - PA_10, // D10 - PA_11, // D11 - PA_12, // D12 - PA_13, // D13 - PA_14, // D14 - PA_15, // D15 - PB_0, // D16/A8 - PB_1, // D17/A9 - PB_2, // D18 - PB_3, // D19 - PB_4, // D20 - PB_5, // D21 - PB_6, // D22 - PB_7, // D23 - PB_8, // D24 - PB_9, // D25 - PB_10, // D26 - PB_12, // D27 - PB_13, // D28 - PB_14, // D29 - PB_15, // D30 - PC_0, // D31/A10 - PC_1, // D32/A11 - PC_2, // D33/A12 - PC_3, // D34/A13 - PC_4, // D35/A14 - PC_5, // D36/A15 - PC_6, // D37 - PC_7, // D38 - PC_8, // D39 - PC_9, // D40 - PC_10, // D41 - PC_11, // D42 - PC_12, // D43 - PC_13, // D44 - PC_14, // D45 - PC_15, // D46 - PD_0, // D47 - PD_1, // D48 - PD_2, // D49 - PD_3, // D50 - PD_4, // D51 - PD_5, // D52 - PD_6, // D53 - PD_7, // D54 - PD_8, // D55 - PD_9, // D56 - PD_10, // D57 - PD_11, // D58 - PD_12, // D59 - PD_13, // D60 - PD_14, // D61 - PD_15, // D62 - PE_0, // D63 - PE_2, // D64 - PE_3, // D65 - PE_4, // D66 - PE_5, // D67 - PE_6, // D68 - PE_7, // D69 - PE_8, // D70 - PE_9, // D71 - PE_10, // D72 - PE_11, // D73 - PE_12, // D74 - PE_13, // D75 - PE_14, // D76 - PE_15, // D77 - PF_0, // D78 - PF_1, // D79 - PF_2, // D80 - PF_3, // D81 - PF_4, // D82 - PF_5, // D83 - PF_6, // D84 - PF_7, // D85 - PF_8, // D86 - PF_9, // D87 - PF_10, // D88 - PF_11, // D89/A16 - PF_12, // D90/A17 - PF_13, // D91/A18 - PF_14, // D92/A19 - PF_15, // D93 - PG_0, // D94 - PG_1, // D95 - PG_2, // D96 - PG_3, // D97 - PG_4, // D98 - PG_5, // D99 - PG_6, // D100 - PG_7, // D101 - PG_8, // D102 - PG_9, // D103 - PG_10, // D104 - PG_11, // D105 - PG_12, // D106 - PG_13, // D107 - PG_14, // D108 - PG_15, // D109 - PH_0, // D110 - PH_1 // D111 -}; - -// Analog (Ax) pin number array -const uint32_t analogInputPin[] = { - 0, // A0, PA0 - 1, // A1, PA1 - 2, // A2, PA2 - 3, // A3, PA3 - 4, // A4, PA4 - 5, // A5, PA5 - 6, // A6, PA6 - 7, // A7, PA7 - 16, // A8, PB0 - 17, // A9, PB1 - 31, // A10, PC0 - 32, // A11, PC1 - 33, // A12, PC2 - 34, // A13, PC3 - 35, // A14, PC4 - 36, // A15, PC5 - 89, // A16, PF11 - 90, // A17, PF12 - 91, // A18, PF13 - 92 // A19, PF14 -}; - -#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573ZIT/variant_generic.h b/variants/STM32H5xx/H573ZIT/variant_generic.h deleted file mode 100644 index a3c4588c43..0000000000 --- a/variants/STM32H5xx/H573ZIT/variant_generic.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#pragma once - -/*---------------------------------------------------------------------------- - * STM32 pins number - *----------------------------------------------------------------------------*/ -#define PA0 PIN_A0 -#define PA1 PIN_A1 -#define PA2 PIN_A2 -#define PA3 PIN_A3 -#define PA4 PIN_A4 -#define PA5 PIN_A5 -#define PA6 PIN_A6 -#define PA7 PIN_A7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 PIN_A8 -#define PB1 PIN_A9 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB12 27 -#define PB13 28 -#define PB14 29 -#define PB15 30 -#define PC0 PIN_A10 -#define PC1 PIN_A11 -#define PC2 PIN_A12 -#define PC3 PIN_A13 -#define PC4 PIN_A14 -#define PC5 PIN_A15 -#define PC6 37 -#define PC7 38 -#define PC8 39 -#define PC9 40 -#define PC10 41 -#define PC11 42 -#define PC12 43 -#define PC13 44 -#define PC14 45 -#define PC15 46 -#define PD0 47 -#define PD1 48 -#define PD2 49 -#define PD3 50 -#define PD4 51 -#define PD5 52 -#define PD6 53 -#define PD7 54 -#define PD8 55 -#define PD9 56 -#define PD10 57 -#define PD11 58 -#define PD12 59 -#define PD13 60 -#define PD14 61 -#define PD15 62 -#define PE0 63 -#define PE2 64 -#define PE3 65 -#define PE4 66 -#define PE5 67 -#define PE6 68 -#define PE7 69 -#define PE8 70 -#define PE9 71 -#define PE10 72 -#define PE11 73 -#define PE12 74 -#define PE13 75 -#define PE14 76 -#define PE15 77 -#define PF0 78 -#define PF1 79 -#define PF2 80 -#define PF3 81 -#define PF4 82 -#define PF5 83 -#define PF6 84 -#define PF7 85 -#define PF8 86 -#define PF9 87 -#define PF10 88 -#define PF11 PIN_A16 -#define PF12 PIN_A17 -#define PF13 PIN_A18 -#define PF14 PIN_A19 -#define PF15 93 -#define PG0 94 -#define PG1 95 -#define PG2 96 -#define PG3 97 -#define PG4 98 -#define PG5 99 -#define PG6 100 -#define PG7 101 -#define PG8 102 -#define PG9 103 -#define PG10 104 -#define PG11 105 -#define PG12 106 -#define PG13 107 -#define PG14 108 -#define PG15 109 -#define PH0 110 -#define PH1 111 - -// Alternate pins number -#define PA0_ALT1 (PA0 | ALT1) -#define PA1_ALT1 (PA1 | ALT1) -#define PA1_ALT2 (PA1 | ALT2) -#define PA2_ALT1 (PA2 | ALT1) -#define PA2_ALT2 (PA2 | ALT2) -#define PA3_ALT1 (PA3 | ALT1) -#define PA3_ALT2 (PA3 | ALT2) -#define PA4_ALT1 (PA4 | ALT1) -#define PA4_ALT2 (PA4 | ALT2) -#define PA5_ALT1 (PA5 | ALT1) -#define PA6_ALT1 (PA6 | ALT1) -#define PA7_ALT1 (PA7 | ALT1) -#define PA7_ALT2 (PA7 | ALT2) -#define PA7_ALT3 (PA7 | ALT3) -#define PA9_ALT1 (PA9 | ALT1) -#define PA10_ALT1 (PA10 | ALT1) -#define PA11_ALT1 (PA11 | ALT1) -#define PA12_ALT1 (PA12 | ALT1) -#define PA15_ALT1 (PA15 | ALT1) -#define PA15_ALT2 (PA15 | ALT2) -#define PB0_ALT1 (PB0 | ALT1) -#define PB0_ALT2 (PB0 | ALT2) -#define PB1_ALT1 (PB1 | ALT1) -#define PB1_ALT2 (PB1 | ALT2) -#define PB3_ALT1 (PB3 | ALT1) -#define PB3_ALT2 (PB3 | ALT2) -#define PB4_ALT1 (PB4 | ALT1) -#define PB4_ALT2 (PB4 | ALT2) -#define PB5_ALT1 (PB5 | ALT1) -#define PB5_ALT2 (PB5 | ALT2) -#define PB6_ALT1 (PB6 | ALT1) -#define PB6_ALT2 (PB6 | ALT2) -#define PB7_ALT1 (PB7 | ALT1) -#define PB8_ALT1 (PB8 | ALT1) -#define PB9_ALT1 (PB9 | ALT1) -#define PB14_ALT1 (PB14 | ALT1) -#define PB14_ALT2 (PB14 | ALT2) -#define PB15_ALT1 (PB15 | ALT1) -#define PB15_ALT2 (PB15 | ALT2) -#define PC0_ALT1 (PC0 | ALT1) -#define PC1_ALT1 (PC1 | ALT1) -#define PC2_ALT1 (PC2 | ALT1) -#define PC3_ALT1 (PC3 | ALT1) -#define PC4_ALT1 (PC4 | ALT1) -#define PC5_ALT1 (PC5 | ALT1) -#define PC6_ALT1 (PC6 | ALT1) -#define PC7_ALT1 (PC7 | ALT1) -#define PC8_ALT1 (PC8 | ALT1) -#define PC9_ALT1 (PC9 | ALT1) -#define PC10_ALT1 (PC10 | ALT1) -#define PC11_ALT1 (PC11 | ALT1) -#define PF8_ALT1 (PF8 | ALT1) -#define PF9_ALT1 (PF9 | ALT1) -#define PG13_ALT1 (PG13 | ALT1) - -#define NUM_DIGITAL_PINS 112 -#define NUM_ANALOG_INPUTS 20 - -// On-board LED pin number -#ifndef LED_BUILTIN - #define LED_BUILTIN PNUM_NOT_DEFINED -#endif - -// On-board user button -#ifndef USER_BTN - #define USER_BTN PNUM_NOT_DEFINED -#endif - -// SPI definitions -#ifndef PIN_SPI_SS - #define PIN_SPI_SS PA4 -#endif -#ifndef PIN_SPI_SS1 - #define PIN_SPI_SS1 PA15 -#endif -#ifndef PIN_SPI_SS2 - #define PIN_SPI_SS2 PG10 -#endif -#ifndef PIN_SPI_SS3 - #define PIN_SPI_SS3 PNUM_NOT_DEFINED -#endif -#ifndef PIN_SPI_MOSI - #define PIN_SPI_MOSI PA7 -#endif -#ifndef PIN_SPI_MISO - #define PIN_SPI_MISO PA6 -#endif -#ifndef PIN_SPI_SCK - #define PIN_SPI_SCK PA5 -#endif - -// I2C definitions -#ifndef PIN_WIRE_SDA - #define PIN_WIRE_SDA PB3 -#endif -#ifndef PIN_WIRE_SCL - #define PIN_WIRE_SCL PB10 -#endif - -// Timer Definitions -// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin -#ifndef TIMER_TONE - #define TIMER_TONE TIM6 -#endif -#ifndef TIMER_SERVO - #define TIMER_SERVO TIM7 -#endif - -// UART Definitions -#ifndef SERIAL_UART_INSTANCE - #define SERIAL_UART_INSTANCE 4 -#endif - -// Default pin used for generic 'Serial' instance -// Mandatory for Firmata -#ifndef PIN_SERIAL_RX - #define PIN_SERIAL_RX PA1 -#endif -#ifndef PIN_SERIAL_TX - #define PIN_SERIAL_TX PA0 -#endif - -// Extra HAL modules -#if !defined(HAL_DAC_MODULE_DISABLED) - #define HAL_DAC_MODULE_ENABLED -#endif -#if !defined(HAL_ETH_MODULE_DISABLED) - #define HAL_ETH_MODULE_ENABLED -#endif -#if !defined(HAL_OSPI_MODULE_DISABLED) - #define HAL_OSPI_MODULE_ENABLED -#endif -#if !defined(HAL_SD_MODULE_DISABLED) - #define HAL_SD_MODULE_ENABLED -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#ifdef __cplusplus - // These serial port names are intended to allow libraries and architecture-neutral - // sketches to automatically default to the correct port name for a particular type - // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, - // the first hardware serial port whose RX/TX pins are not dedicated to another use. - // - // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor - // - // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial - // - // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library - // - // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. - // - // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX - // pins are NOT connected to anything by default. - #ifndef SERIAL_PORT_MONITOR - #define SERIAL_PORT_MONITOR Serial - #endif - #ifndef SERIAL_PORT_HARDWARE - #define SERIAL_PORT_HARDWARE Serial - #endif -#endif diff --git a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c index d176de9f89..1389358868 100644 --- a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32H723VGHx.xml, STM32H723VGTx.xml * STM32H730VBHx.xml, STM32H730VBTx.xml * STM32H733VGHx.xml, STM32H733VGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c index 540b24e5e9..c503e24277 100644 --- a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c +++ b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H723ZEIx.xml, STM32H723ZGIx.xml * STM32H730ZBIx.xml, STM32H733ZGIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c index 18dcdcd9c7..e210312182 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H723ZETx.xml, STM32H723ZGTx.xml * STM32H730ZBTx.xml, STM32H733ZGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c index 8d63e7fe30..d54c5ea4bb 100644 --- a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c +++ b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725AEIx.xml, STM32H725AGIx.xml * STM32H730ABIxQ.xml, STM32H735AGIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c index a00d1821ce..10507d2324 100644 --- a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c +++ b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725IEKx.xml, STM32H725IGKx.xml * STM32H730IBKxQ.xml, STM32H735IGKx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c index 1127748b70..0a21f59317 100644 --- a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725IETx.xml, STM32H725IGTx.xml * STM32H730IBTxQ.xml, STM32H735IGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c index cf186d3ecb..9f143a6a37 100644 --- a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c +++ b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725REVx.xml, STM32H725RGVx.xml * STM32H735RGVx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c index d3e3f9ba0a..201545016f 100644 --- a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c +++ b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725VEHx.xml, STM32H725VGHx.xml * STM32H735VGHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c index 586fb62f2b..7021e21476 100644 --- a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725VETx.xml, STM32H725VGTx.xml * STM32H735VGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c b/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c index 9fc8475093..45f02af3e4 100644 --- a/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c +++ b/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H725VGYx.xml, STM32H735VGYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c index 09635fcc5c..84762e895e 100644 --- a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725ZETx.xml, STM32H725ZGTx.xml * STM32H735ZGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c index ffe8a6bbe6..ec96fdac02 100644 --- a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c +++ b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H742A(G-I)Ix.xml, STM32H743A(G-I)Ix.xml * STM32H753AIIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c index 719aaa602c..3aa35930e5 100644 --- a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H742B(G-I)Tx.xml, STM32H743BGTx.xml * STM32H743BITx.xml, STM32H753BITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c index 2ac5ce804f..17caf474ba 100644 --- a/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32H743IIKx.xml, STM32H743IITx.xml * STM32H750IBKx.xml, STM32H750IBTx.xml * STM32H753IIKx.xml, STM32H753IITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c index 81905ae85d..65a42c6d7b 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32H743V(G-I)Hx.xml, STM32H743VGTx.xml * STM32H743VITx.xml, STM32H750VBTx.xml * STM32H753VIHx.xml, STM32H753VITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c index da341c3e2b..408029db45 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c @@ -17,7 +17,7 @@ * STM32H747XIHx.xml, STM32H750XBHx.xml * STM32H753XIHx.xml, STM32H755XIHx.xml * STM32H757XIHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c index e016bbf421..289459a38d 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32H747IGTx.xml, STM32H747IITx.xml * STM32H750ZBTx.xml, STM32H753ZITx.xml * STM32H757AIIx.xml, STM32H757IITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c index f30f35fdc1..48c8235b2c 100644 --- a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745BGTx.xml, STM32H745BITx.xml * STM32H755BITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c index 15f7c60214..842f859e71 100644 --- a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c +++ b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745IGKx.xml, STM32H745IIKx.xml * STM32H755IIKx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c index 3ba50ed8ee..c284bca31e 100644 --- a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745IGTx.xml, STM32H745IITx.xml * STM32H755IITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c index c2a1cdc621..989bda4f22 100644 --- a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745ZGTx.xml, STM32H745ZITx.xml * STM32H755ZITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c index 91133cd271..8252717595 100644 --- a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H747BGTx.xml, STM32H747BITx.xml * STM32H757BITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c b/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c index a227724a87..bfeef5e1c6 100644 --- a/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c +++ b/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H747ZIYx.xml, STM32H757ZIYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c index cb782c6f49..fdd829305e 100644 --- a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3A(G-I)IxQ.xml, STM32H7B0ABIxQ.xml * STM32H7B3AIIxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c index d7f9159125..4121439b53 100644 --- a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H7A3I(G-I)Kx.xml, STM32H7A3I(G-I)Tx.xml * STM32H7B0IBTx.xml, STM32H7B3IIKx.xml * STM32H7B3IITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c index 8cd805c029..1b5be26017 100644 --- a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3I(G-I)KxQ.xml, STM32H7B0IBKxQ.xml * STM32H7B3IIKxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c index a7f791cb1f..c9ff48bd21 100644 --- a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3I(G-I)TxQ.xml, STM32H7B3IITxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c index ee7c022d02..38cb11ea56 100644 --- a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3L(G-I)HxQ.xml, STM32H7B3LIHxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c index d914cdfb89..b5268ba83f 100644 --- a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3N(G-I)Hx.xml, STM32H7B3NIHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c index b08835dd16..dd0bf7b1fe 100644 --- a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3QIYxQ.xml, STM32H7B3QIYxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c index fcd523b601..6598984f7b 100644 --- a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3R(G-I)Tx.xml, STM32H7B0RBTx.xml * STM32H7B3RITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c index 23245dd44a..c0c167126d 100644 --- a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H7A3V(G-I)Hx.xml, STM32H7A3V(G-I)Tx.xml * STM32H7B0VBTx.xml, STM32H7B3VIHx.xml * STM32H7B3VITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c index 52c2f31e91..0c8aefc07f 100644 --- a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3V(G-I)HxQ.xml, STM32H7B3VIHxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c index f654af6e1e..fa5554b9c9 100644 --- a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3V(G-I)TxQ.xml, STM32H7B3VITxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c index 0b8a96df24..ab23322569 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3Z(G-I)Tx.xml, STM32H7B0ZBTx.xml * STM32H7B3ZITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c index 918a9e706e..2af74bd460 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3Z(G-I)TxQ.xml, STM32H7B3ZITxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010C6T/PeripheralPins.c b/variants/STM32L0xx/L010C6T/PeripheralPins.c index 7524cb3ab0..5a5c092ab4 100644 --- a/variants/STM32L0xx/L010C6T/PeripheralPins.c +++ b/variants/STM32L0xx/L010C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010C6Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c index e0992dfc0e..a4605f14d6 100644 --- a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c +++ b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L010F4Px.xml, STM32L011F(3-4)Px.xml * STM32L021F4Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c index ecbce6dabc..4724ea12f7 100644 --- a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c +++ b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L010K4Tx.xml, STM32L011K(3-4)Tx.xml * STM32L021K4Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010K8T/PeripheralPins.c b/variants/STM32L0xx/L010K8T/PeripheralPins.c index 23ae0c7700..f2eec0c927 100644 --- a/variants/STM32L0xx/L010K8T/PeripheralPins.c +++ b/variants/STM32L0xx/L010K8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010K8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010R8T/PeripheralPins.c b/variants/STM32L0xx/L010R8T/PeripheralPins.c index d6364a4496..f1900c72ad 100644 --- a/variants/STM32L0xx/L010R8T/PeripheralPins.c +++ b/variants/STM32L0xx/L010R8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010R8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010RBT/PeripheralPins.c b/variants/STM32L0xx/L010RBT/PeripheralPins.c index 5db085303d..59bf63db8a 100644 --- a/variants/STM32L0xx/L010RBT/PeripheralPins.c +++ b/variants/STM32L0xx/L010RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010RBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c index be0db0dcbb..54e13b763e 100644 --- a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c +++ b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011D(3-4)Px.xml, STM32L021D4Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c b/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c index 404a07786b..3598af09c4 100644 --- a/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011E(3-4)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c index 7d9078db54..c77351e969 100644 --- a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011F(3-4)Ux.xml, STM32L021F4Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c index f85fab2ea4..ea0942f514 100644 --- a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011G(3-4)Ux.xml, STM32L021G4Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c index c8db2cb560..637539481d 100644 --- a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011K(3-4)Ux.xml, STM32L021K4Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c index c16b709adf..06101e8585 100644 --- a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L031C(4-6)Tx.xml, STM32L031C(4-6)Ux.xml * STM32L041C(4-6)Tx.xml, STM32L041C6Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c index 51961bcdcb..82a05e6c89 100644 --- a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c +++ b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031E(4-6)Yx.xml, STM32L041E6Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c index 5705a7e5f6..c180736ede 100644 --- a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c +++ b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031F(4-6)Px.xml, STM32L041F6Px.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c index 6ba3eee106..b8125b8e64 100644 --- a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c +++ b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031G(4-6)Ux.xml, STM32L041G6Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c index b4c901f1eb..da9b34478d 100644 --- a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c +++ b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031G6UxS.xml, STM32L041G6UxS.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c index 378338cc03..bae02df06e 100644 --- a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c +++ b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031K(4-6)Tx.xml, STM32L041K6Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c index c2b98d476e..faf78d0ecf 100644 --- a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c +++ b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031K(4-6)Ux.xml, STM32L041K6Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c b/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c index 220d590854..d301186304 100644 --- a/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051C(6-8)Tx.xml, STM32L051C(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c b/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c index d1901ba414..b97c1c8746 100644 --- a/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c +++ b/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051K(6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c b/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c index 4fab36b7c4..c64104c235 100644 --- a/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c +++ b/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051K(6-8)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c b/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c index 2c218bbbe8..552c790fe1 100644 --- a/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c +++ b/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051R(6-8)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c b/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c index 5593c52f7b..dfae3e9f89 100644 --- a/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c +++ b/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051R(6-8)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c b/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c index 6e6beafb56..905a3eee84 100644 --- a/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051T(6-8)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c index 671a2019af..fc6d9fd11d 100644 --- a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L053C(6-8)Tx.xml, STM32L053C(6-8)Ux.xml * STM32L062C8Ux.xml, STM32L063C8Tx.xml * STM32L063C8Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c index d3fab5350d..c57b11fef0 100644 --- a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c +++ b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052K(6-8)Tx.xml, STM32L062K8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c index 51a7546ec5..c92118155f 100644 --- a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c +++ b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052K(6-8)Ux.xml, STM32L062K8Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c index 038ee8d06c..3e866c828e 100644 --- a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c +++ b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052R(6-8)Hx.xml, STM32L053R(6-8)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c index c7bee45c91..46292909bb 100644 --- a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c +++ b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L052R(6-8)Tx.xml, STM32L053R(6-8)Tx.xml * STM32L063R8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c index 03cecc1b29..f2761551a9 100644 --- a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c +++ b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052T(6-8)Yx.xml, STM32L052T8Fx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c index 651f6a6318..4d6c13bb2e 100644 --- a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L071C(B-Z)Tx.xml, STM32L071C(B-Z)Ux.xml * STM32L071C8Tx.xml, STM32L071C8Ux.xml * STM32L081C(B-Z)Tx.xml, STM32L081CZUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c b/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c index 5db7c2da29..6f0c8eadc2 100644 --- a/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071C(B-Z)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c index 4e44c274d4..6e92f7a488 100644 --- a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c +++ b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L071K(B-Z)Ux.xml, STM32L071K8Ux.xml * STM32L081KZUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c index 33a636d39c..865c8b6287 100644 --- a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c +++ b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071K(B-Z)Tx.xml, STM32L081KZTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c b/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c index 58adf392a2..9dd000e71a 100644 --- a/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c +++ b/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071R(B-Z)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c index 89706d7495..df9898c2be 100644 --- a/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071R(B-Z)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c index ebbabac3af..7bad6d8f7c 100644 --- a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c +++ b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L071V(B-Z)Ix.xml, STM32L071V(B-Z)Tx.xml * STM32L071V8Ix.xml, STM32L071V8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c index 0fba3ecd47..eecbbda7d3 100644 --- a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L073C(B-Z)Tx.xml, STM32L073C(B-Z)Ux.xml * STM32L082CZUx.xml, STM32L083C(B-Z)Tx.xml * STM32L083CZUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c index 4162a91f83..f29d0ee8ff 100644 --- a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c +++ b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L072C(B-Z)Yx.xml, STM32L072CZEx.xml * STM32L073CZYx.xml, STM32L082CZYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c index 7b7a14e838..a560a5be1e 100644 --- a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L072K(B-Z)Tx.xml, STM32L082K(B-Z)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c index 4848a85c93..d49c054976 100644 --- a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c +++ b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L072K(B-Z)Ux.xml, STM32L082K(B-Z)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c index 462a6e0bb7..090394fe08 100644 --- a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c +++ b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L072R(B-Z)Hx.xml, STM32L072R(B-Z)Ix.xml * STM32L073R(B-Z)Hx.xml, STM32L073RZIx.xml * STM32L083R(B-Z)Hx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c index f8ad212cbb..81c69f8b0c 100644 --- a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L072R(B-Z)Tx.xml, STM32L073R(B-Z)Tx.xml * STM32L083R(B-Z)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c index c901e218d1..e42c0745f0 100644 --- a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c +++ b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c @@ -17,7 +17,7 @@ * STM32L073V8Ix.xml, STM32L073V8Tx.xml * STM32L083V(B-Z)Ix.xml, STM32L083V(B-Z)Tx.xml * STM32L083V8Ix.xml, STM32L083V8Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c index a7b34ca65f..d60bc4773e 100644 --- a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L151C(6-8-B)Ux.xml, STM32L151C(6-8-B)UxA.xml * STM32L152C(6-8-B)Tx.xml, STM32L152C(6-8-B)TxA.xml * STM32L152C(6-8-B)Ux.xml, STM32L152C(6-8-B)UxA.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c index 1cc9afc68e..f716b23ac0 100644 --- a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L100R(8-B)Tx.xml, STM32L100R(8-B)TxA.xml * STM32L151R(6-8-B)Tx.xml, STM32L151R(6-8-B)TxA.xml * STM32L152R(6-8-B)Tx.xml, STM32L152R(6-8-B)TxA.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100RCT/PeripheralPins.c b/variants/STM32L1xx/L100RCT/PeripheralPins.c index 84e954ae97..e9255a491c 100644 --- a/variants/STM32L1xx/L100RCT/PeripheralPins.c +++ b/variants/STM32L1xx/L100RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L100RCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c index 2c8b07cc17..ae0d2264bb 100644 --- a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c +++ b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151CCTx.xml, STM32L151CCUx.xml * STM32L152CCTx.xml, STM32L152CCUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c index ea49608c94..2a570550e0 100644 --- a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151QCHx.xml, STM32L152QCHx.xml * STM32L162QCHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c index 9e659cbe74..bc34918e14 100644 --- a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151QDHx.xml, STM32L152QDHx.xml * STM32L162QDHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c b/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c index 317cbb7759..043804b09d 100644 --- a/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L151QEHx.xml, STM32L152QEHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c index 632fd85722..f9029897a4 100644 --- a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151R(6-8-B)Hx.xml, STM32L151R(6-8-B)HxA.xml * STM32L152R(6-8-B)Hx.xml, STM32L152R(6-8-B)HxA.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c index ae1c3e7109..ec6b7f1a3a 100644 --- a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152RCTx.xml, STM32L152RCTxA.xml * STM32L152UCYx.xml, STM32L162RCTx.xml * STM32L162RCTxA.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c index 07a2558bdf..6b5b6ae10d 100644 --- a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c +++ b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L151RDTx.xml, STM32L151RDYx.xml * STM32L152RDTx.xml, STM32L152RDYx.xml * STM32L162RDTx.xml, STM32L162RDYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c b/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c index fce7713a3c..e7eb6c9852 100644 --- a/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c +++ b/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151RETx.xml, STM32L152RETx.xml * STM32L162RETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c index 165f200d71..30153cc51c 100644 --- a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L151V(8-B)Tx.xml, STM32L151V(8-B)TxA.xml * STM32L152V(8-B)Hx.xml, STM32L152V(8-B)HxA.xml * STM32L152V(8-B)Tx.xml, STM32L152V(8-B)TxA.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c index 30f86d261a..04cef84f49 100644 --- a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152VCTx.xml, STM32L152VCTxA.xml * STM32L162VCHx.xml, STM32L162VCTx.xml * STM32L162VCTxA.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c index e2cc2d0aa6..ff9ce186d4 100644 --- a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c +++ b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152VDTxX.xml, STM32L152VETx.xml * STM32L152VEYx.xml, STM32L162VDYxX.xml * STM32L162VETx.xml, STM32L162VEYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c index cf6d5f54c2..f164609ac7 100644 --- a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c +++ b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151VDTx.xml, STM32L152VDTx.xml * STM32L162VDTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c index 2683bad2f2..6ec872c007 100644 --- a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZCTx.xml, STM32L152ZCTx.xml * STM32L162ZCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c index beabf8169d..3d1fd80c3e 100644 --- a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZDTx.xml, STM32L152ZDTx.xml * STM32L162ZDTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c index c720a6062c..3d85c36c86 100644 --- a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZETx.xml, STM32L152ZETx.xml * STM32L162ZETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c index 3d82795039..80169d8e3f 100644 --- a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412C8Tx.xml, STM32L412C8Ux.xml * STM32L412CBTx.xml, STM32L412CBUx.xml * STM32L422CBTx.xml, STM32L422CBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c index c9515cfd35..f4f8d1a3bb 100644 --- a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412CBTxP.xml, STM32L412CBUxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c index f996060fcc..93d682383b 100644 --- a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412K8Tx.xml, STM32L412K8Ux.xml * STM32L412KBTx.xml, STM32L412KBUx.xml * STM32L422KBTx.xml, STM32L422KBUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c index c70b2605b2..76e5e5fd04 100644 --- a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412R8Ix.xml, STM32L412R8Tx.xml * STM32L412RBIx.xml, STM32L412RBTx.xml * STM32L422RBIx.xml, STM32L422RBTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c index a573c8a89f..1719a7ad30 100644 --- a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412RBIxP.xml, STM32L412RBTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c index babc62c4cf..26ef330f70 100644 --- a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c +++ b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L412T8Yx.xml, STM32L412TBYx.xml * STM32L422TBYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c index d9dff126f0..28dfe678b6 100644 --- a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412TBYxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c index e8d156e6fd..a2d2ac3d88 100644 --- a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431C(B-C)Tx.xml, STM32L431C(B-C)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c index b23cadab10..cf8cdba41a 100644 --- a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c +++ b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431C(B-C)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c index f40b9af129..87b3454734 100644 --- a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c +++ b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431K(B-C)Ux.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c index b093aa4871..7ac1ba4bdd 100644 --- a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L431R(B-C)Ix.xml, STM32L431R(B-C)Tx.xml * STM32L431R(B-C)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c index 87c6a0f5ee..4a915488a0 100644 --- a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431VCIx.xml, STM32L431VCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c index acafc42f67..f5ed03dc97 100644 --- a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c +++ b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L432K(B-C)Ux.xml, STM32L442KCUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c index 663982eb09..b8108ffcc8 100644 --- a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433C(B-C)Tx.xml, STM32L433C(B-C)Ux.xml * STM32L443CCTx.xml, STM32L443CCUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c index 492306255d..2a4ad3a2ef 100644 --- a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433C(B-C)Yx.xml, STM32L443CCFx.xml * STM32L443CCYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c index f3b6c75374..47c1198050 100644 --- a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L433R(B-C)Ix.xml, STM32L433R(B-C)Tx.xml * STM32L433R(B-C)Yx.xml, STM32L443RCIx.xml * STM32L443RCTx.xml, STM32L443RCYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c index 6fd4d4b515..6ce7de5203 100644 --- a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L433RCTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c index b2335ffddb..e7467f9e01 100644 --- a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433VCIx.xml, STM32L433VCTx.xml * STM32L443VCIx.xml, STM32L443VCTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c index a3d7fe1043..0dfbb1f627 100644 --- a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L451C(C-E)Ux.xml, STM32L451CETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c index 063454eba8..4d1bf3101f 100644 --- a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L451R(C-E)Ix.xml, STM32L451R(C-E)Tx.xml * STM32L451R(C-E)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c index b09c4d67ec..2e24345d8a 100644 --- a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L451V(C-E)Ix.xml, STM32L451V(C-E)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c index 8989647e7e..881b0aafce 100644 --- a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L452C(C-E)Ux.xml, STM32L452CETx.xml * STM32L452CETxP.xml, STM32L462CETx.xml * STM32L462CEUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c index a237bf7add..4206229d43 100644 --- a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L452R(C-E)Yx.xml, STM32L452REYxP.xml * STM32L462REIx.xml, STM32L462RETx.xml * STM32L462REYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452RETxP/PeripheralPins.c b/variants/STM32L4xx/L452RETxP/PeripheralPins.c index b7ab60d2a1..d0337046f7 100644 --- a/variants/STM32L4xx/L452RETxP/PeripheralPins.c +++ b/variants/STM32L4xx/L452RETxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L452RETxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c index b93e977b9c..4334919bfc 100644 --- a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L452V(C-E)Ix.xml, STM32L452V(C-E)Tx.xml * STM32L462VEIx.xml, STM32L462VETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c index e0a391222a..f1a2625244 100644 --- a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c +++ b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471Q(E-G)Ix.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c index 87bdfbcf47..f8bab98ce4 100644 --- a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c +++ b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471R(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c index 1aebda33bb..cfae006f70 100644 --- a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c +++ b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471V(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c index 1d45210388..c09f44626a 100644 --- a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471Z(E-G)Jx.xml, STM32L471Z(E-G)Tx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c index 8c7c1149d8..e5a2f15fc5 100644 --- a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L475R(C-E-G)Tx.xml, STM32L476R(C-E-G)Tx.xml * STM32L486RGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c index a372d37220..5ef2ef55d4 100644 --- a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L475V(C-E-G)Tx.xml, STM32L476V(C-E-G)Tx.xml * STM32L486VGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c index 33a75e1c7a..024390edfc 100644 --- a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c +++ b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476J(E-G)Yx.xml, STM32L485J(C-E)Yx.xml * STM32L486JGYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c index af58cb1d26..6ec9a93c90 100644 --- a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476JGYxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c index cdc1bec083..79f99c8be2 100644 --- a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c +++ b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476M(E-G)Yx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c index 31c335c351..9de922530b 100644 --- a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476Q(E-G)Ix.xml, STM32L476QGIxP.xml * STM32L486QGIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c index 0d38e20a85..f98d550fb4 100644 --- a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476VGYxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c index 40067b324c..b100c8e795 100644 --- a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476Z(E-G)Tx.xml, STM32L476ZGJx.xml * STM32L486ZGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c index 34b5109e32..017a25c3e2 100644 --- a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476ZGTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c index b3c7f13f73..0256aefda6 100644 --- a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c +++ b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496A(E-G)Ix.xml, STM32L4A6AGIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c index d3d4360031..7a52106613 100644 --- a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496AGIxP.xml, STM32L4A6AGIxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c index 207b749b56..1b071e5dfd 100644 --- a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L496Q(E-G)Ix.xml, STM32L496QGIxS.xml * STM32L4A6QGIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c index 611075e0fb..b533a04949 100644 --- a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496QGIxP.xml, STM32L4A6QGIxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c index 8e9115b98f..46cf0b412b 100644 --- a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496R(E-G)Tx.xml, STM32L4A6RGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c index 49d755551e..11dfab5355 100644 --- a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496RGTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c index 1145e9069b..00b1dd0cc2 100644 --- a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496V(E-G)Tx.xml, STM32L4A6VGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c index 9df2dce8f1..c846cc32b8 100644 --- a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGTxP.xml, STM32L4A6VGTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c index dca289801e..69cdb6641e 100644 --- a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGYx.xml, STM32L4A6VGYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c index 9dbba9eab6..1f5c2104a5 100644 --- a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGYxP.xml, STM32L4A6VGYxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c index 116b90115b..047c255d3a 100644 --- a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496WGYxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c index 65d6e2a892..afdda05daa 100644 --- a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496Z(E-G)Tx.xml, STM32L4A6ZGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c index 08f77c2b69..866b3414ff 100644 --- a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496ZGTxP.xml, STM32L4A6ZGTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c index e477b2b4c7..ecc6667bfb 100644 --- a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4A6RGTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c index 95b07aa315..bdd575a059 100644 --- a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5A(G-E)Ix.xml, STM32L4Q5AGIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c index bdb3e28510..d70715746c 100644 --- a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5AGIxP.xml, STM32L4Q5AGIxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c index 7de839f6cf..514fcf6c5a 100644 --- a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5C(G-E)Tx.xml, STM32L4P5C(G-E)Ux.xml * STM32L4Q5CGTx.xml, STM32L4Q5CGUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c index 1980a121f9..53349b97bc 100644 --- a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5CGTxP.xml, STM32L4P5CGUxP.xml * STM32L4Q5CGTxP.xml, STM32L4Q5CGUxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c index a7695fd5e9..ba31a2b643 100644 --- a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5Q(G-E)Ix.xml, STM32L4Q5QGIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c index fffaa19592..81a11d7192 100644 --- a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5QGIxP.xml, STM32L4P5QGIxS.xml * STM32L4Q5QGIxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c index cf7bb11f23..c4499fb632 100644 --- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5R(G-E)Tx.xml, STM32L4Q5RGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c index ee0f42384e..41e0045566 100644 --- a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5RGTxP.xml, STM32L4Q5RGTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c index d348ddee5f..e8da02d226 100644 --- a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5V(G-E)Tx.xml, STM32L4Q5VGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c index 2957eb1f18..788c1cda5e 100644 --- a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5V(G-E)Yx.xml, STM32L4Q5VGYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c index 2c2f7fd0ca..799223aa4c 100644 --- a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5VGTxP.xml, STM32L4Q5VGTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c index 804d8646f2..65b93ace9a 100644 --- a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5VGYxP.xml, STM32L4Q5VGYxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c index 2e33b20917..94a72b7003 100644 --- a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5Z(G-E)Tx.xml, STM32L4Q5ZGTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c index d96b19ed2a..ac613062ab 100644 --- a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5ZGTxP.xml, STM32L4Q5ZGTxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c index 1e1aa15836..0236167968 100644 --- a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L4R5A(G-I)Ix.xml, STM32L4R5AIIxP.xml * STM32L4R7AIIx.xml, STM32L4S5AIIx.xml * STM32L4S7AIIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c index 29ff6c58af..cb3a61cc75 100644 --- a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Q(G-I)Ix.xml, STM32L4R5QGIxS.xml * STM32L4R5QIIxP.xml, STM32L4S5QIIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c index c7fbf0e32c..7d5bad6adc 100644 --- a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5V(G-I)Tx.xml, STM32L4R7VITx.xml * STM32L4S5VITx.xml, STM32L4S7VITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c index 6f5a55bd5e..204f4884c7 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Z(G-I)Tx.xml, STM32L4R7ZITx.xml * STM32L4S5ZITx.xml, STM32L4S7ZITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c index b4e54e9635..29e2048582 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Z(G-I)Yx.xml, STM32L4R9Z(G-I)Yx.xml * STM32L4S5ZIYx.xml, STM32L4S9ZIYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c index 5f607943b0..9f130547c2 100644 --- a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R5ZITxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c index f817d89112..ef035f5724 100644 --- a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9A(G-I)Ix.xml, STM32L4S9AIIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c index f4d7fe21f2..5b1db0be71 100644 --- a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9V(G-I)Tx.xml, STM32L4S9VITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c index 28ad28d0ad..0e7a329234 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9Z(G-I)Jx.xml, STM32L4S9ZIJx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c index 4ecbc96d32..8248bb55e2 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9Z(G-I)Tx.xml, STM32L4S9ZITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c index a8fccda116..c89d8c65b2 100644 --- a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9ZIYxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c index d243f13ca1..487dcae134 100644 --- a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c +++ b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L552C(C-E)Tx.xml, STM32L552C(C-E)Ux.xml * STM32L562CETx.xml, STM32L562CEUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c index e75d5bbbe1..3366e67247 100644 --- a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c +++ b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L552CETxP.xml, STM32L552CEUxP.xml * STM32L562CETxP.xml, STM32L562CEUxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c index 420842521f..5969662431 100644 --- a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552MEYxP.xml, STM32L562MEYxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c index 962ba82faa..1c68416a4d 100644 --- a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552MEYxQ.xml, STM32L562MEYxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c index 9adfed6728..061a137d96 100644 --- a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552Q(C-E)IxQ.xml, STM32L562QEIxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c b/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c index 653a278980..7b8f2b1157 100644 --- a/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c +++ b/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552QEIx.xml, STM32L562QEIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c index b2f86051b1..478104adfe 100644 --- a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552QEIxP.xml, STM32L562QEIxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c b/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c index ea4ce236eb..7a44dc7b1b 100644 --- a/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c +++ b/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552R(C-E)Tx.xml, STM32L562RETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c b/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c index 02aa2ccf8d..c81c6dbeb0 100644 --- a/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552RETxP.xml, STM32L562RETxP.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c index 13d89236c8..10cb8b5e45 100644 --- a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552RETxQ.xml, STM32L562RETxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c index c2b8d734c6..d8fd8210f7 100644 --- a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552V(C-E)TxQ.xml, STM32L562VETxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c b/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c index d5182b0ab1..559eff7fec 100644 --- a/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c +++ b/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552VETx.xml, STM32L562VETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c index bc69698811..1b9706ac1a 100644 --- a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552Z(C-E)TxQ.xml, STM32L562ZETxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c b/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c index d80c09aaa1..b213c1b8d2 100644 --- a/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c +++ b/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552ZETx.xml, STM32L562ZETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c index dcf47d0c3a..e203ffdf55 100644 --- a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP151CABx.xml, STM32MP151CADx.xml * STM32MP151DABx.xml, STM32MP151DADx.xml * STM32MP151FABx.xml, STM32MP151FADx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c index f97547205b..49d9e72f62 100644 --- a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32MP151AAAx.xml, STM32MP151CAAx.xml * STM32MP151DAAx.xml, STM32MP151FAAx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c index 3a00300b84..42c20313af 100644 --- a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32MP151AACx.xml, STM32MP151CACx.xml * STM32MP151DACx.xml, STM32MP151FACx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c index 027dacb040..164a818e24 100644 --- a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c @@ -19,7 +19,7 @@ * STM32MP157CABx.xml, STM32MP157CADx.xml * STM32MP157DABx.xml, STM32MP157DADx.xml * STM32MP157FABx.xml, STM32MP157FADx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c index 7dffd5338e..5e5b603930 100644 --- a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP153DAAx.xml, STM32MP153FAAx.xml * STM32MP157AAAx.xml, STM32MP157CAAx.xml * STM32MP157DAAx.xml, STM32MP157FAAx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c index 34123b9ca6..edb9ad769b 100644 --- a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP153DACx.xml, STM32MP153FACx.xml * STM32MP157AACx.xml, STM32MP157CACx.xml * STM32MP157DACx.xml, STM32MP157FACx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c index b8f24d94fc..7e6e0a8545 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTx.xml, STM32U535CCUx.xml * STM32U535CETx.xml, STM32U535CEUx.xml * STM32U545CETx.xml, STM32U545CEUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c index 4b97446d87..5fcb5a4a5a 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTxQ.xml, STM32U535CCUxQ.xml * STM32U535CETxQ.xml, STM32U535CEUxQ.xml * STM32U545CETxQ.xml, STM32U545CEUxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c index 21ac7478cd..7029bea606 100644 --- a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U535JEYxQ.xml, STM32U545JEYxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c index 2490e199ba..111e7c4694 100644 --- a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535NCYxQ.xml, STM32U535NEYxQ.xml * STM32U545NEYxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c index 5802724437..0723a5c1de 100644 --- a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIx.xml, STM32U535RCIx.xml * STM32U535REIx.xml, STM32U545REIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c index c14452eb93..fd4b748f1c 100644 --- a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIxQ.xml, STM32U535RCIxQ.xml * STM32U535REIxQ.xml, STM32U545REIxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c index b956e22e36..fd0124cf6f 100644 --- a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTx.xml, STM32U535RCTx.xml * STM32U535RETx.xml, STM32U545RETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c index 772008a0c9..01f7554346 100644 --- a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTxQ.xml, STM32U535RCTxQ.xml * STM32U535RETxQ.xml, STM32U545RETxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c index e43b756228..79dda1dfa5 100644 --- a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIx.xml, STM32U535VEIx.xml * STM32U545VEIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c index d290168232..273ea8c267 100644 --- a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIxQ.xml, STM32U535VEIxQ.xml * STM32U545VEIxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c index 2c64ad5cc8..1cda066b37 100644 --- a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTx.xml, STM32U535VETx.xml * STM32U545VETx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c index c8a08231c6..19717de6f7 100644 --- a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTxQ.xml, STM32U535VETxQ.xml * STM32U545VETxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c index f935ea60a9..a694abc167 100644 --- a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIx.xml, STM32U575AIIx.xml * STM32U585AIIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c index b03213dce5..1a28b54122 100644 --- a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIxQ.xml, STM32U575AIIxQ.xml * STM32U585AIIxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c index eecda91e9e..aa4678ccb7 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTx.xml, STM32U575CGUx.xml * STM32U575CITx.xml, STM32U575CIUx.xml * STM32U585CITx.xml, STM32U585CIUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c index fcf01b6134..24006e6157 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTxQ.xml, STM32U575CGUxQ.xml * STM32U575CITxQ.xml, STM32U575CIUxQ.xml * STM32U585CITxQ.xml, STM32U585CIUxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c index bd8a033ba5..a51a64d1bb 100644 --- a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575OGYxQ.xml, STM32U575OIYxQ.xml * STM32U585OIYxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c index 2730687437..1b1fce3e63 100644 --- a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIx.xml, STM32U575QIIx.xml * STM32U585QIIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c index c86b3be2be..9b91559d72 100644 --- a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIxQ.xml, STM32U575QIIxQ.xml * STM32U585QIIxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c index 453590c0d9..2657b67c59 100644 --- a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTx.xml, STM32U575RITx.xml * STM32U585RITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c index 99ce3cdfe7..e227d38e55 100644 --- a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTxQ.xml, STM32U575RITxQ.xml * STM32U585RITxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c index 287b69d468..a36cc6b4ae 100644 --- a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTx.xml, STM32U575VITx.xml * STM32U585VITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c index 3644204bb7..3454a17d4f 100644 --- a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTxQ.xml, STM32U575VITxQ.xml * STM32U585VITxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c index e4693fd320..4811e4ad5d 100644 --- a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTx.xml, STM32U575ZITx.xml * STM32U585ZITx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c index 18216a7455..d46d303d62 100644 --- a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTxQ.xml, STM32U575ZITxQ.xml * STM32U585ZITxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c index d3847345b6..786203d4b7 100644 --- a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHx.xml, STM32U595AJHx.xml * STM32U5A5AJHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c index 8c3c4cfbea..c51b85d0d2 100644 --- a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHxQ.xml, STM32U595AJHxQ.xml * STM32U5A5AJHxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c index 403ba22aea..86907ec4bf 100644 --- a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595QIIx.xml, STM32U595QJIx.xml * STM32U5A5QJIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c similarity index 99% rename from variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/PeripheralPins.c rename to variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c index a4bf0fea09..f573c284ee 100644 --- a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c @@ -12,8 +12,8 @@ */ /* * Automatically generated from STM32U595QIIxQ.xml, STM32U595QJIxQ.xml - * STM32U5A5QJIxQ.xml - * CubeMX DB release 6.0.90 + * STM32U5A5QIIxQ.xml, STM32U5A5QJIxQ.xml + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/PinNamesVar.h b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PinNamesVar.h similarity index 100% rename from variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/PinNamesVar.h rename to variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PinNamesVar.h diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/boards_entry.txt b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/boards_entry.txt similarity index 74% rename from variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/boards_entry.txt rename to variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/boards_entry.txt index 5ff2d1d830..05dfc75dd4 100644 --- a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/boards_entry.txt +++ b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/boards_entry.txt @@ -9,7 +9,7 @@ GenU5.menu.pnum.GENERIC_U595QIIXQ.upload.maximum_size=2097152 GenU5.menu.pnum.GENERIC_U595QIIXQ.upload.maximum_data_size=2574336 GenU5.menu.pnum.GENERIC_U595QIIXQ.build.board=GENERIC_U595QIIXQ GenU5.menu.pnum.GENERIC_U595QIIXQ.build.product_line=STM32U595xx -GenU5.menu.pnum.GENERIC_U595QIIXQ.build.variant=STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ +GenU5.menu.pnum.GENERIC_U595QIIXQ.build.variant=STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ # Generic U595QJIxQ GenU5.menu.pnum.GENERIC_U595QJIXQ=Generic U595QJIxQ @@ -17,7 +17,15 @@ GenU5.menu.pnum.GENERIC_U595QJIXQ.upload.maximum_size=4194304 GenU5.menu.pnum.GENERIC_U595QJIXQ.upload.maximum_data_size=2574336 GenU5.menu.pnum.GENERIC_U595QJIXQ.build.board=GENERIC_U595QJIXQ GenU5.menu.pnum.GENERIC_U595QJIXQ.build.product_line=STM32U595xx -GenU5.menu.pnum.GENERIC_U595QJIXQ.build.variant=STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ +GenU5.menu.pnum.GENERIC_U595QJIXQ.build.variant=STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ + +# Generic U5A5QIIxQ +GenU5.menu.pnum.GENERIC_U5A5QIIXQ=Generic U5A5QIIxQ +GenU5.menu.pnum.GENERIC_U5A5QIIXQ.upload.maximum_size=2097152 +GenU5.menu.pnum.GENERIC_U5A5QIIXQ.upload.maximum_data_size=2574336 +GenU5.menu.pnum.GENERIC_U5A5QIIXQ.build.board=GENERIC_U5A5QIIXQ +GenU5.menu.pnum.GENERIC_U5A5QIIXQ.build.product_line=STM32U5A5xx +GenU5.menu.pnum.GENERIC_U5A5QIIXQ.build.variant=STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ # Generic U5A5QJIxQ GenU5.menu.pnum.GENERIC_U5A5QJIXQ=Generic U5A5QJIxQ @@ -25,5 +33,5 @@ GenU5.menu.pnum.GENERIC_U5A5QJIXQ.upload.maximum_size=4194304 GenU5.menu.pnum.GENERIC_U5A5QJIXQ.upload.maximum_data_size=2574336 GenU5.menu.pnum.GENERIC_U5A5QJIXQ.build.board=GENERIC_U5A5QJIXQ GenU5.menu.pnum.GENERIC_U5A5QJIXQ.build.product_line=STM32U5A5xx -GenU5.menu.pnum.GENERIC_U5A5QJIXQ.build.variant=STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ +GenU5.menu.pnum.GENERIC_U5A5QJIXQ.build.variant=STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/generic_clock.c b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/generic_clock.c similarity index 92% rename from variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/generic_clock.c rename to variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/generic_clock.c index 2c19ad4bbf..e6c4833335 100644 --- a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/generic_clock.c +++ b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/generic_clock.c @@ -11,7 +11,7 @@ ******************************************************************************* */ #if defined(ARDUINO_GENERIC_U595QIIXQ) || defined(ARDUINO_GENERIC_U595QJIXQ) ||\ - defined(ARDUINO_GENERIC_U5A5QJIXQ) + defined(ARDUINO_GENERIC_U5A5QIIXQ) || defined(ARDUINO_GENERIC_U5A5QJIXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/variant_generic.cpp b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/variant_generic.cpp similarity index 97% rename from variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/variant_generic.cpp rename to variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/variant_generic.cpp index ea4cf73a23..bbf9ab543b 100644 --- a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/variant_generic.cpp +++ b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/variant_generic.cpp @@ -11,7 +11,7 @@ ******************************************************************************* */ #if defined(ARDUINO_GENERIC_U595QIIXQ) || defined(ARDUINO_GENERIC_U595QJIXQ) ||\ - defined(ARDUINO_GENERIC_U5A5QJIXQ) + defined(ARDUINO_GENERIC_U5A5QIIXQ) || defined(ARDUINO_GENERIC_U5A5QJIXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/variant_generic.h b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/variant_generic.h similarity index 100% rename from variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/variant_generic.h rename to variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/variant_generic.h diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/CMakeLists.txt b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5QJIxQ/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c index 89ab98a9d5..bfbe740262 100644 --- a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITx.xml, STM32U595RJTx.xml * STM32U5A5RJTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c index 2a2ae00734..70195bcc2e 100644 --- a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITxQ.xml, STM32U595RJTxQ.xml * STM32U5A5RJTxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c index e7d9eb6a6f..92988f3f37 100644 --- a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595VITx.xml, STM32U595VJTx.xml * STM32U599VJTx.xml, STM32U5A5VJTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c index 498c2860a2..3a39b3073e 100644 --- a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595VITxQ.xml, STM32U595VJTxQ.xml * STM32U599VITxQ.xml, STM32U599VJTxQ.xml * STM32U5A5VJTxQ.xml, STM32U5A9VJTxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c index 07b0d8d1b5..27692d257e 100644 --- a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZITx.xml, STM32U595ZJTx.xml * STM32U5A5ZJTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c index 88781aa07e..f017c4993a 100644 --- a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595ZITxQ.xml, STM32U595ZJTxQ.xml * STM32U599ZITxQ.xml, STM32U599ZJTxQ.xml * STM32U5A5ZJTxQ.xml, STM32U5A9ZJTxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c index b0ddc494f4..f9800a7414 100644 --- a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZIYxQ.xml, STM32U595ZJYxQ.xml * STM32U5A5ZJYxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c index e60e6fadf4..2fa7095e19 100644 --- a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U599BJYxQ.xml, STM32U5A9BJYxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c index 054d2c7a8f..4290d0882d 100644 --- a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599NIHxQ.xml, STM32U599NJHxQ.xml * STM32U5A9NJHxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c index 7adcb6eef2..629fb5dac3 100644 --- a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599ZIYxQ.xml, STM32U599ZJYxQ.xml * STM32U5A9ZJYxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c index 7c7594fb3a..e62660f63e 100644 --- a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F7VITx.xml, STM32U5F7VJTx.xml * STM32U5G7VJTx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -498,6 +498,7 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PinNamesVar.h b/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PinNamesVar.h index ba783c5e6a..c1062b7395 100644 --- a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PinNamesVar.h +++ b/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PinNamesVar.h @@ -131,6 +131,11 @@ PD_1_ALT1 = PD_1 | ALT1, USB_OTG_HS_DM = PA_11, USB_OTG_HS_DP = PA_12, USB_OTG_HS_ID = PA_10, - USB_OTG_HS_SOF = PA_8, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif USB_OTG_HS_VBUS = PA_9, #endif diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c index 062a51637b..2d33246459 100644 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F7VITxQ.xml, STM32U5F7VJTxQ.xml * STM32U5G7VJTxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -490,6 +490,7 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PinNamesVar.h b/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PinNamesVar.h index 27f34a39cc..cd5687d087 100644 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PinNamesVar.h +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PinNamesVar.h @@ -125,6 +125,11 @@ PD_1_ALT1 = PD_1 | ALT1, USB_OTG_HS_DM = PA_11, USB_OTG_HS_DP = PA_12, USB_OTG_HS_ID = PA_10, - USB_OTG_HS_SOF = PA_8, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif USB_OTG_HS_VBUS = PA_9, #endif diff --git a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c index df0e96b949..ac8063373c 100644 --- a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9BJYxQ.xml, STM32U5G9BJYxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -583,6 +583,7 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PinNamesVar.h b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PinNamesVar.h index b74bf10c98..4542244abd 100644 --- a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PinNamesVar.h +++ b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PinNamesVar.h @@ -139,6 +139,11 @@ PH_12_ALT1 = PH_12 | ALT1, USB_OTG_HS_DM = PA_11, USB_OTG_HS_DP = PA_12, USB_OTG_HS_ID = PA_10, - USB_OTG_HS_SOF = PA_8, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif USB_OTG_HS_VBUS = PA_9, #endif diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c index 7363611ab1..3686c3e5c8 100644 --- a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9NJHxQ.xml, STM32U5G9NJHxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -613,6 +613,7 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PinNamesVar.h b/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PinNamesVar.h index f1e74d4333..c8d62f315c 100644 --- a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PinNamesVar.h +++ b/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PinNamesVar.h @@ -139,6 +139,11 @@ PH_12_ALT1 = PH_12 | ALT1, USB_OTG_HS_DM = PA_11, USB_OTG_HS_DP = PA_12, USB_OTG_HS_ID = PA_10, - USB_OTG_HS_SOF = PA_8, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif USB_OTG_HS_VBUS = PA_9, #endif diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c index 9faef0db1e..11fb3e997b 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F9VITxQ.xml, STM32U5F9VJTxQ.xml * STM32U5G9VJTxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -450,6 +450,7 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PinNamesVar.h b/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PinNamesVar.h index 07e09792f2..b43d93664c 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PinNamesVar.h +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PinNamesVar.h @@ -108,6 +108,11 @@ PH_12_ALT1 = PH_12 | ALT1, USB_OTG_HS_DM = PA_11, USB_OTG_HS_DP = PA_12, USB_OTG_HS_ID = PA_10, - USB_OTG_HS_SOF = PA_8, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif USB_OTG_HS_VBUS = PA_9, #endif diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c index f9fda948d9..bc75b79656 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F9ZIJxQ.xml, STM32U5F9ZJJxQ.xml * STM32U5G9ZJJxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -540,6 +540,7 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PinNamesVar.h b/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PinNamesVar.h index 9084668a2f..dea12a7967 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PinNamesVar.h +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PinNamesVar.h @@ -131,6 +131,11 @@ PH_12_ALT1 = PH_12 | ALT1, USB_OTG_HS_DM = PA_11, USB_OTG_HS_DP = PA_12, USB_OTG_HS_ID = PA_10, - USB_OTG_HS_SOF = PA_8, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif USB_OTG_HS_VBUS = PA_9, #endif diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c index 6f4d78ac21..0e3cd9b767 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F9ZITxQ.xml, STM32U5F9ZJTxQ.xml * STM32U5G9ZJTxQ.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -540,6 +540,7 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP + {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PinNamesVar.h b/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PinNamesVar.h index 4ebee33bde..aac7681c49 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PinNamesVar.h +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PinNamesVar.h @@ -131,6 +131,11 @@ PH_12_ALT1 = PH_12 | ALT1, USB_OTG_HS_DM = PA_11, USB_OTG_HS_DP = PA_12, USB_OTG_HS_ID = PA_10, - USB_OTG_HS_SOF = PA_8, + #ifdef USB_OTG_HS_SOF_PA_8 + USB_OTG_HS_SOF = PA_8, + #endif + #ifdef USB_OTG_HS_SOF_PA_14 + USB_OTG_HS_SOF = PA_14, + #endif USB_OTG_HS_VBUS = PA_9, #endif diff --git a/variants/STM32WBxx/WB10CCU/PeripheralPins.c b/variants/STM32WBxx/WB10CCU/PeripheralPins.c index b20b3a890b..e0543b4e17 100644 --- a/variants/STM32WBxx/WB10CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB10CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB10CCUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCU/PeripheralPins.c b/variants/STM32WBxx/WB15CCU/PeripheralPins.c index 88cec611d5..ad349abd82 100644 --- a/variants/STM32WBxx/WB15CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c index 1a8dd92e97..47ab8161ea 100644 --- a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUxE.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCY/PeripheralPins.c b/variants/STM32WBxx/WB15CCY/PeripheralPins.c index 9daae189cf..9be97a67bf 100644 --- a/variants/STM32WBxx/WB15CCY/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c index 6917d8c24c..bb0451a965 100644 --- a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c +++ b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB1MMCHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c index 6242cbf70d..1822c2d5dd 100644 --- a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c +++ b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB30CEUxA.xml, STM32WB50CGUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c index 39dd4b4b7a..3b638b6e7b 100644 --- a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c +++ b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB35C(C-E)UxA.xml, STM32WB55CCUx.xml * STM32WB55CEUx.xml, STM32WB55CGUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c index 7b3ff8e9b4..a6c1249483 100644 --- a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c +++ b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB55RCVx.xml, STM32WB55REVx.xml * STM32WB55RGVx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c index 901d3dc6aa..da0fac23a8 100644 --- a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c +++ b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WB55VEQx.xml, STM32WB55VEYx.xml * STM32WB55VGQx.xml, STM32WB55VGYx.xml * STM32WB55VYYx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c index 0c7a1c3e6e..a564445d13 100644 --- a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c +++ b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB5MMGHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c index c890453be3..0844016310 100644 --- a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WLE4C8Ux.xml, STM32WLE4CBUx.xml * STM32WLE4CCUx.xml, STM32WLE5C8Ux.xml * STM32WLE5CBUx.xml, STM32WLE5CCUx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c index 5b3fa3f8e1..50387b2d9e 100644 --- a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c +++ b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WLE4J8Ix.xml, STM32WLE4JBIx.xml * STM32WLE4JCIx.xml, STM32WLE5J8Ix.xml * STM32WLE5JBIx.xml, STM32WLE5JCIx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL5MOCH/PeripheralPins.c b/variants/STM32WLxx/WL5MOCH/PeripheralPins.c index cb2fd1d918..5310ca4dda 100644 --- a/variants/STM32WLxx/WL5MOCH/PeripheralPins.c +++ b/variants/STM32WLxx/WL5MOCH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WL5MOCHx.xml - * CubeMX DB release 6.0.90 + * CubeMX DB release 6.0.100 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" From b6995db207acbf0a6a686f9fe54a4d49f9c69912 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 4 Jan 2024 16:26:32 +0100 Subject: [PATCH 71/83] chore(cmake): update after db update Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 6866 ++++++++--------- .../H563A(G-I)I_H573AII/CMakeLists.txt | 31 + .../H563AIIxQ_H573AIIxQ/CMakeLists.txt | 31 + .../CMakeLists.txt | 31 + .../H563IIKxQ_H573IIKxQ/CMakeLists.txt | 33 + .../H563IITxQ_H573IITxQ/CMakeLists.txt | 31 + .../H563MIYxQ_H573MIYxQ/CMakeLists.txt | 31 + .../H563R(G-I)T_H573RIT/CMakeLists.txt | 31 + .../H563R(G-I)V_H573RIV/CMakeLists.txt | 31 + .../H563V(G-I)T_H573VIT/CMakeLists.txt | 31 + .../H563Z(G-I)T_H573ZIT/CMakeLists.txt | 32 + .../CMakeLists.txt | 31 + 12 files changed, 3777 insertions(+), 3433 deletions(-) create mode 100644 variants/STM32H5xx/H563A(G-I)I_H573AII/CMakeLists.txt create mode 100644 variants/STM32H5xx/H563AIIxQ_H573AIIxQ/CMakeLists.txt create mode 100644 variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/CMakeLists.txt create mode 100644 variants/STM32H5xx/H563IIKxQ_H573IIKxQ/CMakeLists.txt create mode 100644 variants/STM32H5xx/H563IITxQ_H573IITxQ/CMakeLists.txt create mode 100644 variants/STM32H5xx/H563MIYxQ_H573MIYxQ/CMakeLists.txt create mode 100644 variants/STM32H5xx/H563R(G-I)T_H573RIT/CMakeLists.txt create mode 100644 variants/STM32H5xx/H563R(G-I)V_H573RIV/CMakeLists.txt create mode 100644 variants/STM32H5xx/H563V(G-I)T_H573VIT/CMakeLists.txt create mode 100644 variants/STM32H5xx/H563Z(G-I)T_H573ZIT/CMakeLists.txt create mode 100644 variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/CMakeLists.txt diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index ef9956129f..e812ef6461 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -107,15 +107,15 @@ target_compile_options(AFROFLIGHT_F103CB_serial_none INTERFACE ) add_library(AFROFLIGHT_F103CB_usb_CDC INTERFACE) target_compile_options(AFROFLIGHT_F103CB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(AFROFLIGHT_F103CB_usb_CDCgen INTERFACE) target_compile_options(AFROFLIGHT_F103CB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(AFROFLIGHT_F103CB_usb_HID INTERFACE) target_compile_options(AFROFLIGHT_F103CB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(AFROFLIGHT_F103CB_usb_none INTERFACE) target_compile_options(AFROFLIGHT_F103CB_usb_none INTERFACE @@ -189,15 +189,15 @@ target_compile_options(AFROFLIGHT_F103CB_12M_serial_none INTERFACE ) add_library(AFROFLIGHT_F103CB_12M_usb_CDC INTERFACE) target_compile_options(AFROFLIGHT_F103CB_12M_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(AFROFLIGHT_F103CB_12M_usb_CDCgen INTERFACE) target_compile_options(AFROFLIGHT_F103CB_12M_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(AFROFLIGHT_F103CB_12M_usb_HID INTERFACE) target_compile_options(AFROFLIGHT_F103CB_12M_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(AFROFLIGHT_F103CB_12M_usb_none INTERFACE) target_compile_options(AFROFLIGHT_F103CB_12M_usb_none INTERFACE @@ -523,15 +523,15 @@ target_compile_options(AGAFIA_SG0_serial_none INTERFACE ) add_library(AGAFIA_SG0_usb_CDC INTERFACE) target_compile_options(AGAFIA_SG0_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(AGAFIA_SG0_usb_CDCgen INTERFACE) target_compile_options(AGAFIA_SG0_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(AGAFIA_SG0_usb_HID INTERFACE) target_compile_options(AGAFIA_SG0_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(AGAFIA_SG0_usb_none INTERFACE) target_compile_options(AGAFIA_SG0_usb_none INTERFACE @@ -593,11 +593,11 @@ target_compile_options(ARMED_V1_serial_none INTERFACE ) add_library(ARMED_V1_usb_CDC INTERFACE) target_compile_options(ARMED_V1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(ARMED_V1_usb_CDCgen INTERFACE) target_compile_options(ARMED_V1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(ARMED_V1_usb_none INTERFACE) target_compile_options(ARMED_V1_usb_none INTERFACE @@ -671,15 +671,15 @@ target_compile_options(AURORA_ONE_serial_none INTERFACE ) add_library(AURORA_ONE_usb_CDC INTERFACE) target_compile_options(AURORA_ONE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(AURORA_ONE_usb_CDCgen INTERFACE) target_compile_options(AURORA_ONE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(AURORA_ONE_usb_HID INTERFACE) target_compile_options(AURORA_ONE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(AURORA_ONE_usb_none INTERFACE) target_compile_options(AURORA_ONE_usb_none INTERFACE @@ -741,15 +741,15 @@ target_compile_options(B_G431B_ESC1_serial_none INTERFACE ) add_library(B_G431B_ESC1_usb_CDC INTERFACE) target_compile_options(B_G431B_ESC1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(B_G431B_ESC1_usb_CDCgen INTERFACE) target_compile_options(B_G431B_ESC1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(B_G431B_ESC1_usb_HID INTERFACE) target_compile_options(B_G431B_ESC1_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(B_G431B_ESC1_usb_none INTERFACE) target_compile_options(B_G431B_ESC1_usb_none INTERFACE @@ -823,15 +823,15 @@ target_compile_options(B_L072Z_LRWAN1_serial_none INTERFACE ) add_library(B_L072Z_LRWAN1_usb_CDC INTERFACE) target_compile_options(B_L072Z_LRWAN1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(B_L072Z_LRWAN1_usb_CDCgen INTERFACE) target_compile_options(B_L072Z_LRWAN1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(B_L072Z_LRWAN1_usb_HID INTERFACE) target_compile_options(B_L072Z_LRWAN1_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(B_L072Z_LRWAN1_usb_none INTERFACE) target_compile_options(B_L072Z_LRWAN1_usb_none INTERFACE @@ -905,15 +905,15 @@ target_compile_options(B_L475E_IOT01A_serial_none INTERFACE ) add_library(B_L475E_IOT01A_usb_CDC INTERFACE) target_compile_options(B_L475E_IOT01A_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(B_L475E_IOT01A_usb_CDCgen INTERFACE) target_compile_options(B_L475E_IOT01A_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(B_L475E_IOT01A_usb_HID INTERFACE) target_compile_options(B_L475E_IOT01A_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(B_L475E_IOT01A_usb_none INTERFACE) target_compile_options(B_L475E_IOT01A_usb_none INTERFACE @@ -987,15 +987,15 @@ target_compile_options(B_L4S5I_IOT01A_serial_none INTERFACE ) add_library(B_L4S5I_IOT01A_usb_CDC INTERFACE) target_compile_options(B_L4S5I_IOT01A_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(B_L4S5I_IOT01A_usb_CDCgen INTERFACE) target_compile_options(B_L4S5I_IOT01A_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(B_L4S5I_IOT01A_usb_HID INTERFACE) target_compile_options(B_L4S5I_IOT01A_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(B_L4S5I_IOT01A_usb_none INTERFACE) target_compile_options(B_L4S5I_IOT01A_usb_none INTERFACE @@ -1069,15 +1069,15 @@ target_compile_options(B_U585I_IOT02A_serial_none INTERFACE ) add_library(B_U585I_IOT02A_usb_CDC INTERFACE) target_compile_options(B_U585I_IOT02A_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(B_U585I_IOT02A_usb_CDCgen INTERFACE) target_compile_options(B_U585I_IOT02A_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(B_U585I_IOT02A_usb_HID INTERFACE) target_compile_options(B_U585I_IOT02A_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(B_U585I_IOT02A_usb_none INTERFACE) target_compile_options(B_U585I_IOT02A_usb_none INTERFACE @@ -1151,15 +1151,15 @@ target_compile_options(BLACK_F407VE_serial_none INTERFACE ) add_library(BLACK_F407VE_usb_CDC INTERFACE) target_compile_options(BLACK_F407VE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACK_F407VE_usb_CDCgen INTERFACE) target_compile_options(BLACK_F407VE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACK_F407VE_usb_HID INTERFACE) target_compile_options(BLACK_F407VE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACK_F407VE_usb_none INTERFACE) target_compile_options(BLACK_F407VE_usb_none INTERFACE @@ -1275,15 +1275,15 @@ target_compile_options(BLACK_F407VG_serial_none INTERFACE ) add_library(BLACK_F407VG_usb_CDC INTERFACE) target_compile_options(BLACK_F407VG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACK_F407VG_usb_CDCgen INTERFACE) target_compile_options(BLACK_F407VG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACK_F407VG_usb_HID INTERFACE) target_compile_options(BLACK_F407VG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACK_F407VG_usb_none INTERFACE) target_compile_options(BLACK_F407VG_usb_none INTERFACE @@ -1399,15 +1399,15 @@ target_compile_options(BLACK_F407ZE_serial_none INTERFACE ) add_library(BLACK_F407ZE_usb_CDC INTERFACE) target_compile_options(BLACK_F407ZE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACK_F407ZE_usb_CDCgen INTERFACE) target_compile_options(BLACK_F407ZE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACK_F407ZE_usb_HID INTERFACE) target_compile_options(BLACK_F407ZE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACK_F407ZE_usb_none INTERFACE) target_compile_options(BLACK_F407ZE_usb_none INTERFACE @@ -1523,15 +1523,15 @@ target_compile_options(BLACK_F407ZG_serial_none INTERFACE ) add_library(BLACK_F407ZG_usb_CDC INTERFACE) target_compile_options(BLACK_F407ZG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACK_F407ZG_usb_CDCgen INTERFACE) target_compile_options(BLACK_F407ZG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACK_F407ZG_usb_HID INTERFACE) target_compile_options(BLACK_F407ZG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACK_F407ZG_usb_none INTERFACE) target_compile_options(BLACK_F407ZG_usb_none INTERFACE @@ -1647,15 +1647,15 @@ target_compile_options(BLACKPILL_F103C8_serial_none INTERFACE ) add_library(BLACKPILL_F103C8_usb_CDC INTERFACE) target_compile_options(BLACKPILL_F103C8_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACKPILL_F103C8_usb_CDCgen INTERFACE) target_compile_options(BLACKPILL_F103C8_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACKPILL_F103C8_usb_HID INTERFACE) target_compile_options(BLACKPILL_F103C8_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACKPILL_F103C8_usb_none INTERFACE) target_compile_options(BLACKPILL_F103C8_usb_none INTERFACE @@ -1855,15 +1855,15 @@ target_compile_options(BLACKPILL_F103CB_serial_none INTERFACE ) add_library(BLACKPILL_F103CB_usb_CDC INTERFACE) target_compile_options(BLACKPILL_F103CB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACKPILL_F103CB_usb_CDCgen INTERFACE) target_compile_options(BLACKPILL_F103CB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACKPILL_F103CB_usb_HID INTERFACE) target_compile_options(BLACKPILL_F103CB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACKPILL_F103CB_usb_none INTERFACE) target_compile_options(BLACKPILL_F103CB_usb_none INTERFACE @@ -2063,15 +2063,15 @@ target_compile_options(BLACKPILL_F303CC_serial_none INTERFACE ) add_library(BLACKPILL_F303CC_usb_CDC INTERFACE) target_compile_options(BLACKPILL_F303CC_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACKPILL_F303CC_usb_CDCgen INTERFACE) target_compile_options(BLACKPILL_F303CC_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACKPILL_F303CC_usb_HID INTERFACE) target_compile_options(BLACKPILL_F303CC_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACKPILL_F303CC_usb_none INTERFACE) target_compile_options(BLACKPILL_F303CC_usb_none INTERFACE @@ -2145,15 +2145,15 @@ target_compile_options(BLACKPILL_F401CC_serial_none INTERFACE ) add_library(BLACKPILL_F401CC_usb_CDC INTERFACE) target_compile_options(BLACKPILL_F401CC_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACKPILL_F401CC_usb_CDCgen INTERFACE) target_compile_options(BLACKPILL_F401CC_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACKPILL_F401CC_usb_HID INTERFACE) target_compile_options(BLACKPILL_F401CC_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACKPILL_F401CC_usb_none INTERFACE) target_compile_options(BLACKPILL_F401CC_usb_none INTERFACE @@ -2269,15 +2269,15 @@ target_compile_options(BLACKPILL_F401CE_serial_none INTERFACE ) add_library(BLACKPILL_F401CE_usb_CDC INTERFACE) target_compile_options(BLACKPILL_F401CE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACKPILL_F401CE_usb_CDCgen INTERFACE) target_compile_options(BLACKPILL_F401CE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACKPILL_F401CE_usb_HID INTERFACE) target_compile_options(BLACKPILL_F401CE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACKPILL_F401CE_usb_none INTERFACE) target_compile_options(BLACKPILL_F401CE_usb_none INTERFACE @@ -2393,15 +2393,15 @@ target_compile_options(BLACKPILL_F411CE_serial_none INTERFACE ) add_library(BLACKPILL_F411CE_usb_CDC INTERFACE) target_compile_options(BLACKPILL_F411CE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLACKPILL_F411CE_usb_CDCgen INTERFACE) target_compile_options(BLACKPILL_F411CE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLACKPILL_F411CE_usb_HID INTERFACE) target_compile_options(BLACKPILL_F411CE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLACKPILL_F411CE_usb_none INTERFACE) target_compile_options(BLACKPILL_F411CE_usb_none INTERFACE @@ -2517,15 +2517,15 @@ target_compile_options(BLUE_F407VE_MINI_serial_none INTERFACE ) add_library(BLUE_F407VE_MINI_usb_CDC INTERFACE) target_compile_options(BLUE_F407VE_MINI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLUE_F407VE_MINI_usb_CDCgen INTERFACE) target_compile_options(BLUE_F407VE_MINI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLUE_F407VE_MINI_usb_HID INTERFACE) target_compile_options(BLUE_F407VE_MINI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLUE_F407VE_MINI_usb_none INTERFACE) target_compile_options(BLUE_F407VE_MINI_usb_none INTERFACE @@ -2641,15 +2641,15 @@ target_compile_options(BLUEBUTTON_F103R8T_serial_none INTERFACE ) add_library(BLUEBUTTON_F103R8T_usb_CDC INTERFACE) target_compile_options(BLUEBUTTON_F103R8T_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLUEBUTTON_F103R8T_usb_CDCgen INTERFACE) target_compile_options(BLUEBUTTON_F103R8T_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLUEBUTTON_F103R8T_usb_HID INTERFACE) target_compile_options(BLUEBUTTON_F103R8T_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLUEBUTTON_F103R8T_usb_none INTERFACE) target_compile_options(BLUEBUTTON_F103R8T_usb_none INTERFACE @@ -2849,15 +2849,15 @@ target_compile_options(BLUEBUTTON_F103RBT_serial_none INTERFACE ) add_library(BLUEBUTTON_F103RBT_usb_CDC INTERFACE) target_compile_options(BLUEBUTTON_F103RBT_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLUEBUTTON_F103RBT_usb_CDCgen INTERFACE) target_compile_options(BLUEBUTTON_F103RBT_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLUEBUTTON_F103RBT_usb_HID INTERFACE) target_compile_options(BLUEBUTTON_F103RBT_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLUEBUTTON_F103RBT_usb_none INTERFACE) target_compile_options(BLUEBUTTON_F103RBT_usb_none INTERFACE @@ -3057,15 +3057,15 @@ target_compile_options(BLUEBUTTON_F103RCT_serial_none INTERFACE ) add_library(BLUEBUTTON_F103RCT_usb_CDC INTERFACE) target_compile_options(BLUEBUTTON_F103RCT_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLUEBUTTON_F103RCT_usb_CDCgen INTERFACE) target_compile_options(BLUEBUTTON_F103RCT_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLUEBUTTON_F103RCT_usb_HID INTERFACE) target_compile_options(BLUEBUTTON_F103RCT_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLUEBUTTON_F103RCT_usb_none INTERFACE) target_compile_options(BLUEBUTTON_F103RCT_usb_none INTERFACE @@ -3265,15 +3265,15 @@ target_compile_options(BLUEBUTTON_F103RET_serial_none INTERFACE ) add_library(BLUEBUTTON_F103RET_usb_CDC INTERFACE) target_compile_options(BLUEBUTTON_F103RET_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLUEBUTTON_F103RET_usb_CDCgen INTERFACE) target_compile_options(BLUEBUTTON_F103RET_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLUEBUTTON_F103RET_usb_HID INTERFACE) target_compile_options(BLUEBUTTON_F103RET_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLUEBUTTON_F103RET_usb_none INTERFACE) target_compile_options(BLUEBUTTON_F103RET_usb_none INTERFACE @@ -3473,15 +3473,15 @@ target_compile_options(BLUEPILL_F103C6_serial_none INTERFACE ) add_library(BLUEPILL_F103C6_usb_CDC INTERFACE) target_compile_options(BLUEPILL_F103C6_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLUEPILL_F103C6_usb_CDCgen INTERFACE) target_compile_options(BLUEPILL_F103C6_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLUEPILL_F103C6_usb_HID INTERFACE) target_compile_options(BLUEPILL_F103C6_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLUEPILL_F103C6_usb_none INTERFACE) target_compile_options(BLUEPILL_F103C6_usb_none INTERFACE @@ -3681,15 +3681,15 @@ target_compile_options(BLUEPILL_F103C8_serial_none INTERFACE ) add_library(BLUEPILL_F103C8_usb_CDC INTERFACE) target_compile_options(BLUEPILL_F103C8_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLUEPILL_F103C8_usb_CDCgen INTERFACE) target_compile_options(BLUEPILL_F103C8_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLUEPILL_F103C8_usb_HID INTERFACE) target_compile_options(BLUEPILL_F103C8_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLUEPILL_F103C8_usb_none INTERFACE) target_compile_options(BLUEPILL_F103C8_usb_none INTERFACE @@ -3889,15 +3889,15 @@ target_compile_options(BLUEPILL_F103CB_serial_none INTERFACE ) add_library(BLUEPILL_F103CB_usb_CDC INTERFACE) target_compile_options(BLUEPILL_F103CB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(BLUEPILL_F103CB_usb_CDCgen INTERFACE) target_compile_options(BLUEPILL_F103CB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(BLUEPILL_F103CB_usb_HID INTERFACE) target_compile_options(BLUEPILL_F103CB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(BLUEPILL_F103CB_usb_none INTERFACE) target_compile_options(BLUEPILL_F103CB_usb_none INTERFACE @@ -4097,15 +4097,15 @@ target_compile_options(CoreBoard_F401RC_serial_none INTERFACE ) add_library(CoreBoard_F401RC_usb_CDC INTERFACE) target_compile_options(CoreBoard_F401RC_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(CoreBoard_F401RC_usb_CDCgen INTERFACE) target_compile_options(CoreBoard_F401RC_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(CoreBoard_F401RC_usb_HID INTERFACE) target_compile_options(CoreBoard_F401RC_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(CoreBoard_F401RC_usb_none INTERFACE) target_compile_options(CoreBoard_F401RC_usb_none INTERFACE @@ -4221,15 +4221,15 @@ target_compile_options(DAISY_PATCH_SM_serial_none INTERFACE ) add_library(DAISY_PATCH_SM_usb_CDC INTERFACE) target_compile_options(DAISY_PATCH_SM_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DAISY_PATCH_SM_usb_CDCgen INTERFACE) target_compile_options(DAISY_PATCH_SM_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DAISY_PATCH_SM_usb_HID INTERFACE) target_compile_options(DAISY_PATCH_SM_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DAISY_PATCH_SM_usb_none INTERFACE) target_compile_options(DAISY_PATCH_SM_usb_none INTERFACE @@ -4303,15 +4303,15 @@ target_compile_options(DAISY_PETAL_SM_serial_none INTERFACE ) add_library(DAISY_PETAL_SM_usb_CDC INTERFACE) target_compile_options(DAISY_PETAL_SM_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DAISY_PETAL_SM_usb_CDCgen INTERFACE) target_compile_options(DAISY_PETAL_SM_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DAISY_PETAL_SM_usb_HID INTERFACE) target_compile_options(DAISY_PETAL_SM_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DAISY_PETAL_SM_usb_none INTERFACE) target_compile_options(DAISY_PETAL_SM_usb_none INTERFACE @@ -4385,15 +4385,15 @@ target_compile_options(DAISY_SEED_serial_none INTERFACE ) add_library(DAISY_SEED_usb_CDC INTERFACE) target_compile_options(DAISY_SEED_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DAISY_SEED_usb_CDCgen INTERFACE) target_compile_options(DAISY_SEED_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DAISY_SEED_usb_HID INTERFACE) target_compile_options(DAISY_SEED_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DAISY_SEED_usb_none INTERFACE) target_compile_options(DAISY_SEED_usb_none INTERFACE @@ -4467,15 +4467,15 @@ target_compile_options(DEMO_F030F4_serial_none INTERFACE ) add_library(DEMO_F030F4_usb_CDC INTERFACE) target_compile_options(DEMO_F030F4_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DEMO_F030F4_usb_CDCgen INTERFACE) target_compile_options(DEMO_F030F4_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DEMO_F030F4_usb_HID INTERFACE) target_compile_options(DEMO_F030F4_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DEMO_F030F4_usb_none INTERFACE) target_compile_options(DEMO_F030F4_usb_none INTERFACE @@ -4537,15 +4537,15 @@ target_compile_options(DEMO_F030F4_16M_serial_none INTERFACE ) add_library(DEMO_F030F4_16M_usb_CDC INTERFACE) target_compile_options(DEMO_F030F4_16M_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DEMO_F030F4_16M_usb_CDCgen INTERFACE) target_compile_options(DEMO_F030F4_16M_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DEMO_F030F4_16M_usb_HID INTERFACE) target_compile_options(DEMO_F030F4_16M_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DEMO_F030F4_16M_usb_none INTERFACE) target_compile_options(DEMO_F030F4_16M_usb_none INTERFACE @@ -4607,15 +4607,15 @@ target_compile_options(DEMO_F030F4_HSI_serial_none INTERFACE ) add_library(DEMO_F030F4_HSI_usb_CDC INTERFACE) target_compile_options(DEMO_F030F4_HSI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DEMO_F030F4_HSI_usb_CDCgen INTERFACE) target_compile_options(DEMO_F030F4_HSI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DEMO_F030F4_HSI_usb_HID INTERFACE) target_compile_options(DEMO_F030F4_HSI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DEMO_F030F4_HSI_usb_none INTERFACE) target_compile_options(DEMO_F030F4_HSI_usb_none INTERFACE @@ -4677,15 +4677,15 @@ target_compile_options(DevEBoxH743VITX_serial_none INTERFACE ) add_library(DevEBoxH743VITX_usb_CDC INTERFACE) target_compile_options(DevEBoxH743VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DevEBoxH743VITX_usb_CDCgen INTERFACE) target_compile_options(DevEBoxH743VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DevEBoxH743VITX_usb_HID INTERFACE) target_compile_options(DevEBoxH743VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DevEBoxH743VITX_usb_none INTERFACE) target_compile_options(DevEBoxH743VITX_usb_none INTERFACE @@ -4759,15 +4759,15 @@ target_compile_options(DevEBoxH750VBTX_serial_none INTERFACE ) add_library(DevEBoxH750VBTX_usb_CDC INTERFACE) target_compile_options(DevEBoxH750VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DevEBoxH750VBTX_usb_CDCgen INTERFACE) target_compile_options(DevEBoxH750VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DevEBoxH750VBTX_usb_HID INTERFACE) target_compile_options(DevEBoxH750VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DevEBoxH750VBTX_usb_none INTERFACE) target_compile_options(DevEBoxH750VBTX_usb_none INTERFACE @@ -4895,15 +4895,15 @@ target_compile_options(DISCO_F030R8_serial_none INTERFACE ) add_library(DISCO_F030R8_usb_CDC INTERFACE) target_compile_options(DISCO_F030R8_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DISCO_F030R8_usb_CDCgen INTERFACE) target_compile_options(DISCO_F030R8_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DISCO_F030R8_usb_HID INTERFACE) target_compile_options(DISCO_F030R8_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DISCO_F030R8_usb_none INTERFACE) target_compile_options(DISCO_F030R8_usb_none INTERFACE @@ -4977,15 +4977,15 @@ target_compile_options(DISCO_F072RB_serial_none INTERFACE ) add_library(DISCO_F072RB_usb_CDC INTERFACE) target_compile_options(DISCO_F072RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DISCO_F072RB_usb_CDCgen INTERFACE) target_compile_options(DISCO_F072RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DISCO_F072RB_usb_HID INTERFACE) target_compile_options(DISCO_F072RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DISCO_F072RB_usb_none INTERFACE) target_compile_options(DISCO_F072RB_usb_none INTERFACE @@ -5059,15 +5059,15 @@ target_compile_options(DISCO_F100RB_serial_none INTERFACE ) add_library(DISCO_F100RB_usb_CDC INTERFACE) target_compile_options(DISCO_F100RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DISCO_F100RB_usb_CDCgen INTERFACE) target_compile_options(DISCO_F100RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DISCO_F100RB_usb_HID INTERFACE) target_compile_options(DISCO_F100RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DISCO_F100RB_usb_none INTERFACE) target_compile_options(DISCO_F100RB_usb_none INTERFACE @@ -5141,15 +5141,15 @@ target_compile_options(DISCO_F303VC_serial_none INTERFACE ) add_library(DISCO_F303VC_usb_CDC INTERFACE) target_compile_options(DISCO_F303VC_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DISCO_F303VC_usb_CDCgen INTERFACE) target_compile_options(DISCO_F303VC_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DISCO_F303VC_usb_HID INTERFACE) target_compile_options(DISCO_F303VC_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DISCO_F303VC_usb_none INTERFACE) target_compile_options(DISCO_F303VC_usb_none INTERFACE @@ -5223,15 +5223,15 @@ target_compile_options(DISCO_F407VG_serial_none INTERFACE ) add_library(DISCO_F407VG_usb_CDC INTERFACE) target_compile_options(DISCO_F407VG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DISCO_F407VG_usb_CDCgen INTERFACE) target_compile_options(DISCO_F407VG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DISCO_F407VG_usb_HID INTERFACE) target_compile_options(DISCO_F407VG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DISCO_F407VG_usb_none INTERFACE) target_compile_options(DISCO_F407VG_usb_none INTERFACE @@ -5305,15 +5305,15 @@ target_compile_options(DISCO_F413ZH_serial_none INTERFACE ) add_library(DISCO_F413ZH_usb_CDC INTERFACE) target_compile_options(DISCO_F413ZH_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DISCO_F413ZH_usb_CDCgen INTERFACE) target_compile_options(DISCO_F413ZH_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DISCO_F413ZH_usb_HID INTERFACE) target_compile_options(DISCO_F413ZH_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DISCO_F413ZH_usb_none INTERFACE) target_compile_options(DISCO_F413ZH_usb_none INTERFACE @@ -5387,15 +5387,15 @@ target_compile_options(DISCO_F746NG_serial_none INTERFACE ) add_library(DISCO_F746NG_usb_CDC INTERFACE) target_compile_options(DISCO_F746NG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DISCO_F746NG_usb_CDCgen INTERFACE) target_compile_options(DISCO_F746NG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DISCO_F746NG_usb_HID INTERFACE) target_compile_options(DISCO_F746NG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DISCO_F746NG_usb_none INTERFACE) target_compile_options(DISCO_F746NG_usb_none INTERFACE @@ -5469,15 +5469,15 @@ target_compile_options(DISCO_G0316_serial_none INTERFACE ) add_library(DISCO_G0316_usb_CDC INTERFACE) target_compile_options(DISCO_G0316_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DISCO_G0316_usb_CDCgen INTERFACE) target_compile_options(DISCO_G0316_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DISCO_G0316_usb_HID INTERFACE) target_compile_options(DISCO_G0316_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DISCO_G0316_usb_none INTERFACE) target_compile_options(DISCO_G0316_usb_none INTERFACE @@ -5551,15 +5551,15 @@ target_compile_options(DIYMORE_F407VGT_serial_none INTERFACE ) add_library(DIYMORE_F407VGT_usb_CDC INTERFACE) target_compile_options(DIYMORE_F407VGT_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(DIYMORE_F407VGT_usb_CDCgen INTERFACE) target_compile_options(DIYMORE_F407VGT_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(DIYMORE_F407VGT_usb_HID INTERFACE) target_compile_options(DIYMORE_F407VGT_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(DIYMORE_F407VGT_usb_none INTERFACE) target_compile_options(DIYMORE_F407VGT_usb_none INTERFACE @@ -5675,11 +5675,11 @@ target_compile_options(EBB42_V1_1_serial_none INTERFACE ) add_library(EBB42_V1_1_usb_CDC INTERFACE) target_compile_options(EBB42_V1_1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(EBB42_V1_1_usb_CDCgen INTERFACE) target_compile_options(EBB42_V1_1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(EBB42_V1_1_usb_none INTERFACE) target_compile_options(EBB42_V1_1_usb_none INTERFACE @@ -5753,11 +5753,11 @@ target_compile_options(EEXTR_F030_V1_serial_none INTERFACE ) add_library(EEXTR_F030_V1_usb_CDC INTERFACE) target_compile_options(EEXTR_F030_V1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(EEXTR_F030_V1_usb_CDCgen INTERFACE) target_compile_options(EEXTR_F030_V1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(EEXTR_F030_V1_usb_none INTERFACE) target_compile_options(EEXTR_F030_V1_usb_none INTERFACE @@ -5939,15 +5939,15 @@ target_compile_options(ETHERCAT_DUINO_serial_none INTERFACE ) add_library(ETHERCAT_DUINO_usb_CDC INTERFACE) target_compile_options(ETHERCAT_DUINO_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(ETHERCAT_DUINO_usb_CDCgen INTERFACE) target_compile_options(ETHERCAT_DUINO_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(ETHERCAT_DUINO_usb_HID INTERFACE) target_compile_options(ETHERCAT_DUINO_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(ETHERCAT_DUINO_usb_none INTERFACE) target_compile_options(ETHERCAT_DUINO_usb_none INTERFACE @@ -6021,15 +6021,15 @@ target_compile_options(FEATHER_F405_serial_none INTERFACE ) add_library(FEATHER_F405_usb_CDC INTERFACE) target_compile_options(FEATHER_F405_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(FEATHER_F405_usb_CDCgen INTERFACE) target_compile_options(FEATHER_F405_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(FEATHER_F405_usb_HID INTERFACE) target_compile_options(FEATHER_F405_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(FEATHER_F405_usb_none INTERFACE) target_compile_options(FEATHER_F405_usb_none INTERFACE @@ -6145,15 +6145,15 @@ target_compile_options(FK407M1_serial_none INTERFACE ) add_library(FK407M1_usb_CDC INTERFACE) target_compile_options(FK407M1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(FK407M1_usb_CDCgen INTERFACE) target_compile_options(FK407M1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(FK407M1_usb_HID INTERFACE) target_compile_options(FK407M1_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(FK407M1_usb_none INTERFACE) target_compile_options(FK407M1_usb_none INTERFACE @@ -6269,11 +6269,11 @@ target_compile_options(FYSETC_S6_serial_none INTERFACE ) add_library(FYSETC_S6_usb_CDC INTERFACE) target_compile_options(FYSETC_S6_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(FYSETC_S6_usb_CDCgen INTERFACE) target_compile_options(FYSETC_S6_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(FYSETC_S6_usb_none INTERFACE) target_compile_options(FYSETC_S6_usb_none INTERFACE @@ -6941,15 +6941,15 @@ target_compile_options(GENERIC_F030C6TX_serial_none INTERFACE ) add_library(GENERIC_F030C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F030C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F030C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F030C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F030C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F030C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F030C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F030C6TX_usb_none INTERFACE @@ -7011,15 +7011,15 @@ target_compile_options(GENERIC_F030C8TX_serial_none INTERFACE ) add_library(GENERIC_F030C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F030C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F030C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F030C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F030C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F030C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F030C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F030C8TX_usb_none INTERFACE @@ -7081,15 +7081,15 @@ target_compile_options(GENERIC_F030F4PX_serial_none INTERFACE ) add_library(GENERIC_F030F4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_F030F4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F030F4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F030F4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F030F4PX_usb_HID INTERFACE) target_compile_options(GENERIC_F030F4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F030F4PX_usb_none INTERFACE) target_compile_options(GENERIC_F030F4PX_usb_none INTERFACE @@ -7151,15 +7151,15 @@ target_compile_options(GENERIC_F030K6TX_serial_none INTERFACE ) add_library(GENERIC_F030K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F030K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F030K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F030K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F030K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F030K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F030K6TX_usb_none INTERFACE) target_compile_options(GENERIC_F030K6TX_usb_none INTERFACE @@ -7221,15 +7221,15 @@ target_compile_options(GENERIC_F030R8TX_serial_none INTERFACE ) add_library(GENERIC_F030R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F030R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F030R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F030R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F030R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F030R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F030R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F030R8TX_usb_none INTERFACE @@ -7291,15 +7291,15 @@ target_compile_options(GENERIC_F031C4TX_serial_none INTERFACE ) add_library(GENERIC_F031C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F031C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031C4TX_usb_none INTERFACE) target_compile_options(GENERIC_F031C4TX_usb_none INTERFACE @@ -7361,15 +7361,15 @@ target_compile_options(GENERIC_F031C6TX_serial_none INTERFACE ) add_library(GENERIC_F031C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F031C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F031C6TX_usb_none INTERFACE @@ -7431,15 +7431,15 @@ target_compile_options(GENERIC_F031E6YX_serial_none INTERFACE ) add_library(GENERIC_F031E6YX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031E6YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031E6YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031E6YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031E6YX_usb_HID INTERFACE) target_compile_options(GENERIC_F031E6YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031E6YX_usb_none INTERFACE) target_compile_options(GENERIC_F031E6YX_usb_none INTERFACE @@ -7501,15 +7501,15 @@ target_compile_options(GENERIC_F031F4PX_serial_none INTERFACE ) add_library(GENERIC_F031F4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031F4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031F4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031F4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031F4PX_usb_HID INTERFACE) target_compile_options(GENERIC_F031F4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031F4PX_usb_none INTERFACE) target_compile_options(GENERIC_F031F4PX_usb_none INTERFACE @@ -7571,15 +7571,15 @@ target_compile_options(GENERIC_F031F6PX_serial_none INTERFACE ) add_library(GENERIC_F031F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_F031F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031F6PX_usb_none INTERFACE) target_compile_options(GENERIC_F031F6PX_usb_none INTERFACE @@ -7641,15 +7641,15 @@ target_compile_options(GENERIC_F031G4UX_serial_none INTERFACE ) add_library(GENERIC_F031G4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031G4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031G4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031G4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031G4UX_usb_HID INTERFACE) target_compile_options(GENERIC_F031G4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031G4UX_usb_none INTERFACE) target_compile_options(GENERIC_F031G4UX_usb_none INTERFACE @@ -7711,15 +7711,15 @@ target_compile_options(GENERIC_F031G6UX_serial_none INTERFACE ) add_library(GENERIC_F031G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F031G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031G6UX_usb_none INTERFACE) target_compile_options(GENERIC_F031G6UX_usb_none INTERFACE @@ -7781,15 +7781,15 @@ target_compile_options(GENERIC_F031K4UX_serial_none INTERFACE ) add_library(GENERIC_F031K4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031K4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031K4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031K4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031K4UX_usb_HID INTERFACE) target_compile_options(GENERIC_F031K4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031K4UX_usb_none INTERFACE) target_compile_options(GENERIC_F031K4UX_usb_none INTERFACE @@ -7851,15 +7851,15 @@ target_compile_options(GENERIC_F031K6TX_serial_none INTERFACE ) add_library(GENERIC_F031K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F031K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031K6TX_usb_none INTERFACE) target_compile_options(GENERIC_F031K6TX_usb_none INTERFACE @@ -7921,15 +7921,15 @@ target_compile_options(GENERIC_F031K6UX_serial_none INTERFACE ) add_library(GENERIC_F031K6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F031K6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F031K6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F031K6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F031K6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F031K6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F031K6UX_usb_none INTERFACE) target_compile_options(GENERIC_F031K6UX_usb_none INTERFACE @@ -7991,15 +7991,15 @@ target_compile_options(GENERIC_F038C6TX_serial_none INTERFACE ) add_library(GENERIC_F038C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F038C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F038C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F038C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F038C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F038C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F038C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F038C6TX_usb_none INTERFACE @@ -8061,15 +8061,15 @@ target_compile_options(GENERIC_F038E6YX_serial_none INTERFACE ) add_library(GENERIC_F038E6YX_usb_CDC INTERFACE) target_compile_options(GENERIC_F038E6YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F038E6YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F038E6YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F038E6YX_usb_HID INTERFACE) target_compile_options(GENERIC_F038E6YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F038E6YX_usb_none INTERFACE) target_compile_options(GENERIC_F038E6YX_usb_none INTERFACE @@ -8131,15 +8131,15 @@ target_compile_options(GENERIC_F038F6PX_serial_none INTERFACE ) add_library(GENERIC_F038F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_F038F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F038F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F038F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F038F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_F038F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F038F6PX_usb_none INTERFACE) target_compile_options(GENERIC_F038F6PX_usb_none INTERFACE @@ -8201,15 +8201,15 @@ target_compile_options(GENERIC_F038G6UX_serial_none INTERFACE ) add_library(GENERIC_F038G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F038G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F038G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F038G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F038G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F038G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F038G6UX_usb_none INTERFACE) target_compile_options(GENERIC_F038G6UX_usb_none INTERFACE @@ -8271,15 +8271,15 @@ target_compile_options(GENERIC_F038K6UX_serial_none INTERFACE ) add_library(GENERIC_F038K6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F038K6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F038K6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F038K6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F038K6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F038K6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F038K6UX_usb_none INTERFACE) target_compile_options(GENERIC_F038K6UX_usb_none INTERFACE @@ -8341,15 +8341,15 @@ target_compile_options(GENERIC_F042C4TX_serial_none INTERFACE ) add_library(GENERIC_F042C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F042C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042C4TX_usb_none INTERFACE) target_compile_options(GENERIC_F042C4TX_usb_none INTERFACE @@ -8411,15 +8411,15 @@ target_compile_options(GENERIC_F042C4UX_serial_none INTERFACE ) add_library(GENERIC_F042C4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042C4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042C4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042C4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042C4UX_usb_HID INTERFACE) target_compile_options(GENERIC_F042C4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042C4UX_usb_none INTERFACE) target_compile_options(GENERIC_F042C4UX_usb_none INTERFACE @@ -8481,15 +8481,15 @@ target_compile_options(GENERIC_F042C6TX_serial_none INTERFACE ) add_library(GENERIC_F042C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F042C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F042C6TX_usb_none INTERFACE @@ -8551,15 +8551,15 @@ target_compile_options(GENERIC_F042C6UX_serial_none INTERFACE ) add_library(GENERIC_F042C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F042C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042C6UX_usb_none INTERFACE) target_compile_options(GENERIC_F042C6UX_usb_none INTERFACE @@ -8621,15 +8621,15 @@ target_compile_options(GENERIC_F042F4PX_serial_none INTERFACE ) add_library(GENERIC_F042F4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042F4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042F4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042F4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042F4PX_usb_HID INTERFACE) target_compile_options(GENERIC_F042F4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042F4PX_usb_none INTERFACE) target_compile_options(GENERIC_F042F4PX_usb_none INTERFACE @@ -8691,15 +8691,15 @@ target_compile_options(GENERIC_F042F6PX_serial_none INTERFACE ) add_library(GENERIC_F042F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_F042F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042F6PX_usb_none INTERFACE) target_compile_options(GENERIC_F042F6PX_usb_none INTERFACE @@ -8761,15 +8761,15 @@ target_compile_options(GENERIC_F042G4UX_serial_none INTERFACE ) add_library(GENERIC_F042G4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042G4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042G4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042G4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042G4UX_usb_HID INTERFACE) target_compile_options(GENERIC_F042G4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042G4UX_usb_none INTERFACE) target_compile_options(GENERIC_F042G4UX_usb_none INTERFACE @@ -8831,15 +8831,15 @@ target_compile_options(GENERIC_F042G6UX_serial_none INTERFACE ) add_library(GENERIC_F042G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F042G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042G6UX_usb_none INTERFACE) target_compile_options(GENERIC_F042G6UX_usb_none INTERFACE @@ -8901,15 +8901,15 @@ target_compile_options(GENERIC_F042K4TX_serial_none INTERFACE ) add_library(GENERIC_F042K4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042K4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042K4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042K4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042K4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F042K4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042K4TX_usb_none INTERFACE) target_compile_options(GENERIC_F042K4TX_usb_none INTERFACE @@ -8971,15 +8971,15 @@ target_compile_options(GENERIC_F042K6TX_serial_none INTERFACE ) add_library(GENERIC_F042K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F042K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042K6TX_usb_none INTERFACE) target_compile_options(GENERIC_F042K6TX_usb_none INTERFACE @@ -9041,15 +9041,15 @@ target_compile_options(GENERIC_F042T6YX_serial_none INTERFACE ) add_library(GENERIC_F042T6YX_usb_CDC INTERFACE) target_compile_options(GENERIC_F042T6YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F042T6YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F042T6YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F042T6YX_usb_HID INTERFACE) target_compile_options(GENERIC_F042T6YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F042T6YX_usb_none INTERFACE) target_compile_options(GENERIC_F042T6YX_usb_none INTERFACE @@ -9111,15 +9111,15 @@ target_compile_options(GENERIC_F048G6UX_serial_none INTERFACE ) add_library(GENERIC_F048G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F048G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F048G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F048G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F048G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F048G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F048G6UX_usb_none INTERFACE) target_compile_options(GENERIC_F048G6UX_usb_none INTERFACE @@ -9181,15 +9181,15 @@ target_compile_options(GENERIC_F048T6YX_serial_none INTERFACE ) add_library(GENERIC_F048T6YX_usb_CDC INTERFACE) target_compile_options(GENERIC_F048T6YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F048T6YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F048T6YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F048T6YX_usb_HID INTERFACE) target_compile_options(GENERIC_F048T6YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F048T6YX_usb_none INTERFACE) target_compile_options(GENERIC_F048T6YX_usb_none INTERFACE @@ -9251,15 +9251,15 @@ target_compile_options(GENERIC_F051C4TX_serial_none INTERFACE ) add_library(GENERIC_F051C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F051C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F051C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F051C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F051C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F051C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F051C4TX_usb_none INTERFACE) target_compile_options(GENERIC_F051C4TX_usb_none INTERFACE @@ -9321,15 +9321,15 @@ target_compile_options(GENERIC_F051C4UX_serial_none INTERFACE ) add_library(GENERIC_F051C4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F051C4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F051C4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F051C4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F051C4UX_usb_HID INTERFACE) target_compile_options(GENERIC_F051C4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F051C4UX_usb_none INTERFACE) target_compile_options(GENERIC_F051C4UX_usb_none INTERFACE @@ -9391,15 +9391,15 @@ target_compile_options(GENERIC_F051K4TX_serial_none INTERFACE ) add_library(GENERIC_F051K4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F051K4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F051K4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F051K4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F051K4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F051K4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F051K4TX_usb_none INTERFACE) target_compile_options(GENERIC_F051K4TX_usb_none INTERFACE @@ -9461,15 +9461,15 @@ target_compile_options(GENERIC_F051K6UX_serial_none INTERFACE ) add_library(GENERIC_F051K6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F051K6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F051K6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F051K6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F051K6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F051K6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F051K6UX_usb_none INTERFACE) target_compile_options(GENERIC_F051K6UX_usb_none INTERFACE @@ -9531,15 +9531,15 @@ target_compile_options(GENERIC_F051K8UX_serial_none INTERFACE ) add_library(GENERIC_F051K8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F051K8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F051K8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F051K8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F051K8UX_usb_HID INTERFACE) target_compile_options(GENERIC_F051K8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F051K8UX_usb_none INTERFACE) target_compile_options(GENERIC_F051K8UX_usb_none INTERFACE @@ -9601,15 +9601,15 @@ target_compile_options(GENERIC_F051R4TX_serial_none INTERFACE ) add_library(GENERIC_F051R4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F051R4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F051R4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F051R4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F051R4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F051R4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F051R4TX_usb_none INTERFACE) target_compile_options(GENERIC_F051R4TX_usb_none INTERFACE @@ -9671,15 +9671,15 @@ target_compile_options(GENERIC_F051T8YX_serial_none INTERFACE ) add_library(GENERIC_F051T8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_F051T8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F051T8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F051T8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F051T8YX_usb_HID INTERFACE) target_compile_options(GENERIC_F051T8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F051T8YX_usb_none INTERFACE) target_compile_options(GENERIC_F051T8YX_usb_none INTERFACE @@ -9741,15 +9741,15 @@ target_compile_options(GENERIC_F058C8UX_serial_none INTERFACE ) add_library(GENERIC_F058C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F058C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F058C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F058C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F058C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_F058C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F058C8UX_usb_none INTERFACE) target_compile_options(GENERIC_F058C8UX_usb_none INTERFACE @@ -9811,15 +9811,15 @@ target_compile_options(GENERIC_F058R8HX_serial_none INTERFACE ) add_library(GENERIC_F058R8HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F058R8HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F058R8HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F058R8HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F058R8HX_usb_HID INTERFACE) target_compile_options(GENERIC_F058R8HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F058R8HX_usb_none INTERFACE) target_compile_options(GENERIC_F058R8HX_usb_none INTERFACE @@ -9881,15 +9881,15 @@ target_compile_options(GENERIC_F058R8TX_serial_none INTERFACE ) add_library(GENERIC_F058R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F058R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F058R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F058R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F058R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F058R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F058R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F058R8TX_usb_none INTERFACE @@ -9951,15 +9951,15 @@ target_compile_options(GENERIC_F058T8YX_serial_none INTERFACE ) add_library(GENERIC_F058T8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_F058T8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F058T8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F058T8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F058T8YX_usb_HID INTERFACE) target_compile_options(GENERIC_F058T8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F058T8YX_usb_none INTERFACE) target_compile_options(GENERIC_F058T8YX_usb_none INTERFACE @@ -10021,15 +10021,15 @@ target_compile_options(GENERIC_F070CBTX_serial_none INTERFACE ) add_library(GENERIC_F070CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F070CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F070CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F070CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F070CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F070CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F070CBTX_usb_none INTERFACE) target_compile_options(GENERIC_F070CBTX_usb_none INTERFACE @@ -10091,15 +10091,15 @@ target_compile_options(GENERIC_F070RBTX_serial_none INTERFACE ) add_library(GENERIC_F070RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F070RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F070RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F070RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F070RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F070RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F070RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F070RBTX_usb_none INTERFACE @@ -10161,15 +10161,15 @@ target_compile_options(GENERIC_F071C8TX_serial_none INTERFACE ) add_library(GENERIC_F071C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F071C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F071C8TX_usb_none INTERFACE @@ -10231,15 +10231,15 @@ target_compile_options(GENERIC_F071C8UX_serial_none INTERFACE ) add_library(GENERIC_F071C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_F071C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071C8UX_usb_none INTERFACE) target_compile_options(GENERIC_F071C8UX_usb_none INTERFACE @@ -10301,15 +10301,15 @@ target_compile_options(GENERIC_F071CBTX_serial_none INTERFACE ) add_library(GENERIC_F071CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F071CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071CBTX_usb_none INTERFACE) target_compile_options(GENERIC_F071CBTX_usb_none INTERFACE @@ -10371,15 +10371,15 @@ target_compile_options(GENERIC_F071CBUX_serial_none INTERFACE ) add_library(GENERIC_F071CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_F071CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071CBUX_usb_none INTERFACE) target_compile_options(GENERIC_F071CBUX_usb_none INTERFACE @@ -10441,15 +10441,15 @@ target_compile_options(GENERIC_F071CBYX_serial_none INTERFACE ) add_library(GENERIC_F071CBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071CBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071CBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071CBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071CBYX_usb_HID INTERFACE) target_compile_options(GENERIC_F071CBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071CBYX_usb_none INTERFACE) target_compile_options(GENERIC_F071CBYX_usb_none INTERFACE @@ -10511,15 +10511,15 @@ target_compile_options(GENERIC_F071RBTX_serial_none INTERFACE ) add_library(GENERIC_F071RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F071RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F071RBTX_usb_none INTERFACE @@ -10581,15 +10581,15 @@ target_compile_options(GENERIC_F071V8HX_serial_none INTERFACE ) add_library(GENERIC_F071V8HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071V8HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071V8HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071V8HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071V8HX_usb_HID INTERFACE) target_compile_options(GENERIC_F071V8HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071V8HX_usb_none INTERFACE) target_compile_options(GENERIC_F071V8HX_usb_none INTERFACE @@ -10651,15 +10651,15 @@ target_compile_options(GENERIC_F071V8TX_serial_none INTERFACE ) add_library(GENERIC_F071V8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071V8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071V8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071V8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071V8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F071V8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071V8TX_usb_none INTERFACE) target_compile_options(GENERIC_F071V8TX_usb_none INTERFACE @@ -10721,15 +10721,15 @@ target_compile_options(GENERIC_F071VBHX_serial_none INTERFACE ) add_library(GENERIC_F071VBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071VBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071VBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071VBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071VBHX_usb_HID INTERFACE) target_compile_options(GENERIC_F071VBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071VBHX_usb_none INTERFACE) target_compile_options(GENERIC_F071VBHX_usb_none INTERFACE @@ -10791,15 +10791,15 @@ target_compile_options(GENERIC_F071VBTX_serial_none INTERFACE ) add_library(GENERIC_F071VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F071VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F071VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F071VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F071VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F071VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F071VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F071VBTX_usb_none INTERFACE @@ -10861,15 +10861,15 @@ target_compile_options(GENERIC_F072C8TX_serial_none INTERFACE ) add_library(GENERIC_F072C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F072C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F072C8TX_usb_none INTERFACE @@ -10931,15 +10931,15 @@ target_compile_options(GENERIC_F072C8UX_serial_none INTERFACE ) add_library(GENERIC_F072C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_F072C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072C8UX_usb_none INTERFACE) target_compile_options(GENERIC_F072C8UX_usb_none INTERFACE @@ -11001,15 +11001,15 @@ target_compile_options(GENERIC_F072CBTX_serial_none INTERFACE ) add_library(GENERIC_F072CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F072CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072CBTX_usb_none INTERFACE) target_compile_options(GENERIC_F072CBTX_usb_none INTERFACE @@ -11071,15 +11071,15 @@ target_compile_options(GENERIC_F072CBUX_serial_none INTERFACE ) add_library(GENERIC_F072CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_F072CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072CBUX_usb_none INTERFACE) target_compile_options(GENERIC_F072CBUX_usb_none INTERFACE @@ -11141,15 +11141,15 @@ target_compile_options(GENERIC_F072CBYX_serial_none INTERFACE ) add_library(GENERIC_F072CBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072CBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072CBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072CBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072CBYX_usb_HID INTERFACE) target_compile_options(GENERIC_F072CBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072CBYX_usb_none INTERFACE) target_compile_options(GENERIC_F072CBYX_usb_none INTERFACE @@ -11211,15 +11211,15 @@ target_compile_options(GENERIC_F072R8TX_serial_none INTERFACE ) add_library(GENERIC_F072R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F072R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F072R8TX_usb_none INTERFACE @@ -11281,15 +11281,15 @@ target_compile_options(GENERIC_F072RBHX_serial_none INTERFACE ) add_library(GENERIC_F072RBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072RBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072RBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072RBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072RBHX_usb_HID INTERFACE) target_compile_options(GENERIC_F072RBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072RBHX_usb_none INTERFACE) target_compile_options(GENERIC_F072RBHX_usb_none INTERFACE @@ -11351,15 +11351,15 @@ target_compile_options(GENERIC_F072RBIX_serial_none INTERFACE ) add_library(GENERIC_F072RBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072RBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072RBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072RBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072RBIX_usb_HID INTERFACE) target_compile_options(GENERIC_F072RBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072RBIX_usb_none INTERFACE) target_compile_options(GENERIC_F072RBIX_usb_none INTERFACE @@ -11421,15 +11421,15 @@ target_compile_options(GENERIC_F072RBTX_serial_none INTERFACE ) add_library(GENERIC_F072RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F072RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F072RBTX_usb_none INTERFACE @@ -11491,15 +11491,15 @@ target_compile_options(GENERIC_F072V8HX_serial_none INTERFACE ) add_library(GENERIC_F072V8HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072V8HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072V8HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072V8HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072V8HX_usb_HID INTERFACE) target_compile_options(GENERIC_F072V8HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072V8HX_usb_none INTERFACE) target_compile_options(GENERIC_F072V8HX_usb_none INTERFACE @@ -11561,15 +11561,15 @@ target_compile_options(GENERIC_F072V8TX_serial_none INTERFACE ) add_library(GENERIC_F072V8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072V8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072V8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072V8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072V8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F072V8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072V8TX_usb_none INTERFACE) target_compile_options(GENERIC_F072V8TX_usb_none INTERFACE @@ -11631,15 +11631,15 @@ target_compile_options(GENERIC_F072VBHX_serial_none INTERFACE ) add_library(GENERIC_F072VBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072VBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072VBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072VBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072VBHX_usb_HID INTERFACE) target_compile_options(GENERIC_F072VBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072VBHX_usb_none INTERFACE) target_compile_options(GENERIC_F072VBHX_usb_none INTERFACE @@ -11701,15 +11701,15 @@ target_compile_options(GENERIC_F072VBTX_serial_none INTERFACE ) add_library(GENERIC_F072VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F072VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F072VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F072VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F072VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F072VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F072VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F072VBTX_usb_none INTERFACE @@ -11771,15 +11771,15 @@ target_compile_options(GENERIC_F078CBTX_serial_none INTERFACE ) add_library(GENERIC_F078CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F078CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F078CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F078CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F078CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F078CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F078CBTX_usb_none INTERFACE) target_compile_options(GENERIC_F078CBTX_usb_none INTERFACE @@ -11841,15 +11841,15 @@ target_compile_options(GENERIC_F078CBUX_serial_none INTERFACE ) add_library(GENERIC_F078CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F078CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F078CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F078CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F078CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_F078CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F078CBUX_usb_none INTERFACE) target_compile_options(GENERIC_F078CBUX_usb_none INTERFACE @@ -11911,15 +11911,15 @@ target_compile_options(GENERIC_F078CBYX_serial_none INTERFACE ) add_library(GENERIC_F078CBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F078CBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F078CBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F078CBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F078CBYX_usb_HID INTERFACE) target_compile_options(GENERIC_F078CBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F078CBYX_usb_none INTERFACE) target_compile_options(GENERIC_F078CBYX_usb_none INTERFACE @@ -11981,15 +11981,15 @@ target_compile_options(GENERIC_F078RBHX_serial_none INTERFACE ) add_library(GENERIC_F078RBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F078RBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F078RBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F078RBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F078RBHX_usb_HID INTERFACE) target_compile_options(GENERIC_F078RBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F078RBHX_usb_none INTERFACE) target_compile_options(GENERIC_F078RBHX_usb_none INTERFACE @@ -12051,15 +12051,15 @@ target_compile_options(GENERIC_F078RBTX_serial_none INTERFACE ) add_library(GENERIC_F078RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F078RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F078RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F078RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F078RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F078RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F078RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F078RBTX_usb_none INTERFACE @@ -12121,15 +12121,15 @@ target_compile_options(GENERIC_F078VBHX_serial_none INTERFACE ) add_library(GENERIC_F078VBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F078VBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F078VBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F078VBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F078VBHX_usb_HID INTERFACE) target_compile_options(GENERIC_F078VBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F078VBHX_usb_none INTERFACE) target_compile_options(GENERIC_F078VBHX_usb_none INTERFACE @@ -12191,15 +12191,15 @@ target_compile_options(GENERIC_F078VBTX_serial_none INTERFACE ) add_library(GENERIC_F078VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F078VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F078VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F078VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F078VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F078VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F078VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F078VBTX_usb_none INTERFACE @@ -12261,15 +12261,15 @@ target_compile_options(GENERIC_F091CBTX_serial_none INTERFACE ) add_library(GENERIC_F091CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F091CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091CBTX_usb_none INTERFACE) target_compile_options(GENERIC_F091CBTX_usb_none INTERFACE @@ -12331,15 +12331,15 @@ target_compile_options(GENERIC_F091CBUX_serial_none INTERFACE ) add_library(GENERIC_F091CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_F091CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091CBUX_usb_none INTERFACE) target_compile_options(GENERIC_F091CBUX_usb_none INTERFACE @@ -12401,15 +12401,15 @@ target_compile_options(GENERIC_F091CCTX_serial_none INTERFACE ) add_library(GENERIC_F091CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F091CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091CCTX_usb_none INTERFACE) target_compile_options(GENERIC_F091CCTX_usb_none INTERFACE @@ -12471,15 +12471,15 @@ target_compile_options(GENERIC_F091CCUX_serial_none INTERFACE ) add_library(GENERIC_F091CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_F091CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091CCUX_usb_none INTERFACE) target_compile_options(GENERIC_F091CCUX_usb_none INTERFACE @@ -12541,15 +12541,15 @@ target_compile_options(GENERIC_F091RBTX_serial_none INTERFACE ) add_library(GENERIC_F091RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F091RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F091RBTX_usb_none INTERFACE @@ -12611,15 +12611,15 @@ target_compile_options(GENERIC_F091RCHX_serial_none INTERFACE ) add_library(GENERIC_F091RCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091RCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091RCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091RCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091RCHX_usb_HID INTERFACE) target_compile_options(GENERIC_F091RCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091RCHX_usb_none INTERFACE) target_compile_options(GENERIC_F091RCHX_usb_none INTERFACE @@ -12681,15 +12681,15 @@ target_compile_options(GENERIC_F091RCTX_serial_none INTERFACE ) add_library(GENERIC_F091RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F091RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F091RCTX_usb_none INTERFACE @@ -12751,15 +12751,15 @@ target_compile_options(GENERIC_F091RCYX_serial_none INTERFACE ) add_library(GENERIC_F091RCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091RCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091RCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091RCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091RCYX_usb_HID INTERFACE) target_compile_options(GENERIC_F091RCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091RCYX_usb_none INTERFACE) target_compile_options(GENERIC_F091RCYX_usb_none INTERFACE @@ -12821,15 +12821,15 @@ target_compile_options(GENERIC_F091VBTX_serial_none INTERFACE ) add_library(GENERIC_F091VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F091VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F091VBTX_usb_none INTERFACE @@ -12891,15 +12891,15 @@ target_compile_options(GENERIC_F091VCHX_serial_none INTERFACE ) add_library(GENERIC_F091VCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091VCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091VCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091VCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091VCHX_usb_HID INTERFACE) target_compile_options(GENERIC_F091VCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091VCHX_usb_none INTERFACE) target_compile_options(GENERIC_F091VCHX_usb_none INTERFACE @@ -12961,15 +12961,15 @@ target_compile_options(GENERIC_F091VCTX_serial_none INTERFACE ) add_library(GENERIC_F091VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F091VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F091VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F091VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F091VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F091VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F091VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F091VCTX_usb_none INTERFACE @@ -13031,15 +13031,15 @@ target_compile_options(GENERIC_F098CCTX_serial_none INTERFACE ) add_library(GENERIC_F098CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F098CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F098CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F098CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F098CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F098CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F098CCTX_usb_none INTERFACE) target_compile_options(GENERIC_F098CCTX_usb_none INTERFACE @@ -13101,15 +13101,15 @@ target_compile_options(GENERIC_F098CCUX_serial_none INTERFACE ) add_library(GENERIC_F098CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F098CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F098CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F098CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F098CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_F098CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F098CCUX_usb_none INTERFACE) target_compile_options(GENERIC_F098CCUX_usb_none INTERFACE @@ -13171,15 +13171,15 @@ target_compile_options(GENERIC_F098RCHX_serial_none INTERFACE ) add_library(GENERIC_F098RCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F098RCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F098RCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F098RCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F098RCHX_usb_HID INTERFACE) target_compile_options(GENERIC_F098RCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F098RCHX_usb_none INTERFACE) target_compile_options(GENERIC_F098RCHX_usb_none INTERFACE @@ -13241,15 +13241,15 @@ target_compile_options(GENERIC_F098RCTX_serial_none INTERFACE ) add_library(GENERIC_F098RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F098RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F098RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F098RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F098RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F098RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F098RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F098RCTX_usb_none INTERFACE @@ -13311,15 +13311,15 @@ target_compile_options(GENERIC_F098RCYX_serial_none INTERFACE ) add_library(GENERIC_F098RCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F098RCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F098RCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F098RCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F098RCYX_usb_HID INTERFACE) target_compile_options(GENERIC_F098RCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F098RCYX_usb_none INTERFACE) target_compile_options(GENERIC_F098RCYX_usb_none INTERFACE @@ -13381,15 +13381,15 @@ target_compile_options(GENERIC_F098VCHX_serial_none INTERFACE ) add_library(GENERIC_F098VCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F098VCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F098VCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F098VCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F098VCHX_usb_HID INTERFACE) target_compile_options(GENERIC_F098VCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F098VCHX_usb_none INTERFACE) target_compile_options(GENERIC_F098VCHX_usb_none INTERFACE @@ -13451,15 +13451,15 @@ target_compile_options(GENERIC_F098VCTX_serial_none INTERFACE ) add_library(GENERIC_F098VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F098VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F098VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F098VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F098VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F098VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F098VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F098VCTX_usb_none INTERFACE @@ -13521,15 +13521,15 @@ target_compile_options(GENERIC_F100C4TX_serial_none INTERFACE ) add_library(GENERIC_F100C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F100C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100C4TX_usb_none INTERFACE) target_compile_options(GENERIC_F100C4TX_usb_none INTERFACE @@ -13729,15 +13729,15 @@ target_compile_options(GENERIC_F100C6TX_serial_none INTERFACE ) add_library(GENERIC_F100C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F100C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F100C6TX_usb_none INTERFACE @@ -13937,15 +13937,15 @@ target_compile_options(GENERIC_F100C8TX_serial_none INTERFACE ) add_library(GENERIC_F100C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F100C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F100C8TX_usb_none INTERFACE @@ -14145,15 +14145,15 @@ target_compile_options(GENERIC_F100CBTX_serial_none INTERFACE ) add_library(GENERIC_F100CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F100CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100CBTX_usb_none INTERFACE) target_compile_options(GENERIC_F100CBTX_usb_none INTERFACE @@ -14353,15 +14353,15 @@ target_compile_options(GENERIC_F100R4HX_serial_none INTERFACE ) add_library(GENERIC_F100R4HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100R4HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100R4HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100R4HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100R4HX_usb_HID INTERFACE) target_compile_options(GENERIC_F100R4HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100R4HX_usb_none INTERFACE) target_compile_options(GENERIC_F100R4HX_usb_none INTERFACE @@ -14561,15 +14561,15 @@ target_compile_options(GENERIC_F100R6HX_serial_none INTERFACE ) add_library(GENERIC_F100R6HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100R6HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100R6HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100R6HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100R6HX_usb_HID INTERFACE) target_compile_options(GENERIC_F100R6HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100R6HX_usb_none INTERFACE) target_compile_options(GENERIC_F100R6HX_usb_none INTERFACE @@ -14769,15 +14769,15 @@ target_compile_options(GENERIC_F100R8TX_serial_none INTERFACE ) add_library(GENERIC_F100R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F100R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F100R8TX_usb_none INTERFACE @@ -14977,15 +14977,15 @@ target_compile_options(GENERIC_F100RBTX_serial_none INTERFACE ) add_library(GENERIC_F100RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F100RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F100RBTX_usb_none INTERFACE @@ -15185,15 +15185,15 @@ target_compile_options(GENERIC_F100V8TX_serial_none INTERFACE ) add_library(GENERIC_F100V8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100V8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100V8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100V8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100V8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F100V8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100V8TX_usb_none INTERFACE) target_compile_options(GENERIC_F100V8TX_usb_none INTERFACE @@ -15393,15 +15393,15 @@ target_compile_options(GENERIC_F100VBTX_serial_none INTERFACE ) add_library(GENERIC_F100VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F100VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F100VBTX_usb_none INTERFACE @@ -15601,15 +15601,15 @@ target_compile_options(GENERIC_F100ZCTX_serial_none INTERFACE ) add_library(GENERIC_F100ZCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100ZCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100ZCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100ZCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100ZCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F100ZCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100ZCTX_usb_none INTERFACE) target_compile_options(GENERIC_F100ZCTX_usb_none INTERFACE @@ -15809,15 +15809,15 @@ target_compile_options(GENERIC_F100ZDTX_serial_none INTERFACE ) add_library(GENERIC_F100ZDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100ZDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100ZDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100ZDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100ZDTX_usb_HID INTERFACE) target_compile_options(GENERIC_F100ZDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100ZDTX_usb_none INTERFACE) target_compile_options(GENERIC_F100ZDTX_usb_none INTERFACE @@ -16017,15 +16017,15 @@ target_compile_options(GENERIC_F100ZETX_serial_none INTERFACE ) add_library(GENERIC_F100ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F100ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F100ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F100ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F100ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F100ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F100ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F100ZETX_usb_none INTERFACE @@ -16225,15 +16225,15 @@ target_compile_options(GENERIC_F101C4TX_serial_none INTERFACE ) add_library(GENERIC_F101C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F101C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101C4TX_usb_none INTERFACE) target_compile_options(GENERIC_F101C4TX_usb_none INTERFACE @@ -16433,15 +16433,15 @@ target_compile_options(GENERIC_F101C6TX_serial_none INTERFACE ) add_library(GENERIC_F101C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F101C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F101C6TX_usb_none INTERFACE @@ -16641,15 +16641,15 @@ target_compile_options(GENERIC_F101R4TX_serial_none INTERFACE ) add_library(GENERIC_F101R4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101R4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101R4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101R4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101R4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F101R4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101R4TX_usb_none INTERFACE) target_compile_options(GENERIC_F101R4TX_usb_none INTERFACE @@ -16849,15 +16849,15 @@ target_compile_options(GENERIC_F101R6TX_serial_none INTERFACE ) add_library(GENERIC_F101R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F101R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101R6TX_usb_none INTERFACE) target_compile_options(GENERIC_F101R6TX_usb_none INTERFACE @@ -17057,15 +17057,15 @@ target_compile_options(GENERIC_F101T4UX_serial_none INTERFACE ) add_library(GENERIC_F101T4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101T4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101T4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101T4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101T4UX_usb_HID INTERFACE) target_compile_options(GENERIC_F101T4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101T4UX_usb_none INTERFACE) target_compile_options(GENERIC_F101T4UX_usb_none INTERFACE @@ -17265,15 +17265,15 @@ target_compile_options(GENERIC_F101T6UX_serial_none INTERFACE ) add_library(GENERIC_F101T6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101T6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101T6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101T6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101T6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F101T6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101T6UX_usb_none INTERFACE) target_compile_options(GENERIC_F101T6UX_usb_none INTERFACE @@ -17473,15 +17473,15 @@ target_compile_options(GENERIC_F101V8TX_serial_none INTERFACE ) add_library(GENERIC_F101V8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101V8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101V8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101V8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101V8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F101V8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101V8TX_usb_none INTERFACE) target_compile_options(GENERIC_F101V8TX_usb_none INTERFACE @@ -17681,15 +17681,15 @@ target_compile_options(GENERIC_F101VBTX_serial_none INTERFACE ) add_library(GENERIC_F101VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F101VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F101VBTX_usb_none INTERFACE @@ -17889,15 +17889,15 @@ target_compile_options(GENERIC_F101ZCTX_serial_none INTERFACE ) add_library(GENERIC_F101ZCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101ZCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101ZCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101ZCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101ZCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F101ZCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101ZCTX_usb_none INTERFACE) target_compile_options(GENERIC_F101ZCTX_usb_none INTERFACE @@ -18097,15 +18097,15 @@ target_compile_options(GENERIC_F101ZDTX_serial_none INTERFACE ) add_library(GENERIC_F101ZDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101ZDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101ZDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101ZDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101ZDTX_usb_HID INTERFACE) target_compile_options(GENERIC_F101ZDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101ZDTX_usb_none INTERFACE) target_compile_options(GENERIC_F101ZDTX_usb_none INTERFACE @@ -18305,15 +18305,15 @@ target_compile_options(GENERIC_F101ZETX_serial_none INTERFACE ) add_library(GENERIC_F101ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F101ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F101ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F101ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F101ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F101ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F101ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F101ZETX_usb_none INTERFACE @@ -18513,15 +18513,15 @@ target_compile_options(GENERIC_F103C4TX_serial_none INTERFACE ) add_library(GENERIC_F103C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F103C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103C4TX_usb_none INTERFACE) target_compile_options(GENERIC_F103C4TX_usb_none INTERFACE @@ -18721,15 +18721,15 @@ target_compile_options(GENERIC_F103C6TX_serial_none INTERFACE ) add_library(GENERIC_F103C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F103C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F103C6TX_usb_none INTERFACE @@ -18929,15 +18929,15 @@ target_compile_options(GENERIC_F103C6UX_serial_none INTERFACE ) add_library(GENERIC_F103C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F103C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103C6UX_usb_none INTERFACE) target_compile_options(GENERIC_F103C6UX_usb_none INTERFACE @@ -19137,15 +19137,15 @@ target_compile_options(GENERIC_F103C8TX_serial_none INTERFACE ) add_library(GENERIC_F103C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F103C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F103C8TX_usb_none INTERFACE @@ -19345,15 +19345,15 @@ target_compile_options(GENERIC_F103CBTX_serial_none INTERFACE ) add_library(GENERIC_F103CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103CBTX_usb_none INTERFACE) target_compile_options(GENERIC_F103CBTX_usb_none INTERFACE @@ -19553,15 +19553,15 @@ target_compile_options(GENERIC_F103CBUX_serial_none INTERFACE ) add_library(GENERIC_F103CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_F103CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103CBUX_usb_none INTERFACE) target_compile_options(GENERIC_F103CBUX_usb_none INTERFACE @@ -19761,15 +19761,15 @@ target_compile_options(GENERIC_F103R4HX_serial_none INTERFACE ) add_library(GENERIC_F103R4HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103R4HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103R4HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103R4HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103R4HX_usb_HID INTERFACE) target_compile_options(GENERIC_F103R4HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103R4HX_usb_none INTERFACE) target_compile_options(GENERIC_F103R4HX_usb_none INTERFACE @@ -19969,15 +19969,15 @@ target_compile_options(GENERIC_F103R4TX_serial_none INTERFACE ) add_library(GENERIC_F103R4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103R4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103R4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103R4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103R4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F103R4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103R4TX_usb_none INTERFACE) target_compile_options(GENERIC_F103R4TX_usb_none INTERFACE @@ -20177,15 +20177,15 @@ target_compile_options(GENERIC_F103R6HX_serial_none INTERFACE ) add_library(GENERIC_F103R6HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103R6HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103R6HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103R6HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103R6HX_usb_HID INTERFACE) target_compile_options(GENERIC_F103R6HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103R6HX_usb_none INTERFACE) target_compile_options(GENERIC_F103R6HX_usb_none INTERFACE @@ -20385,15 +20385,15 @@ target_compile_options(GENERIC_F103R6TX_serial_none INTERFACE ) add_library(GENERIC_F103R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F103R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103R6TX_usb_none INTERFACE) target_compile_options(GENERIC_F103R6TX_usb_none INTERFACE @@ -20593,15 +20593,15 @@ target_compile_options(GENERIC_F103R8HX_serial_none INTERFACE ) add_library(GENERIC_F103R8HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103R8HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103R8HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103R8HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103R8HX_usb_HID INTERFACE) target_compile_options(GENERIC_F103R8HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103R8HX_usb_none INTERFACE) target_compile_options(GENERIC_F103R8HX_usb_none INTERFACE @@ -20801,15 +20801,15 @@ target_compile_options(GENERIC_F103R8TX_serial_none INTERFACE ) add_library(GENERIC_F103R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F103R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F103R8TX_usb_none INTERFACE @@ -21009,15 +21009,15 @@ target_compile_options(GENERIC_F103RBHX_serial_none INTERFACE ) add_library(GENERIC_F103RBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103RBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103RBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103RBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103RBHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103RBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103RBHX_usb_none INTERFACE) target_compile_options(GENERIC_F103RBHX_usb_none INTERFACE @@ -21217,15 +21217,15 @@ target_compile_options(GENERIC_F103RBTX_serial_none INTERFACE ) add_library(GENERIC_F103RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F103RBTX_usb_none INTERFACE @@ -21425,15 +21425,15 @@ target_compile_options(GENERIC_F103RCTX_serial_none INTERFACE ) add_library(GENERIC_F103RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F103RCTX_usb_none INTERFACE @@ -21633,15 +21633,15 @@ target_compile_options(GENERIC_F103RCYX_serial_none INTERFACE ) add_library(GENERIC_F103RCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103RCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103RCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103RCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103RCYX_usb_HID INTERFACE) target_compile_options(GENERIC_F103RCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103RCYX_usb_none INTERFACE) target_compile_options(GENERIC_F103RCYX_usb_none INTERFACE @@ -21841,15 +21841,15 @@ target_compile_options(GENERIC_F103RDTX_serial_none INTERFACE ) add_library(GENERIC_F103RDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103RDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103RDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103RDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103RDTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103RDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103RDTX_usb_none INTERFACE) target_compile_options(GENERIC_F103RDTX_usb_none INTERFACE @@ -22049,15 +22049,15 @@ target_compile_options(GENERIC_F103RDYX_serial_none INTERFACE ) add_library(GENERIC_F103RDYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103RDYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103RDYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103RDYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103RDYX_usb_HID INTERFACE) target_compile_options(GENERIC_F103RDYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103RDYX_usb_none INTERFACE) target_compile_options(GENERIC_F103RDYX_usb_none INTERFACE @@ -22257,15 +22257,15 @@ target_compile_options(GENERIC_F103RETX_serial_none INTERFACE ) add_library(GENERIC_F103RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F103RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103RETX_usb_none INTERFACE) target_compile_options(GENERIC_F103RETX_usb_none INTERFACE @@ -22465,15 +22465,15 @@ target_compile_options(GENERIC_F103REYX_serial_none INTERFACE ) add_library(GENERIC_F103REYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103REYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103REYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103REYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103REYX_usb_HID INTERFACE) target_compile_options(GENERIC_F103REYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103REYX_usb_none INTERFACE) target_compile_options(GENERIC_F103REYX_usb_none INTERFACE @@ -22673,15 +22673,15 @@ target_compile_options(GENERIC_F103RFTX_serial_none INTERFACE ) add_library(GENERIC_F103RFTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103RFTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103RFTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103RFTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103RFTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103RFTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103RFTX_usb_none INTERFACE) target_compile_options(GENERIC_F103RFTX_usb_none INTERFACE @@ -22881,15 +22881,15 @@ target_compile_options(GENERIC_F103RGTX_serial_none INTERFACE ) add_library(GENERIC_F103RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103RGTX_usb_none INTERFACE) target_compile_options(GENERIC_F103RGTX_usb_none INTERFACE @@ -23089,15 +23089,15 @@ target_compile_options(GENERIC_F103T4UX_serial_none INTERFACE ) add_library(GENERIC_F103T4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103T4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103T4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103T4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103T4UX_usb_HID INTERFACE) target_compile_options(GENERIC_F103T4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103T4UX_usb_none INTERFACE) target_compile_options(GENERIC_F103T4UX_usb_none INTERFACE @@ -23297,15 +23297,15 @@ target_compile_options(GENERIC_F103T6UX_serial_none INTERFACE ) add_library(GENERIC_F103T6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103T6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103T6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103T6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103T6UX_usb_HID INTERFACE) target_compile_options(GENERIC_F103T6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103T6UX_usb_none INTERFACE) target_compile_options(GENERIC_F103T6UX_usb_none INTERFACE @@ -23505,15 +23505,15 @@ target_compile_options(GENERIC_F103T8UX_serial_none INTERFACE ) add_library(GENERIC_F103T8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103T8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103T8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103T8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103T8UX_usb_HID INTERFACE) target_compile_options(GENERIC_F103T8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103T8UX_usb_none INTERFACE) target_compile_options(GENERIC_F103T8UX_usb_none INTERFACE @@ -23713,15 +23713,15 @@ target_compile_options(GENERIC_F103TBUX_serial_none INTERFACE ) add_library(GENERIC_F103TBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103TBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103TBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103TBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103TBUX_usb_HID INTERFACE) target_compile_options(GENERIC_F103TBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103TBUX_usb_none INTERFACE) target_compile_options(GENERIC_F103TBUX_usb_none INTERFACE @@ -23921,15 +23921,15 @@ target_compile_options(GENERIC_F103V8HX_serial_none INTERFACE ) add_library(GENERIC_F103V8HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103V8HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103V8HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103V8HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103V8HX_usb_HID INTERFACE) target_compile_options(GENERIC_F103V8HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103V8HX_usb_none INTERFACE) target_compile_options(GENERIC_F103V8HX_usb_none INTERFACE @@ -24129,15 +24129,15 @@ target_compile_options(GENERIC_F103V8TX_serial_none INTERFACE ) add_library(GENERIC_F103V8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103V8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103V8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103V8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103V8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F103V8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103V8TX_usb_none INTERFACE) target_compile_options(GENERIC_F103V8TX_usb_none INTERFACE @@ -24337,15 +24337,15 @@ target_compile_options(GENERIC_F103VBHX_serial_none INTERFACE ) add_library(GENERIC_F103VBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VBHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VBHX_usb_none INTERFACE) target_compile_options(GENERIC_F103VBHX_usb_none INTERFACE @@ -24545,15 +24545,15 @@ target_compile_options(GENERIC_F103VBIX_serial_none INTERFACE ) add_library(GENERIC_F103VBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VBIX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VBIX_usb_none INTERFACE) target_compile_options(GENERIC_F103VBIX_usb_none INTERFACE @@ -24753,15 +24753,15 @@ target_compile_options(GENERIC_F103VBTX_serial_none INTERFACE ) add_library(GENERIC_F103VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F103VBTX_usb_none INTERFACE @@ -24961,15 +24961,15 @@ target_compile_options(GENERIC_F103VCHX_serial_none INTERFACE ) add_library(GENERIC_F103VCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VCHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VCHX_usb_none INTERFACE) target_compile_options(GENERIC_F103VCHX_usb_none INTERFACE @@ -25169,15 +25169,15 @@ target_compile_options(GENERIC_F103VCTX_serial_none INTERFACE ) add_library(GENERIC_F103VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F103VCTX_usb_none INTERFACE @@ -25377,15 +25377,15 @@ target_compile_options(GENERIC_F103VDHX_serial_none INTERFACE ) add_library(GENERIC_F103VDHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VDHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VDHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VDHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VDHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VDHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VDHX_usb_none INTERFACE) target_compile_options(GENERIC_F103VDHX_usb_none INTERFACE @@ -25585,15 +25585,15 @@ target_compile_options(GENERIC_F103VDTX_serial_none INTERFACE ) add_library(GENERIC_F103VDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VDTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VDTX_usb_none INTERFACE) target_compile_options(GENERIC_F103VDTX_usb_none INTERFACE @@ -25793,15 +25793,15 @@ target_compile_options(GENERIC_F103VEHX_serial_none INTERFACE ) add_library(GENERIC_F103VEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VEHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VEHX_usb_none INTERFACE) target_compile_options(GENERIC_F103VEHX_usb_none INTERFACE @@ -26001,15 +26001,15 @@ target_compile_options(GENERIC_F103VETX_serial_none INTERFACE ) add_library(GENERIC_F103VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VETX_usb_none INTERFACE) target_compile_options(GENERIC_F103VETX_usb_none INTERFACE @@ -26209,15 +26209,15 @@ target_compile_options(GENERIC_F103VFTX_serial_none INTERFACE ) add_library(GENERIC_F103VFTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VFTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VFTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VFTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VFTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VFTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VFTX_usb_none INTERFACE) target_compile_options(GENERIC_F103VFTX_usb_none INTERFACE @@ -26417,15 +26417,15 @@ target_compile_options(GENERIC_F103VGTX_serial_none INTERFACE ) add_library(GENERIC_F103VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103VGTX_usb_none INTERFACE) target_compile_options(GENERIC_F103VGTX_usb_none INTERFACE @@ -26625,15 +26625,15 @@ target_compile_options(GENERIC_F103ZCHX_serial_none INTERFACE ) add_library(GENERIC_F103ZCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZCHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZCHX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZCHX_usb_none INTERFACE @@ -26833,15 +26833,15 @@ target_compile_options(GENERIC_F103ZCTX_serial_none INTERFACE ) add_library(GENERIC_F103ZCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZCTX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZCTX_usb_none INTERFACE @@ -27041,15 +27041,15 @@ target_compile_options(GENERIC_F103ZDHX_serial_none INTERFACE ) add_library(GENERIC_F103ZDHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZDHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZDHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZDHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZDHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZDHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZDHX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZDHX_usb_none INTERFACE @@ -27249,15 +27249,15 @@ target_compile_options(GENERIC_F103ZDTX_serial_none INTERFACE ) add_library(GENERIC_F103ZDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZDTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZDTX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZDTX_usb_none INTERFACE @@ -27457,15 +27457,15 @@ target_compile_options(GENERIC_F103ZEHX_serial_none INTERFACE ) add_library(GENERIC_F103ZEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZEHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZEHX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZEHX_usb_none INTERFACE @@ -27665,15 +27665,15 @@ target_compile_options(GENERIC_F103ZETX_serial_none INTERFACE ) add_library(GENERIC_F103ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZETX_usb_none INTERFACE @@ -27873,15 +27873,15 @@ target_compile_options(GENERIC_F103ZFHX_serial_none INTERFACE ) add_library(GENERIC_F103ZFHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZFHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZFHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZFHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZFHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZFHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZFHX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZFHX_usb_none INTERFACE @@ -28081,15 +28081,15 @@ target_compile_options(GENERIC_F103ZFTX_serial_none INTERFACE ) add_library(GENERIC_F103ZFTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZFTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZFTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZFTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZFTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZFTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZFTX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZFTX_usb_none INTERFACE @@ -28289,15 +28289,15 @@ target_compile_options(GENERIC_F103ZGHX_serial_none INTERFACE ) add_library(GENERIC_F103ZGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZGHX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZGHX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZGHX_usb_none INTERFACE @@ -28497,15 +28497,15 @@ target_compile_options(GENERIC_F103ZGTX_serial_none INTERFACE ) add_library(GENERIC_F103ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F103ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F103ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F103ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F103ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F103ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F103ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F103ZGTX_usb_none INTERFACE @@ -28705,15 +28705,15 @@ target_compile_options(GENERIC_F205RBTX_serial_none INTERFACE ) add_library(GENERIC_F205RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F205RBTX_usb_none INTERFACE @@ -28787,15 +28787,15 @@ target_compile_options(GENERIC_F205RCTX_serial_none INTERFACE ) add_library(GENERIC_F205RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F205RCTX_usb_none INTERFACE @@ -28869,15 +28869,15 @@ target_compile_options(GENERIC_F205RETX_serial_none INTERFACE ) add_library(GENERIC_F205RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F205RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205RETX_usb_none INTERFACE) target_compile_options(GENERIC_F205RETX_usb_none INTERFACE @@ -28951,15 +28951,15 @@ target_compile_options(GENERIC_F205REYX_serial_none INTERFACE ) add_library(GENERIC_F205REYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205REYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205REYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205REYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205REYX_usb_HID INTERFACE) target_compile_options(GENERIC_F205REYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205REYX_usb_none INTERFACE) target_compile_options(GENERIC_F205REYX_usb_none INTERFACE @@ -29033,15 +29033,15 @@ target_compile_options(GENERIC_F205RFTX_serial_none INTERFACE ) add_library(GENERIC_F205RFTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205RFTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205RFTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205RFTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205RFTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205RFTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205RFTX_usb_none INTERFACE) target_compile_options(GENERIC_F205RFTX_usb_none INTERFACE @@ -29115,15 +29115,15 @@ target_compile_options(GENERIC_F205RGEX_serial_none INTERFACE ) add_library(GENERIC_F205RGEX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205RGEX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205RGEX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205RGEX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205RGEX_usb_HID INTERFACE) target_compile_options(GENERIC_F205RGEX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205RGEX_usb_none INTERFACE) target_compile_options(GENERIC_F205RGEX_usb_none INTERFACE @@ -29197,15 +29197,15 @@ target_compile_options(GENERIC_F205RGTX_serial_none INTERFACE ) add_library(GENERIC_F205RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205RGTX_usb_none INTERFACE) target_compile_options(GENERIC_F205RGTX_usb_none INTERFACE @@ -29279,15 +29279,15 @@ target_compile_options(GENERIC_F205RGYX_serial_none INTERFACE ) add_library(GENERIC_F205RGYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205RGYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205RGYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205RGYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205RGYX_usb_HID INTERFACE) target_compile_options(GENERIC_F205RGYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205RGYX_usb_none INTERFACE) target_compile_options(GENERIC_F205RGYX_usb_none INTERFACE @@ -29361,15 +29361,15 @@ target_compile_options(GENERIC_F205VBTX_serial_none INTERFACE ) add_library(GENERIC_F205VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F205VBTX_usb_none INTERFACE @@ -29443,15 +29443,15 @@ target_compile_options(GENERIC_F205VCTX_serial_none INTERFACE ) add_library(GENERIC_F205VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F205VCTX_usb_none INTERFACE @@ -29525,15 +29525,15 @@ target_compile_options(GENERIC_F205VETX_serial_none INTERFACE ) add_library(GENERIC_F205VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F205VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205VETX_usb_none INTERFACE) target_compile_options(GENERIC_F205VETX_usb_none INTERFACE @@ -29607,15 +29607,15 @@ target_compile_options(GENERIC_F205VFTX_serial_none INTERFACE ) add_library(GENERIC_F205VFTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205VFTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205VFTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205VFTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205VFTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205VFTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205VFTX_usb_none INTERFACE) target_compile_options(GENERIC_F205VFTX_usb_none INTERFACE @@ -29689,15 +29689,15 @@ target_compile_options(GENERIC_F205VGTX_serial_none INTERFACE ) add_library(GENERIC_F205VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205VGTX_usb_none INTERFACE) target_compile_options(GENERIC_F205VGTX_usb_none INTERFACE @@ -29771,15 +29771,15 @@ target_compile_options(GENERIC_F205ZCTX_serial_none INTERFACE ) add_library(GENERIC_F205ZCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205ZCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205ZCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205ZCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205ZCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205ZCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205ZCTX_usb_none INTERFACE) target_compile_options(GENERIC_F205ZCTX_usb_none INTERFACE @@ -29853,15 +29853,15 @@ target_compile_options(GENERIC_F205ZETX_serial_none INTERFACE ) add_library(GENERIC_F205ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F205ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F205ZETX_usb_none INTERFACE @@ -29935,15 +29935,15 @@ target_compile_options(GENERIC_F205ZFTX_serial_none INTERFACE ) add_library(GENERIC_F205ZFTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205ZFTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205ZFTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205ZFTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205ZFTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205ZFTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205ZFTX_usb_none INTERFACE) target_compile_options(GENERIC_F205ZFTX_usb_none INTERFACE @@ -30017,15 +30017,15 @@ target_compile_options(GENERIC_F205ZGTX_serial_none INTERFACE ) add_library(GENERIC_F205ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F205ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F205ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F205ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F205ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F205ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F205ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F205ZGTX_usb_none INTERFACE @@ -30099,15 +30099,15 @@ target_compile_options(GENERIC_F207ICHX_serial_none INTERFACE ) add_library(GENERIC_F207ICHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207ICHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207ICHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207ICHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207ICHX_usb_HID INTERFACE) target_compile_options(GENERIC_F207ICHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207ICHX_usb_none INTERFACE) target_compile_options(GENERIC_F207ICHX_usb_none INTERFACE @@ -30181,15 +30181,15 @@ target_compile_options(GENERIC_F207ICTX_serial_none INTERFACE ) add_library(GENERIC_F207ICTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207ICTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207ICTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207ICTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207ICTX_usb_HID INTERFACE) target_compile_options(GENERIC_F207ICTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207ICTX_usb_none INTERFACE) target_compile_options(GENERIC_F207ICTX_usb_none INTERFACE @@ -30263,15 +30263,15 @@ target_compile_options(GENERIC_F207IEHX_serial_none INTERFACE ) add_library(GENERIC_F207IEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207IEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207IEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207IEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207IEHX_usb_HID INTERFACE) target_compile_options(GENERIC_F207IEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207IEHX_usb_none INTERFACE) target_compile_options(GENERIC_F207IEHX_usb_none INTERFACE @@ -30345,15 +30345,15 @@ target_compile_options(GENERIC_F207IETX_serial_none INTERFACE ) add_library(GENERIC_F207IETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207IETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207IETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207IETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207IETX_usb_HID INTERFACE) target_compile_options(GENERIC_F207IETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207IETX_usb_none INTERFACE) target_compile_options(GENERIC_F207IETX_usb_none INTERFACE @@ -30427,15 +30427,15 @@ target_compile_options(GENERIC_F207IFHX_serial_none INTERFACE ) add_library(GENERIC_F207IFHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207IFHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207IFHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207IFHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207IFHX_usb_HID INTERFACE) target_compile_options(GENERIC_F207IFHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207IFHX_usb_none INTERFACE) target_compile_options(GENERIC_F207IFHX_usb_none INTERFACE @@ -30509,15 +30509,15 @@ target_compile_options(GENERIC_F207IFTX_serial_none INTERFACE ) add_library(GENERIC_F207IFTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207IFTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207IFTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207IFTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207IFTX_usb_HID INTERFACE) target_compile_options(GENERIC_F207IFTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207IFTX_usb_none INTERFACE) target_compile_options(GENERIC_F207IFTX_usb_none INTERFACE @@ -30591,15 +30591,15 @@ target_compile_options(GENERIC_F207IGHX_serial_none INTERFACE ) add_library(GENERIC_F207IGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207IGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207IGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207IGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207IGHX_usb_HID INTERFACE) target_compile_options(GENERIC_F207IGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207IGHX_usb_none INTERFACE) target_compile_options(GENERIC_F207IGHX_usb_none INTERFACE @@ -30673,15 +30673,15 @@ target_compile_options(GENERIC_F207IGTX_serial_none INTERFACE ) add_library(GENERIC_F207IGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207IGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207IGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207IGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207IGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F207IGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207IGTX_usb_none INTERFACE) target_compile_options(GENERIC_F207IGTX_usb_none INTERFACE @@ -30755,15 +30755,15 @@ target_compile_options(GENERIC_F207VCTX_serial_none INTERFACE ) add_library(GENERIC_F207VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F207VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F207VCTX_usb_none INTERFACE @@ -30837,15 +30837,15 @@ target_compile_options(GENERIC_F207VETX_serial_none INTERFACE ) add_library(GENERIC_F207VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F207VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207VETX_usb_none INTERFACE) target_compile_options(GENERIC_F207VETX_usb_none INTERFACE @@ -30919,15 +30919,15 @@ target_compile_options(GENERIC_F207VFTX_serial_none INTERFACE ) add_library(GENERIC_F207VFTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207VFTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207VFTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207VFTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207VFTX_usb_HID INTERFACE) target_compile_options(GENERIC_F207VFTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207VFTX_usb_none INTERFACE) target_compile_options(GENERIC_F207VFTX_usb_none INTERFACE @@ -31001,15 +31001,15 @@ target_compile_options(GENERIC_F207VGTX_serial_none INTERFACE ) add_library(GENERIC_F207VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F207VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207VGTX_usb_none INTERFACE) target_compile_options(GENERIC_F207VGTX_usb_none INTERFACE @@ -31083,15 +31083,15 @@ target_compile_options(GENERIC_F207ZCTX_serial_none INTERFACE ) add_library(GENERIC_F207ZCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207ZCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207ZCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207ZCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207ZCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F207ZCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207ZCTX_usb_none INTERFACE) target_compile_options(GENERIC_F207ZCTX_usb_none INTERFACE @@ -31165,15 +31165,15 @@ target_compile_options(GENERIC_F207ZETX_serial_none INTERFACE ) add_library(GENERIC_F207ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F207ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F207ZETX_usb_none INTERFACE @@ -31247,15 +31247,15 @@ target_compile_options(GENERIC_F207ZFTX_serial_none INTERFACE ) add_library(GENERIC_F207ZFTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207ZFTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207ZFTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207ZFTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207ZFTX_usb_HID INTERFACE) target_compile_options(GENERIC_F207ZFTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207ZFTX_usb_none INTERFACE) target_compile_options(GENERIC_F207ZFTX_usb_none INTERFACE @@ -31329,15 +31329,15 @@ target_compile_options(GENERIC_F207ZGTX_serial_none INTERFACE ) add_library(GENERIC_F207ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F207ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F207ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F207ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F207ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F207ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F207ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F207ZGTX_usb_none INTERFACE @@ -31411,15 +31411,15 @@ target_compile_options(GENERIC_F215RETX_serial_none INTERFACE ) add_library(GENERIC_F215RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F215RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F215RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F215RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F215RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F215RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F215RETX_usb_none INTERFACE) target_compile_options(GENERIC_F215RETX_usb_none INTERFACE @@ -31493,15 +31493,15 @@ target_compile_options(GENERIC_F215RGTX_serial_none INTERFACE ) add_library(GENERIC_F215RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F215RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F215RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F215RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F215RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F215RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F215RGTX_usb_none INTERFACE) target_compile_options(GENERIC_F215RGTX_usb_none INTERFACE @@ -31575,15 +31575,15 @@ target_compile_options(GENERIC_F215VETX_serial_none INTERFACE ) add_library(GENERIC_F215VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F215VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F215VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F215VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F215VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F215VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F215VETX_usb_none INTERFACE) target_compile_options(GENERIC_F215VETX_usb_none INTERFACE @@ -31657,15 +31657,15 @@ target_compile_options(GENERIC_F215VGTX_serial_none INTERFACE ) add_library(GENERIC_F215VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F215VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F215VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F215VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F215VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F215VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F215VGTX_usb_none INTERFACE) target_compile_options(GENERIC_F215VGTX_usb_none INTERFACE @@ -31739,15 +31739,15 @@ target_compile_options(GENERIC_F215ZETX_serial_none INTERFACE ) add_library(GENERIC_F215ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F215ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F215ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F215ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F215ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F215ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F215ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F215ZETX_usb_none INTERFACE @@ -31821,15 +31821,15 @@ target_compile_options(GENERIC_F215ZGTX_serial_none INTERFACE ) add_library(GENERIC_F215ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F215ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F215ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F215ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F215ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F215ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F215ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F215ZGTX_usb_none INTERFACE @@ -31903,15 +31903,15 @@ target_compile_options(GENERIC_F217IEHX_serial_none INTERFACE ) add_library(GENERIC_F217IEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F217IEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F217IEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F217IEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F217IEHX_usb_HID INTERFACE) target_compile_options(GENERIC_F217IEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F217IEHX_usb_none INTERFACE) target_compile_options(GENERIC_F217IEHX_usb_none INTERFACE @@ -31985,15 +31985,15 @@ target_compile_options(GENERIC_F217IETX_serial_none INTERFACE ) add_library(GENERIC_F217IETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F217IETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F217IETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F217IETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F217IETX_usb_HID INTERFACE) target_compile_options(GENERIC_F217IETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F217IETX_usb_none INTERFACE) target_compile_options(GENERIC_F217IETX_usb_none INTERFACE @@ -32067,15 +32067,15 @@ target_compile_options(GENERIC_F217IGHX_serial_none INTERFACE ) add_library(GENERIC_F217IGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F217IGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F217IGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F217IGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F217IGHX_usb_HID INTERFACE) target_compile_options(GENERIC_F217IGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F217IGHX_usb_none INTERFACE) target_compile_options(GENERIC_F217IGHX_usb_none INTERFACE @@ -32149,15 +32149,15 @@ target_compile_options(GENERIC_F217IGTX_serial_none INTERFACE ) add_library(GENERIC_F217IGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F217IGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F217IGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F217IGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F217IGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F217IGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F217IGTX_usb_none INTERFACE) target_compile_options(GENERIC_F217IGTX_usb_none INTERFACE @@ -32231,15 +32231,15 @@ target_compile_options(GENERIC_F217VETX_serial_none INTERFACE ) add_library(GENERIC_F217VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F217VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F217VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F217VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F217VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F217VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F217VETX_usb_none INTERFACE) target_compile_options(GENERIC_F217VETX_usb_none INTERFACE @@ -32313,15 +32313,15 @@ target_compile_options(GENERIC_F217VGTX_serial_none INTERFACE ) add_library(GENERIC_F217VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F217VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F217VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F217VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F217VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F217VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F217VGTX_usb_none INTERFACE) target_compile_options(GENERIC_F217VGTX_usb_none INTERFACE @@ -32395,15 +32395,15 @@ target_compile_options(GENERIC_F217ZETX_serial_none INTERFACE ) add_library(GENERIC_F217ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F217ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F217ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F217ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F217ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F217ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F217ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F217ZETX_usb_none INTERFACE @@ -32477,15 +32477,15 @@ target_compile_options(GENERIC_F217ZGTX_serial_none INTERFACE ) add_library(GENERIC_F217ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F217ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F217ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F217ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F217ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F217ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F217ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F217ZGTX_usb_none INTERFACE @@ -32559,15 +32559,15 @@ target_compile_options(GENERIC_F301C6TX_serial_none INTERFACE ) add_library(GENERIC_F301C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F301C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F301C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F301C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F301C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F301C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F301C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F301C6TX_usb_none INTERFACE @@ -32641,15 +32641,15 @@ target_compile_options(GENERIC_F301C8TX_serial_none INTERFACE ) add_library(GENERIC_F301C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F301C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F301C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F301C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F301C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F301C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F301C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F301C8TX_usb_none INTERFACE @@ -32723,15 +32723,15 @@ target_compile_options(GENERIC_F301C8YX_serial_none INTERFACE ) add_library(GENERIC_F301C8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_F301C8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F301C8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F301C8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F301C8YX_usb_HID INTERFACE) target_compile_options(GENERIC_F301C8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F301C8YX_usb_none INTERFACE) target_compile_options(GENERIC_F301C8YX_usb_none INTERFACE @@ -32805,15 +32805,15 @@ target_compile_options(GENERIC_F301K6TX_serial_none INTERFACE ) add_library(GENERIC_F301K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F301K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F301K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F301K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F301K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F301K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F301K6TX_usb_none INTERFACE) target_compile_options(GENERIC_F301K6TX_usb_none INTERFACE @@ -32887,15 +32887,15 @@ target_compile_options(GENERIC_F301K8TX_serial_none INTERFACE ) add_library(GENERIC_F301K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F301K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F301K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F301K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F301K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F301K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F301K8TX_usb_none INTERFACE) target_compile_options(GENERIC_F301K8TX_usb_none INTERFACE @@ -32969,15 +32969,15 @@ target_compile_options(GENERIC_F301R6TX_serial_none INTERFACE ) add_library(GENERIC_F301R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F301R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F301R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F301R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F301R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F301R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F301R6TX_usb_none INTERFACE) target_compile_options(GENERIC_F301R6TX_usb_none INTERFACE @@ -33051,15 +33051,15 @@ target_compile_options(GENERIC_F301R8TX_serial_none INTERFACE ) add_library(GENERIC_F301R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F301R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F301R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F301R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F301R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F301R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F301R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F301R8TX_usb_none INTERFACE @@ -33133,15 +33133,15 @@ target_compile_options(GENERIC_F302R6TX_serial_none INTERFACE ) add_library(GENERIC_F302R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F302R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F302R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F302R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F302R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F302R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F302R6TX_usb_none INTERFACE) target_compile_options(GENERIC_F302R6TX_usb_none INTERFACE @@ -33215,15 +33215,15 @@ target_compile_options(GENERIC_F302R8TX_serial_none INTERFACE ) add_library(GENERIC_F302R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F302R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F302R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F302R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F302R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F302R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F302R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F302R8TX_usb_none INTERFACE @@ -33297,15 +33297,15 @@ target_compile_options(GENERIC_F303C6TX_serial_none INTERFACE ) add_library(GENERIC_F303C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F303C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F303C6TX_usb_none INTERFACE @@ -33379,15 +33379,15 @@ target_compile_options(GENERIC_F303C8TX_serial_none INTERFACE ) add_library(GENERIC_F303C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F303C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F303C8TX_usb_none INTERFACE @@ -33461,15 +33461,15 @@ target_compile_options(GENERIC_F303CBTX_serial_none INTERFACE ) add_library(GENERIC_F303CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F303CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303CBTX_usb_none INTERFACE) target_compile_options(GENERIC_F303CBTX_usb_none INTERFACE @@ -33543,15 +33543,15 @@ target_compile_options(GENERIC_F303CCTX_serial_none INTERFACE ) add_library(GENERIC_F303CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F303CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303CCTX_usb_none INTERFACE) target_compile_options(GENERIC_F303CCTX_usb_none INTERFACE @@ -33625,15 +33625,15 @@ target_compile_options(GENERIC_F303K6TX_serial_none INTERFACE ) add_library(GENERIC_F303K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F303K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303K6TX_usb_none INTERFACE) target_compile_options(GENERIC_F303K6TX_usb_none INTERFACE @@ -33707,15 +33707,15 @@ target_compile_options(GENERIC_F303K8TX_serial_none INTERFACE ) add_library(GENERIC_F303K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F303K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303K8TX_usb_none INTERFACE) target_compile_options(GENERIC_F303K8TX_usb_none INTERFACE @@ -33789,15 +33789,15 @@ target_compile_options(GENERIC_F303R6TX_serial_none INTERFACE ) add_library(GENERIC_F303R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F303R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303R6TX_usb_none INTERFACE) target_compile_options(GENERIC_F303R6TX_usb_none INTERFACE @@ -33871,15 +33871,15 @@ target_compile_options(GENERIC_F303R8TX_serial_none INTERFACE ) add_library(GENERIC_F303R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F303R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F303R8TX_usb_none INTERFACE @@ -33953,15 +33953,15 @@ target_compile_options(GENERIC_F303RBTX_serial_none INTERFACE ) add_library(GENERIC_F303RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F303RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F303RBTX_usb_none INTERFACE @@ -34035,15 +34035,15 @@ target_compile_options(GENERIC_F303RCTX_serial_none INTERFACE ) add_library(GENERIC_F303RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F303RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F303RCTX_usb_none INTERFACE @@ -34117,15 +34117,15 @@ target_compile_options(GENERIC_F303RDTX_serial_none INTERFACE ) add_library(GENERIC_F303RDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303RDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303RDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303RDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303RDTX_usb_HID INTERFACE) target_compile_options(GENERIC_F303RDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303RDTX_usb_none INTERFACE) target_compile_options(GENERIC_F303RDTX_usb_none INTERFACE @@ -34199,15 +34199,15 @@ target_compile_options(GENERIC_F303RETX_serial_none INTERFACE ) add_library(GENERIC_F303RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F303RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303RETX_usb_none INTERFACE) target_compile_options(GENERIC_F303RETX_usb_none INTERFACE @@ -34281,15 +34281,15 @@ target_compile_options(GENERIC_F303VBTX_serial_none INTERFACE ) add_library(GENERIC_F303VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F303VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F303VBTX_usb_none INTERFACE @@ -34363,15 +34363,15 @@ target_compile_options(GENERIC_F303VCTX_serial_none INTERFACE ) add_library(GENERIC_F303VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F303VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F303VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F303VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F303VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F303VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F303VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F303VCTX_usb_none INTERFACE @@ -34445,15 +34445,15 @@ target_compile_options(GENERIC_F318C8TX_serial_none INTERFACE ) add_library(GENERIC_F318C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F318C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F318C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F318C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F318C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F318C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F318C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F318C8TX_usb_none INTERFACE @@ -34527,15 +34527,15 @@ target_compile_options(GENERIC_F318C8YX_serial_none INTERFACE ) add_library(GENERIC_F318C8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_F318C8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F318C8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F318C8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F318C8YX_usb_HID INTERFACE) target_compile_options(GENERIC_F318C8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F318C8YX_usb_none INTERFACE) target_compile_options(GENERIC_F318C8YX_usb_none INTERFACE @@ -34609,15 +34609,15 @@ target_compile_options(GENERIC_F318K8UX_serial_none INTERFACE ) add_library(GENERIC_F318K8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F318K8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F318K8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F318K8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F318K8UX_usb_HID INTERFACE) target_compile_options(GENERIC_F318K8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F318K8UX_usb_none INTERFACE) target_compile_options(GENERIC_F318K8UX_usb_none INTERFACE @@ -34691,15 +34691,15 @@ target_compile_options(GENERIC_F328C8TX_serial_none INTERFACE ) add_library(GENERIC_F328C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F328C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F328C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F328C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F328C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F328C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F328C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F328C8TX_usb_none INTERFACE @@ -34773,15 +34773,15 @@ target_compile_options(GENERIC_F334C4TX_serial_none INTERFACE ) add_library(GENERIC_F334C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F334C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F334C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F334C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F334C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F334C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F334C4TX_usb_none INTERFACE) target_compile_options(GENERIC_F334C4TX_usb_none INTERFACE @@ -34855,15 +34855,15 @@ target_compile_options(GENERIC_F334C6TX_serial_none INTERFACE ) add_library(GENERIC_F334C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F334C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F334C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F334C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F334C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F334C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F334C6TX_usb_none INTERFACE) target_compile_options(GENERIC_F334C6TX_usb_none INTERFACE @@ -34937,15 +34937,15 @@ target_compile_options(GENERIC_F334C8TX_serial_none INTERFACE ) add_library(GENERIC_F334C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F334C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F334C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F334C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F334C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F334C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F334C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F334C8TX_usb_none INTERFACE @@ -35019,15 +35019,15 @@ target_compile_options(GENERIC_F334K4TX_serial_none INTERFACE ) add_library(GENERIC_F334K4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F334K4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F334K4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F334K4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F334K4TX_usb_HID INTERFACE) target_compile_options(GENERIC_F334K4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F334K4TX_usb_none INTERFACE) target_compile_options(GENERIC_F334K4TX_usb_none INTERFACE @@ -35101,15 +35101,15 @@ target_compile_options(GENERIC_F334K6TX_serial_none INTERFACE ) add_library(GENERIC_F334K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F334K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F334K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F334K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F334K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F334K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F334K6TX_usb_none INTERFACE) target_compile_options(GENERIC_F334K6TX_usb_none INTERFACE @@ -35183,15 +35183,15 @@ target_compile_options(GENERIC_F334K8TX_serial_none INTERFACE ) add_library(GENERIC_F334K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F334K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F334K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F334K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F334K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F334K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F334K8TX_usb_none INTERFACE) target_compile_options(GENERIC_F334K8TX_usb_none INTERFACE @@ -35265,15 +35265,15 @@ target_compile_options(GENERIC_F334R6TX_serial_none INTERFACE ) add_library(GENERIC_F334R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F334R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F334R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F334R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F334R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_F334R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F334R6TX_usb_none INTERFACE) target_compile_options(GENERIC_F334R6TX_usb_none INTERFACE @@ -35347,15 +35347,15 @@ target_compile_options(GENERIC_F334R8TX_serial_none INTERFACE ) add_library(GENERIC_F334R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F334R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F334R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F334R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F334R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F334R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F334R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F334R8TX_usb_none INTERFACE @@ -35429,15 +35429,15 @@ target_compile_options(GENERIC_F358CCTX_serial_none INTERFACE ) add_library(GENERIC_F358CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F358CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F358CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F358CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F358CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F358CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F358CCTX_usb_none INTERFACE) target_compile_options(GENERIC_F358CCTX_usb_none INTERFACE @@ -35511,15 +35511,15 @@ target_compile_options(GENERIC_F358RCTX_serial_none INTERFACE ) add_library(GENERIC_F358RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F358RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F358RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F358RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F358RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F358RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F358RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F358RCTX_usb_none INTERFACE @@ -35593,15 +35593,15 @@ target_compile_options(GENERIC_F358VCTX_serial_none INTERFACE ) add_library(GENERIC_F358VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F358VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F358VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F358VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F358VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F358VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F358VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F358VCTX_usb_none INTERFACE @@ -35675,15 +35675,15 @@ target_compile_options(GENERIC_F378CCTX_serial_none INTERFACE ) add_library(GENERIC_F378CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F378CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F378CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F378CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F378CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F378CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F378CCTX_usb_none INTERFACE) target_compile_options(GENERIC_F378CCTX_usb_none INTERFACE @@ -35757,15 +35757,15 @@ target_compile_options(GENERIC_F378RCTX_serial_none INTERFACE ) add_library(GENERIC_F378RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F378RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F378RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F378RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F378RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F378RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F378RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F378RCTX_usb_none INTERFACE @@ -35839,15 +35839,15 @@ target_compile_options(GENERIC_F378RCYX_serial_none INTERFACE ) add_library(GENERIC_F378RCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F378RCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F378RCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F378RCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F378RCYX_usb_HID INTERFACE) target_compile_options(GENERIC_F378RCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F378RCYX_usb_none INTERFACE) target_compile_options(GENERIC_F378RCYX_usb_none INTERFACE @@ -35921,15 +35921,15 @@ target_compile_options(GENERIC_F378VCHX_serial_none INTERFACE ) add_library(GENERIC_F378VCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F378VCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F378VCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F378VCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F378VCHX_usb_HID INTERFACE) target_compile_options(GENERIC_F378VCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F378VCHX_usb_none INTERFACE) target_compile_options(GENERIC_F378VCHX_usb_none INTERFACE @@ -36003,15 +36003,15 @@ target_compile_options(GENERIC_F378VCTX_serial_none INTERFACE ) add_library(GENERIC_F378VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F378VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F378VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F378VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F378VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F378VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F378VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F378VCTX_usb_none INTERFACE @@ -36085,15 +36085,15 @@ target_compile_options(GENERIC_F398VETX_serial_none INTERFACE ) add_library(GENERIC_F398VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F398VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F398VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F398VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F398VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F398VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F398VETX_usb_none INTERFACE) target_compile_options(GENERIC_F398VETX_usb_none INTERFACE @@ -36167,15 +36167,15 @@ target_compile_options(GENERIC_F401CBUX_serial_none INTERFACE ) add_library(GENERIC_F401CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_F401CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401CBUX_usb_none INTERFACE) target_compile_options(GENERIC_F401CBUX_usb_none INTERFACE @@ -36291,15 +36291,15 @@ target_compile_options(GENERIC_F401CBYX_serial_none INTERFACE ) add_library(GENERIC_F401CBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401CBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401CBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401CBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401CBYX_usb_HID INTERFACE) target_compile_options(GENERIC_F401CBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401CBYX_usb_none INTERFACE) target_compile_options(GENERIC_F401CBYX_usb_none INTERFACE @@ -36415,15 +36415,15 @@ target_compile_options(GENERIC_F401CCFX_serial_none INTERFACE ) add_library(GENERIC_F401CCFX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401CCFX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401CCFX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401CCFX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401CCFX_usb_HID INTERFACE) target_compile_options(GENERIC_F401CCFX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401CCFX_usb_none INTERFACE) target_compile_options(GENERIC_F401CCFX_usb_none INTERFACE @@ -36539,15 +36539,15 @@ target_compile_options(GENERIC_F401CCUX_serial_none INTERFACE ) add_library(GENERIC_F401CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_F401CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401CCUX_usb_none INTERFACE) target_compile_options(GENERIC_F401CCUX_usb_none INTERFACE @@ -36663,15 +36663,15 @@ target_compile_options(GENERIC_F401CCYX_serial_none INTERFACE ) add_library(GENERIC_F401CCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401CCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401CCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401CCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401CCYX_usb_HID INTERFACE) target_compile_options(GENERIC_F401CCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401CCYX_usb_none INTERFACE) target_compile_options(GENERIC_F401CCYX_usb_none INTERFACE @@ -36787,15 +36787,15 @@ target_compile_options(GENERIC_F401CDUX_serial_none INTERFACE ) add_library(GENERIC_F401CDUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401CDUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401CDUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401CDUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401CDUX_usb_HID INTERFACE) target_compile_options(GENERIC_F401CDUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401CDUX_usb_none INTERFACE) target_compile_options(GENERIC_F401CDUX_usb_none INTERFACE @@ -36911,15 +36911,15 @@ target_compile_options(GENERIC_F401CDYX_serial_none INTERFACE ) add_library(GENERIC_F401CDYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401CDYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401CDYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401CDYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401CDYX_usb_HID INTERFACE) target_compile_options(GENERIC_F401CDYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401CDYX_usb_none INTERFACE) target_compile_options(GENERIC_F401CDYX_usb_none INTERFACE @@ -37035,15 +37035,15 @@ target_compile_options(GENERIC_F401CEUX_serial_none INTERFACE ) add_library(GENERIC_F401CEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401CEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401CEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401CEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401CEUX_usb_HID INTERFACE) target_compile_options(GENERIC_F401CEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401CEUX_usb_none INTERFACE) target_compile_options(GENERIC_F401CEUX_usb_none INTERFACE @@ -37159,15 +37159,15 @@ target_compile_options(GENERIC_F401CEYX_serial_none INTERFACE ) add_library(GENERIC_F401CEYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401CEYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401CEYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401CEYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401CEYX_usb_HID INTERFACE) target_compile_options(GENERIC_F401CEYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401CEYX_usb_none INTERFACE) target_compile_options(GENERIC_F401CEYX_usb_none INTERFACE @@ -37283,15 +37283,15 @@ target_compile_options(GENERIC_F401RBTX_serial_none INTERFACE ) add_library(GENERIC_F401RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F401RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F401RBTX_usb_none INTERFACE @@ -37407,15 +37407,15 @@ target_compile_options(GENERIC_F401RCTX_serial_none INTERFACE ) add_library(GENERIC_F401RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F401RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F401RCTX_usb_none INTERFACE @@ -37531,15 +37531,15 @@ target_compile_options(GENERIC_F401RDTX_serial_none INTERFACE ) add_library(GENERIC_F401RDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401RDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401RDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401RDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401RDTX_usb_HID INTERFACE) target_compile_options(GENERIC_F401RDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401RDTX_usb_none INTERFACE) target_compile_options(GENERIC_F401RDTX_usb_none INTERFACE @@ -37655,15 +37655,15 @@ target_compile_options(GENERIC_F401RETX_serial_none INTERFACE ) add_library(GENERIC_F401RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F401RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401RETX_usb_none INTERFACE) target_compile_options(GENERIC_F401RETX_usb_none INTERFACE @@ -37779,15 +37779,15 @@ target_compile_options(GENERIC_F401VBTX_serial_none INTERFACE ) add_library(GENERIC_F401VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F401VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401VBTX_usb_none INTERFACE) target_compile_options(GENERIC_F401VBTX_usb_none INTERFACE @@ -37903,15 +37903,15 @@ target_compile_options(GENERIC_F401VCTX_serial_none INTERFACE ) add_library(GENERIC_F401VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F401VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F401VCTX_usb_none INTERFACE @@ -38027,15 +38027,15 @@ target_compile_options(GENERIC_F401VDTX_serial_none INTERFACE ) add_library(GENERIC_F401VDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401VDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401VDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401VDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401VDTX_usb_HID INTERFACE) target_compile_options(GENERIC_F401VDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401VDTX_usb_none INTERFACE) target_compile_options(GENERIC_F401VDTX_usb_none INTERFACE @@ -38151,15 +38151,15 @@ target_compile_options(GENERIC_F401VETX_serial_none INTERFACE ) add_library(GENERIC_F401VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F401VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F401VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F401VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F401VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F401VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F401VETX_usb_none INTERFACE) target_compile_options(GENERIC_F401VETX_usb_none INTERFACE @@ -38275,15 +38275,15 @@ target_compile_options(GENERIC_F405RGTX_serial_none INTERFACE ) add_library(GENERIC_F405RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F405RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F405RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F405RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F405RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F405RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F405RGTX_usb_none INTERFACE) target_compile_options(GENERIC_F405RGTX_usb_none INTERFACE @@ -38399,15 +38399,15 @@ target_compile_options(GENERIC_F407VETX_serial_none INTERFACE ) add_library(GENERIC_F407VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F407VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F407VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F407VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F407VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F407VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F407VETX_usb_none INTERFACE) target_compile_options(GENERIC_F407VETX_usb_none INTERFACE @@ -38523,15 +38523,15 @@ target_compile_options(GENERIC_F407VGTX_serial_none INTERFACE ) add_library(GENERIC_F407VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F407VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F407VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F407VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F407VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F407VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F407VGTX_usb_none INTERFACE) target_compile_options(GENERIC_F407VGTX_usb_none INTERFACE @@ -38647,15 +38647,15 @@ target_compile_options(GENERIC_F407ZETX_serial_none INTERFACE ) add_library(GENERIC_F407ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F407ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F407ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F407ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F407ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F407ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F407ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F407ZETX_usb_none INTERFACE @@ -38771,15 +38771,15 @@ target_compile_options(GENERIC_F407ZGTX_serial_none INTERFACE ) add_library(GENERIC_F407ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F407ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F407ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F407ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F407ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F407ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F407ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F407ZGTX_usb_none INTERFACE @@ -38895,15 +38895,15 @@ target_compile_options(GENERIC_F410C8TX_serial_none INTERFACE ) add_library(GENERIC_F410C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F410C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410C8TX_usb_none INTERFACE) target_compile_options(GENERIC_F410C8TX_usb_none INTERFACE @@ -39019,15 +39019,15 @@ target_compile_options(GENERIC_F410C8UX_serial_none INTERFACE ) add_library(GENERIC_F410C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_F410C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410C8UX_usb_none INTERFACE) target_compile_options(GENERIC_F410C8UX_usb_none INTERFACE @@ -39143,15 +39143,15 @@ target_compile_options(GENERIC_F410CBTX_serial_none INTERFACE ) add_library(GENERIC_F410CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F410CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410CBTX_usb_none INTERFACE) target_compile_options(GENERIC_F410CBTX_usb_none INTERFACE @@ -39267,15 +39267,15 @@ target_compile_options(GENERIC_F410CBUX_serial_none INTERFACE ) add_library(GENERIC_F410CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_F410CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410CBUX_usb_none INTERFACE) target_compile_options(GENERIC_F410CBUX_usb_none INTERFACE @@ -39391,15 +39391,15 @@ target_compile_options(GENERIC_F410R8IX_serial_none INTERFACE ) add_library(GENERIC_F410R8IX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410R8IX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410R8IX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410R8IX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410R8IX_usb_HID INTERFACE) target_compile_options(GENERIC_F410R8IX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410R8IX_usb_none INTERFACE) target_compile_options(GENERIC_F410R8IX_usb_none INTERFACE @@ -39515,15 +39515,15 @@ target_compile_options(GENERIC_F410R8TX_serial_none INTERFACE ) add_library(GENERIC_F410R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F410R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F410R8TX_usb_none INTERFACE @@ -39639,15 +39639,15 @@ target_compile_options(GENERIC_F410RBIX_serial_none INTERFACE ) add_library(GENERIC_F410RBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410RBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410RBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410RBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410RBIX_usb_HID INTERFACE) target_compile_options(GENERIC_F410RBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410RBIX_usb_none INTERFACE) target_compile_options(GENERIC_F410RBIX_usb_none INTERFACE @@ -39763,15 +39763,15 @@ target_compile_options(GENERIC_F410RBTX_serial_none INTERFACE ) add_library(GENERIC_F410RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_F410RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410RBTX_usb_none INTERFACE) target_compile_options(GENERIC_F410RBTX_usb_none INTERFACE @@ -39887,15 +39887,15 @@ target_compile_options(GENERIC_F410T8YX_serial_none INTERFACE ) add_library(GENERIC_F410T8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410T8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410T8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410T8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410T8YX_usb_HID INTERFACE) target_compile_options(GENERIC_F410T8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410T8YX_usb_none INTERFACE) target_compile_options(GENERIC_F410T8YX_usb_none INTERFACE @@ -40011,15 +40011,15 @@ target_compile_options(GENERIC_F410TBYX_serial_none INTERFACE ) add_library(GENERIC_F410TBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F410TBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F410TBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F410TBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F410TBYX_usb_HID INTERFACE) target_compile_options(GENERIC_F410TBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F410TBYX_usb_none INTERFACE) target_compile_options(GENERIC_F410TBYX_usb_none INTERFACE @@ -40135,15 +40135,15 @@ target_compile_options(GENERIC_F411CCUX_serial_none INTERFACE ) add_library(GENERIC_F411CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F411CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F411CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F411CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F411CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_F411CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F411CCUX_usb_none INTERFACE) target_compile_options(GENERIC_F411CCUX_usb_none INTERFACE @@ -40259,15 +40259,15 @@ target_compile_options(GENERIC_F411CCYX_serial_none INTERFACE ) add_library(GENERIC_F411CCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F411CCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F411CCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F411CCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F411CCYX_usb_HID INTERFACE) target_compile_options(GENERIC_F411CCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F411CCYX_usb_none INTERFACE) target_compile_options(GENERIC_F411CCYX_usb_none INTERFACE @@ -40383,15 +40383,15 @@ target_compile_options(GENERIC_F411CEUX_serial_none INTERFACE ) add_library(GENERIC_F411CEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F411CEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F411CEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F411CEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F411CEUX_usb_HID INTERFACE) target_compile_options(GENERIC_F411CEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F411CEUX_usb_none INTERFACE) target_compile_options(GENERIC_F411CEUX_usb_none INTERFACE @@ -40507,15 +40507,15 @@ target_compile_options(GENERIC_F411CEYX_serial_none INTERFACE ) add_library(GENERIC_F411CEYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F411CEYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F411CEYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F411CEYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F411CEYX_usb_HID INTERFACE) target_compile_options(GENERIC_F411CEYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F411CEYX_usb_none INTERFACE) target_compile_options(GENERIC_F411CEYX_usb_none INTERFACE @@ -40631,15 +40631,15 @@ target_compile_options(GENERIC_F411RCTX_serial_none INTERFACE ) add_library(GENERIC_F411RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F411RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F411RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F411RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F411RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F411RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F411RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F411RCTX_usb_none INTERFACE @@ -40755,15 +40755,15 @@ target_compile_options(GENERIC_F411RETX_serial_none INTERFACE ) add_library(GENERIC_F411RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F411RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F411RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F411RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F411RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F411RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F411RETX_usb_none INTERFACE) target_compile_options(GENERIC_F411RETX_usb_none INTERFACE @@ -40879,15 +40879,15 @@ target_compile_options(GENERIC_F412CEUX_serial_none INTERFACE ) add_library(GENERIC_F412CEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412CEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412CEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412CEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412CEUX_usb_HID INTERFACE) target_compile_options(GENERIC_F412CEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412CEUX_usb_none INTERFACE) target_compile_options(GENERIC_F412CEUX_usb_none INTERFACE @@ -41003,15 +41003,15 @@ target_compile_options(GENERIC_F412CGUX_serial_none INTERFACE ) add_library(GENERIC_F412CGUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412CGUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412CGUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412CGUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412CGUX_usb_HID INTERFACE) target_compile_options(GENERIC_F412CGUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412CGUX_usb_none INTERFACE) target_compile_options(GENERIC_F412CGUX_usb_none INTERFACE @@ -41127,15 +41127,15 @@ target_compile_options(GENERIC_F412RETX_serial_none INTERFACE ) add_library(GENERIC_F412RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F412RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412RETX_usb_none INTERFACE) target_compile_options(GENERIC_F412RETX_usb_none INTERFACE @@ -41251,15 +41251,15 @@ target_compile_options(GENERIC_F412REYX_serial_none INTERFACE ) add_library(GENERIC_F412REYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412REYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412REYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412REYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412REYX_usb_HID INTERFACE) target_compile_options(GENERIC_F412REYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412REYX_usb_none INTERFACE) target_compile_options(GENERIC_F412REYX_usb_none INTERFACE @@ -41375,15 +41375,15 @@ target_compile_options(GENERIC_F412REYXP_serial_none INTERFACE ) add_library(GENERIC_F412REYXP_usb_CDC INTERFACE) target_compile_options(GENERIC_F412REYXP_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412REYXP_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412REYXP_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412REYXP_usb_HID INTERFACE) target_compile_options(GENERIC_F412REYXP_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412REYXP_usb_none INTERFACE) target_compile_options(GENERIC_F412REYXP_usb_none INTERFACE @@ -41499,15 +41499,15 @@ target_compile_options(GENERIC_F412RGTX_serial_none INTERFACE ) add_library(GENERIC_F412RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F412RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412RGTX_usb_none INTERFACE) target_compile_options(GENERIC_F412RGTX_usb_none INTERFACE @@ -41623,15 +41623,15 @@ target_compile_options(GENERIC_F412RGYX_serial_none INTERFACE ) add_library(GENERIC_F412RGYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412RGYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412RGYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412RGYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412RGYX_usb_HID INTERFACE) target_compile_options(GENERIC_F412RGYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412RGYX_usb_none INTERFACE) target_compile_options(GENERIC_F412RGYX_usb_none INTERFACE @@ -41747,15 +41747,15 @@ target_compile_options(GENERIC_F412RGYXP_serial_none INTERFACE ) add_library(GENERIC_F412RGYXP_usb_CDC INTERFACE) target_compile_options(GENERIC_F412RGYXP_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412RGYXP_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412RGYXP_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412RGYXP_usb_HID INTERFACE) target_compile_options(GENERIC_F412RGYXP_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412RGYXP_usb_none INTERFACE) target_compile_options(GENERIC_F412RGYXP_usb_none INTERFACE @@ -41871,15 +41871,15 @@ target_compile_options(GENERIC_F412ZEJX_serial_none INTERFACE ) add_library(GENERIC_F412ZEJX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412ZEJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412ZEJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412ZEJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412ZEJX_usb_HID INTERFACE) target_compile_options(GENERIC_F412ZEJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412ZEJX_usb_none INTERFACE) target_compile_options(GENERIC_F412ZEJX_usb_none INTERFACE @@ -41995,15 +41995,15 @@ target_compile_options(GENERIC_F412ZETX_serial_none INTERFACE ) add_library(GENERIC_F412ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F412ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F412ZETX_usb_none INTERFACE @@ -42119,15 +42119,15 @@ target_compile_options(GENERIC_F412ZGJX_serial_none INTERFACE ) add_library(GENERIC_F412ZGJX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412ZGJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412ZGJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412ZGJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412ZGJX_usb_HID INTERFACE) target_compile_options(GENERIC_F412ZGJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412ZGJX_usb_none INTERFACE) target_compile_options(GENERIC_F412ZGJX_usb_none INTERFACE @@ -42243,15 +42243,15 @@ target_compile_options(GENERIC_F412ZGTX_serial_none INTERFACE ) add_library(GENERIC_F412ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F412ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F412ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F412ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F412ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F412ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F412ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F412ZGTX_usb_none INTERFACE @@ -42367,15 +42367,15 @@ target_compile_options(GENERIC_F413CGUX_serial_none INTERFACE ) add_library(GENERIC_F413CGUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F413CGUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F413CGUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F413CGUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F413CGUX_usb_HID INTERFACE) target_compile_options(GENERIC_F413CGUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F413CGUX_usb_none INTERFACE) target_compile_options(GENERIC_F413CGUX_usb_none INTERFACE @@ -42491,15 +42491,15 @@ target_compile_options(GENERIC_F413CHUX_serial_none INTERFACE ) add_library(GENERIC_F413CHUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F413CHUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F413CHUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F413CHUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F413CHUX_usb_HID INTERFACE) target_compile_options(GENERIC_F413CHUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F413CHUX_usb_none INTERFACE) target_compile_options(GENERIC_F413CHUX_usb_none INTERFACE @@ -42615,15 +42615,15 @@ target_compile_options(GENERIC_F413RGTX_serial_none INTERFACE ) add_library(GENERIC_F413RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F413RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F413RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F413RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F413RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F413RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F413RGTX_usb_none INTERFACE) target_compile_options(GENERIC_F413RGTX_usb_none INTERFACE @@ -42739,15 +42739,15 @@ target_compile_options(GENERIC_F413RHTX_serial_none INTERFACE ) add_library(GENERIC_F413RHTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F413RHTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F413RHTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F413RHTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F413RHTX_usb_HID INTERFACE) target_compile_options(GENERIC_F413RHTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F413RHTX_usb_none INTERFACE) target_compile_options(GENERIC_F413RHTX_usb_none INTERFACE @@ -42863,15 +42863,15 @@ target_compile_options(GENERIC_F413ZGJX_serial_none INTERFACE ) add_library(GENERIC_F413ZGJX_usb_CDC INTERFACE) target_compile_options(GENERIC_F413ZGJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F413ZGJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F413ZGJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F413ZGJX_usb_HID INTERFACE) target_compile_options(GENERIC_F413ZGJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F413ZGJX_usb_none INTERFACE) target_compile_options(GENERIC_F413ZGJX_usb_none INTERFACE @@ -42987,15 +42987,15 @@ target_compile_options(GENERIC_F413ZGTX_serial_none INTERFACE ) add_library(GENERIC_F413ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F413ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F413ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F413ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F413ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F413ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F413ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F413ZGTX_usb_none INTERFACE @@ -43111,15 +43111,15 @@ target_compile_options(GENERIC_F413ZHJX_serial_none INTERFACE ) add_library(GENERIC_F413ZHJX_usb_CDC INTERFACE) target_compile_options(GENERIC_F413ZHJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F413ZHJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F413ZHJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F413ZHJX_usb_HID INTERFACE) target_compile_options(GENERIC_F413ZHJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F413ZHJX_usb_none INTERFACE) target_compile_options(GENERIC_F413ZHJX_usb_none INTERFACE @@ -43235,15 +43235,15 @@ target_compile_options(GENERIC_F413ZHTX_serial_none INTERFACE ) add_library(GENERIC_F413ZHTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F413ZHTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F413ZHTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F413ZHTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F413ZHTX_usb_HID INTERFACE) target_compile_options(GENERIC_F413ZHTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F413ZHTX_usb_none INTERFACE) target_compile_options(GENERIC_F413ZHTX_usb_none INTERFACE @@ -43359,15 +43359,15 @@ target_compile_options(GENERIC_F415RGTX_serial_none INTERFACE ) add_library(GENERIC_F415RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F415RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F415RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F415RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F415RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F415RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F415RGTX_usb_none INTERFACE) target_compile_options(GENERIC_F415RGTX_usb_none INTERFACE @@ -43483,15 +43483,15 @@ target_compile_options(GENERIC_F417VETX_serial_none INTERFACE ) add_library(GENERIC_F417VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F417VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F417VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F417VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F417VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F417VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F417VETX_usb_none INTERFACE) target_compile_options(GENERIC_F417VETX_usb_none INTERFACE @@ -43607,15 +43607,15 @@ target_compile_options(GENERIC_F417VGTX_serial_none INTERFACE ) add_library(GENERIC_F417VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F417VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F417VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F417VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F417VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F417VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F417VGTX_usb_none INTERFACE) target_compile_options(GENERIC_F417VGTX_usb_none INTERFACE @@ -43731,15 +43731,15 @@ target_compile_options(GENERIC_F417ZETX_serial_none INTERFACE ) add_library(GENERIC_F417ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F417ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F417ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F417ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F417ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F417ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F417ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F417ZETX_usb_none INTERFACE @@ -43855,15 +43855,15 @@ target_compile_options(GENERIC_F417ZGTX_serial_none INTERFACE ) add_library(GENERIC_F417ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F417ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F417ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F417ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F417ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F417ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F417ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F417ZGTX_usb_none INTERFACE @@ -43979,15 +43979,15 @@ target_compile_options(GENERIC_F423CHUX_serial_none INTERFACE ) add_library(GENERIC_F423CHUX_usb_CDC INTERFACE) target_compile_options(GENERIC_F423CHUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F423CHUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F423CHUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F423CHUX_usb_HID INTERFACE) target_compile_options(GENERIC_F423CHUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F423CHUX_usb_none INTERFACE) target_compile_options(GENERIC_F423CHUX_usb_none INTERFACE @@ -44103,15 +44103,15 @@ target_compile_options(GENERIC_F423RHTX_serial_none INTERFACE ) add_library(GENERIC_F423RHTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F423RHTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F423RHTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F423RHTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F423RHTX_usb_HID INTERFACE) target_compile_options(GENERIC_F423RHTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F423RHTX_usb_none INTERFACE) target_compile_options(GENERIC_F423RHTX_usb_none INTERFACE @@ -44227,15 +44227,15 @@ target_compile_options(GENERIC_F423ZHJX_serial_none INTERFACE ) add_library(GENERIC_F423ZHJX_usb_CDC INTERFACE) target_compile_options(GENERIC_F423ZHJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F423ZHJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F423ZHJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F423ZHJX_usb_HID INTERFACE) target_compile_options(GENERIC_F423ZHJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F423ZHJX_usb_none INTERFACE) target_compile_options(GENERIC_F423ZHJX_usb_none INTERFACE @@ -44351,15 +44351,15 @@ target_compile_options(GENERIC_F423ZHTX_serial_none INTERFACE ) add_library(GENERIC_F423ZHTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F423ZHTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F423ZHTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F423ZHTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F423ZHTX_usb_HID INTERFACE) target_compile_options(GENERIC_F423ZHTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F423ZHTX_usb_none INTERFACE) target_compile_options(GENERIC_F423ZHTX_usb_none INTERFACE @@ -44475,15 +44475,15 @@ target_compile_options(GENERIC_F427ZGTX_serial_none INTERFACE ) add_library(GENERIC_F427ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F427ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F427ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F427ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F427ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F427ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F427ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F427ZGTX_usb_none INTERFACE @@ -44599,15 +44599,15 @@ target_compile_options(GENERIC_F427ZITX_serial_none INTERFACE ) add_library(GENERIC_F427ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F427ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F427ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F427ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F427ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_F427ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F427ZITX_usb_none INTERFACE) target_compile_options(GENERIC_F427ZITX_usb_none INTERFACE @@ -44723,15 +44723,15 @@ target_compile_options(GENERIC_F429ZETX_serial_none INTERFACE ) add_library(GENERIC_F429ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F429ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F429ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F429ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F429ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F429ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F429ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F429ZETX_usb_none INTERFACE @@ -44847,15 +44847,15 @@ target_compile_options(GENERIC_F429ZGTX_serial_none INTERFACE ) add_library(GENERIC_F429ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F429ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F429ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F429ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F429ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F429ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F429ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F429ZGTX_usb_none INTERFACE @@ -44971,15 +44971,15 @@ target_compile_options(GENERIC_F429ZGYX_serial_none INTERFACE ) add_library(GENERIC_F429ZGYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F429ZGYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F429ZGYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F429ZGYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F429ZGYX_usb_HID INTERFACE) target_compile_options(GENERIC_F429ZGYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F429ZGYX_usb_none INTERFACE) target_compile_options(GENERIC_F429ZGYX_usb_none INTERFACE @@ -45095,15 +45095,15 @@ target_compile_options(GENERIC_F429ZITX_serial_none INTERFACE ) add_library(GENERIC_F429ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F429ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F429ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F429ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F429ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_F429ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F429ZITX_usb_none INTERFACE) target_compile_options(GENERIC_F429ZITX_usb_none INTERFACE @@ -45219,15 +45219,15 @@ target_compile_options(GENERIC_F429ZIYX_serial_none INTERFACE ) add_library(GENERIC_F429ZIYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F429ZIYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F429ZIYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F429ZIYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F429ZIYX_usb_HID INTERFACE) target_compile_options(GENERIC_F429ZIYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F429ZIYX_usb_none INTERFACE) target_compile_options(GENERIC_F429ZIYX_usb_none INTERFACE @@ -45343,15 +45343,15 @@ target_compile_options(GENERIC_F437ZGTX_serial_none INTERFACE ) add_library(GENERIC_F437ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F437ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F437ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F437ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F437ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F437ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F437ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F437ZGTX_usb_none INTERFACE @@ -45467,15 +45467,15 @@ target_compile_options(GENERIC_F437ZITX_serial_none INTERFACE ) add_library(GENERIC_F437ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F437ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F437ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F437ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F437ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_F437ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F437ZITX_usb_none INTERFACE) target_compile_options(GENERIC_F437ZITX_usb_none INTERFACE @@ -45591,15 +45591,15 @@ target_compile_options(GENERIC_F439ZGTX_serial_none INTERFACE ) add_library(GENERIC_F439ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F439ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F439ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F439ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F439ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F439ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F439ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F439ZGTX_usb_none INTERFACE @@ -45715,15 +45715,15 @@ target_compile_options(GENERIC_F439ZGYX_serial_none INTERFACE ) add_library(GENERIC_F439ZGYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F439ZGYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F439ZGYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F439ZGYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F439ZGYX_usb_HID INTERFACE) target_compile_options(GENERIC_F439ZGYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F439ZGYX_usb_none INTERFACE) target_compile_options(GENERIC_F439ZGYX_usb_none INTERFACE @@ -45839,15 +45839,15 @@ target_compile_options(GENERIC_F439ZITX_serial_none INTERFACE ) add_library(GENERIC_F439ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F439ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F439ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F439ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F439ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_F439ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F439ZITX_usb_none INTERFACE) target_compile_options(GENERIC_F439ZITX_usb_none INTERFACE @@ -45963,15 +45963,15 @@ target_compile_options(GENERIC_F439ZIYX_serial_none INTERFACE ) add_library(GENERIC_F439ZIYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F439ZIYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F439ZIYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F439ZIYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F439ZIYX_usb_HID INTERFACE) target_compile_options(GENERIC_F439ZIYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F439ZIYX_usb_none INTERFACE) target_compile_options(GENERIC_F439ZIYX_usb_none INTERFACE @@ -46087,15 +46087,15 @@ target_compile_options(GENERIC_F446RCTX_serial_none INTERFACE ) add_library(GENERIC_F446RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F446RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F446RCTX_usb_none INTERFACE @@ -46211,15 +46211,15 @@ target_compile_options(GENERIC_F446RETX_serial_none INTERFACE ) add_library(GENERIC_F446RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F446RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446RETX_usb_none INTERFACE) target_compile_options(GENERIC_F446RETX_usb_none INTERFACE @@ -46335,15 +46335,15 @@ target_compile_options(GENERIC_F446VCTX_serial_none INTERFACE ) add_library(GENERIC_F446VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F446VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446VCTX_usb_none INTERFACE) target_compile_options(GENERIC_F446VCTX_usb_none INTERFACE @@ -46459,15 +46459,15 @@ target_compile_options(GENERIC_F446VETX_serial_none INTERFACE ) add_library(GENERIC_F446VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446VETX_usb_HID INTERFACE) target_compile_options(GENERIC_F446VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446VETX_usb_none INTERFACE) target_compile_options(GENERIC_F446VETX_usb_none INTERFACE @@ -46583,15 +46583,15 @@ target_compile_options(GENERIC_F446ZCHX_serial_none INTERFACE ) add_library(GENERIC_F446ZCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446ZCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446ZCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446ZCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446ZCHX_usb_HID INTERFACE) target_compile_options(GENERIC_F446ZCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446ZCHX_usb_none INTERFACE) target_compile_options(GENERIC_F446ZCHX_usb_none INTERFACE @@ -46707,15 +46707,15 @@ target_compile_options(GENERIC_F446ZCJX_serial_none INTERFACE ) add_library(GENERIC_F446ZCJX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446ZCJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446ZCJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446ZCJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446ZCJX_usb_HID INTERFACE) target_compile_options(GENERIC_F446ZCJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446ZCJX_usb_none INTERFACE) target_compile_options(GENERIC_F446ZCJX_usb_none INTERFACE @@ -46831,15 +46831,15 @@ target_compile_options(GENERIC_F446ZCTX_serial_none INTERFACE ) add_library(GENERIC_F446ZCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446ZCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446ZCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446ZCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446ZCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F446ZCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446ZCTX_usb_none INTERFACE) target_compile_options(GENERIC_F446ZCTX_usb_none INTERFACE @@ -46955,15 +46955,15 @@ target_compile_options(GENERIC_F446ZEHX_serial_none INTERFACE ) add_library(GENERIC_F446ZEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446ZEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446ZEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446ZEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446ZEHX_usb_HID INTERFACE) target_compile_options(GENERIC_F446ZEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446ZEHX_usb_none INTERFACE) target_compile_options(GENERIC_F446ZEHX_usb_none INTERFACE @@ -47079,15 +47079,15 @@ target_compile_options(GENERIC_F446ZEJX_serial_none INTERFACE ) add_library(GENERIC_F446ZEJX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446ZEJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446ZEJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446ZEJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446ZEJX_usb_HID INTERFACE) target_compile_options(GENERIC_F446ZEJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446ZEJX_usb_none INTERFACE) target_compile_options(GENERIC_F446ZEJX_usb_none INTERFACE @@ -47203,15 +47203,15 @@ target_compile_options(GENERIC_F446ZETX_serial_none INTERFACE ) add_library(GENERIC_F446ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F446ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F446ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F446ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F446ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F446ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F446ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F446ZETX_usb_none INTERFACE @@ -47327,15 +47327,15 @@ target_compile_options(GENERIC_F722RCTX_serial_none INTERFACE ) add_library(GENERIC_F722RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F722RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F722RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F722RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F722RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F722RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F722RCTX_usb_none INTERFACE) target_compile_options(GENERIC_F722RCTX_usb_none INTERFACE @@ -47409,15 +47409,15 @@ target_compile_options(GENERIC_F722RETX_serial_none INTERFACE ) add_library(GENERIC_F722RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F722RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F722RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F722RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F722RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F722RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F722RETX_usb_none INTERFACE) target_compile_options(GENERIC_F722RETX_usb_none INTERFACE @@ -47491,15 +47491,15 @@ target_compile_options(GENERIC_F722ZCTX_serial_none INTERFACE ) add_library(GENERIC_F722ZCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F722ZCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F722ZCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F722ZCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F722ZCTX_usb_HID INTERFACE) target_compile_options(GENERIC_F722ZCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F722ZCTX_usb_none INTERFACE) target_compile_options(GENERIC_F722ZCTX_usb_none INTERFACE @@ -47573,15 +47573,15 @@ target_compile_options(GENERIC_F722ZETX_serial_none INTERFACE ) add_library(GENERIC_F722ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F722ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F722ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F722ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F722ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F722ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F722ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F722ZETX_usb_none INTERFACE @@ -47655,15 +47655,15 @@ target_compile_options(GENERIC_F723ICKX_serial_none INTERFACE ) add_library(GENERIC_F723ICKX_usb_CDC INTERFACE) target_compile_options(GENERIC_F723ICKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F723ICKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F723ICKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F723ICKX_usb_HID INTERFACE) target_compile_options(GENERIC_F723ICKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F723ICKX_usb_none INTERFACE) target_compile_options(GENERIC_F723ICKX_usb_none INTERFACE @@ -47737,15 +47737,15 @@ target_compile_options(GENERIC_F723ICTX_serial_none INTERFACE ) add_library(GENERIC_F723ICTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F723ICTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F723ICTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F723ICTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F723ICTX_usb_HID INTERFACE) target_compile_options(GENERIC_F723ICTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F723ICTX_usb_none INTERFACE) target_compile_options(GENERIC_F723ICTX_usb_none INTERFACE @@ -47819,15 +47819,15 @@ target_compile_options(GENERIC_F723IEKX_serial_none INTERFACE ) add_library(GENERIC_F723IEKX_usb_CDC INTERFACE) target_compile_options(GENERIC_F723IEKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F723IEKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F723IEKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F723IEKX_usb_HID INTERFACE) target_compile_options(GENERIC_F723IEKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F723IEKX_usb_none INTERFACE) target_compile_options(GENERIC_F723IEKX_usb_none INTERFACE @@ -47901,15 +47901,15 @@ target_compile_options(GENERIC_F723IETX_serial_none INTERFACE ) add_library(GENERIC_F723IETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F723IETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F723IETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F723IETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F723IETX_usb_HID INTERFACE) target_compile_options(GENERIC_F723IETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F723IETX_usb_none INTERFACE) target_compile_options(GENERIC_F723IETX_usb_none INTERFACE @@ -47983,15 +47983,15 @@ target_compile_options(GENERIC_F730I8KX_serial_none INTERFACE ) add_library(GENERIC_F730I8KX_usb_CDC INTERFACE) target_compile_options(GENERIC_F730I8KX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F730I8KX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F730I8KX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F730I8KX_usb_HID INTERFACE) target_compile_options(GENERIC_F730I8KX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F730I8KX_usb_none INTERFACE) target_compile_options(GENERIC_F730I8KX_usb_none INTERFACE @@ -48065,15 +48065,15 @@ target_compile_options(GENERIC_F730R8TX_serial_none INTERFACE ) add_library(GENERIC_F730R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F730R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F730R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F730R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F730R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F730R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F730R8TX_usb_none INTERFACE) target_compile_options(GENERIC_F730R8TX_usb_none INTERFACE @@ -48147,15 +48147,15 @@ target_compile_options(GENERIC_F732RETX_serial_none INTERFACE ) add_library(GENERIC_F732RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F732RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F732RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F732RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F732RETX_usb_HID INTERFACE) target_compile_options(GENERIC_F732RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F732RETX_usb_none INTERFACE) target_compile_options(GENERIC_F732RETX_usb_none INTERFACE @@ -48229,15 +48229,15 @@ target_compile_options(GENERIC_F732ZETX_serial_none INTERFACE ) add_library(GENERIC_F732ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F732ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F732ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F732ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F732ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F732ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F732ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F732ZETX_usb_none INTERFACE @@ -48311,15 +48311,15 @@ target_compile_options(GENERIC_F733IEKX_serial_none INTERFACE ) add_library(GENERIC_F733IEKX_usb_CDC INTERFACE) target_compile_options(GENERIC_F733IEKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F733IEKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F733IEKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F733IEKX_usb_HID INTERFACE) target_compile_options(GENERIC_F733IEKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F733IEKX_usb_none INTERFACE) target_compile_options(GENERIC_F733IEKX_usb_none INTERFACE @@ -48393,15 +48393,15 @@ target_compile_options(GENERIC_F733IETX_serial_none INTERFACE ) add_library(GENERIC_F733IETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F733IETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F733IETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F733IETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F733IETX_usb_HID INTERFACE) target_compile_options(GENERIC_F733IETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F733IETX_usb_none INTERFACE) target_compile_options(GENERIC_F733IETX_usb_none INTERFACE @@ -48475,15 +48475,15 @@ target_compile_options(GENERIC_F745ZETX_serial_none INTERFACE ) add_library(GENERIC_F745ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F745ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F745ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F745ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F745ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F745ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F745ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F745ZETX_usb_none INTERFACE @@ -48557,15 +48557,15 @@ target_compile_options(GENERIC_F745ZGTX_serial_none INTERFACE ) add_library(GENERIC_F745ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F745ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F745ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F745ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F745ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F745ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F745ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F745ZGTX_usb_none INTERFACE @@ -48639,15 +48639,15 @@ target_compile_options(GENERIC_F746BETX_serial_none INTERFACE ) add_library(GENERIC_F746BETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F746BETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F746BETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F746BETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F746BETX_usb_HID INTERFACE) target_compile_options(GENERIC_F746BETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F746BETX_usb_none INTERFACE) target_compile_options(GENERIC_F746BETX_usb_none INTERFACE @@ -48721,15 +48721,15 @@ target_compile_options(GENERIC_F746BGTX_serial_none INTERFACE ) add_library(GENERIC_F746BGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F746BGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F746BGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F746BGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F746BGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F746BGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F746BGTX_usb_none INTERFACE) target_compile_options(GENERIC_F746BGTX_usb_none INTERFACE @@ -48803,15 +48803,15 @@ target_compile_options(GENERIC_F746NEHX_serial_none INTERFACE ) add_library(GENERIC_F746NEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F746NEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F746NEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F746NEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F746NEHX_usb_HID INTERFACE) target_compile_options(GENERIC_F746NEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F746NEHX_usb_none INTERFACE) target_compile_options(GENERIC_F746NEHX_usb_none INTERFACE @@ -48885,15 +48885,15 @@ target_compile_options(GENERIC_F746NGHX_serial_none INTERFACE ) add_library(GENERIC_F746NGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F746NGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F746NGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F746NGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F746NGHX_usb_HID INTERFACE) target_compile_options(GENERIC_F746NGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F746NGHX_usb_none INTERFACE) target_compile_options(GENERIC_F746NGHX_usb_none INTERFACE @@ -48967,15 +48967,15 @@ target_compile_options(GENERIC_F746ZETX_serial_none INTERFACE ) add_library(GENERIC_F746ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_F746ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F746ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F746ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F746ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_F746ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F746ZETX_usb_none INTERFACE) target_compile_options(GENERIC_F746ZETX_usb_none INTERFACE @@ -49049,15 +49049,15 @@ target_compile_options(GENERIC_F746ZEYX_serial_none INTERFACE ) add_library(GENERIC_F746ZEYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F746ZEYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F746ZEYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F746ZEYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F746ZEYX_usb_HID INTERFACE) target_compile_options(GENERIC_F746ZEYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F746ZEYX_usb_none INTERFACE) target_compile_options(GENERIC_F746ZEYX_usb_none INTERFACE @@ -49131,15 +49131,15 @@ target_compile_options(GENERIC_F746ZGTX_serial_none INTERFACE ) add_library(GENERIC_F746ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F746ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F746ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F746ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F746ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F746ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F746ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F746ZGTX_usb_none INTERFACE @@ -49213,15 +49213,15 @@ target_compile_options(GENERIC_F746ZGYX_serial_none INTERFACE ) add_library(GENERIC_F746ZGYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F746ZGYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F746ZGYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F746ZGYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F746ZGYX_usb_HID INTERFACE) target_compile_options(GENERIC_F746ZGYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F746ZGYX_usb_none INTERFACE) target_compile_options(GENERIC_F746ZGYX_usb_none INTERFACE @@ -49295,15 +49295,15 @@ target_compile_options(GENERIC_F750N8HX_serial_none INTERFACE ) add_library(GENERIC_F750N8HX_usb_CDC INTERFACE) target_compile_options(GENERIC_F750N8HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F750N8HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F750N8HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F750N8HX_usb_HID INTERFACE) target_compile_options(GENERIC_F750N8HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F750N8HX_usb_none INTERFACE) target_compile_options(GENERIC_F750N8HX_usb_none INTERFACE @@ -49377,15 +49377,15 @@ target_compile_options(GENERIC_F750Z8TX_serial_none INTERFACE ) add_library(GENERIC_F750Z8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_F750Z8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F750Z8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F750Z8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F750Z8TX_usb_HID INTERFACE) target_compile_options(GENERIC_F750Z8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F750Z8TX_usb_none INTERFACE) target_compile_options(GENERIC_F750Z8TX_usb_none INTERFACE @@ -49459,15 +49459,15 @@ target_compile_options(GENERIC_F756BGTX_serial_none INTERFACE ) add_library(GENERIC_F756BGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F756BGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F756BGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F756BGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F756BGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F756BGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F756BGTX_usb_none INTERFACE) target_compile_options(GENERIC_F756BGTX_usb_none INTERFACE @@ -49541,15 +49541,15 @@ target_compile_options(GENERIC_F756NGHX_serial_none INTERFACE ) add_library(GENERIC_F756NGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F756NGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F756NGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F756NGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F756NGHX_usb_HID INTERFACE) target_compile_options(GENERIC_F756NGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F756NGHX_usb_none INTERFACE) target_compile_options(GENERIC_F756NGHX_usb_none INTERFACE @@ -49623,15 +49623,15 @@ target_compile_options(GENERIC_F756ZGTX_serial_none INTERFACE ) add_library(GENERIC_F756ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F756ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F756ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F756ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F756ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F756ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F756ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F756ZGTX_usb_none INTERFACE @@ -49705,15 +49705,15 @@ target_compile_options(GENERIC_F756ZGYX_serial_none INTERFACE ) add_library(GENERIC_F756ZGYX_usb_CDC INTERFACE) target_compile_options(GENERIC_F756ZGYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F756ZGYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F756ZGYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F756ZGYX_usb_HID INTERFACE) target_compile_options(GENERIC_F756ZGYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F756ZGYX_usb_none INTERFACE) target_compile_options(GENERIC_F756ZGYX_usb_none INTERFACE @@ -49787,15 +49787,15 @@ target_compile_options(GENERIC_F765IGKX_serial_none INTERFACE ) add_library(GENERIC_F765IGKX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765IGKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765IGKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765IGKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765IGKX_usb_HID INTERFACE) target_compile_options(GENERIC_F765IGKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765IGKX_usb_none INTERFACE) target_compile_options(GENERIC_F765IGKX_usb_none INTERFACE @@ -49869,15 +49869,15 @@ target_compile_options(GENERIC_F765IGTX_serial_none INTERFACE ) add_library(GENERIC_F765IGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765IGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765IGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765IGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765IGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F765IGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765IGTX_usb_none INTERFACE) target_compile_options(GENERIC_F765IGTX_usb_none INTERFACE @@ -49951,15 +49951,15 @@ target_compile_options(GENERIC_F765IIKX_serial_none INTERFACE ) add_library(GENERIC_F765IIKX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765IIKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765IIKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765IIKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765IIKX_usb_HID INTERFACE) target_compile_options(GENERIC_F765IIKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765IIKX_usb_none INTERFACE) target_compile_options(GENERIC_F765IIKX_usb_none INTERFACE @@ -50033,15 +50033,15 @@ target_compile_options(GENERIC_F765IITX_serial_none INTERFACE ) add_library(GENERIC_F765IITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765IITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765IITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765IITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765IITX_usb_HID INTERFACE) target_compile_options(GENERIC_F765IITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765IITX_usb_none INTERFACE) target_compile_options(GENERIC_F765IITX_usb_none INTERFACE @@ -50115,15 +50115,15 @@ target_compile_options(GENERIC_F765VGHX_serial_none INTERFACE ) add_library(GENERIC_F765VGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765VGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765VGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765VGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765VGHX_usb_HID INTERFACE) target_compile_options(GENERIC_F765VGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765VGHX_usb_none INTERFACE) target_compile_options(GENERIC_F765VGHX_usb_none INTERFACE @@ -50197,15 +50197,15 @@ target_compile_options(GENERIC_F765VGTX_serial_none INTERFACE ) add_library(GENERIC_F765VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F765VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765VGTX_usb_none INTERFACE) target_compile_options(GENERIC_F765VGTX_usb_none INTERFACE @@ -50279,15 +50279,15 @@ target_compile_options(GENERIC_F765VIHX_serial_none INTERFACE ) add_library(GENERIC_F765VIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765VIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765VIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765VIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765VIHX_usb_HID INTERFACE) target_compile_options(GENERIC_F765VIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765VIHX_usb_none INTERFACE) target_compile_options(GENERIC_F765VIHX_usb_none INTERFACE @@ -50361,15 +50361,15 @@ target_compile_options(GENERIC_F765VITX_serial_none INTERFACE ) add_library(GENERIC_F765VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765VITX_usb_HID INTERFACE) target_compile_options(GENERIC_F765VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765VITX_usb_none INTERFACE) target_compile_options(GENERIC_F765VITX_usb_none INTERFACE @@ -50443,15 +50443,15 @@ target_compile_options(GENERIC_F765ZGTX_serial_none INTERFACE ) add_library(GENERIC_F765ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F765ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F765ZGTX_usb_none INTERFACE @@ -50525,15 +50525,15 @@ target_compile_options(GENERIC_F765ZITX_serial_none INTERFACE ) add_library(GENERIC_F765ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F765ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F765ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F765ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F765ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_F765ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F765ZITX_usb_none INTERFACE) target_compile_options(GENERIC_F765ZITX_usb_none INTERFACE @@ -50607,15 +50607,15 @@ target_compile_options(GENERIC_F767IGKX_serial_none INTERFACE ) add_library(GENERIC_F767IGKX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767IGKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767IGKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767IGKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767IGKX_usb_HID INTERFACE) target_compile_options(GENERIC_F767IGKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767IGKX_usb_none INTERFACE) target_compile_options(GENERIC_F767IGKX_usb_none INTERFACE @@ -50689,15 +50689,15 @@ target_compile_options(GENERIC_F767IGTX_serial_none INTERFACE ) add_library(GENERIC_F767IGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767IGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767IGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767IGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767IGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F767IGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767IGTX_usb_none INTERFACE) target_compile_options(GENERIC_F767IGTX_usb_none INTERFACE @@ -50771,15 +50771,15 @@ target_compile_options(GENERIC_F767IIKX_serial_none INTERFACE ) add_library(GENERIC_F767IIKX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767IIKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767IIKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767IIKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767IIKX_usb_HID INTERFACE) target_compile_options(GENERIC_F767IIKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767IIKX_usb_none INTERFACE) target_compile_options(GENERIC_F767IIKX_usb_none INTERFACE @@ -50853,15 +50853,15 @@ target_compile_options(GENERIC_F767IITX_serial_none INTERFACE ) add_library(GENERIC_F767IITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767IITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767IITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767IITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767IITX_usb_HID INTERFACE) target_compile_options(GENERIC_F767IITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767IITX_usb_none INTERFACE) target_compile_options(GENERIC_F767IITX_usb_none INTERFACE @@ -50935,15 +50935,15 @@ target_compile_options(GENERIC_F767VGHX_serial_none INTERFACE ) add_library(GENERIC_F767VGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767VGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767VGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767VGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767VGHX_usb_HID INTERFACE) target_compile_options(GENERIC_F767VGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767VGHX_usb_none INTERFACE) target_compile_options(GENERIC_F767VGHX_usb_none INTERFACE @@ -51017,15 +51017,15 @@ target_compile_options(GENERIC_F767VGTX_serial_none INTERFACE ) add_library(GENERIC_F767VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F767VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767VGTX_usb_none INTERFACE) target_compile_options(GENERIC_F767VGTX_usb_none INTERFACE @@ -51099,15 +51099,15 @@ target_compile_options(GENERIC_F767VIHX_serial_none INTERFACE ) add_library(GENERIC_F767VIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767VIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767VIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767VIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767VIHX_usb_HID INTERFACE) target_compile_options(GENERIC_F767VIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767VIHX_usb_none INTERFACE) target_compile_options(GENERIC_F767VIHX_usb_none INTERFACE @@ -51181,15 +51181,15 @@ target_compile_options(GENERIC_F767VITX_serial_none INTERFACE ) add_library(GENERIC_F767VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767VITX_usb_HID INTERFACE) target_compile_options(GENERIC_F767VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767VITX_usb_none INTERFACE) target_compile_options(GENERIC_F767VITX_usb_none INTERFACE @@ -51263,15 +51263,15 @@ target_compile_options(GENERIC_F767ZGTX_serial_none INTERFACE ) add_library(GENERIC_F767ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_F767ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_F767ZGTX_usb_none INTERFACE @@ -51345,15 +51345,15 @@ target_compile_options(GENERIC_F767ZITX_serial_none INTERFACE ) add_library(GENERIC_F767ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F767ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F767ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F767ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F767ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_F767ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F767ZITX_usb_none INTERFACE) target_compile_options(GENERIC_F767ZITX_usb_none INTERFACE @@ -51427,15 +51427,15 @@ target_compile_options(GENERIC_F777IIKX_serial_none INTERFACE ) add_library(GENERIC_F777IIKX_usb_CDC INTERFACE) target_compile_options(GENERIC_F777IIKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F777IIKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F777IIKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F777IIKX_usb_HID INTERFACE) target_compile_options(GENERIC_F777IIKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F777IIKX_usb_none INTERFACE) target_compile_options(GENERIC_F777IIKX_usb_none INTERFACE @@ -51509,15 +51509,15 @@ target_compile_options(GENERIC_F777IITX_serial_none INTERFACE ) add_library(GENERIC_F777IITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F777IITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F777IITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F777IITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F777IITX_usb_HID INTERFACE) target_compile_options(GENERIC_F777IITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F777IITX_usb_none INTERFACE) target_compile_options(GENERIC_F777IITX_usb_none INTERFACE @@ -51591,15 +51591,15 @@ target_compile_options(GENERIC_F777VIHX_serial_none INTERFACE ) add_library(GENERIC_F777VIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_F777VIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F777VIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F777VIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F777VIHX_usb_HID INTERFACE) target_compile_options(GENERIC_F777VIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F777VIHX_usb_none INTERFACE) target_compile_options(GENERIC_F777VIHX_usb_none INTERFACE @@ -51673,15 +51673,15 @@ target_compile_options(GENERIC_F777VITX_serial_none INTERFACE ) add_library(GENERIC_F777VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F777VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F777VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F777VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F777VITX_usb_HID INTERFACE) target_compile_options(GENERIC_F777VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F777VITX_usb_none INTERFACE) target_compile_options(GENERIC_F777VITX_usb_none INTERFACE @@ -51755,15 +51755,15 @@ target_compile_options(GENERIC_F777ZITX_serial_none INTERFACE ) add_library(GENERIC_F777ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_F777ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_F777ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_F777ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_F777ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_F777ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_F777ZITX_usb_none INTERFACE) target_compile_options(GENERIC_F777ZITX_usb_none INTERFACE @@ -51837,15 +51837,15 @@ target_compile_options(GENERIC_G030C6TX_serial_none INTERFACE ) add_library(GENERIC_G030C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G030C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G030C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G030C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G030C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G030C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G030C6TX_usb_none INTERFACE) target_compile_options(GENERIC_G030C6TX_usb_none INTERFACE @@ -51907,15 +51907,15 @@ target_compile_options(GENERIC_G030C8TX_serial_none INTERFACE ) add_library(GENERIC_G030C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G030C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G030C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G030C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G030C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G030C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G030C8TX_usb_none INTERFACE) target_compile_options(GENERIC_G030C8TX_usb_none INTERFACE @@ -51977,15 +51977,15 @@ target_compile_options(GENERIC_G030F6PX_serial_none INTERFACE ) add_library(GENERIC_G030F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G030F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G030F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G030F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G030F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_G030F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G030F6PX_usb_none INTERFACE) target_compile_options(GENERIC_G030F6PX_usb_none INTERFACE @@ -52047,15 +52047,15 @@ target_compile_options(GENERIC_G030J6MX_serial_none INTERFACE ) add_library(GENERIC_G030J6MX_usb_CDC INTERFACE) target_compile_options(GENERIC_G030J6MX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G030J6MX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G030J6MX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G030J6MX_usb_HID INTERFACE) target_compile_options(GENERIC_G030J6MX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G030J6MX_usb_none INTERFACE) target_compile_options(GENERIC_G030J6MX_usb_none INTERFACE @@ -52117,15 +52117,15 @@ target_compile_options(GENERIC_G030K6TX_serial_none INTERFACE ) add_library(GENERIC_G030K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G030K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G030K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G030K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G030K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G030K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G030K6TX_usb_none INTERFACE) target_compile_options(GENERIC_G030K6TX_usb_none INTERFACE @@ -52187,15 +52187,15 @@ target_compile_options(GENERIC_G030K8TX_serial_none INTERFACE ) add_library(GENERIC_G030K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G030K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G030K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G030K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G030K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G030K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G030K8TX_usb_none INTERFACE) target_compile_options(GENERIC_G030K8TX_usb_none INTERFACE @@ -52257,15 +52257,15 @@ target_compile_options(GENERIC_G031C4TX_serial_none INTERFACE ) add_library(GENERIC_G031C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_G031C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031C4TX_usb_none INTERFACE) target_compile_options(GENERIC_G031C4TX_usb_none INTERFACE @@ -52327,15 +52327,15 @@ target_compile_options(GENERIC_G031C4UX_serial_none INTERFACE ) add_library(GENERIC_G031C4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031C4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031C4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031C4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031C4UX_usb_HID INTERFACE) target_compile_options(GENERIC_G031C4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031C4UX_usb_none INTERFACE) target_compile_options(GENERIC_G031C4UX_usb_none INTERFACE @@ -52397,15 +52397,15 @@ target_compile_options(GENERIC_G031C6TX_serial_none INTERFACE ) add_library(GENERIC_G031C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G031C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031C6TX_usb_none INTERFACE) target_compile_options(GENERIC_G031C6TX_usb_none INTERFACE @@ -52467,15 +52467,15 @@ target_compile_options(GENERIC_G031C6UX_serial_none INTERFACE ) add_library(GENERIC_G031C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G031C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031C6UX_usb_none INTERFACE) target_compile_options(GENERIC_G031C6UX_usb_none INTERFACE @@ -52537,15 +52537,15 @@ target_compile_options(GENERIC_G031C8TX_serial_none INTERFACE ) add_library(GENERIC_G031C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G031C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031C8TX_usb_none INTERFACE) target_compile_options(GENERIC_G031C8TX_usb_none INTERFACE @@ -52607,15 +52607,15 @@ target_compile_options(GENERIC_G031C8UX_serial_none INTERFACE ) add_library(GENERIC_G031C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G031C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031C8UX_usb_none INTERFACE) target_compile_options(GENERIC_G031C8UX_usb_none INTERFACE @@ -52677,15 +52677,15 @@ target_compile_options(GENERIC_G031F4PX_serial_none INTERFACE ) add_library(GENERIC_G031F4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031F4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031F4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031F4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031F4PX_usb_HID INTERFACE) target_compile_options(GENERIC_G031F4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031F4PX_usb_none INTERFACE) target_compile_options(GENERIC_G031F4PX_usb_none INTERFACE @@ -52747,15 +52747,15 @@ target_compile_options(GENERIC_G031F6PX_serial_none INTERFACE ) add_library(GENERIC_G031F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_G031F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031F6PX_usb_none INTERFACE) target_compile_options(GENERIC_G031F6PX_usb_none INTERFACE @@ -52817,15 +52817,15 @@ target_compile_options(GENERIC_G031F8PX_serial_none INTERFACE ) add_library(GENERIC_G031F8PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031F8PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031F8PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031F8PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031F8PX_usb_HID INTERFACE) target_compile_options(GENERIC_G031F8PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031F8PX_usb_none INTERFACE) target_compile_options(GENERIC_G031F8PX_usb_none INTERFACE @@ -52887,15 +52887,15 @@ target_compile_options(GENERIC_G031G4UX_serial_none INTERFACE ) add_library(GENERIC_G031G4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031G4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031G4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031G4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031G4UX_usb_HID INTERFACE) target_compile_options(GENERIC_G031G4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031G4UX_usb_none INTERFACE) target_compile_options(GENERIC_G031G4UX_usb_none INTERFACE @@ -52957,15 +52957,15 @@ target_compile_options(GENERIC_G031G6UX_serial_none INTERFACE ) add_library(GENERIC_G031G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G031G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031G6UX_usb_none INTERFACE) target_compile_options(GENERIC_G031G6UX_usb_none INTERFACE @@ -53027,15 +53027,15 @@ target_compile_options(GENERIC_G031G8UX_serial_none INTERFACE ) add_library(GENERIC_G031G8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031G8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031G8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031G8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031G8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G031G8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031G8UX_usb_none INTERFACE) target_compile_options(GENERIC_G031G8UX_usb_none INTERFACE @@ -53097,15 +53097,15 @@ target_compile_options(GENERIC_G031J4MX_serial_none INTERFACE ) add_library(GENERIC_G031J4MX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031J4MX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031J4MX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031J4MX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031J4MX_usb_HID INTERFACE) target_compile_options(GENERIC_G031J4MX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031J4MX_usb_none INTERFACE) target_compile_options(GENERIC_G031J4MX_usb_none INTERFACE @@ -53167,15 +53167,15 @@ target_compile_options(GENERIC_G031J6MX_serial_none INTERFACE ) add_library(GENERIC_G031J6MX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031J6MX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031J6MX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031J6MX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031J6MX_usb_HID INTERFACE) target_compile_options(GENERIC_G031J6MX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031J6MX_usb_none INTERFACE) target_compile_options(GENERIC_G031J6MX_usb_none INTERFACE @@ -53237,15 +53237,15 @@ target_compile_options(GENERIC_G031K4TX_serial_none INTERFACE ) add_library(GENERIC_G031K4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031K4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031K4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031K4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031K4TX_usb_HID INTERFACE) target_compile_options(GENERIC_G031K4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031K4TX_usb_none INTERFACE) target_compile_options(GENERIC_G031K4TX_usb_none INTERFACE @@ -53307,15 +53307,15 @@ target_compile_options(GENERIC_G031K4UX_serial_none INTERFACE ) add_library(GENERIC_G031K4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031K4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031K4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031K4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031K4UX_usb_HID INTERFACE) target_compile_options(GENERIC_G031K4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031K4UX_usb_none INTERFACE) target_compile_options(GENERIC_G031K4UX_usb_none INTERFACE @@ -53377,15 +53377,15 @@ target_compile_options(GENERIC_G031K6TX_serial_none INTERFACE ) add_library(GENERIC_G031K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G031K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031K6TX_usb_none INTERFACE) target_compile_options(GENERIC_G031K6TX_usb_none INTERFACE @@ -53447,15 +53447,15 @@ target_compile_options(GENERIC_G031K6UX_serial_none INTERFACE ) add_library(GENERIC_G031K6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031K6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031K6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031K6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031K6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G031K6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031K6UX_usb_none INTERFACE) target_compile_options(GENERIC_G031K6UX_usb_none INTERFACE @@ -53517,15 +53517,15 @@ target_compile_options(GENERIC_G031K8TX_serial_none INTERFACE ) add_library(GENERIC_G031K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G031K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031K8TX_usb_none INTERFACE) target_compile_options(GENERIC_G031K8TX_usb_none INTERFACE @@ -53587,15 +53587,15 @@ target_compile_options(GENERIC_G031K8UX_serial_none INTERFACE ) add_library(GENERIC_G031K8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031K8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031K8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031K8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031K8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G031K8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031K8UX_usb_none INTERFACE) target_compile_options(GENERIC_G031K8UX_usb_none INTERFACE @@ -53657,15 +53657,15 @@ target_compile_options(GENERIC_G031Y8YX_serial_none INTERFACE ) add_library(GENERIC_G031Y8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_G031Y8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G031Y8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G031Y8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G031Y8YX_usb_HID INTERFACE) target_compile_options(GENERIC_G031Y8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G031Y8YX_usb_none INTERFACE) target_compile_options(GENERIC_G031Y8YX_usb_none INTERFACE @@ -53727,15 +53727,15 @@ target_compile_options(GENERIC_G041C6TX_serial_none INTERFACE ) add_library(GENERIC_G041C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G041C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041C6TX_usb_none INTERFACE) target_compile_options(GENERIC_G041C6TX_usb_none INTERFACE @@ -53797,15 +53797,15 @@ target_compile_options(GENERIC_G041C6UX_serial_none INTERFACE ) add_library(GENERIC_G041C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G041C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041C6UX_usb_none INTERFACE) target_compile_options(GENERIC_G041C6UX_usb_none INTERFACE @@ -53867,15 +53867,15 @@ target_compile_options(GENERIC_G041C8TX_serial_none INTERFACE ) add_library(GENERIC_G041C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G041C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041C8TX_usb_none INTERFACE) target_compile_options(GENERIC_G041C8TX_usb_none INTERFACE @@ -53937,15 +53937,15 @@ target_compile_options(GENERIC_G041C8UX_serial_none INTERFACE ) add_library(GENERIC_G041C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G041C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041C8UX_usb_none INTERFACE) target_compile_options(GENERIC_G041C8UX_usb_none INTERFACE @@ -54007,15 +54007,15 @@ target_compile_options(GENERIC_G041F6PX_serial_none INTERFACE ) add_library(GENERIC_G041F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_G041F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041F6PX_usb_none INTERFACE) target_compile_options(GENERIC_G041F6PX_usb_none INTERFACE @@ -54077,15 +54077,15 @@ target_compile_options(GENERIC_G041F8PX_serial_none INTERFACE ) add_library(GENERIC_G041F8PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041F8PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041F8PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041F8PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041F8PX_usb_HID INTERFACE) target_compile_options(GENERIC_G041F8PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041F8PX_usb_none INTERFACE) target_compile_options(GENERIC_G041F8PX_usb_none INTERFACE @@ -54147,15 +54147,15 @@ target_compile_options(GENERIC_G041G6UX_serial_none INTERFACE ) add_library(GENERIC_G041G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G041G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041G6UX_usb_none INTERFACE) target_compile_options(GENERIC_G041G6UX_usb_none INTERFACE @@ -54217,15 +54217,15 @@ target_compile_options(GENERIC_G041G8UX_serial_none INTERFACE ) add_library(GENERIC_G041G8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041G8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041G8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041G8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041G8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G041G8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041G8UX_usb_none INTERFACE) target_compile_options(GENERIC_G041G8UX_usb_none INTERFACE @@ -54287,15 +54287,15 @@ target_compile_options(GENERIC_G041J6MX_serial_none INTERFACE ) add_library(GENERIC_G041J6MX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041J6MX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041J6MX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041J6MX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041J6MX_usb_HID INTERFACE) target_compile_options(GENERIC_G041J6MX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041J6MX_usb_none INTERFACE) target_compile_options(GENERIC_G041J6MX_usb_none INTERFACE @@ -54357,15 +54357,15 @@ target_compile_options(GENERIC_G041K6TX_serial_none INTERFACE ) add_library(GENERIC_G041K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G041K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041K6TX_usb_none INTERFACE) target_compile_options(GENERIC_G041K6TX_usb_none INTERFACE @@ -54427,15 +54427,15 @@ target_compile_options(GENERIC_G041K6UX_serial_none INTERFACE ) add_library(GENERIC_G041K6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041K6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041K6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041K6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041K6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G041K6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041K6UX_usb_none INTERFACE) target_compile_options(GENERIC_G041K6UX_usb_none INTERFACE @@ -54497,15 +54497,15 @@ target_compile_options(GENERIC_G041K8TX_serial_none INTERFACE ) add_library(GENERIC_G041K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G041K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041K8TX_usb_none INTERFACE) target_compile_options(GENERIC_G041K8TX_usb_none INTERFACE @@ -54567,15 +54567,15 @@ target_compile_options(GENERIC_G041K8UX_serial_none INTERFACE ) add_library(GENERIC_G041K8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041K8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041K8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041K8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041K8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G041K8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041K8UX_usb_none INTERFACE) target_compile_options(GENERIC_G041K8UX_usb_none INTERFACE @@ -54637,15 +54637,15 @@ target_compile_options(GENERIC_G041Y8YX_serial_none INTERFACE ) add_library(GENERIC_G041Y8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_G041Y8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G041Y8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G041Y8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G041Y8YX_usb_HID INTERFACE) target_compile_options(GENERIC_G041Y8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G041Y8YX_usb_none INTERFACE) target_compile_options(GENERIC_G041Y8YX_usb_none INTERFACE @@ -54707,15 +54707,15 @@ target_compile_options(GENERIC_G050C6TX_serial_none INTERFACE ) add_library(GENERIC_G050C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G050C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G050C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G050C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G050C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G050C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G050C6TX_usb_none INTERFACE) target_compile_options(GENERIC_G050C6TX_usb_none INTERFACE @@ -54777,15 +54777,15 @@ target_compile_options(GENERIC_G050C8TX_serial_none INTERFACE ) add_library(GENERIC_G050C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G050C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G050C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G050C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G050C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G050C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G050C8TX_usb_none INTERFACE) target_compile_options(GENERIC_G050C8TX_usb_none INTERFACE @@ -54847,15 +54847,15 @@ target_compile_options(GENERIC_G050F6PX_serial_none INTERFACE ) add_library(GENERIC_G050F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G050F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G050F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G050F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G050F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_G050F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G050F6PX_usb_none INTERFACE) target_compile_options(GENERIC_G050F6PX_usb_none INTERFACE @@ -54917,15 +54917,15 @@ target_compile_options(GENERIC_G050K6TX_serial_none INTERFACE ) add_library(GENERIC_G050K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G050K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G050K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G050K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G050K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G050K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G050K6TX_usb_none INTERFACE) target_compile_options(GENERIC_G050K6TX_usb_none INTERFACE @@ -54987,15 +54987,15 @@ target_compile_options(GENERIC_G050K8TX_serial_none INTERFACE ) add_library(GENERIC_G050K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G050K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G050K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G050K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G050K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G050K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G050K8TX_usb_none INTERFACE) target_compile_options(GENERIC_G050K8TX_usb_none INTERFACE @@ -55057,15 +55057,15 @@ target_compile_options(GENERIC_G051C6TX_serial_none INTERFACE ) add_library(GENERIC_G051C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G051C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051C6TX_usb_none INTERFACE) target_compile_options(GENERIC_G051C6TX_usb_none INTERFACE @@ -55127,15 +55127,15 @@ target_compile_options(GENERIC_G051C6UX_serial_none INTERFACE ) add_library(GENERIC_G051C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G051C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051C6UX_usb_none INTERFACE) target_compile_options(GENERIC_G051C6UX_usb_none INTERFACE @@ -55197,15 +55197,15 @@ target_compile_options(GENERIC_G051C8TX_serial_none INTERFACE ) add_library(GENERIC_G051C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G051C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051C8TX_usb_none INTERFACE) target_compile_options(GENERIC_G051C8TX_usb_none INTERFACE @@ -55267,15 +55267,15 @@ target_compile_options(GENERIC_G051C8UX_serial_none INTERFACE ) add_library(GENERIC_G051C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G051C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051C8UX_usb_none INTERFACE) target_compile_options(GENERIC_G051C8UX_usb_none INTERFACE @@ -55337,15 +55337,15 @@ target_compile_options(GENERIC_G051F6PX_serial_none INTERFACE ) add_library(GENERIC_G051F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_G051F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051F6PX_usb_none INTERFACE) target_compile_options(GENERIC_G051F6PX_usb_none INTERFACE @@ -55407,15 +55407,15 @@ target_compile_options(GENERIC_G051F8PX_serial_none INTERFACE ) add_library(GENERIC_G051F8PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051F8PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051F8PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051F8PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051F8PX_usb_HID INTERFACE) target_compile_options(GENERIC_G051F8PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051F8PX_usb_none INTERFACE) target_compile_options(GENERIC_G051F8PX_usb_none INTERFACE @@ -55477,15 +55477,15 @@ target_compile_options(GENERIC_G051F8YX_serial_none INTERFACE ) add_library(GENERIC_G051F8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051F8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051F8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051F8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051F8YX_usb_HID INTERFACE) target_compile_options(GENERIC_G051F8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051F8YX_usb_none INTERFACE) target_compile_options(GENERIC_G051F8YX_usb_none INTERFACE @@ -55547,15 +55547,15 @@ target_compile_options(GENERIC_G051G6UX_serial_none INTERFACE ) add_library(GENERIC_G051G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G051G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051G6UX_usb_none INTERFACE) target_compile_options(GENERIC_G051G6UX_usb_none INTERFACE @@ -55617,15 +55617,15 @@ target_compile_options(GENERIC_G051G8UX_serial_none INTERFACE ) add_library(GENERIC_G051G8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051G8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051G8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051G8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051G8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G051G8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051G8UX_usb_none INTERFACE) target_compile_options(GENERIC_G051G8UX_usb_none INTERFACE @@ -55687,15 +55687,15 @@ target_compile_options(GENERIC_G051K6TX_serial_none INTERFACE ) add_library(GENERIC_G051K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G051K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051K6TX_usb_none INTERFACE) target_compile_options(GENERIC_G051K6TX_usb_none INTERFACE @@ -55757,15 +55757,15 @@ target_compile_options(GENERIC_G051K6UX_serial_none INTERFACE ) add_library(GENERIC_G051K6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051K6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051K6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051K6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051K6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G051K6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051K6UX_usb_none INTERFACE) target_compile_options(GENERIC_G051K6UX_usb_none INTERFACE @@ -55827,15 +55827,15 @@ target_compile_options(GENERIC_G051K8TX_serial_none INTERFACE ) add_library(GENERIC_G051K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G051K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051K8TX_usb_none INTERFACE) target_compile_options(GENERIC_G051K8TX_usb_none INTERFACE @@ -55897,15 +55897,15 @@ target_compile_options(GENERIC_G051K8UX_serial_none INTERFACE ) add_library(GENERIC_G051K8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G051K8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G051K8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G051K8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G051K8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G051K8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G051K8UX_usb_none INTERFACE) target_compile_options(GENERIC_G051K8UX_usb_none INTERFACE @@ -55967,15 +55967,15 @@ target_compile_options(GENERIC_G061C6TX_serial_none INTERFACE ) add_library(GENERIC_G061C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G061C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061C6TX_usb_none INTERFACE) target_compile_options(GENERIC_G061C6TX_usb_none INTERFACE @@ -56037,15 +56037,15 @@ target_compile_options(GENERIC_G061C6UX_serial_none INTERFACE ) add_library(GENERIC_G061C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G061C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061C6UX_usb_none INTERFACE) target_compile_options(GENERIC_G061C6UX_usb_none INTERFACE @@ -56107,15 +56107,15 @@ target_compile_options(GENERIC_G061C8TX_serial_none INTERFACE ) add_library(GENERIC_G061C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G061C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061C8TX_usb_none INTERFACE) target_compile_options(GENERIC_G061C8TX_usb_none INTERFACE @@ -56177,15 +56177,15 @@ target_compile_options(GENERIC_G061C8UX_serial_none INTERFACE ) add_library(GENERIC_G061C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G061C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061C8UX_usb_none INTERFACE) target_compile_options(GENERIC_G061C8UX_usb_none INTERFACE @@ -56247,15 +56247,15 @@ target_compile_options(GENERIC_G061F6PX_serial_none INTERFACE ) add_library(GENERIC_G061F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_G061F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061F6PX_usb_none INTERFACE) target_compile_options(GENERIC_G061F6PX_usb_none INTERFACE @@ -56317,15 +56317,15 @@ target_compile_options(GENERIC_G061F8PX_serial_none INTERFACE ) add_library(GENERIC_G061F8PX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061F8PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061F8PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061F8PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061F8PX_usb_HID INTERFACE) target_compile_options(GENERIC_G061F8PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061F8PX_usb_none INTERFACE) target_compile_options(GENERIC_G061F8PX_usb_none INTERFACE @@ -56387,15 +56387,15 @@ target_compile_options(GENERIC_G061F8YX_serial_none INTERFACE ) add_library(GENERIC_G061F8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061F8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061F8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061F8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061F8YX_usb_HID INTERFACE) target_compile_options(GENERIC_G061F8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061F8YX_usb_none INTERFACE) target_compile_options(GENERIC_G061F8YX_usb_none INTERFACE @@ -56457,15 +56457,15 @@ target_compile_options(GENERIC_G061G6UX_serial_none INTERFACE ) add_library(GENERIC_G061G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G061G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061G6UX_usb_none INTERFACE) target_compile_options(GENERIC_G061G6UX_usb_none INTERFACE @@ -56527,15 +56527,15 @@ target_compile_options(GENERIC_G061G8UX_serial_none INTERFACE ) add_library(GENERIC_G061G8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061G8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061G8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061G8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061G8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G061G8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061G8UX_usb_none INTERFACE) target_compile_options(GENERIC_G061G8UX_usb_none INTERFACE @@ -56597,15 +56597,15 @@ target_compile_options(GENERIC_G061K6TX_serial_none INTERFACE ) add_library(GENERIC_G061K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G061K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061K6TX_usb_none INTERFACE) target_compile_options(GENERIC_G061K6TX_usb_none INTERFACE @@ -56667,15 +56667,15 @@ target_compile_options(GENERIC_G061K6UX_serial_none INTERFACE ) add_library(GENERIC_G061K6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061K6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061K6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061K6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061K6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G061K6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061K6UX_usb_none INTERFACE) target_compile_options(GENERIC_G061K6UX_usb_none INTERFACE @@ -56737,15 +56737,15 @@ target_compile_options(GENERIC_G061K8TX_serial_none INTERFACE ) add_library(GENERIC_G061K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G061K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061K8TX_usb_none INTERFACE) target_compile_options(GENERIC_G061K8TX_usb_none INTERFACE @@ -56807,15 +56807,15 @@ target_compile_options(GENERIC_G061K8UX_serial_none INTERFACE ) add_library(GENERIC_G061K8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G061K8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G061K8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G061K8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G061K8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G061K8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G061K8UX_usb_none INTERFACE) target_compile_options(GENERIC_G061K8UX_usb_none INTERFACE @@ -56877,15 +56877,15 @@ target_compile_options(GENERIC_G070CBTX_serial_none INTERFACE ) add_library(GENERIC_G070CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G070CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G070CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G070CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G070CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G070CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G070CBTX_usb_none INTERFACE) target_compile_options(GENERIC_G070CBTX_usb_none INTERFACE @@ -56947,15 +56947,15 @@ target_compile_options(GENERIC_G070KBTX_serial_none INTERFACE ) add_library(GENERIC_G070KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G070KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G070KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G070KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G070KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G070KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G070KBTX_usb_none INTERFACE) target_compile_options(GENERIC_G070KBTX_usb_none INTERFACE @@ -57017,15 +57017,15 @@ target_compile_options(GENERIC_G070RBTX_serial_none INTERFACE ) add_library(GENERIC_G070RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G070RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G070RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G070RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G070RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G070RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G070RBTX_usb_none INTERFACE) target_compile_options(GENERIC_G070RBTX_usb_none INTERFACE @@ -57087,15 +57087,15 @@ target_compile_options(GENERIC_G071C6TX_serial_none INTERFACE ) add_library(GENERIC_G071C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G071C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071C6TX_usb_none INTERFACE) target_compile_options(GENERIC_G071C6TX_usb_none INTERFACE @@ -57157,15 +57157,15 @@ target_compile_options(GENERIC_G071C6UX_serial_none INTERFACE ) add_library(GENERIC_G071C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G071C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071C6UX_usb_none INTERFACE) target_compile_options(GENERIC_G071C6UX_usb_none INTERFACE @@ -57227,15 +57227,15 @@ target_compile_options(GENERIC_G071C8TX_serial_none INTERFACE ) add_library(GENERIC_G071C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G071C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071C8TX_usb_none INTERFACE) target_compile_options(GENERIC_G071C8TX_usb_none INTERFACE @@ -57297,15 +57297,15 @@ target_compile_options(GENERIC_G071C8UX_serial_none INTERFACE ) add_library(GENERIC_G071C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G071C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071C8UX_usb_none INTERFACE) target_compile_options(GENERIC_G071C8UX_usb_none INTERFACE @@ -57367,15 +57367,15 @@ target_compile_options(GENERIC_G071CBTX_serial_none INTERFACE ) add_library(GENERIC_G071CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G071CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071CBTX_usb_none INTERFACE) target_compile_options(GENERIC_G071CBTX_usb_none INTERFACE @@ -57437,15 +57437,15 @@ target_compile_options(GENERIC_G071CBUX_serial_none INTERFACE ) add_library(GENERIC_G071CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G071CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071CBUX_usb_none INTERFACE) target_compile_options(GENERIC_G071CBUX_usb_none INTERFACE @@ -57507,15 +57507,15 @@ target_compile_options(GENERIC_G071EBYX_serial_none INTERFACE ) add_library(GENERIC_G071EBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071EBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071EBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071EBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071EBYX_usb_HID INTERFACE) target_compile_options(GENERIC_G071EBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071EBYX_usb_none INTERFACE) target_compile_options(GENERIC_G071EBYX_usb_none INTERFACE @@ -57577,15 +57577,15 @@ target_compile_options(GENERIC_G071G6UX_serial_none INTERFACE ) add_library(GENERIC_G071G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G071G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071G6UX_usb_none INTERFACE) target_compile_options(GENERIC_G071G6UX_usb_none INTERFACE @@ -57647,15 +57647,15 @@ target_compile_options(GENERIC_G071G8UX_serial_none INTERFACE ) add_library(GENERIC_G071G8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071G8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071G8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071G8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071G8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G071G8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071G8UX_usb_none INTERFACE) target_compile_options(GENERIC_G071G8UX_usb_none INTERFACE @@ -57717,15 +57717,15 @@ target_compile_options(GENERIC_G071G8UXN_serial_none INTERFACE ) add_library(GENERIC_G071G8UXN_usb_CDC INTERFACE) target_compile_options(GENERIC_G071G8UXN_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071G8UXN_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071G8UXN_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071G8UXN_usb_HID INTERFACE) target_compile_options(GENERIC_G071G8UXN_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071G8UXN_usb_none INTERFACE) target_compile_options(GENERIC_G071G8UXN_usb_none INTERFACE @@ -57787,15 +57787,15 @@ target_compile_options(GENERIC_G071GBUX_serial_none INTERFACE ) add_library(GENERIC_G071GBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071GBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071GBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071GBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071GBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G071GBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071GBUX_usb_none INTERFACE) target_compile_options(GENERIC_G071GBUX_usb_none INTERFACE @@ -57857,15 +57857,15 @@ target_compile_options(GENERIC_G071GBUXN_serial_none INTERFACE ) add_library(GENERIC_G071GBUXN_usb_CDC INTERFACE) target_compile_options(GENERIC_G071GBUXN_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071GBUXN_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071GBUXN_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071GBUXN_usb_HID INTERFACE) target_compile_options(GENERIC_G071GBUXN_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071GBUXN_usb_none INTERFACE) target_compile_options(GENERIC_G071GBUXN_usb_none INTERFACE @@ -57927,15 +57927,15 @@ target_compile_options(GENERIC_G071K6TX_serial_none INTERFACE ) add_library(GENERIC_G071K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G071K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071K6TX_usb_none INTERFACE) target_compile_options(GENERIC_G071K6TX_usb_none INTERFACE @@ -57997,15 +57997,15 @@ target_compile_options(GENERIC_G071K6UX_serial_none INTERFACE ) add_library(GENERIC_G071K6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071K6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071K6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071K6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071K6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G071K6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071K6UX_usb_none INTERFACE) target_compile_options(GENERIC_G071K6UX_usb_none INTERFACE @@ -58067,15 +58067,15 @@ target_compile_options(GENERIC_G071K8TX_serial_none INTERFACE ) add_library(GENERIC_G071K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G071K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071K8TX_usb_none INTERFACE) target_compile_options(GENERIC_G071K8TX_usb_none INTERFACE @@ -58137,15 +58137,15 @@ target_compile_options(GENERIC_G071K8UX_serial_none INTERFACE ) add_library(GENERIC_G071K8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071K8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071K8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071K8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071K8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G071K8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071K8UX_usb_none INTERFACE) target_compile_options(GENERIC_G071K8UX_usb_none INTERFACE @@ -58207,15 +58207,15 @@ target_compile_options(GENERIC_G071KBTX_serial_none INTERFACE ) add_library(GENERIC_G071KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G071KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071KBTX_usb_none INTERFACE) target_compile_options(GENERIC_G071KBTX_usb_none INTERFACE @@ -58277,15 +58277,15 @@ target_compile_options(GENERIC_G071KBUX_serial_none INTERFACE ) add_library(GENERIC_G071KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G071KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071KBUX_usb_none INTERFACE) target_compile_options(GENERIC_G071KBUX_usb_none INTERFACE @@ -58347,15 +58347,15 @@ target_compile_options(GENERIC_G071R6TX_serial_none INTERFACE ) add_library(GENERIC_G071R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G071R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071R6TX_usb_none INTERFACE) target_compile_options(GENERIC_G071R6TX_usb_none INTERFACE @@ -58417,15 +58417,15 @@ target_compile_options(GENERIC_G071R8TX_serial_none INTERFACE ) add_library(GENERIC_G071R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G071R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071R8TX_usb_none INTERFACE) target_compile_options(GENERIC_G071R8TX_usb_none INTERFACE @@ -58487,15 +58487,15 @@ target_compile_options(GENERIC_G071RBIX_serial_none INTERFACE ) add_library(GENERIC_G071RBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071RBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071RBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071RBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071RBIX_usb_HID INTERFACE) target_compile_options(GENERIC_G071RBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071RBIX_usb_none INTERFACE) target_compile_options(GENERIC_G071RBIX_usb_none INTERFACE @@ -58557,15 +58557,15 @@ target_compile_options(GENERIC_G071RBTX_serial_none INTERFACE ) add_library(GENERIC_G071RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G071RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G071RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G071RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G071RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G071RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G071RBTX_usb_none INTERFACE) target_compile_options(GENERIC_G071RBTX_usb_none INTERFACE @@ -58627,15 +58627,15 @@ target_compile_options(GENERIC_G081CBTX_serial_none INTERFACE ) add_library(GENERIC_G081CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G081CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G081CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G081CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G081CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G081CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G081CBTX_usb_none INTERFACE) target_compile_options(GENERIC_G081CBTX_usb_none INTERFACE @@ -58697,15 +58697,15 @@ target_compile_options(GENERIC_G081CBUX_serial_none INTERFACE ) add_library(GENERIC_G081CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G081CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G081CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G081CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G081CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G081CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G081CBUX_usb_none INTERFACE) target_compile_options(GENERIC_G081CBUX_usb_none INTERFACE @@ -58767,15 +58767,15 @@ target_compile_options(GENERIC_G081EBYX_serial_none INTERFACE ) add_library(GENERIC_G081EBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_G081EBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G081EBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G081EBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G081EBYX_usb_HID INTERFACE) target_compile_options(GENERIC_G081EBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G081EBYX_usb_none INTERFACE) target_compile_options(GENERIC_G081EBYX_usb_none INTERFACE @@ -58837,15 +58837,15 @@ target_compile_options(GENERIC_G081GBUX_serial_none INTERFACE ) add_library(GENERIC_G081GBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G081GBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G081GBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G081GBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G081GBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G081GBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G081GBUX_usb_none INTERFACE) target_compile_options(GENERIC_G081GBUX_usb_none INTERFACE @@ -58907,15 +58907,15 @@ target_compile_options(GENERIC_G081GBUXN_serial_none INTERFACE ) add_library(GENERIC_G081GBUXN_usb_CDC INTERFACE) target_compile_options(GENERIC_G081GBUXN_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G081GBUXN_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G081GBUXN_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G081GBUXN_usb_HID INTERFACE) target_compile_options(GENERIC_G081GBUXN_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G081GBUXN_usb_none INTERFACE) target_compile_options(GENERIC_G081GBUXN_usb_none INTERFACE @@ -58977,15 +58977,15 @@ target_compile_options(GENERIC_G081KBTX_serial_none INTERFACE ) add_library(GENERIC_G081KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G081KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G081KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G081KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G081KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G081KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G081KBTX_usb_none INTERFACE) target_compile_options(GENERIC_G081KBTX_usb_none INTERFACE @@ -59047,15 +59047,15 @@ target_compile_options(GENERIC_G081KBUX_serial_none INTERFACE ) add_library(GENERIC_G081KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G081KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G081KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G081KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G081KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G081KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G081KBUX_usb_none INTERFACE) target_compile_options(GENERIC_G081KBUX_usb_none INTERFACE @@ -59117,15 +59117,15 @@ target_compile_options(GENERIC_G081RBIX_serial_none INTERFACE ) add_library(GENERIC_G081RBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G081RBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G081RBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G081RBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G081RBIX_usb_HID INTERFACE) target_compile_options(GENERIC_G081RBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G081RBIX_usb_none INTERFACE) target_compile_options(GENERIC_G081RBIX_usb_none INTERFACE @@ -59187,15 +59187,15 @@ target_compile_options(GENERIC_G081RBTX_serial_none INTERFACE ) add_library(GENERIC_G081RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G081RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G081RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G081RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G081RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G081RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G081RBTX_usb_none INTERFACE) target_compile_options(GENERIC_G081RBTX_usb_none INTERFACE @@ -59257,15 +59257,15 @@ target_compile_options(GENERIC_G0B0CETX_serial_none INTERFACE ) add_library(GENERIC_G0B0CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B0CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B0CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B0CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B0CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B0CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B0CETX_usb_none INTERFACE) target_compile_options(GENERIC_G0B0CETX_usb_none INTERFACE @@ -59327,15 +59327,15 @@ target_compile_options(GENERIC_G0B0RETX_serial_none INTERFACE ) add_library(GENERIC_G0B0RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B0RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B0RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B0RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B0RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B0RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B0RETX_usb_none INTERFACE) target_compile_options(GENERIC_G0B0RETX_usb_none INTERFACE @@ -59397,15 +59397,15 @@ target_compile_options(GENERIC_G0B0VETX_serial_none INTERFACE ) add_library(GENERIC_G0B0VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B0VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B0VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B0VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B0VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B0VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B0VETX_usb_none INTERFACE) target_compile_options(GENERIC_G0B0VETX_usb_none INTERFACE @@ -59467,15 +59467,15 @@ target_compile_options(GENERIC_G0B1CBTX_serial_none INTERFACE ) add_library(GENERIC_G0B1CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1CBTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1CBTX_usb_none INTERFACE @@ -59537,15 +59537,15 @@ target_compile_options(GENERIC_G0B1CBUX_serial_none INTERFACE ) add_library(GENERIC_G0B1CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1CBUX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1CBUX_usb_none INTERFACE @@ -59607,15 +59607,15 @@ target_compile_options(GENERIC_G0B1CCTX_serial_none INTERFACE ) add_library(GENERIC_G0B1CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1CCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1CCTX_usb_none INTERFACE @@ -59677,15 +59677,15 @@ target_compile_options(GENERIC_G0B1CCUX_serial_none INTERFACE ) add_library(GENERIC_G0B1CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1CCUX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1CCUX_usb_none INTERFACE @@ -59747,15 +59747,15 @@ target_compile_options(GENERIC_G0B1CETX_serial_none INTERFACE ) add_library(GENERIC_G0B1CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1CETX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1CETX_usb_none INTERFACE @@ -59817,15 +59817,15 @@ target_compile_options(GENERIC_G0B1CEUX_serial_none INTERFACE ) add_library(GENERIC_G0B1CEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1CEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1CEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1CEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1CEUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1CEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1CEUX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1CEUX_usb_none INTERFACE @@ -59887,15 +59887,15 @@ target_compile_options(GENERIC_G0B1KBTX_serial_none INTERFACE ) add_library(GENERIC_G0B1KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1KBTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1KBTX_usb_none INTERFACE @@ -59957,15 +59957,15 @@ target_compile_options(GENERIC_G0B1KBUX_serial_none INTERFACE ) add_library(GENERIC_G0B1KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1KBUX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1KBUX_usb_none INTERFACE @@ -60027,15 +60027,15 @@ target_compile_options(GENERIC_G0B1KCTX_serial_none INTERFACE ) add_library(GENERIC_G0B1KCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1KCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1KCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1KCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1KCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1KCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1KCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1KCTX_usb_none INTERFACE @@ -60097,15 +60097,15 @@ target_compile_options(GENERIC_G0B1KCUX_serial_none INTERFACE ) add_library(GENERIC_G0B1KCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1KCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1KCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1KCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1KCUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1KCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1KCUX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1KCUX_usb_none INTERFACE @@ -60167,15 +60167,15 @@ target_compile_options(GENERIC_G0B1KETX_serial_none INTERFACE ) add_library(GENERIC_G0B1KETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1KETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1KETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1KETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1KETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1KETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1KETX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1KETX_usb_none INTERFACE @@ -60237,15 +60237,15 @@ target_compile_options(GENERIC_G0B1KEUX_serial_none INTERFACE ) add_library(GENERIC_G0B1KEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1KEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1KEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1KEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1KEUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1KEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1KEUX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1KEUX_usb_none INTERFACE @@ -60307,15 +60307,15 @@ target_compile_options(GENERIC_G0B1MBTX_serial_none INTERFACE ) add_library(GENERIC_G0B1MBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1MBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1MBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1MBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1MBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1MBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1MBTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1MBTX_usb_none INTERFACE @@ -60377,15 +60377,15 @@ target_compile_options(GENERIC_G0B1MCTX_serial_none INTERFACE ) add_library(GENERIC_G0B1MCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1MCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1MCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1MCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1MCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1MCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1MCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1MCTX_usb_none INTERFACE @@ -60447,15 +60447,15 @@ target_compile_options(GENERIC_G0B1METX_serial_none INTERFACE ) add_library(GENERIC_G0B1METX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1METX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1METX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1METX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1METX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1METX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1METX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1METX_usb_none INTERFACE @@ -60517,15 +60517,15 @@ target_compile_options(GENERIC_G0B1NEYX_serial_none INTERFACE ) add_library(GENERIC_G0B1NEYX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1NEYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1NEYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1NEYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1NEYX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1NEYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1NEYX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1NEYX_usb_none INTERFACE @@ -60587,15 +60587,15 @@ target_compile_options(GENERIC_G0B1RBTX_serial_none INTERFACE ) add_library(GENERIC_G0B1RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1RBTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1RBTX_usb_none INTERFACE @@ -60657,15 +60657,15 @@ target_compile_options(GENERIC_G0B1RCTX_serial_none INTERFACE ) add_library(GENERIC_G0B1RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1RCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1RCTX_usb_none INTERFACE @@ -60727,15 +60727,15 @@ target_compile_options(GENERIC_G0B1RETX_serial_none INTERFACE ) add_library(GENERIC_G0B1RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1RETX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1RETX_usb_none INTERFACE @@ -60797,15 +60797,15 @@ target_compile_options(GENERIC_G0B1VBIX_serial_none INTERFACE ) add_library(GENERIC_G0B1VBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1VBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1VBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1VBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1VBIX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1VBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1VBIX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1VBIX_usb_none INTERFACE @@ -60867,15 +60867,15 @@ target_compile_options(GENERIC_G0B1VBTX_serial_none INTERFACE ) add_library(GENERIC_G0B1VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1VBTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1VBTX_usb_none INTERFACE @@ -60937,15 +60937,15 @@ target_compile_options(GENERIC_G0B1VCIX_serial_none INTERFACE ) add_library(GENERIC_G0B1VCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1VCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1VCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1VCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1VCIX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1VCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1VCIX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1VCIX_usb_none INTERFACE @@ -61007,15 +61007,15 @@ target_compile_options(GENERIC_G0B1VCTX_serial_none INTERFACE ) add_library(GENERIC_G0B1VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1VCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1VCTX_usb_none INTERFACE @@ -61077,15 +61077,15 @@ target_compile_options(GENERIC_G0B1VEIX_serial_none INTERFACE ) add_library(GENERIC_G0B1VEIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1VEIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1VEIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1VEIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1VEIX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1VEIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1VEIX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1VEIX_usb_none INTERFACE @@ -61147,15 +61147,15 @@ target_compile_options(GENERIC_G0B1VETX_serial_none INTERFACE ) add_library(GENERIC_G0B1VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0B1VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0B1VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0B1VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0B1VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0B1VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0B1VETX_usb_none INTERFACE) target_compile_options(GENERIC_G0B1VETX_usb_none INTERFACE @@ -61217,15 +61217,15 @@ target_compile_options(GENERIC_G0C1CCTX_serial_none INTERFACE ) add_library(GENERIC_G0C1CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1CCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1CCTX_usb_none INTERFACE @@ -61287,15 +61287,15 @@ target_compile_options(GENERIC_G0C1CCUX_serial_none INTERFACE ) add_library(GENERIC_G0C1CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1CCUX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1CCUX_usb_none INTERFACE @@ -61357,15 +61357,15 @@ target_compile_options(GENERIC_G0C1CETX_serial_none INTERFACE ) add_library(GENERIC_G0C1CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1CETX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1CETX_usb_none INTERFACE @@ -61427,15 +61427,15 @@ target_compile_options(GENERIC_G0C1CEUX_serial_none INTERFACE ) add_library(GENERIC_G0C1CEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1CEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1CEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1CEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1CEUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1CEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1CEUX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1CEUX_usb_none INTERFACE @@ -61497,15 +61497,15 @@ target_compile_options(GENERIC_G0C1KCTX_serial_none INTERFACE ) add_library(GENERIC_G0C1KCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1KCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1KCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1KCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1KCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1KCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1KCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1KCTX_usb_none INTERFACE @@ -61567,15 +61567,15 @@ target_compile_options(GENERIC_G0C1KCUX_serial_none INTERFACE ) add_library(GENERIC_G0C1KCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1KCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1KCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1KCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1KCUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1KCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1KCUX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1KCUX_usb_none INTERFACE @@ -61637,15 +61637,15 @@ target_compile_options(GENERIC_G0C1KETX_serial_none INTERFACE ) add_library(GENERIC_G0C1KETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1KETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1KETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1KETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1KETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1KETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1KETX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1KETX_usb_none INTERFACE @@ -61707,15 +61707,15 @@ target_compile_options(GENERIC_G0C1KEUX_serial_none INTERFACE ) add_library(GENERIC_G0C1KEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1KEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1KEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1KEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1KEUX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1KEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1KEUX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1KEUX_usb_none INTERFACE @@ -61777,15 +61777,15 @@ target_compile_options(GENERIC_G0C1MCTX_serial_none INTERFACE ) add_library(GENERIC_G0C1MCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1MCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1MCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1MCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1MCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1MCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1MCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1MCTX_usb_none INTERFACE @@ -61847,15 +61847,15 @@ target_compile_options(GENERIC_G0C1METX_serial_none INTERFACE ) add_library(GENERIC_G0C1METX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1METX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1METX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1METX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1METX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1METX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1METX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1METX_usb_none INTERFACE @@ -61917,15 +61917,15 @@ target_compile_options(GENERIC_G0C1NEYX_serial_none INTERFACE ) add_library(GENERIC_G0C1NEYX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1NEYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1NEYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1NEYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1NEYX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1NEYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1NEYX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1NEYX_usb_none INTERFACE @@ -61987,15 +61987,15 @@ target_compile_options(GENERIC_G0C1RCTX_serial_none INTERFACE ) add_library(GENERIC_G0C1RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1RCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1RCTX_usb_none INTERFACE @@ -62057,15 +62057,15 @@ target_compile_options(GENERIC_G0C1RETX_serial_none INTERFACE ) add_library(GENERIC_G0C1RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1RETX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1RETX_usb_none INTERFACE @@ -62127,15 +62127,15 @@ target_compile_options(GENERIC_G0C1VCIX_serial_none INTERFACE ) add_library(GENERIC_G0C1VCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1VCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1VCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1VCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1VCIX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1VCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1VCIX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1VCIX_usb_none INTERFACE @@ -62197,15 +62197,15 @@ target_compile_options(GENERIC_G0C1VCTX_serial_none INTERFACE ) add_library(GENERIC_G0C1VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1VCTX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1VCTX_usb_none INTERFACE @@ -62267,15 +62267,15 @@ target_compile_options(GENERIC_G0C1VEIX_serial_none INTERFACE ) add_library(GENERIC_G0C1VEIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1VEIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1VEIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1VEIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1VEIX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1VEIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1VEIX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1VEIX_usb_none INTERFACE @@ -62337,15 +62337,15 @@ target_compile_options(GENERIC_G0C1VETX_serial_none INTERFACE ) add_library(GENERIC_G0C1VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G0C1VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G0C1VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G0C1VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G0C1VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G0C1VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G0C1VETX_usb_none INTERFACE) target_compile_options(GENERIC_G0C1VETX_usb_none INTERFACE @@ -62407,15 +62407,15 @@ target_compile_options(GENERIC_G431C6TX_serial_none INTERFACE ) add_library(GENERIC_G431C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431C6TX_usb_none INTERFACE) target_compile_options(GENERIC_G431C6TX_usb_none INTERFACE @@ -62489,15 +62489,15 @@ target_compile_options(GENERIC_G431C6UX_serial_none INTERFACE ) add_library(GENERIC_G431C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G431C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431C6UX_usb_none INTERFACE) target_compile_options(GENERIC_G431C6UX_usb_none INTERFACE @@ -62571,15 +62571,15 @@ target_compile_options(GENERIC_G431C8TX_serial_none INTERFACE ) add_library(GENERIC_G431C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431C8TX_usb_none INTERFACE) target_compile_options(GENERIC_G431C8TX_usb_none INTERFACE @@ -62653,15 +62653,15 @@ target_compile_options(GENERIC_G431C8UX_serial_none INTERFACE ) add_library(GENERIC_G431C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G431C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431C8UX_usb_none INTERFACE) target_compile_options(GENERIC_G431C8UX_usb_none INTERFACE @@ -62735,15 +62735,15 @@ target_compile_options(GENERIC_G431CBTX_serial_none INTERFACE ) add_library(GENERIC_G431CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G431CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431CBTX_usb_none INTERFACE) target_compile_options(GENERIC_G431CBTX_usb_none INTERFACE @@ -62817,15 +62817,15 @@ target_compile_options(GENERIC_G431CBUX_serial_none INTERFACE ) add_library(GENERIC_G431CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G431CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431CBUX_usb_none INTERFACE) target_compile_options(GENERIC_G431CBUX_usb_none INTERFACE @@ -62899,15 +62899,15 @@ target_compile_options(GENERIC_G431K6TX_serial_none INTERFACE ) add_library(GENERIC_G431K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431K6TX_usb_none INTERFACE) target_compile_options(GENERIC_G431K6TX_usb_none INTERFACE @@ -62981,15 +62981,15 @@ target_compile_options(GENERIC_G431K6UX_serial_none INTERFACE ) add_library(GENERIC_G431K6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431K6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431K6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431K6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431K6UX_usb_HID INTERFACE) target_compile_options(GENERIC_G431K6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431K6UX_usb_none INTERFACE) target_compile_options(GENERIC_G431K6UX_usb_none INTERFACE @@ -63063,15 +63063,15 @@ target_compile_options(GENERIC_G431K8TX_serial_none INTERFACE ) add_library(GENERIC_G431K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431K8TX_usb_none INTERFACE) target_compile_options(GENERIC_G431K8TX_usb_none INTERFACE @@ -63145,15 +63145,15 @@ target_compile_options(GENERIC_G431K8UX_serial_none INTERFACE ) add_library(GENERIC_G431K8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431K8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431K8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431K8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431K8UX_usb_HID INTERFACE) target_compile_options(GENERIC_G431K8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431K8UX_usb_none INTERFACE) target_compile_options(GENERIC_G431K8UX_usb_none INTERFACE @@ -63227,15 +63227,15 @@ target_compile_options(GENERIC_G431KBTX_serial_none INTERFACE ) add_library(GENERIC_G431KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G431KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431KBTX_usb_none INTERFACE) target_compile_options(GENERIC_G431KBTX_usb_none INTERFACE @@ -63309,15 +63309,15 @@ target_compile_options(GENERIC_G431KBUX_serial_none INTERFACE ) add_library(GENERIC_G431KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G431KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431KBUX_usb_none INTERFACE) target_compile_options(GENERIC_G431KBUX_usb_none INTERFACE @@ -63391,15 +63391,15 @@ target_compile_options(GENERIC_G431M6TX_serial_none INTERFACE ) add_library(GENERIC_G431M6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431M6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431M6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431M6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431M6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431M6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431M6TX_usb_none INTERFACE) target_compile_options(GENERIC_G431M6TX_usb_none INTERFACE @@ -63473,15 +63473,15 @@ target_compile_options(GENERIC_G431M8TX_serial_none INTERFACE ) add_library(GENERIC_G431M8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431M8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431M8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431M8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431M8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431M8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431M8TX_usb_none INTERFACE) target_compile_options(GENERIC_G431M8TX_usb_none INTERFACE @@ -63555,15 +63555,15 @@ target_compile_options(GENERIC_G431MBTX_serial_none INTERFACE ) add_library(GENERIC_G431MBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431MBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431MBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431MBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431MBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G431MBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431MBTX_usb_none INTERFACE) target_compile_options(GENERIC_G431MBTX_usb_none INTERFACE @@ -63637,15 +63637,15 @@ target_compile_options(GENERIC_G431R6IX_serial_none INTERFACE ) add_library(GENERIC_G431R6IX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431R6IX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431R6IX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431R6IX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431R6IX_usb_HID INTERFACE) target_compile_options(GENERIC_G431R6IX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431R6IX_usb_none INTERFACE) target_compile_options(GENERIC_G431R6IX_usb_none INTERFACE @@ -63719,15 +63719,15 @@ target_compile_options(GENERIC_G431R6TX_serial_none INTERFACE ) add_library(GENERIC_G431R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431R6TX_usb_none INTERFACE) target_compile_options(GENERIC_G431R6TX_usb_none INTERFACE @@ -63801,15 +63801,15 @@ target_compile_options(GENERIC_G431R8IX_serial_none INTERFACE ) add_library(GENERIC_G431R8IX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431R8IX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431R8IX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431R8IX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431R8IX_usb_HID INTERFACE) target_compile_options(GENERIC_G431R8IX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431R8IX_usb_none INTERFACE) target_compile_options(GENERIC_G431R8IX_usb_none INTERFACE @@ -63883,15 +63883,15 @@ target_compile_options(GENERIC_G431R8TX_serial_none INTERFACE ) add_library(GENERIC_G431R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431R8TX_usb_none INTERFACE) target_compile_options(GENERIC_G431R8TX_usb_none INTERFACE @@ -63965,15 +63965,15 @@ target_compile_options(GENERIC_G431RBIX_serial_none INTERFACE ) add_library(GENERIC_G431RBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431RBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431RBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431RBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431RBIX_usb_HID INTERFACE) target_compile_options(GENERIC_G431RBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431RBIX_usb_none INTERFACE) target_compile_options(GENERIC_G431RBIX_usb_none INTERFACE @@ -64047,15 +64047,15 @@ target_compile_options(GENERIC_G431RBTX_serial_none INTERFACE ) add_library(GENERIC_G431RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G431RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431RBTX_usb_none INTERFACE) target_compile_options(GENERIC_G431RBTX_usb_none INTERFACE @@ -64129,15 +64129,15 @@ target_compile_options(GENERIC_G431V6TX_serial_none INTERFACE ) add_library(GENERIC_G431V6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431V6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431V6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431V6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431V6TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431V6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431V6TX_usb_none INTERFACE) target_compile_options(GENERIC_G431V6TX_usb_none INTERFACE @@ -64211,15 +64211,15 @@ target_compile_options(GENERIC_G431V8TX_serial_none INTERFACE ) add_library(GENERIC_G431V8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431V8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431V8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431V8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431V8TX_usb_HID INTERFACE) target_compile_options(GENERIC_G431V8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431V8TX_usb_none INTERFACE) target_compile_options(GENERIC_G431V8TX_usb_none INTERFACE @@ -64293,15 +64293,15 @@ target_compile_options(GENERIC_G431VBTX_serial_none INTERFACE ) add_library(GENERIC_G431VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G431VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G431VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G431VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G431VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G431VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G431VBTX_usb_none INTERFACE) target_compile_options(GENERIC_G431VBTX_usb_none INTERFACE @@ -64375,15 +64375,15 @@ target_compile_options(GENERIC_G441CBTX_serial_none INTERFACE ) add_library(GENERIC_G441CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G441CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G441CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G441CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G441CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G441CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G441CBTX_usb_none INTERFACE) target_compile_options(GENERIC_G441CBTX_usb_none INTERFACE @@ -64457,15 +64457,15 @@ target_compile_options(GENERIC_G441CBUX_serial_none INTERFACE ) add_library(GENERIC_G441CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G441CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G441CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G441CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G441CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G441CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G441CBUX_usb_none INTERFACE) target_compile_options(GENERIC_G441CBUX_usb_none INTERFACE @@ -64539,15 +64539,15 @@ target_compile_options(GENERIC_G441KBTX_serial_none INTERFACE ) add_library(GENERIC_G441KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G441KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G441KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G441KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G441KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G441KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G441KBTX_usb_none INTERFACE) target_compile_options(GENERIC_G441KBTX_usb_none INTERFACE @@ -64621,15 +64621,15 @@ target_compile_options(GENERIC_G441KBUX_serial_none INTERFACE ) add_library(GENERIC_G441KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G441KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G441KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G441KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G441KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_G441KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G441KBUX_usb_none INTERFACE) target_compile_options(GENERIC_G441KBUX_usb_none INTERFACE @@ -64703,15 +64703,15 @@ target_compile_options(GENERIC_G441MBTX_serial_none INTERFACE ) add_library(GENERIC_G441MBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G441MBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G441MBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G441MBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G441MBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G441MBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G441MBTX_usb_none INTERFACE) target_compile_options(GENERIC_G441MBTX_usb_none INTERFACE @@ -64785,15 +64785,15 @@ target_compile_options(GENERIC_G441RBIX_serial_none INTERFACE ) add_library(GENERIC_G441RBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G441RBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G441RBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G441RBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G441RBIX_usb_HID INTERFACE) target_compile_options(GENERIC_G441RBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G441RBIX_usb_none INTERFACE) target_compile_options(GENERIC_G441RBIX_usb_none INTERFACE @@ -64867,15 +64867,15 @@ target_compile_options(GENERIC_G441RBTX_serial_none INTERFACE ) add_library(GENERIC_G441RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G441RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G441RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G441RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G441RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G441RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G441RBTX_usb_none INTERFACE) target_compile_options(GENERIC_G441RBTX_usb_none INTERFACE @@ -64949,15 +64949,15 @@ target_compile_options(GENERIC_G441VBTX_serial_none INTERFACE ) add_library(GENERIC_G441VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G441VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G441VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G441VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G441VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G441VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G441VBTX_usb_none INTERFACE) target_compile_options(GENERIC_G441VBTX_usb_none INTERFACE @@ -65031,15 +65031,15 @@ target_compile_options(GENERIC_G471CCTX_serial_none INTERFACE ) add_library(GENERIC_G471CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G471CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471CCTX_usb_none INTERFACE) target_compile_options(GENERIC_G471CCTX_usb_none INTERFACE @@ -65113,15 +65113,15 @@ target_compile_options(GENERIC_G471CETX_serial_none INTERFACE ) add_library(GENERIC_G471CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G471CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471CETX_usb_none INTERFACE) target_compile_options(GENERIC_G471CETX_usb_none INTERFACE @@ -65195,15 +65195,15 @@ target_compile_options(GENERIC_G471MCTX_serial_none INTERFACE ) add_library(GENERIC_G471MCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471MCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471MCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471MCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471MCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G471MCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471MCTX_usb_none INTERFACE) target_compile_options(GENERIC_G471MCTX_usb_none INTERFACE @@ -65277,15 +65277,15 @@ target_compile_options(GENERIC_G471METX_serial_none INTERFACE ) add_library(GENERIC_G471METX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471METX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471METX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471METX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471METX_usb_HID INTERFACE) target_compile_options(GENERIC_G471METX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471METX_usb_none INTERFACE) target_compile_options(GENERIC_G471METX_usb_none INTERFACE @@ -65359,15 +65359,15 @@ target_compile_options(GENERIC_G471QCTX_serial_none INTERFACE ) add_library(GENERIC_G471QCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471QCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471QCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471QCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471QCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G471QCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471QCTX_usb_none INTERFACE) target_compile_options(GENERIC_G471QCTX_usb_none INTERFACE @@ -65441,15 +65441,15 @@ target_compile_options(GENERIC_G471QETX_serial_none INTERFACE ) add_library(GENERIC_G471QETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471QETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471QETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471QETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471QETX_usb_HID INTERFACE) target_compile_options(GENERIC_G471QETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471QETX_usb_none INTERFACE) target_compile_options(GENERIC_G471QETX_usb_none INTERFACE @@ -65523,15 +65523,15 @@ target_compile_options(GENERIC_G471RCTX_serial_none INTERFACE ) add_library(GENERIC_G471RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G471RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471RCTX_usb_none INTERFACE) target_compile_options(GENERIC_G471RCTX_usb_none INTERFACE @@ -65605,15 +65605,15 @@ target_compile_options(GENERIC_G471RETX_serial_none INTERFACE ) add_library(GENERIC_G471RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G471RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471RETX_usb_none INTERFACE) target_compile_options(GENERIC_G471RETX_usb_none INTERFACE @@ -65687,15 +65687,15 @@ target_compile_options(GENERIC_G471VCHX_serial_none INTERFACE ) add_library(GENERIC_G471VCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471VCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471VCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471VCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471VCHX_usb_HID INTERFACE) target_compile_options(GENERIC_G471VCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471VCHX_usb_none INTERFACE) target_compile_options(GENERIC_G471VCHX_usb_none INTERFACE @@ -65769,15 +65769,15 @@ target_compile_options(GENERIC_G471VCIX_serial_none INTERFACE ) add_library(GENERIC_G471VCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471VCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471VCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471VCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471VCIX_usb_HID INTERFACE) target_compile_options(GENERIC_G471VCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471VCIX_usb_none INTERFACE) target_compile_options(GENERIC_G471VCIX_usb_none INTERFACE @@ -65851,15 +65851,15 @@ target_compile_options(GENERIC_G471VCTX_serial_none INTERFACE ) add_library(GENERIC_G471VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G471VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471VCTX_usb_none INTERFACE) target_compile_options(GENERIC_G471VCTX_usb_none INTERFACE @@ -65933,15 +65933,15 @@ target_compile_options(GENERIC_G471VEHX_serial_none INTERFACE ) add_library(GENERIC_G471VEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471VEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471VEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471VEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471VEHX_usb_HID INTERFACE) target_compile_options(GENERIC_G471VEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471VEHX_usb_none INTERFACE) target_compile_options(GENERIC_G471VEHX_usb_none INTERFACE @@ -66015,15 +66015,15 @@ target_compile_options(GENERIC_G471VEIX_serial_none INTERFACE ) add_library(GENERIC_G471VEIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471VEIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471VEIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471VEIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471VEIX_usb_HID INTERFACE) target_compile_options(GENERIC_G471VEIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471VEIX_usb_none INTERFACE) target_compile_options(GENERIC_G471VEIX_usb_none INTERFACE @@ -66097,15 +66097,15 @@ target_compile_options(GENERIC_G471VETX_serial_none INTERFACE ) add_library(GENERIC_G471VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G471VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G471VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G471VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G471VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G471VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G471VETX_usb_none INTERFACE) target_compile_options(GENERIC_G471VETX_usb_none INTERFACE @@ -66179,15 +66179,15 @@ target_compile_options(GENERIC_G473CBTX_serial_none INTERFACE ) add_library(GENERIC_G473CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473CBTX_usb_none INTERFACE) target_compile_options(GENERIC_G473CBTX_usb_none INTERFACE @@ -66261,15 +66261,15 @@ target_compile_options(GENERIC_G473CCTX_serial_none INTERFACE ) add_library(GENERIC_G473CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473CCTX_usb_none INTERFACE) target_compile_options(GENERIC_G473CCTX_usb_none INTERFACE @@ -66343,15 +66343,15 @@ target_compile_options(GENERIC_G473CETX_serial_none INTERFACE ) add_library(GENERIC_G473CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G473CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473CETX_usb_none INTERFACE) target_compile_options(GENERIC_G473CETX_usb_none INTERFACE @@ -66425,15 +66425,15 @@ target_compile_options(GENERIC_G473MBTX_serial_none INTERFACE ) add_library(GENERIC_G473MBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473MBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473MBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473MBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473MBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473MBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473MBTX_usb_none INTERFACE) target_compile_options(GENERIC_G473MBTX_usb_none INTERFACE @@ -66507,15 +66507,15 @@ target_compile_options(GENERIC_G473MCTX_serial_none INTERFACE ) add_library(GENERIC_G473MCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473MCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473MCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473MCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473MCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473MCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473MCTX_usb_none INTERFACE) target_compile_options(GENERIC_G473MCTX_usb_none INTERFACE @@ -66589,15 +66589,15 @@ target_compile_options(GENERIC_G473METX_serial_none INTERFACE ) add_library(GENERIC_G473METX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473METX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473METX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473METX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473METX_usb_HID INTERFACE) target_compile_options(GENERIC_G473METX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473METX_usb_none INTERFACE) target_compile_options(GENERIC_G473METX_usb_none INTERFACE @@ -66671,15 +66671,15 @@ target_compile_options(GENERIC_G473PBIX_serial_none INTERFACE ) add_library(GENERIC_G473PBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473PBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473PBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473PBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473PBIX_usb_HID INTERFACE) target_compile_options(GENERIC_G473PBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473PBIX_usb_none INTERFACE) target_compile_options(GENERIC_G473PBIX_usb_none INTERFACE @@ -66753,15 +66753,15 @@ target_compile_options(GENERIC_G473PCIX_serial_none INTERFACE ) add_library(GENERIC_G473PCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473PCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473PCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473PCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473PCIX_usb_HID INTERFACE) target_compile_options(GENERIC_G473PCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473PCIX_usb_none INTERFACE) target_compile_options(GENERIC_G473PCIX_usb_none INTERFACE @@ -66835,15 +66835,15 @@ target_compile_options(GENERIC_G473PEIX_serial_none INTERFACE ) add_library(GENERIC_G473PEIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473PEIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473PEIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473PEIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473PEIX_usb_HID INTERFACE) target_compile_options(GENERIC_G473PEIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473PEIX_usb_none INTERFACE) target_compile_options(GENERIC_G473PEIX_usb_none INTERFACE @@ -66917,15 +66917,15 @@ target_compile_options(GENERIC_G473QBTX_serial_none INTERFACE ) add_library(GENERIC_G473QBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473QBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473QBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473QBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473QBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473QBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473QBTX_usb_none INTERFACE) target_compile_options(GENERIC_G473QBTX_usb_none INTERFACE @@ -66999,15 +66999,15 @@ target_compile_options(GENERIC_G473QCTX_serial_none INTERFACE ) add_library(GENERIC_G473QCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473QCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473QCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473QCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473QCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473QCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473QCTX_usb_none INTERFACE) target_compile_options(GENERIC_G473QCTX_usb_none INTERFACE @@ -67081,15 +67081,15 @@ target_compile_options(GENERIC_G473QETX_serial_none INTERFACE ) add_library(GENERIC_G473QETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473QETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473QETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473QETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473QETX_usb_HID INTERFACE) target_compile_options(GENERIC_G473QETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473QETX_usb_none INTERFACE) target_compile_options(GENERIC_G473QETX_usb_none INTERFACE @@ -67163,15 +67163,15 @@ target_compile_options(GENERIC_G473RBTX_serial_none INTERFACE ) add_library(GENERIC_G473RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473RBTX_usb_none INTERFACE) target_compile_options(GENERIC_G473RBTX_usb_none INTERFACE @@ -67245,15 +67245,15 @@ target_compile_options(GENERIC_G473RCTX_serial_none INTERFACE ) add_library(GENERIC_G473RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473RCTX_usb_none INTERFACE) target_compile_options(GENERIC_G473RCTX_usb_none INTERFACE @@ -67327,15 +67327,15 @@ target_compile_options(GENERIC_G473RETX_serial_none INTERFACE ) add_library(GENERIC_G473RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G473RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473RETX_usb_none INTERFACE) target_compile_options(GENERIC_G473RETX_usb_none INTERFACE @@ -67409,15 +67409,15 @@ target_compile_options(GENERIC_G473VBHX_serial_none INTERFACE ) add_library(GENERIC_G473VBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473VBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473VBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473VBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473VBHX_usb_HID INTERFACE) target_compile_options(GENERIC_G473VBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473VBHX_usb_none INTERFACE) target_compile_options(GENERIC_G473VBHX_usb_none INTERFACE @@ -67491,15 +67491,15 @@ target_compile_options(GENERIC_G473VBTX_serial_none INTERFACE ) add_library(GENERIC_G473VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473VBTX_usb_none INTERFACE) target_compile_options(GENERIC_G473VBTX_usb_none INTERFACE @@ -67573,15 +67573,15 @@ target_compile_options(GENERIC_G473VCHX_serial_none INTERFACE ) add_library(GENERIC_G473VCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473VCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473VCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473VCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473VCHX_usb_HID INTERFACE) target_compile_options(GENERIC_G473VCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473VCHX_usb_none INTERFACE) target_compile_options(GENERIC_G473VCHX_usb_none INTERFACE @@ -67655,15 +67655,15 @@ target_compile_options(GENERIC_G473VCTX_serial_none INTERFACE ) add_library(GENERIC_G473VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G473VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473VCTX_usb_none INTERFACE) target_compile_options(GENERIC_G473VCTX_usb_none INTERFACE @@ -67737,15 +67737,15 @@ target_compile_options(GENERIC_G473VEHX_serial_none INTERFACE ) add_library(GENERIC_G473VEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473VEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473VEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473VEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473VEHX_usb_HID INTERFACE) target_compile_options(GENERIC_G473VEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473VEHX_usb_none INTERFACE) target_compile_options(GENERIC_G473VEHX_usb_none INTERFACE @@ -67819,15 +67819,15 @@ target_compile_options(GENERIC_G473VETX_serial_none INTERFACE ) add_library(GENERIC_G473VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G473VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G473VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G473VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G473VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G473VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G473VETX_usb_none INTERFACE) target_compile_options(GENERIC_G473VETX_usb_none INTERFACE @@ -67901,15 +67901,15 @@ target_compile_options(GENERIC_G474CBTX_serial_none INTERFACE ) add_library(GENERIC_G474CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474CBTX_usb_none INTERFACE) target_compile_options(GENERIC_G474CBTX_usb_none INTERFACE @@ -67983,15 +67983,15 @@ target_compile_options(GENERIC_G474CCTX_serial_none INTERFACE ) add_library(GENERIC_G474CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474CCTX_usb_none INTERFACE) target_compile_options(GENERIC_G474CCTX_usb_none INTERFACE @@ -68065,15 +68065,15 @@ target_compile_options(GENERIC_G474CETX_serial_none INTERFACE ) add_library(GENERIC_G474CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G474CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474CETX_usb_none INTERFACE) target_compile_options(GENERIC_G474CETX_usb_none INTERFACE @@ -68147,15 +68147,15 @@ target_compile_options(GENERIC_G474MBTX_serial_none INTERFACE ) add_library(GENERIC_G474MBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474MBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474MBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474MBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474MBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474MBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474MBTX_usb_none INTERFACE) target_compile_options(GENERIC_G474MBTX_usb_none INTERFACE @@ -68229,15 +68229,15 @@ target_compile_options(GENERIC_G474MCTX_serial_none INTERFACE ) add_library(GENERIC_G474MCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474MCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474MCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474MCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474MCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474MCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474MCTX_usb_none INTERFACE) target_compile_options(GENERIC_G474MCTX_usb_none INTERFACE @@ -68311,15 +68311,15 @@ target_compile_options(GENERIC_G474METX_serial_none INTERFACE ) add_library(GENERIC_G474METX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474METX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474METX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474METX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474METX_usb_HID INTERFACE) target_compile_options(GENERIC_G474METX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474METX_usb_none INTERFACE) target_compile_options(GENERIC_G474METX_usb_none INTERFACE @@ -68393,15 +68393,15 @@ target_compile_options(GENERIC_G474PBIX_serial_none INTERFACE ) add_library(GENERIC_G474PBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474PBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474PBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474PBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474PBIX_usb_HID INTERFACE) target_compile_options(GENERIC_G474PBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474PBIX_usb_none INTERFACE) target_compile_options(GENERIC_G474PBIX_usb_none INTERFACE @@ -68475,15 +68475,15 @@ target_compile_options(GENERIC_G474PCIX_serial_none INTERFACE ) add_library(GENERIC_G474PCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474PCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474PCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474PCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474PCIX_usb_HID INTERFACE) target_compile_options(GENERIC_G474PCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474PCIX_usb_none INTERFACE) target_compile_options(GENERIC_G474PCIX_usb_none INTERFACE @@ -68557,15 +68557,15 @@ target_compile_options(GENERIC_G474PEIX_serial_none INTERFACE ) add_library(GENERIC_G474PEIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474PEIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474PEIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474PEIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474PEIX_usb_HID INTERFACE) target_compile_options(GENERIC_G474PEIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474PEIX_usb_none INTERFACE) target_compile_options(GENERIC_G474PEIX_usb_none INTERFACE @@ -68639,15 +68639,15 @@ target_compile_options(GENERIC_G474QBTX_serial_none INTERFACE ) add_library(GENERIC_G474QBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474QBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474QBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474QBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474QBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474QBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474QBTX_usb_none INTERFACE) target_compile_options(GENERIC_G474QBTX_usb_none INTERFACE @@ -68721,15 +68721,15 @@ target_compile_options(GENERIC_G474QCTX_serial_none INTERFACE ) add_library(GENERIC_G474QCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474QCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474QCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474QCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474QCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474QCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474QCTX_usb_none INTERFACE) target_compile_options(GENERIC_G474QCTX_usb_none INTERFACE @@ -68803,15 +68803,15 @@ target_compile_options(GENERIC_G474QETX_serial_none INTERFACE ) add_library(GENERIC_G474QETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474QETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474QETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474QETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474QETX_usb_HID INTERFACE) target_compile_options(GENERIC_G474QETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474QETX_usb_none INTERFACE) target_compile_options(GENERIC_G474QETX_usb_none INTERFACE @@ -68885,15 +68885,15 @@ target_compile_options(GENERIC_G474RBTX_serial_none INTERFACE ) add_library(GENERIC_G474RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474RBTX_usb_none INTERFACE) target_compile_options(GENERIC_G474RBTX_usb_none INTERFACE @@ -68967,15 +68967,15 @@ target_compile_options(GENERIC_G474RCTX_serial_none INTERFACE ) add_library(GENERIC_G474RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474RCTX_usb_none INTERFACE) target_compile_options(GENERIC_G474RCTX_usb_none INTERFACE @@ -69049,15 +69049,15 @@ target_compile_options(GENERIC_G474RETX_serial_none INTERFACE ) add_library(GENERIC_G474RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G474RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474RETX_usb_none INTERFACE) target_compile_options(GENERIC_G474RETX_usb_none INTERFACE @@ -69131,15 +69131,15 @@ target_compile_options(GENERIC_G474VBHX_serial_none INTERFACE ) add_library(GENERIC_G474VBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474VBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474VBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474VBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474VBHX_usb_HID INTERFACE) target_compile_options(GENERIC_G474VBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474VBHX_usb_none INTERFACE) target_compile_options(GENERIC_G474VBHX_usb_none INTERFACE @@ -69213,15 +69213,15 @@ target_compile_options(GENERIC_G474VBTX_serial_none INTERFACE ) add_library(GENERIC_G474VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474VBTX_usb_none INTERFACE) target_compile_options(GENERIC_G474VBTX_usb_none INTERFACE @@ -69295,15 +69295,15 @@ target_compile_options(GENERIC_G474VCHX_serial_none INTERFACE ) add_library(GENERIC_G474VCHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474VCHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474VCHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474VCHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474VCHX_usb_HID INTERFACE) target_compile_options(GENERIC_G474VCHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474VCHX_usb_none INTERFACE) target_compile_options(GENERIC_G474VCHX_usb_none INTERFACE @@ -69377,15 +69377,15 @@ target_compile_options(GENERIC_G474VCTX_serial_none INTERFACE ) add_library(GENERIC_G474VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G474VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474VCTX_usb_none INTERFACE) target_compile_options(GENERIC_G474VCTX_usb_none INTERFACE @@ -69459,15 +69459,15 @@ target_compile_options(GENERIC_G474VEHX_serial_none INTERFACE ) add_library(GENERIC_G474VEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474VEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474VEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474VEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474VEHX_usb_HID INTERFACE) target_compile_options(GENERIC_G474VEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474VEHX_usb_none INTERFACE) target_compile_options(GENERIC_G474VEHX_usb_none INTERFACE @@ -69541,15 +69541,15 @@ target_compile_options(GENERIC_G474VETX_serial_none INTERFACE ) add_library(GENERIC_G474VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G474VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G474VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G474VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G474VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G474VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G474VETX_usb_none INTERFACE) target_compile_options(GENERIC_G474VETX_usb_none INTERFACE @@ -69623,15 +69623,15 @@ target_compile_options(GENERIC_G483CETX_serial_none INTERFACE ) add_library(GENERIC_G483CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G483CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G483CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G483CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G483CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G483CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G483CETX_usb_none INTERFACE) target_compile_options(GENERIC_G483CETX_usb_none INTERFACE @@ -69705,15 +69705,15 @@ target_compile_options(GENERIC_G483METX_serial_none INTERFACE ) add_library(GENERIC_G483METX_usb_CDC INTERFACE) target_compile_options(GENERIC_G483METX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G483METX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G483METX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G483METX_usb_HID INTERFACE) target_compile_options(GENERIC_G483METX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G483METX_usb_none INTERFACE) target_compile_options(GENERIC_G483METX_usb_none INTERFACE @@ -69787,15 +69787,15 @@ target_compile_options(GENERIC_G483PEIX_serial_none INTERFACE ) add_library(GENERIC_G483PEIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G483PEIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G483PEIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G483PEIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G483PEIX_usb_HID INTERFACE) target_compile_options(GENERIC_G483PEIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G483PEIX_usb_none INTERFACE) target_compile_options(GENERIC_G483PEIX_usb_none INTERFACE @@ -69869,15 +69869,15 @@ target_compile_options(GENERIC_G483QETX_serial_none INTERFACE ) add_library(GENERIC_G483QETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G483QETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G483QETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G483QETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G483QETX_usb_HID INTERFACE) target_compile_options(GENERIC_G483QETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G483QETX_usb_none INTERFACE) target_compile_options(GENERIC_G483QETX_usb_none INTERFACE @@ -69951,15 +69951,15 @@ target_compile_options(GENERIC_G483RETX_serial_none INTERFACE ) add_library(GENERIC_G483RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G483RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G483RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G483RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G483RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G483RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G483RETX_usb_none INTERFACE) target_compile_options(GENERIC_G483RETX_usb_none INTERFACE @@ -70033,15 +70033,15 @@ target_compile_options(GENERIC_G483VEHX_serial_none INTERFACE ) add_library(GENERIC_G483VEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G483VEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G483VEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G483VEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G483VEHX_usb_HID INTERFACE) target_compile_options(GENERIC_G483VEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G483VEHX_usb_none INTERFACE) target_compile_options(GENERIC_G483VEHX_usb_none INTERFACE @@ -70115,15 +70115,15 @@ target_compile_options(GENERIC_G483VETX_serial_none INTERFACE ) add_library(GENERIC_G483VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G483VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G483VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G483VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G483VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G483VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G483VETX_usb_none INTERFACE) target_compile_options(GENERIC_G483VETX_usb_none INTERFACE @@ -70197,15 +70197,15 @@ target_compile_options(GENERIC_G484CETX_serial_none INTERFACE ) add_library(GENERIC_G484CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G484CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G484CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G484CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G484CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G484CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G484CETX_usb_none INTERFACE) target_compile_options(GENERIC_G484CETX_usb_none INTERFACE @@ -70279,15 +70279,15 @@ target_compile_options(GENERIC_G484METX_serial_none INTERFACE ) add_library(GENERIC_G484METX_usb_CDC INTERFACE) target_compile_options(GENERIC_G484METX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G484METX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G484METX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G484METX_usb_HID INTERFACE) target_compile_options(GENERIC_G484METX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G484METX_usb_none INTERFACE) target_compile_options(GENERIC_G484METX_usb_none INTERFACE @@ -70361,15 +70361,15 @@ target_compile_options(GENERIC_G484PEIX_serial_none INTERFACE ) add_library(GENERIC_G484PEIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G484PEIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G484PEIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G484PEIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G484PEIX_usb_HID INTERFACE) target_compile_options(GENERIC_G484PEIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G484PEIX_usb_none INTERFACE) target_compile_options(GENERIC_G484PEIX_usb_none INTERFACE @@ -70443,15 +70443,15 @@ target_compile_options(GENERIC_G484QETX_serial_none INTERFACE ) add_library(GENERIC_G484QETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G484QETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G484QETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G484QETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G484QETX_usb_HID INTERFACE) target_compile_options(GENERIC_G484QETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G484QETX_usb_none INTERFACE) target_compile_options(GENERIC_G484QETX_usb_none INTERFACE @@ -70525,15 +70525,15 @@ target_compile_options(GENERIC_G484RETX_serial_none INTERFACE ) add_library(GENERIC_G484RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G484RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G484RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G484RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G484RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G484RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G484RETX_usb_none INTERFACE) target_compile_options(GENERIC_G484RETX_usb_none INTERFACE @@ -70607,15 +70607,15 @@ target_compile_options(GENERIC_G484VEHX_serial_none INTERFACE ) add_library(GENERIC_G484VEHX_usb_CDC INTERFACE) target_compile_options(GENERIC_G484VEHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G484VEHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G484VEHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G484VEHX_usb_HID INTERFACE) target_compile_options(GENERIC_G484VEHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G484VEHX_usb_none INTERFACE) target_compile_options(GENERIC_G484VEHX_usb_none INTERFACE @@ -70689,15 +70689,15 @@ target_compile_options(GENERIC_G484VETX_serial_none INTERFACE ) add_library(GENERIC_G484VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G484VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G484VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G484VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G484VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G484VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G484VETX_usb_none INTERFACE) target_compile_options(GENERIC_G484VETX_usb_none INTERFACE @@ -70771,15 +70771,15 @@ target_compile_options(GENERIC_G491CCTX_serial_none INTERFACE ) add_library(GENERIC_G491CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G491CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491CCTX_usb_none INTERFACE) target_compile_options(GENERIC_G491CCTX_usb_none INTERFACE @@ -70853,15 +70853,15 @@ target_compile_options(GENERIC_G491CETX_serial_none INTERFACE ) add_library(GENERIC_G491CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G491CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491CETX_usb_none INTERFACE) target_compile_options(GENERIC_G491CETX_usb_none INTERFACE @@ -70935,15 +70935,15 @@ target_compile_options(GENERIC_G491KCUX_serial_none INTERFACE ) add_library(GENERIC_G491KCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491KCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491KCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491KCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491KCUX_usb_HID INTERFACE) target_compile_options(GENERIC_G491KCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491KCUX_usb_none INTERFACE) target_compile_options(GENERIC_G491KCUX_usb_none INTERFACE @@ -71017,15 +71017,15 @@ target_compile_options(GENERIC_G491KEUX_serial_none INTERFACE ) add_library(GENERIC_G491KEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491KEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491KEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491KEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491KEUX_usb_HID INTERFACE) target_compile_options(GENERIC_G491KEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491KEUX_usb_none INTERFACE) target_compile_options(GENERIC_G491KEUX_usb_none INTERFACE @@ -71099,15 +71099,15 @@ target_compile_options(GENERIC_G491MCSX_serial_none INTERFACE ) add_library(GENERIC_G491MCSX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491MCSX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491MCSX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491MCSX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491MCSX_usb_HID INTERFACE) target_compile_options(GENERIC_G491MCSX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491MCSX_usb_none INTERFACE) target_compile_options(GENERIC_G491MCSX_usb_none INTERFACE @@ -71181,15 +71181,15 @@ target_compile_options(GENERIC_G491MCTX_serial_none INTERFACE ) add_library(GENERIC_G491MCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491MCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491MCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491MCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491MCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G491MCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491MCTX_usb_none INTERFACE) target_compile_options(GENERIC_G491MCTX_usb_none INTERFACE @@ -71263,15 +71263,15 @@ target_compile_options(GENERIC_G491MESX_serial_none INTERFACE ) add_library(GENERIC_G491MESX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491MESX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491MESX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491MESX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491MESX_usb_HID INTERFACE) target_compile_options(GENERIC_G491MESX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491MESX_usb_none INTERFACE) target_compile_options(GENERIC_G491MESX_usb_none INTERFACE @@ -71345,15 +71345,15 @@ target_compile_options(GENERIC_G491METX_serial_none INTERFACE ) add_library(GENERIC_G491METX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491METX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491METX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491METX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491METX_usb_HID INTERFACE) target_compile_options(GENERIC_G491METX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491METX_usb_none INTERFACE) target_compile_options(GENERIC_G491METX_usb_none INTERFACE @@ -71427,15 +71427,15 @@ target_compile_options(GENERIC_G491RCIX_serial_none INTERFACE ) add_library(GENERIC_G491RCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491RCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491RCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491RCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491RCIX_usb_HID INTERFACE) target_compile_options(GENERIC_G491RCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491RCIX_usb_none INTERFACE) target_compile_options(GENERIC_G491RCIX_usb_none INTERFACE @@ -71509,15 +71509,15 @@ target_compile_options(GENERIC_G491RCTX_serial_none INTERFACE ) add_library(GENERIC_G491RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G491RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491RCTX_usb_none INTERFACE) target_compile_options(GENERIC_G491RCTX_usb_none INTERFACE @@ -71591,15 +71591,15 @@ target_compile_options(GENERIC_G491REIX_serial_none INTERFACE ) add_library(GENERIC_G491REIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491REIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491REIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491REIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491REIX_usb_HID INTERFACE) target_compile_options(GENERIC_G491REIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491REIX_usb_none INTERFACE) target_compile_options(GENERIC_G491REIX_usb_none INTERFACE @@ -71673,15 +71673,15 @@ target_compile_options(GENERIC_G491RETX_serial_none INTERFACE ) add_library(GENERIC_G491RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G491RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491RETX_usb_none INTERFACE) target_compile_options(GENERIC_G491RETX_usb_none INTERFACE @@ -71755,15 +71755,15 @@ target_compile_options(GENERIC_G491REYX_serial_none INTERFACE ) add_library(GENERIC_G491REYX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491REYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491REYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491REYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491REYX_usb_HID INTERFACE) target_compile_options(GENERIC_G491REYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491REYX_usb_none INTERFACE) target_compile_options(GENERIC_G491REYX_usb_none INTERFACE @@ -71837,15 +71837,15 @@ target_compile_options(GENERIC_G491VCTX_serial_none INTERFACE ) add_library(GENERIC_G491VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_G491VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491VCTX_usb_none INTERFACE) target_compile_options(GENERIC_G491VCTX_usb_none INTERFACE @@ -71919,15 +71919,15 @@ target_compile_options(GENERIC_G491VETX_serial_none INTERFACE ) add_library(GENERIC_G491VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G491VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G491VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G491VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G491VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G491VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G491VETX_usb_none INTERFACE) target_compile_options(GENERIC_G491VETX_usb_none INTERFACE @@ -72001,15 +72001,15 @@ target_compile_options(GENERIC_G4A1CETX_serial_none INTERFACE ) add_library(GENERIC_G4A1CETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G4A1CETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G4A1CETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G4A1CETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G4A1CETX_usb_HID INTERFACE) target_compile_options(GENERIC_G4A1CETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G4A1CETX_usb_none INTERFACE) target_compile_options(GENERIC_G4A1CETX_usb_none INTERFACE @@ -72083,15 +72083,15 @@ target_compile_options(GENERIC_G4A1KEUX_serial_none INTERFACE ) add_library(GENERIC_G4A1KEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_G4A1KEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G4A1KEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G4A1KEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G4A1KEUX_usb_HID INTERFACE) target_compile_options(GENERIC_G4A1KEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G4A1KEUX_usb_none INTERFACE) target_compile_options(GENERIC_G4A1KEUX_usb_none INTERFACE @@ -72165,15 +72165,15 @@ target_compile_options(GENERIC_G4A1MESX_serial_none INTERFACE ) add_library(GENERIC_G4A1MESX_usb_CDC INTERFACE) target_compile_options(GENERIC_G4A1MESX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G4A1MESX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G4A1MESX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G4A1MESX_usb_HID INTERFACE) target_compile_options(GENERIC_G4A1MESX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G4A1MESX_usb_none INTERFACE) target_compile_options(GENERIC_G4A1MESX_usb_none INTERFACE @@ -72247,15 +72247,15 @@ target_compile_options(GENERIC_G4A1METX_serial_none INTERFACE ) add_library(GENERIC_G4A1METX_usb_CDC INTERFACE) target_compile_options(GENERIC_G4A1METX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G4A1METX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G4A1METX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G4A1METX_usb_HID INTERFACE) target_compile_options(GENERIC_G4A1METX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G4A1METX_usb_none INTERFACE) target_compile_options(GENERIC_G4A1METX_usb_none INTERFACE @@ -72329,15 +72329,15 @@ target_compile_options(GENERIC_G4A1REIX_serial_none INTERFACE ) add_library(GENERIC_G4A1REIX_usb_CDC INTERFACE) target_compile_options(GENERIC_G4A1REIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G4A1REIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G4A1REIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G4A1REIX_usb_HID INTERFACE) target_compile_options(GENERIC_G4A1REIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G4A1REIX_usb_none INTERFACE) target_compile_options(GENERIC_G4A1REIX_usb_none INTERFACE @@ -72411,15 +72411,15 @@ target_compile_options(GENERIC_G4A1RETX_serial_none INTERFACE ) add_library(GENERIC_G4A1RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G4A1RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G4A1RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G4A1RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G4A1RETX_usb_HID INTERFACE) target_compile_options(GENERIC_G4A1RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G4A1RETX_usb_none INTERFACE) target_compile_options(GENERIC_G4A1RETX_usb_none INTERFACE @@ -72493,15 +72493,15 @@ target_compile_options(GENERIC_G4A1REYX_serial_none INTERFACE ) add_library(GENERIC_G4A1REYX_usb_CDC INTERFACE) target_compile_options(GENERIC_G4A1REYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G4A1REYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G4A1REYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G4A1REYX_usb_HID INTERFACE) target_compile_options(GENERIC_G4A1REYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G4A1REYX_usb_none INTERFACE) target_compile_options(GENERIC_G4A1REYX_usb_none INTERFACE @@ -72575,15 +72575,15 @@ target_compile_options(GENERIC_G4A1VETX_serial_none INTERFACE ) add_library(GENERIC_G4A1VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_G4A1VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_G4A1VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_G4A1VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_G4A1VETX_usb_HID INTERFACE) target_compile_options(GENERIC_G4A1VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_G4A1VETX_usb_none INTERFACE) target_compile_options(GENERIC_G4A1VETX_usb_none INTERFACE @@ -72657,15 +72657,15 @@ target_compile_options(GENERIC_H503RBTX_serial_none INTERFACE ) add_library(GENERIC_H503RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H503RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H503RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H503RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H503RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_H503RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H503RBTX_usb_none INTERFACE) target_compile_options(GENERIC_H503RBTX_usb_none INTERFACE @@ -72687,7 +72687,7 @@ target_compile_options(GENERIC_H503RBTX_xusb_HSFS INTERFACE # GENERIC_H563IIKXQ # ----------------------------------------------------------------------------- -set(GENERIC_H563IIKXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563IIKxQ") +set(GENERIC_H563IIKXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563IIKxQ_H573IIKxQ") set(GENERIC_H563IIKXQ_MAXSIZE 2097152) set(GENERIC_H563IIKXQ_MAXDATASIZE 655360) set(GENERIC_H563IIKXQ_MCU cortex-m33) @@ -72739,15 +72739,15 @@ target_compile_options(GENERIC_H563IIKXQ_serial_none INTERFACE ) add_library(GENERIC_H563IIKXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_H563IIKXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H563IIKXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H563IIKXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H563IIKXQ_usb_HID INTERFACE) target_compile_options(GENERIC_H563IIKXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H563IIKXQ_usb_none INTERFACE) target_compile_options(GENERIC_H563IIKXQ_usb_none INTERFACE @@ -72769,7 +72769,7 @@ target_compile_options(GENERIC_H563IIKXQ_xusb_HSFS INTERFACE # GENERIC_H563ZGTX # ----------------------------------------------------------------------------- -set(GENERIC_H563ZGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T") +set(GENERIC_H563ZGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T_H573ZIT") set(GENERIC_H563ZGTX_MAXSIZE 1048576) set(GENERIC_H563ZGTX_MAXDATASIZE 655360) set(GENERIC_H563ZGTX_MCU cortex-m33) @@ -72821,15 +72821,15 @@ target_compile_options(GENERIC_H563ZGTX_serial_none INTERFACE ) add_library(GENERIC_H563ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H563ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H563ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H563ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H563ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H563ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H563ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_H563ZGTX_usb_none INTERFACE @@ -72851,7 +72851,7 @@ target_compile_options(GENERIC_H563ZGTX_xusb_HSFS INTERFACE # GENERIC_H563ZITX # ----------------------------------------------------------------------------- -set(GENERIC_H563ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T") +set(GENERIC_H563ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T_H573ZIT") set(GENERIC_H563ZITX_MAXSIZE 2097152) set(GENERIC_H563ZITX_MAXDATASIZE 655360) set(GENERIC_H563ZITX_MCU cortex-m33) @@ -72903,15 +72903,15 @@ target_compile_options(GENERIC_H563ZITX_serial_none INTERFACE ) add_library(GENERIC_H563ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H563ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H563ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H563ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H563ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_H563ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H563ZITX_usb_none INTERFACE) target_compile_options(GENERIC_H563ZITX_usb_none INTERFACE @@ -72933,7 +72933,7 @@ target_compile_options(GENERIC_H563ZITX_xusb_HSFS INTERFACE # GENERIC_H573IIKXQ # ----------------------------------------------------------------------------- -set(GENERIC_H573IIKXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H573IIKxQ") +set(GENERIC_H573IIKXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563IIKxQ_H573IIKxQ") set(GENERIC_H573IIKXQ_MAXSIZE 2097152) set(GENERIC_H573IIKXQ_MAXDATASIZE 655360) set(GENERIC_H573IIKXQ_MCU cortex-m33) @@ -72985,15 +72985,15 @@ target_compile_options(GENERIC_H573IIKXQ_serial_none INTERFACE ) add_library(GENERIC_H573IIKXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_H573IIKXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H573IIKXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H573IIKXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H573IIKXQ_usb_HID INTERFACE) target_compile_options(GENERIC_H573IIKXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H573IIKXQ_usb_none INTERFACE) target_compile_options(GENERIC_H573IIKXQ_usb_none INTERFACE @@ -73015,7 +73015,7 @@ target_compile_options(GENERIC_H573IIKXQ_xusb_HSFS INTERFACE # GENERIC_H573ZITX # ----------------------------------------------------------------------------- -set(GENERIC_H573ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H573ZIT") +set(GENERIC_H573ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T_H573ZIT") set(GENERIC_H573ZITX_MAXSIZE 2097152) set(GENERIC_H573ZITX_MAXDATASIZE 655360) set(GENERIC_H573ZITX_MCU cortex-m33) @@ -73067,15 +73067,15 @@ target_compile_options(GENERIC_H573ZITX_serial_none INTERFACE ) add_library(GENERIC_H573ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H573ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H573ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H573ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H573ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_H573ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H573ZITX_usb_none INTERFACE) target_compile_options(GENERIC_H573ZITX_usb_none INTERFACE @@ -73149,15 +73149,15 @@ target_compile_options(GENERIC_H723ZETX_serial_none INTERFACE ) add_library(GENERIC_H723ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_H723ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H723ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H723ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H723ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_H723ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H723ZETX_usb_none INTERFACE) target_compile_options(GENERIC_H723ZETX_usb_none INTERFACE @@ -73231,15 +73231,15 @@ target_compile_options(GENERIC_H723ZGTX_serial_none INTERFACE ) add_library(GENERIC_H723ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H723ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H723ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H723ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H723ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H723ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H723ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_H723ZGTX_usb_none INTERFACE @@ -73313,15 +73313,15 @@ target_compile_options(GENERIC_H730ZBTX_serial_none INTERFACE ) add_library(GENERIC_H730ZBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H730ZBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H730ZBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H730ZBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H730ZBTX_usb_HID INTERFACE) target_compile_options(GENERIC_H730ZBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H730ZBTX_usb_none INTERFACE) target_compile_options(GENERIC_H730ZBTX_usb_none INTERFACE @@ -73395,15 +73395,15 @@ target_compile_options(GENERIC_H733ZGTX_serial_none INTERFACE ) add_library(GENERIC_H733ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H733ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H733ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H733ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H733ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H733ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H733ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_H733ZGTX_usb_none INTERFACE @@ -73477,15 +73477,15 @@ target_compile_options(GENERIC_H742IGKX_serial_none INTERFACE ) add_library(GENERIC_H742IGKX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742IGKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742IGKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742IGKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742IGKX_usb_HID INTERFACE) target_compile_options(GENERIC_H742IGKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742IGKX_usb_none INTERFACE) target_compile_options(GENERIC_H742IGKX_usb_none INTERFACE @@ -73559,15 +73559,15 @@ target_compile_options(GENERIC_H742IGTX_serial_none INTERFACE ) add_library(GENERIC_H742IGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742IGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742IGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742IGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742IGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H742IGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742IGTX_usb_none INTERFACE) target_compile_options(GENERIC_H742IGTX_usb_none INTERFACE @@ -73641,15 +73641,15 @@ target_compile_options(GENERIC_H742IIKX_serial_none INTERFACE ) add_library(GENERIC_H742IIKX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742IIKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742IIKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742IIKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742IIKX_usb_HID INTERFACE) target_compile_options(GENERIC_H742IIKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742IIKX_usb_none INTERFACE) target_compile_options(GENERIC_H742IIKX_usb_none INTERFACE @@ -73723,15 +73723,15 @@ target_compile_options(GENERIC_H742IITX_serial_none INTERFACE ) add_library(GENERIC_H742IITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742IITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742IITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742IITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742IITX_usb_HID INTERFACE) target_compile_options(GENERIC_H742IITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742IITX_usb_none INTERFACE) target_compile_options(GENERIC_H742IITX_usb_none INTERFACE @@ -73805,15 +73805,15 @@ target_compile_options(GENERIC_H742VGHX_serial_none INTERFACE ) add_library(GENERIC_H742VGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742VGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742VGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742VGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742VGHX_usb_HID INTERFACE) target_compile_options(GENERIC_H742VGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742VGHX_usb_none INTERFACE) target_compile_options(GENERIC_H742VGHX_usb_none INTERFACE @@ -73887,15 +73887,15 @@ target_compile_options(GENERIC_H742VGTX_serial_none INTERFACE ) add_library(GENERIC_H742VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H742VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742VGTX_usb_none INTERFACE) target_compile_options(GENERIC_H742VGTX_usb_none INTERFACE @@ -73969,15 +73969,15 @@ target_compile_options(GENERIC_H742VIHX_serial_none INTERFACE ) add_library(GENERIC_H742VIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742VIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742VIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742VIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742VIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H742VIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742VIHX_usb_none INTERFACE) target_compile_options(GENERIC_H742VIHX_usb_none INTERFACE @@ -74051,15 +74051,15 @@ target_compile_options(GENERIC_H742VITX_serial_none INTERFACE ) add_library(GENERIC_H742VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742VITX_usb_HID INTERFACE) target_compile_options(GENERIC_H742VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742VITX_usb_none INTERFACE) target_compile_options(GENERIC_H742VITX_usb_none INTERFACE @@ -74133,15 +74133,15 @@ target_compile_options(GENERIC_H742XGHX_serial_none INTERFACE ) add_library(GENERIC_H742XGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742XGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742XGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742XGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742XGHX_usb_HID INTERFACE) target_compile_options(GENERIC_H742XGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742XGHX_usb_none INTERFACE) target_compile_options(GENERIC_H742XGHX_usb_none INTERFACE @@ -74215,15 +74215,15 @@ target_compile_options(GENERIC_H742XIHX_serial_none INTERFACE ) add_library(GENERIC_H742XIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742XIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742XIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742XIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742XIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H742XIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742XIHX_usb_none INTERFACE) target_compile_options(GENERIC_H742XIHX_usb_none INTERFACE @@ -74297,15 +74297,15 @@ target_compile_options(GENERIC_H742ZGTX_serial_none INTERFACE ) add_library(GENERIC_H742ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H742ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_H742ZGTX_usb_none INTERFACE @@ -74379,15 +74379,15 @@ target_compile_options(GENERIC_H742ZITX_serial_none INTERFACE ) add_library(GENERIC_H742ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H742ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H742ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H742ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H742ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_H742ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H742ZITX_usb_none INTERFACE) target_compile_options(GENERIC_H742ZITX_usb_none INTERFACE @@ -74461,15 +74461,15 @@ target_compile_options(GENERIC_H743IGKX_serial_none INTERFACE ) add_library(GENERIC_H743IGKX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743IGKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743IGKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743IGKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743IGKX_usb_HID INTERFACE) target_compile_options(GENERIC_H743IGKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743IGKX_usb_none INTERFACE) target_compile_options(GENERIC_H743IGKX_usb_none INTERFACE @@ -74543,15 +74543,15 @@ target_compile_options(GENERIC_H743IGTX_serial_none INTERFACE ) add_library(GENERIC_H743IGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743IGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743IGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743IGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743IGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H743IGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743IGTX_usb_none INTERFACE) target_compile_options(GENERIC_H743IGTX_usb_none INTERFACE @@ -74625,15 +74625,15 @@ target_compile_options(GENERIC_H743IIKX_serial_none INTERFACE ) add_library(GENERIC_H743IIKX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743IIKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743IIKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743IIKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743IIKX_usb_HID INTERFACE) target_compile_options(GENERIC_H743IIKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743IIKX_usb_none INTERFACE) target_compile_options(GENERIC_H743IIKX_usb_none INTERFACE @@ -74707,15 +74707,15 @@ target_compile_options(GENERIC_H743IITX_serial_none INTERFACE ) add_library(GENERIC_H743IITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743IITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743IITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743IITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743IITX_usb_HID INTERFACE) target_compile_options(GENERIC_H743IITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743IITX_usb_none INTERFACE) target_compile_options(GENERIC_H743IITX_usb_none INTERFACE @@ -74789,15 +74789,15 @@ target_compile_options(GENERIC_H743VGHX_serial_none INTERFACE ) add_library(GENERIC_H743VGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743VGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743VGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743VGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743VGHX_usb_HID INTERFACE) target_compile_options(GENERIC_H743VGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743VGHX_usb_none INTERFACE) target_compile_options(GENERIC_H743VGHX_usb_none INTERFACE @@ -74871,15 +74871,15 @@ target_compile_options(GENERIC_H743VGTX_serial_none INTERFACE ) add_library(GENERIC_H743VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H743VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743VGTX_usb_none INTERFACE) target_compile_options(GENERIC_H743VGTX_usb_none INTERFACE @@ -74953,15 +74953,15 @@ target_compile_options(GENERIC_H743VIHX_serial_none INTERFACE ) add_library(GENERIC_H743VIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743VIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743VIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743VIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743VIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H743VIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743VIHX_usb_none INTERFACE) target_compile_options(GENERIC_H743VIHX_usb_none INTERFACE @@ -75035,15 +75035,15 @@ target_compile_options(GENERIC_H743VITX_serial_none INTERFACE ) add_library(GENERIC_H743VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743VITX_usb_HID INTERFACE) target_compile_options(GENERIC_H743VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743VITX_usb_none INTERFACE) target_compile_options(GENERIC_H743VITX_usb_none INTERFACE @@ -75117,15 +75117,15 @@ target_compile_options(GENERIC_H743XGHX_serial_none INTERFACE ) add_library(GENERIC_H743XGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743XGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743XGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743XGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743XGHX_usb_HID INTERFACE) target_compile_options(GENERIC_H743XGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743XGHX_usb_none INTERFACE) target_compile_options(GENERIC_H743XGHX_usb_none INTERFACE @@ -75199,15 +75199,15 @@ target_compile_options(GENERIC_H743XIHX_serial_none INTERFACE ) add_library(GENERIC_H743XIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743XIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743XIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743XIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743XIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H743XIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743XIHX_usb_none INTERFACE) target_compile_options(GENERIC_H743XIHX_usb_none INTERFACE @@ -75281,15 +75281,15 @@ target_compile_options(GENERIC_H743ZGTX_serial_none INTERFACE ) add_library(GENERIC_H743ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H743ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_H743ZGTX_usb_none INTERFACE @@ -75363,15 +75363,15 @@ target_compile_options(GENERIC_H743ZITX_serial_none INTERFACE ) add_library(GENERIC_H743ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H743ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H743ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H743ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H743ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_H743ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H743ZITX_usb_none INTERFACE) target_compile_options(GENERIC_H743ZITX_usb_none INTERFACE @@ -75445,15 +75445,15 @@ target_compile_options(GENERIC_H745XGHX_serial_none INTERFACE ) add_library(GENERIC_H745XGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H745XGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H745XGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H745XGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H745XGHX_usb_HID INTERFACE) target_compile_options(GENERIC_H745XGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H745XGHX_usb_none INTERFACE) target_compile_options(GENERIC_H745XGHX_usb_none INTERFACE @@ -75527,15 +75527,15 @@ target_compile_options(GENERIC_H745XIHX_serial_none INTERFACE ) add_library(GENERIC_H745XIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H745XIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H745XIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H745XIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H745XIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H745XIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H745XIHX_usb_none INTERFACE) target_compile_options(GENERIC_H745XIHX_usb_none INTERFACE @@ -75609,15 +75609,15 @@ target_compile_options(GENERIC_H747AGIX_serial_none INTERFACE ) add_library(GENERIC_H747AGIX_usb_CDC INTERFACE) target_compile_options(GENERIC_H747AGIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H747AGIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H747AGIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H747AGIX_usb_HID INTERFACE) target_compile_options(GENERIC_H747AGIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H747AGIX_usb_none INTERFACE) target_compile_options(GENERIC_H747AGIX_usb_none INTERFACE @@ -75691,15 +75691,15 @@ target_compile_options(GENERIC_H747AIIX_serial_none INTERFACE ) add_library(GENERIC_H747AIIX_usb_CDC INTERFACE) target_compile_options(GENERIC_H747AIIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H747AIIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H747AIIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H747AIIX_usb_HID INTERFACE) target_compile_options(GENERIC_H747AIIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H747AIIX_usb_none INTERFACE) target_compile_options(GENERIC_H747AIIX_usb_none INTERFACE @@ -75773,15 +75773,15 @@ target_compile_options(GENERIC_H747IGTX_serial_none INTERFACE ) add_library(GENERIC_H747IGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H747IGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H747IGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H747IGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H747IGTX_usb_HID INTERFACE) target_compile_options(GENERIC_H747IGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H747IGTX_usb_none INTERFACE) target_compile_options(GENERIC_H747IGTX_usb_none INTERFACE @@ -75855,15 +75855,15 @@ target_compile_options(GENERIC_H747IITX_serial_none INTERFACE ) add_library(GENERIC_H747IITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H747IITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H747IITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H747IITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H747IITX_usb_HID INTERFACE) target_compile_options(GENERIC_H747IITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H747IITX_usb_none INTERFACE) target_compile_options(GENERIC_H747IITX_usb_none INTERFACE @@ -75937,15 +75937,15 @@ target_compile_options(GENERIC_H747XGHX_serial_none INTERFACE ) add_library(GENERIC_H747XGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H747XGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H747XGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H747XGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H747XGHX_usb_HID INTERFACE) target_compile_options(GENERIC_H747XGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H747XGHX_usb_none INTERFACE) target_compile_options(GENERIC_H747XGHX_usb_none INTERFACE @@ -76019,15 +76019,15 @@ target_compile_options(GENERIC_H747XIHX_serial_none INTERFACE ) add_library(GENERIC_H747XIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H747XIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H747XIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H747XIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H747XIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H747XIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H747XIHX_usb_none INTERFACE) target_compile_options(GENERIC_H747XIHX_usb_none INTERFACE @@ -76101,15 +76101,15 @@ target_compile_options(GENERIC_H750IBKX_serial_none INTERFACE ) add_library(GENERIC_H750IBKX_usb_CDC INTERFACE) target_compile_options(GENERIC_H750IBKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H750IBKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H750IBKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H750IBKX_usb_HID INTERFACE) target_compile_options(GENERIC_H750IBKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H750IBKX_usb_none INTERFACE) target_compile_options(GENERIC_H750IBKX_usb_none INTERFACE @@ -76183,15 +76183,15 @@ target_compile_options(GENERIC_H750IBTX_serial_none INTERFACE ) add_library(GENERIC_H750IBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H750IBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H750IBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H750IBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H750IBTX_usb_HID INTERFACE) target_compile_options(GENERIC_H750IBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H750IBTX_usb_none INTERFACE) target_compile_options(GENERIC_H750IBTX_usb_none INTERFACE @@ -76265,15 +76265,15 @@ target_compile_options(GENERIC_H750VBTX_serial_none INTERFACE ) add_library(GENERIC_H750VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H750VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H750VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H750VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H750VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_H750VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H750VBTX_usb_none INTERFACE) target_compile_options(GENERIC_H750VBTX_usb_none INTERFACE @@ -76347,15 +76347,15 @@ target_compile_options(GENERIC_H750XBHX_serial_none INTERFACE ) add_library(GENERIC_H750XBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H750XBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H750XBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H750XBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H750XBHX_usb_HID INTERFACE) target_compile_options(GENERIC_H750XBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H750XBHX_usb_none INTERFACE) target_compile_options(GENERIC_H750XBHX_usb_none INTERFACE @@ -76429,15 +76429,15 @@ target_compile_options(GENERIC_H750ZBTX_serial_none INTERFACE ) add_library(GENERIC_H750ZBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_H750ZBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H750ZBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H750ZBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H750ZBTX_usb_HID INTERFACE) target_compile_options(GENERIC_H750ZBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H750ZBTX_usb_none INTERFACE) target_compile_options(GENERIC_H750ZBTX_usb_none INTERFACE @@ -76511,15 +76511,15 @@ target_compile_options(GENERIC_H753IIKX_serial_none INTERFACE ) add_library(GENERIC_H753IIKX_usb_CDC INTERFACE) target_compile_options(GENERIC_H753IIKX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H753IIKX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H753IIKX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H753IIKX_usb_HID INTERFACE) target_compile_options(GENERIC_H753IIKX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H753IIKX_usb_none INTERFACE) target_compile_options(GENERIC_H753IIKX_usb_none INTERFACE @@ -76593,15 +76593,15 @@ target_compile_options(GENERIC_H753IITX_serial_none INTERFACE ) add_library(GENERIC_H753IITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H753IITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H753IITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H753IITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H753IITX_usb_HID INTERFACE) target_compile_options(GENERIC_H753IITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H753IITX_usb_none INTERFACE) target_compile_options(GENERIC_H753IITX_usb_none INTERFACE @@ -76675,15 +76675,15 @@ target_compile_options(GENERIC_H753VIHX_serial_none INTERFACE ) add_library(GENERIC_H753VIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H753VIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H753VIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H753VIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H753VIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H753VIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H753VIHX_usb_none INTERFACE) target_compile_options(GENERIC_H753VIHX_usb_none INTERFACE @@ -76757,15 +76757,15 @@ target_compile_options(GENERIC_H753VITX_serial_none INTERFACE ) add_library(GENERIC_H753VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H753VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H753VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H753VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H753VITX_usb_HID INTERFACE) target_compile_options(GENERIC_H753VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H753VITX_usb_none INTERFACE) target_compile_options(GENERIC_H753VITX_usb_none INTERFACE @@ -76839,15 +76839,15 @@ target_compile_options(GENERIC_H753XIHX_serial_none INTERFACE ) add_library(GENERIC_H753XIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H753XIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H753XIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H753XIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H753XIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H753XIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H753XIHX_usb_none INTERFACE) target_compile_options(GENERIC_H753XIHX_usb_none INTERFACE @@ -76921,15 +76921,15 @@ target_compile_options(GENERIC_H753ZITX_serial_none INTERFACE ) add_library(GENERIC_H753ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H753ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H753ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H753ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H753ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_H753ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H753ZITX_usb_none INTERFACE) target_compile_options(GENERIC_H753ZITX_usb_none INTERFACE @@ -77003,15 +77003,15 @@ target_compile_options(GENERIC_H755XIHX_serial_none INTERFACE ) add_library(GENERIC_H755XIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H755XIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H755XIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H755XIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H755XIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H755XIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H755XIHX_usb_none INTERFACE) target_compile_options(GENERIC_H755XIHX_usb_none INTERFACE @@ -77085,15 +77085,15 @@ target_compile_options(GENERIC_H757AIIX_serial_none INTERFACE ) add_library(GENERIC_H757AIIX_usb_CDC INTERFACE) target_compile_options(GENERIC_H757AIIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H757AIIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H757AIIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H757AIIX_usb_HID INTERFACE) target_compile_options(GENERIC_H757AIIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H757AIIX_usb_none INTERFACE) target_compile_options(GENERIC_H757AIIX_usb_none INTERFACE @@ -77167,15 +77167,15 @@ target_compile_options(GENERIC_H757IITX_serial_none INTERFACE ) add_library(GENERIC_H757IITX_usb_CDC INTERFACE) target_compile_options(GENERIC_H757IITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H757IITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H757IITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H757IITX_usb_HID INTERFACE) target_compile_options(GENERIC_H757IITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H757IITX_usb_none INTERFACE) target_compile_options(GENERIC_H757IITX_usb_none INTERFACE @@ -77249,15 +77249,15 @@ target_compile_options(GENERIC_H757XIHX_serial_none INTERFACE ) add_library(GENERIC_H757XIHX_usb_CDC INTERFACE) target_compile_options(GENERIC_H757XIHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_H757XIHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_H757XIHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_H757XIHX_usb_HID INTERFACE) target_compile_options(GENERIC_H757XIHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_H757XIHX_usb_none INTERFACE) target_compile_options(GENERIC_H757XIHX_usb_none INTERFACE @@ -77331,15 +77331,15 @@ target_compile_options(GENERIC_L010C6TX_serial_none INTERFACE ) add_library(GENERIC_L010C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L010C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L010C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L010C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L010C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L010C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L010C6TX_usb_none INTERFACE) target_compile_options(GENERIC_L010C6TX_usb_none INTERFACE @@ -77401,15 +77401,15 @@ target_compile_options(GENERIC_L010F4PX_serial_none INTERFACE ) add_library(GENERIC_L010F4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L010F4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L010F4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L010F4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L010F4PX_usb_HID INTERFACE) target_compile_options(GENERIC_L010F4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L010F4PX_usb_none INTERFACE) target_compile_options(GENERIC_L010F4PX_usb_none INTERFACE @@ -77471,15 +77471,15 @@ target_compile_options(GENERIC_L010K4TX_serial_none INTERFACE ) add_library(GENERIC_L010K4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L010K4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L010K4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L010K4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L010K4TX_usb_HID INTERFACE) target_compile_options(GENERIC_L010K4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L010K4TX_usb_none INTERFACE) target_compile_options(GENERIC_L010K4TX_usb_none INTERFACE @@ -77541,15 +77541,15 @@ target_compile_options(GENERIC_L010R8TX_serial_none INTERFACE ) add_library(GENERIC_L010R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L010R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L010R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L010R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L010R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L010R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L010R8TX_usb_none INTERFACE) target_compile_options(GENERIC_L010R8TX_usb_none INTERFACE @@ -77611,15 +77611,15 @@ target_compile_options(GENERIC_L010RBTX_serial_none INTERFACE ) add_library(GENERIC_L010RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L010RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L010RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L010RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L010RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L010RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L010RBTX_usb_none INTERFACE) target_compile_options(GENERIC_L010RBTX_usb_none INTERFACE @@ -77681,15 +77681,15 @@ target_compile_options(GENERIC_L011D3PX_serial_none INTERFACE ) add_library(GENERIC_L011D3PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011D3PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011D3PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011D3PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011D3PX_usb_HID INTERFACE) target_compile_options(GENERIC_L011D3PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011D3PX_usb_none INTERFACE) target_compile_options(GENERIC_L011D3PX_usb_none INTERFACE @@ -77751,15 +77751,15 @@ target_compile_options(GENERIC_L011D4PX_serial_none INTERFACE ) add_library(GENERIC_L011D4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011D4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011D4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011D4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011D4PX_usb_HID INTERFACE) target_compile_options(GENERIC_L011D4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011D4PX_usb_none INTERFACE) target_compile_options(GENERIC_L011D4PX_usb_none INTERFACE @@ -77821,15 +77821,15 @@ target_compile_options(GENERIC_L011E3YX_serial_none INTERFACE ) add_library(GENERIC_L011E3YX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011E3YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011E3YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011E3YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011E3YX_usb_HID INTERFACE) target_compile_options(GENERIC_L011E3YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011E3YX_usb_none INTERFACE) target_compile_options(GENERIC_L011E3YX_usb_none INTERFACE @@ -77891,15 +77891,15 @@ target_compile_options(GENERIC_L011E4YX_serial_none INTERFACE ) add_library(GENERIC_L011E4YX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011E4YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011E4YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011E4YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011E4YX_usb_HID INTERFACE) target_compile_options(GENERIC_L011E4YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011E4YX_usb_none INTERFACE) target_compile_options(GENERIC_L011E4YX_usb_none INTERFACE @@ -77961,15 +77961,15 @@ target_compile_options(GENERIC_L011F3PX_serial_none INTERFACE ) add_library(GENERIC_L011F3PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011F3PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011F3PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011F3PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011F3PX_usb_HID INTERFACE) target_compile_options(GENERIC_L011F3PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011F3PX_usb_none INTERFACE) target_compile_options(GENERIC_L011F3PX_usb_none INTERFACE @@ -78031,15 +78031,15 @@ target_compile_options(GENERIC_L011F3UX_serial_none INTERFACE ) add_library(GENERIC_L011F3UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011F3UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011F3UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011F3UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011F3UX_usb_HID INTERFACE) target_compile_options(GENERIC_L011F3UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011F3UX_usb_none INTERFACE) target_compile_options(GENERIC_L011F3UX_usb_none INTERFACE @@ -78101,15 +78101,15 @@ target_compile_options(GENERIC_L011F4PX_serial_none INTERFACE ) add_library(GENERIC_L011F4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011F4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011F4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011F4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011F4PX_usb_HID INTERFACE) target_compile_options(GENERIC_L011F4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011F4PX_usb_none INTERFACE) target_compile_options(GENERIC_L011F4PX_usb_none INTERFACE @@ -78171,15 +78171,15 @@ target_compile_options(GENERIC_L011F4UX_serial_none INTERFACE ) add_library(GENERIC_L011F4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011F4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011F4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011F4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011F4UX_usb_HID INTERFACE) target_compile_options(GENERIC_L011F4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011F4UX_usb_none INTERFACE) target_compile_options(GENERIC_L011F4UX_usb_none INTERFACE @@ -78241,15 +78241,15 @@ target_compile_options(GENERIC_L011G3UX_serial_none INTERFACE ) add_library(GENERIC_L011G3UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011G3UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011G3UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011G3UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011G3UX_usb_HID INTERFACE) target_compile_options(GENERIC_L011G3UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011G3UX_usb_none INTERFACE) target_compile_options(GENERIC_L011G3UX_usb_none INTERFACE @@ -78311,15 +78311,15 @@ target_compile_options(GENERIC_L011G4UX_serial_none INTERFACE ) add_library(GENERIC_L011G4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011G4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011G4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011G4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011G4UX_usb_HID INTERFACE) target_compile_options(GENERIC_L011G4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011G4UX_usb_none INTERFACE) target_compile_options(GENERIC_L011G4UX_usb_none INTERFACE @@ -78381,15 +78381,15 @@ target_compile_options(GENERIC_L011K3TX_serial_none INTERFACE ) add_library(GENERIC_L011K3TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011K3TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011K3TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011K3TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011K3TX_usb_HID INTERFACE) target_compile_options(GENERIC_L011K3TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011K3TX_usb_none INTERFACE) target_compile_options(GENERIC_L011K3TX_usb_none INTERFACE @@ -78451,15 +78451,15 @@ target_compile_options(GENERIC_L011K3UX_serial_none INTERFACE ) add_library(GENERIC_L011K3UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011K3UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011K3UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011K3UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011K3UX_usb_HID INTERFACE) target_compile_options(GENERIC_L011K3UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011K3UX_usb_none INTERFACE) target_compile_options(GENERIC_L011K3UX_usb_none INTERFACE @@ -78521,15 +78521,15 @@ target_compile_options(GENERIC_L011K4TX_serial_none INTERFACE ) add_library(GENERIC_L011K4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011K4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011K4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011K4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011K4TX_usb_HID INTERFACE) target_compile_options(GENERIC_L011K4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011K4TX_usb_none INTERFACE) target_compile_options(GENERIC_L011K4TX_usb_none INTERFACE @@ -78591,15 +78591,15 @@ target_compile_options(GENERIC_L011K4UX_serial_none INTERFACE ) add_library(GENERIC_L011K4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L011K4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L011K4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L011K4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L011K4UX_usb_HID INTERFACE) target_compile_options(GENERIC_L011K4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L011K4UX_usb_none INTERFACE) target_compile_options(GENERIC_L011K4UX_usb_none INTERFACE @@ -78661,15 +78661,15 @@ target_compile_options(GENERIC_L021D4PX_serial_none INTERFACE ) add_library(GENERIC_L021D4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L021D4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L021D4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L021D4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L021D4PX_usb_HID INTERFACE) target_compile_options(GENERIC_L021D4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L021D4PX_usb_none INTERFACE) target_compile_options(GENERIC_L021D4PX_usb_none INTERFACE @@ -78731,15 +78731,15 @@ target_compile_options(GENERIC_L021F4PX_serial_none INTERFACE ) add_library(GENERIC_L021F4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L021F4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L021F4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L021F4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L021F4PX_usb_HID INTERFACE) target_compile_options(GENERIC_L021F4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L021F4PX_usb_none INTERFACE) target_compile_options(GENERIC_L021F4PX_usb_none INTERFACE @@ -78801,15 +78801,15 @@ target_compile_options(GENERIC_L021F4UX_serial_none INTERFACE ) add_library(GENERIC_L021F4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L021F4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L021F4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L021F4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L021F4UX_usb_HID INTERFACE) target_compile_options(GENERIC_L021F4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L021F4UX_usb_none INTERFACE) target_compile_options(GENERIC_L021F4UX_usb_none INTERFACE @@ -78871,15 +78871,15 @@ target_compile_options(GENERIC_L021G4UX_serial_none INTERFACE ) add_library(GENERIC_L021G4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L021G4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L021G4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L021G4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L021G4UX_usb_HID INTERFACE) target_compile_options(GENERIC_L021G4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L021G4UX_usb_none INTERFACE) target_compile_options(GENERIC_L021G4UX_usb_none INTERFACE @@ -78941,15 +78941,15 @@ target_compile_options(GENERIC_L021K4TX_serial_none INTERFACE ) add_library(GENERIC_L021K4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L021K4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L021K4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L021K4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L021K4TX_usb_HID INTERFACE) target_compile_options(GENERIC_L021K4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L021K4TX_usb_none INTERFACE) target_compile_options(GENERIC_L021K4TX_usb_none INTERFACE @@ -79011,15 +79011,15 @@ target_compile_options(GENERIC_L021K4UX_serial_none INTERFACE ) add_library(GENERIC_L021K4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L021K4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L021K4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L021K4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L021K4UX_usb_HID INTERFACE) target_compile_options(GENERIC_L021K4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L021K4UX_usb_none INTERFACE) target_compile_options(GENERIC_L021K4UX_usb_none INTERFACE @@ -79081,15 +79081,15 @@ target_compile_options(GENERIC_L031C4TX_serial_none INTERFACE ) add_library(GENERIC_L031C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_L031C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031C4TX_usb_none INTERFACE) target_compile_options(GENERIC_L031C4TX_usb_none INTERFACE @@ -79151,15 +79151,15 @@ target_compile_options(GENERIC_L031C4UX_serial_none INTERFACE ) add_library(GENERIC_L031C4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031C4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031C4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031C4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031C4UX_usb_HID INTERFACE) target_compile_options(GENERIC_L031C4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031C4UX_usb_none INTERFACE) target_compile_options(GENERIC_L031C4UX_usb_none INTERFACE @@ -79221,15 +79221,15 @@ target_compile_options(GENERIC_L031C6TX_serial_none INTERFACE ) add_library(GENERIC_L031C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L031C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031C6TX_usb_none INTERFACE) target_compile_options(GENERIC_L031C6TX_usb_none INTERFACE @@ -79291,15 +79291,15 @@ target_compile_options(GENERIC_L031C6UX_serial_none INTERFACE ) add_library(GENERIC_L031C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L031C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031C6UX_usb_none INTERFACE) target_compile_options(GENERIC_L031C6UX_usb_none INTERFACE @@ -79361,15 +79361,15 @@ target_compile_options(GENERIC_L031E4YX_serial_none INTERFACE ) add_library(GENERIC_L031E4YX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031E4YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031E4YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031E4YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031E4YX_usb_HID INTERFACE) target_compile_options(GENERIC_L031E4YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031E4YX_usb_none INTERFACE) target_compile_options(GENERIC_L031E4YX_usb_none INTERFACE @@ -79431,15 +79431,15 @@ target_compile_options(GENERIC_L031E6YX_serial_none INTERFACE ) add_library(GENERIC_L031E6YX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031E6YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031E6YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031E6YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031E6YX_usb_HID INTERFACE) target_compile_options(GENERIC_L031E6YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031E6YX_usb_none INTERFACE) target_compile_options(GENERIC_L031E6YX_usb_none INTERFACE @@ -79501,15 +79501,15 @@ target_compile_options(GENERIC_L031F4PX_serial_none INTERFACE ) add_library(GENERIC_L031F4PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031F4PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031F4PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031F4PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031F4PX_usb_HID INTERFACE) target_compile_options(GENERIC_L031F4PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031F4PX_usb_none INTERFACE) target_compile_options(GENERIC_L031F4PX_usb_none INTERFACE @@ -79571,15 +79571,15 @@ target_compile_options(GENERIC_L031F6PX_serial_none INTERFACE ) add_library(GENERIC_L031F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_L031F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031F6PX_usb_none INTERFACE) target_compile_options(GENERIC_L031F6PX_usb_none INTERFACE @@ -79641,15 +79641,15 @@ target_compile_options(GENERIC_L031G4UX_serial_none INTERFACE ) add_library(GENERIC_L031G4UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031G4UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031G4UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031G4UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031G4UX_usb_HID INTERFACE) target_compile_options(GENERIC_L031G4UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031G4UX_usb_none INTERFACE) target_compile_options(GENERIC_L031G4UX_usb_none INTERFACE @@ -79711,15 +79711,15 @@ target_compile_options(GENERIC_L031G6UX_serial_none INTERFACE ) add_library(GENERIC_L031G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L031G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031G6UX_usb_none INTERFACE) target_compile_options(GENERIC_L031G6UX_usb_none INTERFACE @@ -79781,15 +79781,15 @@ target_compile_options(GENERIC_L031K4TX_serial_none INTERFACE ) add_library(GENERIC_L031K4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031K4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031K4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031K4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031K4TX_usb_HID INTERFACE) target_compile_options(GENERIC_L031K4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031K4TX_usb_none INTERFACE) target_compile_options(GENERIC_L031K4TX_usb_none INTERFACE @@ -79851,15 +79851,15 @@ target_compile_options(GENERIC_L031K6TX_serial_none INTERFACE ) add_library(GENERIC_L031K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L031K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L031K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L031K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L031K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L031K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L031K6TX_usb_none INTERFACE) target_compile_options(GENERIC_L031K6TX_usb_none INTERFACE @@ -79921,15 +79921,15 @@ target_compile_options(GENERIC_L041C4TX_serial_none INTERFACE ) add_library(GENERIC_L041C4TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L041C4TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L041C4TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L041C4TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L041C4TX_usb_HID INTERFACE) target_compile_options(GENERIC_L041C4TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L041C4TX_usb_none INTERFACE) target_compile_options(GENERIC_L041C4TX_usb_none INTERFACE @@ -79991,15 +79991,15 @@ target_compile_options(GENERIC_L041C6TX_serial_none INTERFACE ) add_library(GENERIC_L041C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L041C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L041C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L041C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L041C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L041C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L041C6TX_usb_none INTERFACE) target_compile_options(GENERIC_L041C6TX_usb_none INTERFACE @@ -80061,15 +80061,15 @@ target_compile_options(GENERIC_L041C6UX_serial_none INTERFACE ) add_library(GENERIC_L041C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L041C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L041C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L041C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L041C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L041C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L041C6UX_usb_none INTERFACE) target_compile_options(GENERIC_L041C6UX_usb_none INTERFACE @@ -80131,15 +80131,15 @@ target_compile_options(GENERIC_L041E6YX_serial_none INTERFACE ) add_library(GENERIC_L041E6YX_usb_CDC INTERFACE) target_compile_options(GENERIC_L041E6YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L041E6YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L041E6YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L041E6YX_usb_HID INTERFACE) target_compile_options(GENERIC_L041E6YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L041E6YX_usb_none INTERFACE) target_compile_options(GENERIC_L041E6YX_usb_none INTERFACE @@ -80201,15 +80201,15 @@ target_compile_options(GENERIC_L041F6PX_serial_none INTERFACE ) add_library(GENERIC_L041F6PX_usb_CDC INTERFACE) target_compile_options(GENERIC_L041F6PX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L041F6PX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L041F6PX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L041F6PX_usb_HID INTERFACE) target_compile_options(GENERIC_L041F6PX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L041F6PX_usb_none INTERFACE) target_compile_options(GENERIC_L041F6PX_usb_none INTERFACE @@ -80271,15 +80271,15 @@ target_compile_options(GENERIC_L041G6UX_serial_none INTERFACE ) add_library(GENERIC_L041G6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L041G6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L041G6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L041G6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L041G6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L041G6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L041G6UX_usb_none INTERFACE) target_compile_options(GENERIC_L041G6UX_usb_none INTERFACE @@ -80341,15 +80341,15 @@ target_compile_options(GENERIC_L041K6TX_serial_none INTERFACE ) add_library(GENERIC_L041K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L041K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L041K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L041K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L041K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L041K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L041K6TX_usb_none INTERFACE) target_compile_options(GENERIC_L041K6TX_usb_none INTERFACE @@ -80411,15 +80411,15 @@ target_compile_options(GENERIC_L051C6TX_serial_none INTERFACE ) add_library(GENERIC_L051C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L051C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L051C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L051C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L051C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L051C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L051C6TX_usb_none INTERFACE) target_compile_options(GENERIC_L051C6TX_usb_none INTERFACE @@ -80481,15 +80481,15 @@ target_compile_options(GENERIC_L051C6UX_serial_none INTERFACE ) add_library(GENERIC_L051C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L051C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L051C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L051C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L051C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L051C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L051C6UX_usb_none INTERFACE) target_compile_options(GENERIC_L051C6UX_usb_none INTERFACE @@ -80551,15 +80551,15 @@ target_compile_options(GENERIC_L051C8TX_serial_none INTERFACE ) add_library(GENERIC_L051C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L051C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L051C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L051C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L051C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L051C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L051C8TX_usb_none INTERFACE) target_compile_options(GENERIC_L051C8TX_usb_none INTERFACE @@ -80621,15 +80621,15 @@ target_compile_options(GENERIC_L051C8UX_serial_none INTERFACE ) add_library(GENERIC_L051C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L051C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L051C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L051C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L051C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_L051C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L051C8UX_usb_none INTERFACE) target_compile_options(GENERIC_L051C8UX_usb_none INTERFACE @@ -80691,15 +80691,15 @@ target_compile_options(GENERIC_L052C6TX_serial_none INTERFACE ) add_library(GENERIC_L052C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L052C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052C6TX_usb_none INTERFACE) target_compile_options(GENERIC_L052C6TX_usb_none INTERFACE @@ -80761,15 +80761,15 @@ target_compile_options(GENERIC_L052C6UX_serial_none INTERFACE ) add_library(GENERIC_L052C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L052C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052C6UX_usb_none INTERFACE) target_compile_options(GENERIC_L052C6UX_usb_none INTERFACE @@ -80831,15 +80831,15 @@ target_compile_options(GENERIC_L052C8TX_serial_none INTERFACE ) add_library(GENERIC_L052C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L052C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052C8TX_usb_none INTERFACE) target_compile_options(GENERIC_L052C8TX_usb_none INTERFACE @@ -80901,15 +80901,15 @@ target_compile_options(GENERIC_L052C8UX_serial_none INTERFACE ) add_library(GENERIC_L052C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_L052C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052C8UX_usb_none INTERFACE) target_compile_options(GENERIC_L052C8UX_usb_none INTERFACE @@ -80971,15 +80971,15 @@ target_compile_options(GENERIC_L052K6TX_serial_none INTERFACE ) add_library(GENERIC_L052K6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052K6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052K6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052K6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052K6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L052K6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052K6TX_usb_none INTERFACE) target_compile_options(GENERIC_L052K6TX_usb_none INTERFACE @@ -81041,15 +81041,15 @@ target_compile_options(GENERIC_L052K8TX_serial_none INTERFACE ) add_library(GENERIC_L052K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L052K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052K8TX_usb_none INTERFACE) target_compile_options(GENERIC_L052K8TX_usb_none INTERFACE @@ -81111,15 +81111,15 @@ target_compile_options(GENERIC_L052R6HX_serial_none INTERFACE ) add_library(GENERIC_L052R6HX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052R6HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052R6HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052R6HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052R6HX_usb_HID INTERFACE) target_compile_options(GENERIC_L052R6HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052R6HX_usb_none INTERFACE) target_compile_options(GENERIC_L052R6HX_usb_none INTERFACE @@ -81181,15 +81181,15 @@ target_compile_options(GENERIC_L052R6TX_serial_none INTERFACE ) add_library(GENERIC_L052R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L052R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052R6TX_usb_none INTERFACE) target_compile_options(GENERIC_L052R6TX_usb_none INTERFACE @@ -81251,15 +81251,15 @@ target_compile_options(GENERIC_L052R8HX_serial_none INTERFACE ) add_library(GENERIC_L052R8HX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052R8HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052R8HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052R8HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052R8HX_usb_HID INTERFACE) target_compile_options(GENERIC_L052R8HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052R8HX_usb_none INTERFACE) target_compile_options(GENERIC_L052R8HX_usb_none INTERFACE @@ -81321,15 +81321,15 @@ target_compile_options(GENERIC_L052R8TX_serial_none INTERFACE ) add_library(GENERIC_L052R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L052R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052R8TX_usb_none INTERFACE) target_compile_options(GENERIC_L052R8TX_usb_none INTERFACE @@ -81391,15 +81391,15 @@ target_compile_options(GENERIC_L052T6YX_serial_none INTERFACE ) add_library(GENERIC_L052T6YX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052T6YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052T6YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052T6YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052T6YX_usb_HID INTERFACE) target_compile_options(GENERIC_L052T6YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052T6YX_usb_none INTERFACE) target_compile_options(GENERIC_L052T6YX_usb_none INTERFACE @@ -81461,15 +81461,15 @@ target_compile_options(GENERIC_L052T8FX_serial_none INTERFACE ) add_library(GENERIC_L052T8FX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052T8FX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052T8FX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052T8FX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052T8FX_usb_HID INTERFACE) target_compile_options(GENERIC_L052T8FX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052T8FX_usb_none INTERFACE) target_compile_options(GENERIC_L052T8FX_usb_none INTERFACE @@ -81531,15 +81531,15 @@ target_compile_options(GENERIC_L052T8YX_serial_none INTERFACE ) add_library(GENERIC_L052T8YX_usb_CDC INTERFACE) target_compile_options(GENERIC_L052T8YX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L052T8YX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L052T8YX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L052T8YX_usb_HID INTERFACE) target_compile_options(GENERIC_L052T8YX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L052T8YX_usb_none INTERFACE) target_compile_options(GENERIC_L052T8YX_usb_none INTERFACE @@ -81601,15 +81601,15 @@ target_compile_options(GENERIC_L053C6TX_serial_none INTERFACE ) add_library(GENERIC_L053C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L053C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L053C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L053C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L053C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L053C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L053C6TX_usb_none INTERFACE) target_compile_options(GENERIC_L053C6TX_usb_none INTERFACE @@ -81671,15 +81671,15 @@ target_compile_options(GENERIC_L053C6UX_serial_none INTERFACE ) add_library(GENERIC_L053C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L053C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L053C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L053C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L053C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L053C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L053C6UX_usb_none INTERFACE) target_compile_options(GENERIC_L053C6UX_usb_none INTERFACE @@ -81741,15 +81741,15 @@ target_compile_options(GENERIC_L053C8TX_serial_none INTERFACE ) add_library(GENERIC_L053C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L053C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L053C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L053C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L053C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L053C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L053C8TX_usb_none INTERFACE) target_compile_options(GENERIC_L053C8TX_usb_none INTERFACE @@ -81811,15 +81811,15 @@ target_compile_options(GENERIC_L053C8UX_serial_none INTERFACE ) add_library(GENERIC_L053C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L053C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L053C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L053C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L053C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_L053C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L053C8UX_usb_none INTERFACE) target_compile_options(GENERIC_L053C8UX_usb_none INTERFACE @@ -81881,15 +81881,15 @@ target_compile_options(GENERIC_L053R6HX_serial_none INTERFACE ) add_library(GENERIC_L053R6HX_usb_CDC INTERFACE) target_compile_options(GENERIC_L053R6HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L053R6HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L053R6HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L053R6HX_usb_HID INTERFACE) target_compile_options(GENERIC_L053R6HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L053R6HX_usb_none INTERFACE) target_compile_options(GENERIC_L053R6HX_usb_none INTERFACE @@ -81951,15 +81951,15 @@ target_compile_options(GENERIC_L053R6TX_serial_none INTERFACE ) add_library(GENERIC_L053R6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L053R6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L053R6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L053R6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L053R6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L053R6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L053R6TX_usb_none INTERFACE) target_compile_options(GENERIC_L053R6TX_usb_none INTERFACE @@ -82021,15 +82021,15 @@ target_compile_options(GENERIC_L053R8HX_serial_none INTERFACE ) add_library(GENERIC_L053R8HX_usb_CDC INTERFACE) target_compile_options(GENERIC_L053R8HX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L053R8HX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L053R8HX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L053R8HX_usb_HID INTERFACE) target_compile_options(GENERIC_L053R8HX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L053R8HX_usb_none INTERFACE) target_compile_options(GENERIC_L053R8HX_usb_none INTERFACE @@ -82091,15 +82091,15 @@ target_compile_options(GENERIC_L053R8TX_serial_none INTERFACE ) add_library(GENERIC_L053R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L053R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L053R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L053R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L053R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L053R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L053R8TX_usb_none INTERFACE) target_compile_options(GENERIC_L053R8TX_usb_none INTERFACE @@ -82161,15 +82161,15 @@ target_compile_options(GENERIC_L062C8UX_serial_none INTERFACE ) add_library(GENERIC_L062C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L062C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L062C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L062C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L062C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_L062C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L062C8UX_usb_none INTERFACE) target_compile_options(GENERIC_L062C8UX_usb_none INTERFACE @@ -82231,15 +82231,15 @@ target_compile_options(GENERIC_L062K8TX_serial_none INTERFACE ) add_library(GENERIC_L062K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L062K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L062K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L062K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L062K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L062K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L062K8TX_usb_none INTERFACE) target_compile_options(GENERIC_L062K8TX_usb_none INTERFACE @@ -82301,15 +82301,15 @@ target_compile_options(GENERIC_L063C8TX_serial_none INTERFACE ) add_library(GENERIC_L063C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L063C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L063C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L063C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L063C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L063C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L063C8TX_usb_none INTERFACE) target_compile_options(GENERIC_L063C8TX_usb_none INTERFACE @@ -82371,15 +82371,15 @@ target_compile_options(GENERIC_L063C8UX_serial_none INTERFACE ) add_library(GENERIC_L063C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L063C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L063C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L063C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L063C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_L063C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L063C8UX_usb_none INTERFACE) target_compile_options(GENERIC_L063C8UX_usb_none INTERFACE @@ -82441,15 +82441,15 @@ target_compile_options(GENERIC_L063R8TX_serial_none INTERFACE ) add_library(GENERIC_L063R8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L063R8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L063R8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L063R8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L063R8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L063R8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L063R8TX_usb_none INTERFACE) target_compile_options(GENERIC_L063R8TX_usb_none INTERFACE @@ -82511,15 +82511,15 @@ target_compile_options(GENERIC_L072CBTX_serial_none INTERFACE ) add_library(GENERIC_L072CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L072CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072CBTX_usb_none INTERFACE) target_compile_options(GENERIC_L072CBTX_usb_none INTERFACE @@ -82581,15 +82581,15 @@ target_compile_options(GENERIC_L072CBUX_serial_none INTERFACE ) add_library(GENERIC_L072CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L072CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072CBUX_usb_none INTERFACE) target_compile_options(GENERIC_L072CBUX_usb_none INTERFACE @@ -82651,15 +82651,15 @@ target_compile_options(GENERIC_L072CBYX_serial_none INTERFACE ) add_library(GENERIC_L072CBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072CBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072CBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072CBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072CBYX_usb_HID INTERFACE) target_compile_options(GENERIC_L072CBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072CBYX_usb_none INTERFACE) target_compile_options(GENERIC_L072CBYX_usb_none INTERFACE @@ -82721,15 +82721,15 @@ target_compile_options(GENERIC_L072CZEX_serial_none INTERFACE ) add_library(GENERIC_L072CZEX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072CZEX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072CZEX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072CZEX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072CZEX_usb_HID INTERFACE) target_compile_options(GENERIC_L072CZEX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072CZEX_usb_none INTERFACE) target_compile_options(GENERIC_L072CZEX_usb_none INTERFACE @@ -82791,15 +82791,15 @@ target_compile_options(GENERIC_L072CZTX_serial_none INTERFACE ) add_library(GENERIC_L072CZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072CZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072CZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072CZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072CZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L072CZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072CZTX_usb_none INTERFACE) target_compile_options(GENERIC_L072CZTX_usb_none INTERFACE @@ -82861,15 +82861,15 @@ target_compile_options(GENERIC_L072CZUX_serial_none INTERFACE ) add_library(GENERIC_L072CZUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072CZUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072CZUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072CZUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072CZUX_usb_HID INTERFACE) target_compile_options(GENERIC_L072CZUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072CZUX_usb_none INTERFACE) target_compile_options(GENERIC_L072CZUX_usb_none INTERFACE @@ -82931,15 +82931,15 @@ target_compile_options(GENERIC_L072CZYX_serial_none INTERFACE ) add_library(GENERIC_L072CZYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072CZYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072CZYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072CZYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072CZYX_usb_HID INTERFACE) target_compile_options(GENERIC_L072CZYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072CZYX_usb_none INTERFACE) target_compile_options(GENERIC_L072CZYX_usb_none INTERFACE @@ -83001,15 +83001,15 @@ target_compile_options(GENERIC_L072KBTX_serial_none INTERFACE ) add_library(GENERIC_L072KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L072KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072KBTX_usb_none INTERFACE) target_compile_options(GENERIC_L072KBTX_usb_none INTERFACE @@ -83071,15 +83071,15 @@ target_compile_options(GENERIC_L072KBUX_serial_none INTERFACE ) add_library(GENERIC_L072KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L072KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072KBUX_usb_none INTERFACE) target_compile_options(GENERIC_L072KBUX_usb_none INTERFACE @@ -83141,15 +83141,15 @@ target_compile_options(GENERIC_L072KZTX_serial_none INTERFACE ) add_library(GENERIC_L072KZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072KZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072KZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072KZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072KZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L072KZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072KZTX_usb_none INTERFACE) target_compile_options(GENERIC_L072KZTX_usb_none INTERFACE @@ -83211,15 +83211,15 @@ target_compile_options(GENERIC_L072KZUX_serial_none INTERFACE ) add_library(GENERIC_L072KZUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072KZUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072KZUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072KZUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072KZUX_usb_HID INTERFACE) target_compile_options(GENERIC_L072KZUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072KZUX_usb_none INTERFACE) target_compile_options(GENERIC_L072KZUX_usb_none INTERFACE @@ -83281,15 +83281,15 @@ target_compile_options(GENERIC_L072RBHX_serial_none INTERFACE ) add_library(GENERIC_L072RBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072RBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072RBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072RBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072RBHX_usb_HID INTERFACE) target_compile_options(GENERIC_L072RBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072RBHX_usb_none INTERFACE) target_compile_options(GENERIC_L072RBHX_usb_none INTERFACE @@ -83351,15 +83351,15 @@ target_compile_options(GENERIC_L072RBIX_serial_none INTERFACE ) add_library(GENERIC_L072RBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072RBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072RBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072RBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072RBIX_usb_HID INTERFACE) target_compile_options(GENERIC_L072RBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072RBIX_usb_none INTERFACE) target_compile_options(GENERIC_L072RBIX_usb_none INTERFACE @@ -83421,15 +83421,15 @@ target_compile_options(GENERIC_L072RBTX_serial_none INTERFACE ) add_library(GENERIC_L072RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L072RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072RBTX_usb_none INTERFACE) target_compile_options(GENERIC_L072RBTX_usb_none INTERFACE @@ -83491,15 +83491,15 @@ target_compile_options(GENERIC_L072RZHX_serial_none INTERFACE ) add_library(GENERIC_L072RZHX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072RZHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072RZHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072RZHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072RZHX_usb_HID INTERFACE) target_compile_options(GENERIC_L072RZHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072RZHX_usb_none INTERFACE) target_compile_options(GENERIC_L072RZHX_usb_none INTERFACE @@ -83561,15 +83561,15 @@ target_compile_options(GENERIC_L072RZIX_serial_none INTERFACE ) add_library(GENERIC_L072RZIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072RZIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072RZIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072RZIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072RZIX_usb_HID INTERFACE) target_compile_options(GENERIC_L072RZIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072RZIX_usb_none INTERFACE) target_compile_options(GENERIC_L072RZIX_usb_none INTERFACE @@ -83631,15 +83631,15 @@ target_compile_options(GENERIC_L072RZTX_serial_none INTERFACE ) add_library(GENERIC_L072RZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072RZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072RZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072RZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072RZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L072RZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072RZTX_usb_none INTERFACE) target_compile_options(GENERIC_L072RZTX_usb_none INTERFACE @@ -83701,15 +83701,15 @@ target_compile_options(GENERIC_L072V8IX_serial_none INTERFACE ) add_library(GENERIC_L072V8IX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072V8IX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072V8IX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072V8IX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072V8IX_usb_HID INTERFACE) target_compile_options(GENERIC_L072V8IX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072V8IX_usb_none INTERFACE) target_compile_options(GENERIC_L072V8IX_usb_none INTERFACE @@ -83771,15 +83771,15 @@ target_compile_options(GENERIC_L072V8TX_serial_none INTERFACE ) add_library(GENERIC_L072V8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072V8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072V8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072V8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072V8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L072V8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072V8TX_usb_none INTERFACE) target_compile_options(GENERIC_L072V8TX_usb_none INTERFACE @@ -83841,15 +83841,15 @@ target_compile_options(GENERIC_L072VBIX_serial_none INTERFACE ) add_library(GENERIC_L072VBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072VBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072VBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072VBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072VBIX_usb_HID INTERFACE) target_compile_options(GENERIC_L072VBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072VBIX_usb_none INTERFACE) target_compile_options(GENERIC_L072VBIX_usb_none INTERFACE @@ -83911,15 +83911,15 @@ target_compile_options(GENERIC_L072VBTX_serial_none INTERFACE ) add_library(GENERIC_L072VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L072VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072VBTX_usb_none INTERFACE) target_compile_options(GENERIC_L072VBTX_usb_none INTERFACE @@ -83981,15 +83981,15 @@ target_compile_options(GENERIC_L072VZIX_serial_none INTERFACE ) add_library(GENERIC_L072VZIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072VZIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072VZIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072VZIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072VZIX_usb_HID INTERFACE) target_compile_options(GENERIC_L072VZIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072VZIX_usb_none INTERFACE) target_compile_options(GENERIC_L072VZIX_usb_none INTERFACE @@ -84051,15 +84051,15 @@ target_compile_options(GENERIC_L072VZTX_serial_none INTERFACE ) add_library(GENERIC_L072VZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L072VZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L072VZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L072VZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L072VZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L072VZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L072VZTX_usb_none INTERFACE) target_compile_options(GENERIC_L072VZTX_usb_none INTERFACE @@ -84121,15 +84121,15 @@ target_compile_options(GENERIC_L073CBTX_serial_none INTERFACE ) add_library(GENERIC_L073CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L073CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073CBTX_usb_none INTERFACE) target_compile_options(GENERIC_L073CBTX_usb_none INTERFACE @@ -84191,15 +84191,15 @@ target_compile_options(GENERIC_L073CBUX_serial_none INTERFACE ) add_library(GENERIC_L073CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L073CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073CBUX_usb_none INTERFACE) target_compile_options(GENERIC_L073CBUX_usb_none INTERFACE @@ -84261,15 +84261,15 @@ target_compile_options(GENERIC_L073CZTX_serial_none INTERFACE ) add_library(GENERIC_L073CZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073CZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073CZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073CZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073CZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L073CZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073CZTX_usb_none INTERFACE) target_compile_options(GENERIC_L073CZTX_usb_none INTERFACE @@ -84331,15 +84331,15 @@ target_compile_options(GENERIC_L073CZUX_serial_none INTERFACE ) add_library(GENERIC_L073CZUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073CZUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073CZUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073CZUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073CZUX_usb_HID INTERFACE) target_compile_options(GENERIC_L073CZUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073CZUX_usb_none INTERFACE) target_compile_options(GENERIC_L073CZUX_usb_none INTERFACE @@ -84401,15 +84401,15 @@ target_compile_options(GENERIC_L073CZYX_serial_none INTERFACE ) add_library(GENERIC_L073CZYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073CZYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073CZYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073CZYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073CZYX_usb_HID INTERFACE) target_compile_options(GENERIC_L073CZYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073CZYX_usb_none INTERFACE) target_compile_options(GENERIC_L073CZYX_usb_none INTERFACE @@ -84471,15 +84471,15 @@ target_compile_options(GENERIC_L073RBHX_serial_none INTERFACE ) add_library(GENERIC_L073RBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073RBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073RBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073RBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073RBHX_usb_HID INTERFACE) target_compile_options(GENERIC_L073RBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073RBHX_usb_none INTERFACE) target_compile_options(GENERIC_L073RBHX_usb_none INTERFACE @@ -84541,15 +84541,15 @@ target_compile_options(GENERIC_L073RBTX_serial_none INTERFACE ) add_library(GENERIC_L073RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L073RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073RBTX_usb_none INTERFACE) target_compile_options(GENERIC_L073RBTX_usb_none INTERFACE @@ -84611,15 +84611,15 @@ target_compile_options(GENERIC_L073RZHX_serial_none INTERFACE ) add_library(GENERIC_L073RZHX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073RZHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073RZHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073RZHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073RZHX_usb_HID INTERFACE) target_compile_options(GENERIC_L073RZHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073RZHX_usb_none INTERFACE) target_compile_options(GENERIC_L073RZHX_usb_none INTERFACE @@ -84681,15 +84681,15 @@ target_compile_options(GENERIC_L073RZIX_serial_none INTERFACE ) add_library(GENERIC_L073RZIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073RZIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073RZIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073RZIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073RZIX_usb_HID INTERFACE) target_compile_options(GENERIC_L073RZIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073RZIX_usb_none INTERFACE) target_compile_options(GENERIC_L073RZIX_usb_none INTERFACE @@ -84751,15 +84751,15 @@ target_compile_options(GENERIC_L073RZTX_serial_none INTERFACE ) add_library(GENERIC_L073RZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073RZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073RZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073RZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073RZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L073RZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073RZTX_usb_none INTERFACE) target_compile_options(GENERIC_L073RZTX_usb_none INTERFACE @@ -84821,15 +84821,15 @@ target_compile_options(GENERIC_L073V8IX_serial_none INTERFACE ) add_library(GENERIC_L073V8IX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073V8IX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073V8IX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073V8IX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073V8IX_usb_HID INTERFACE) target_compile_options(GENERIC_L073V8IX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073V8IX_usb_none INTERFACE) target_compile_options(GENERIC_L073V8IX_usb_none INTERFACE @@ -84891,15 +84891,15 @@ target_compile_options(GENERIC_L073V8TX_serial_none INTERFACE ) add_library(GENERIC_L073V8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073V8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073V8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073V8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073V8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L073V8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073V8TX_usb_none INTERFACE) target_compile_options(GENERIC_L073V8TX_usb_none INTERFACE @@ -84961,15 +84961,15 @@ target_compile_options(GENERIC_L073VBIX_serial_none INTERFACE ) add_library(GENERIC_L073VBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073VBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073VBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073VBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073VBIX_usb_HID INTERFACE) target_compile_options(GENERIC_L073VBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073VBIX_usb_none INTERFACE) target_compile_options(GENERIC_L073VBIX_usb_none INTERFACE @@ -85031,15 +85031,15 @@ target_compile_options(GENERIC_L073VBTX_serial_none INTERFACE ) add_library(GENERIC_L073VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L073VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073VBTX_usb_none INTERFACE) target_compile_options(GENERIC_L073VBTX_usb_none INTERFACE @@ -85101,15 +85101,15 @@ target_compile_options(GENERIC_L073VZIX_serial_none INTERFACE ) add_library(GENERIC_L073VZIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073VZIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073VZIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073VZIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073VZIX_usb_HID INTERFACE) target_compile_options(GENERIC_L073VZIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073VZIX_usb_none INTERFACE) target_compile_options(GENERIC_L073VZIX_usb_none INTERFACE @@ -85171,15 +85171,15 @@ target_compile_options(GENERIC_L073VZTX_serial_none INTERFACE ) add_library(GENERIC_L073VZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L073VZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L073VZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L073VZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L073VZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L073VZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L073VZTX_usb_none INTERFACE) target_compile_options(GENERIC_L073VZTX_usb_none INTERFACE @@ -85241,15 +85241,15 @@ target_compile_options(GENERIC_L082CZUX_serial_none INTERFACE ) add_library(GENERIC_L082CZUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L082CZUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L082CZUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L082CZUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L082CZUX_usb_HID INTERFACE) target_compile_options(GENERIC_L082CZUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L082CZUX_usb_none INTERFACE) target_compile_options(GENERIC_L082CZUX_usb_none INTERFACE @@ -85311,15 +85311,15 @@ target_compile_options(GENERIC_L082CZYX_serial_none INTERFACE ) add_library(GENERIC_L082CZYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L082CZYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L082CZYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L082CZYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L082CZYX_usb_HID INTERFACE) target_compile_options(GENERIC_L082CZYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L082CZYX_usb_none INTERFACE) target_compile_options(GENERIC_L082CZYX_usb_none INTERFACE @@ -85381,15 +85381,15 @@ target_compile_options(GENERIC_L082KBTX_serial_none INTERFACE ) add_library(GENERIC_L082KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L082KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L082KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L082KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L082KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L082KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L082KBTX_usb_none INTERFACE) target_compile_options(GENERIC_L082KBTX_usb_none INTERFACE @@ -85451,15 +85451,15 @@ target_compile_options(GENERIC_L082KBUX_serial_none INTERFACE ) add_library(GENERIC_L082KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L082KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L082KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L082KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L082KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L082KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L082KBUX_usb_none INTERFACE) target_compile_options(GENERIC_L082KBUX_usb_none INTERFACE @@ -85521,15 +85521,15 @@ target_compile_options(GENERIC_L082KZTX_serial_none INTERFACE ) add_library(GENERIC_L082KZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L082KZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L082KZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L082KZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L082KZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L082KZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L082KZTX_usb_none INTERFACE) target_compile_options(GENERIC_L082KZTX_usb_none INTERFACE @@ -85591,15 +85591,15 @@ target_compile_options(GENERIC_L082KZUX_serial_none INTERFACE ) add_library(GENERIC_L082KZUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L082KZUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L082KZUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L082KZUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L082KZUX_usb_HID INTERFACE) target_compile_options(GENERIC_L082KZUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L082KZUX_usb_none INTERFACE) target_compile_options(GENERIC_L082KZUX_usb_none INTERFACE @@ -85661,15 +85661,15 @@ target_compile_options(GENERIC_L083CBTX_serial_none INTERFACE ) add_library(GENERIC_L083CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L083CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083CBTX_usb_none INTERFACE) target_compile_options(GENERIC_L083CBTX_usb_none INTERFACE @@ -85731,15 +85731,15 @@ target_compile_options(GENERIC_L083CZTX_serial_none INTERFACE ) add_library(GENERIC_L083CZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083CZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083CZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083CZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083CZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L083CZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083CZTX_usb_none INTERFACE) target_compile_options(GENERIC_L083CZTX_usb_none INTERFACE @@ -85801,15 +85801,15 @@ target_compile_options(GENERIC_L083CZUX_serial_none INTERFACE ) add_library(GENERIC_L083CZUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083CZUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083CZUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083CZUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083CZUX_usb_HID INTERFACE) target_compile_options(GENERIC_L083CZUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083CZUX_usb_none INTERFACE) target_compile_options(GENERIC_L083CZUX_usb_none INTERFACE @@ -85871,15 +85871,15 @@ target_compile_options(GENERIC_L083RBHX_serial_none INTERFACE ) add_library(GENERIC_L083RBHX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083RBHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083RBHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083RBHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083RBHX_usb_HID INTERFACE) target_compile_options(GENERIC_L083RBHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083RBHX_usb_none INTERFACE) target_compile_options(GENERIC_L083RBHX_usb_none INTERFACE @@ -85941,15 +85941,15 @@ target_compile_options(GENERIC_L083RBTX_serial_none INTERFACE ) add_library(GENERIC_L083RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L083RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083RBTX_usb_none INTERFACE) target_compile_options(GENERIC_L083RBTX_usb_none INTERFACE @@ -86011,15 +86011,15 @@ target_compile_options(GENERIC_L083RZHX_serial_none INTERFACE ) add_library(GENERIC_L083RZHX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083RZHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083RZHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083RZHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083RZHX_usb_HID INTERFACE) target_compile_options(GENERIC_L083RZHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083RZHX_usb_none INTERFACE) target_compile_options(GENERIC_L083RZHX_usb_none INTERFACE @@ -86081,15 +86081,15 @@ target_compile_options(GENERIC_L083RZTX_serial_none INTERFACE ) add_library(GENERIC_L083RZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083RZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083RZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083RZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083RZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L083RZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083RZTX_usb_none INTERFACE) target_compile_options(GENERIC_L083RZTX_usb_none INTERFACE @@ -86151,15 +86151,15 @@ target_compile_options(GENERIC_L083V8IX_serial_none INTERFACE ) add_library(GENERIC_L083V8IX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083V8IX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083V8IX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083V8IX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083V8IX_usb_HID INTERFACE) target_compile_options(GENERIC_L083V8IX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083V8IX_usb_none INTERFACE) target_compile_options(GENERIC_L083V8IX_usb_none INTERFACE @@ -86221,15 +86221,15 @@ target_compile_options(GENERIC_L083V8TX_serial_none INTERFACE ) add_library(GENERIC_L083V8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083V8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083V8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083V8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083V8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L083V8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083V8TX_usb_none INTERFACE) target_compile_options(GENERIC_L083V8TX_usb_none INTERFACE @@ -86291,15 +86291,15 @@ target_compile_options(GENERIC_L083VBIX_serial_none INTERFACE ) add_library(GENERIC_L083VBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083VBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083VBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083VBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083VBIX_usb_HID INTERFACE) target_compile_options(GENERIC_L083VBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083VBIX_usb_none INTERFACE) target_compile_options(GENERIC_L083VBIX_usb_none INTERFACE @@ -86361,15 +86361,15 @@ target_compile_options(GENERIC_L083VBTX_serial_none INTERFACE ) add_library(GENERIC_L083VBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083VBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083VBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L083VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083VBTX_usb_none INTERFACE) target_compile_options(GENERIC_L083VBTX_usb_none INTERFACE @@ -86431,15 +86431,15 @@ target_compile_options(GENERIC_L083VZIX_serial_none INTERFACE ) add_library(GENERIC_L083VZIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083VZIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083VZIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083VZIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083VZIX_usb_HID INTERFACE) target_compile_options(GENERIC_L083VZIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083VZIX_usb_none INTERFACE) target_compile_options(GENERIC_L083VZIX_usb_none INTERFACE @@ -86501,15 +86501,15 @@ target_compile_options(GENERIC_L083VZTX_serial_none INTERFACE ) add_library(GENERIC_L083VZTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L083VZTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L083VZTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L083VZTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L083VZTX_usb_HID INTERFACE) target_compile_options(GENERIC_L083VZTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L083VZTX_usb_none INTERFACE) target_compile_options(GENERIC_L083VZTX_usb_none INTERFACE @@ -86571,15 +86571,15 @@ target_compile_options(GENERIC_L100C6UX_serial_none INTERFACE ) add_library(GENERIC_L100C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L100C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L100C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L100C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L100C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L100C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L100C6UX_usb_none INTERFACE) target_compile_options(GENERIC_L100C6UX_usb_none INTERFACE @@ -86641,15 +86641,15 @@ target_compile_options(GENERIC_L100C6UXA_serial_none INTERFACE ) add_library(GENERIC_L100C6UXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L100C6UXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L100C6UXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L100C6UXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L100C6UXA_usb_HID INTERFACE) target_compile_options(GENERIC_L100C6UXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L100C6UXA_usb_none INTERFACE) target_compile_options(GENERIC_L100C6UXA_usb_none INTERFACE @@ -86711,15 +86711,15 @@ target_compile_options(GENERIC_L151C6TX_serial_none INTERFACE ) add_library(GENERIC_L151C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L151C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L151C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151C6TX_usb_none INTERFACE) target_compile_options(GENERIC_L151C6TX_usb_none INTERFACE @@ -86781,15 +86781,15 @@ target_compile_options(GENERIC_L151C6TXA_serial_none INTERFACE ) add_library(GENERIC_L151C6TXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L151C6TXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151C6TXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151C6TXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151C6TXA_usb_HID INTERFACE) target_compile_options(GENERIC_L151C6TXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151C6TXA_usb_none INTERFACE) target_compile_options(GENERIC_L151C6TXA_usb_none INTERFACE @@ -86851,15 +86851,15 @@ target_compile_options(GENERIC_L151C6UX_serial_none INTERFACE ) add_library(GENERIC_L151C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L151C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L151C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151C6UX_usb_none INTERFACE) target_compile_options(GENERIC_L151C6UX_usb_none INTERFACE @@ -86921,15 +86921,15 @@ target_compile_options(GENERIC_L151C6UXA_serial_none INTERFACE ) add_library(GENERIC_L151C6UXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L151C6UXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151C6UXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151C6UXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151C6UXA_usb_HID INTERFACE) target_compile_options(GENERIC_L151C6UXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151C6UXA_usb_none INTERFACE) target_compile_options(GENERIC_L151C6UXA_usb_none INTERFACE @@ -86991,15 +86991,15 @@ target_compile_options(GENERIC_L151C8TX_serial_none INTERFACE ) add_library(GENERIC_L151C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L151C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L151C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151C8TX_usb_none INTERFACE) target_compile_options(GENERIC_L151C8TX_usb_none INTERFACE @@ -87061,15 +87061,15 @@ target_compile_options(GENERIC_L151C8TXA_serial_none INTERFACE ) add_library(GENERIC_L151C8TXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L151C8TXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151C8TXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151C8TXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151C8TXA_usb_HID INTERFACE) target_compile_options(GENERIC_L151C8TXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151C8TXA_usb_none INTERFACE) target_compile_options(GENERIC_L151C8TXA_usb_none INTERFACE @@ -87131,15 +87131,15 @@ target_compile_options(GENERIC_L151C8UX_serial_none INTERFACE ) add_library(GENERIC_L151C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L151C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_L151C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151C8UX_usb_none INTERFACE) target_compile_options(GENERIC_L151C8UX_usb_none INTERFACE @@ -87201,15 +87201,15 @@ target_compile_options(GENERIC_L151C8UXA_serial_none INTERFACE ) add_library(GENERIC_L151C8UXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L151C8UXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151C8UXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151C8UXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151C8UXA_usb_HID INTERFACE) target_compile_options(GENERIC_L151C8UXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151C8UXA_usb_none INTERFACE) target_compile_options(GENERIC_L151C8UXA_usb_none INTERFACE @@ -87271,15 +87271,15 @@ target_compile_options(GENERIC_L151CBTX_serial_none INTERFACE ) add_library(GENERIC_L151CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L151CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L151CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151CBTX_usb_none INTERFACE) target_compile_options(GENERIC_L151CBTX_usb_none INTERFACE @@ -87341,15 +87341,15 @@ target_compile_options(GENERIC_L151CBTXA_serial_none INTERFACE ) add_library(GENERIC_L151CBTXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L151CBTXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151CBTXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151CBTXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151CBTXA_usb_HID INTERFACE) target_compile_options(GENERIC_L151CBTXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151CBTXA_usb_none INTERFACE) target_compile_options(GENERIC_L151CBTXA_usb_none INTERFACE @@ -87411,15 +87411,15 @@ target_compile_options(GENERIC_L151CBUX_serial_none INTERFACE ) add_library(GENERIC_L151CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L151CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L151CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151CBUX_usb_none INTERFACE) target_compile_options(GENERIC_L151CBUX_usb_none INTERFACE @@ -87481,15 +87481,15 @@ target_compile_options(GENERIC_L151CBUXA_serial_none INTERFACE ) add_library(GENERIC_L151CBUXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L151CBUXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151CBUXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151CBUXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151CBUXA_usb_HID INTERFACE) target_compile_options(GENERIC_L151CBUXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151CBUXA_usb_none INTERFACE) target_compile_options(GENERIC_L151CBUXA_usb_none INTERFACE @@ -87551,15 +87551,15 @@ target_compile_options(GENERIC_L151RETX_serial_none INTERFACE ) add_library(GENERIC_L151RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L151RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151RETX_usb_HID INTERFACE) target_compile_options(GENERIC_L151RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151RETX_usb_none INTERFACE) target_compile_options(GENERIC_L151RETX_usb_none INTERFACE @@ -87621,15 +87621,15 @@ target_compile_options(GENERIC_L151ZDTX_serial_none INTERFACE ) add_library(GENERIC_L151ZDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L151ZDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L151ZDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L151ZDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L151ZDTX_usb_HID INTERFACE) target_compile_options(GENERIC_L151ZDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L151ZDTX_usb_none INTERFACE) target_compile_options(GENERIC_L151ZDTX_usb_none INTERFACE @@ -87691,15 +87691,15 @@ target_compile_options(GENERIC_L152C6TX_serial_none INTERFACE ) add_library(GENERIC_L152C6TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L152C6TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152C6TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152C6TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152C6TX_usb_HID INTERFACE) target_compile_options(GENERIC_L152C6TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152C6TX_usb_none INTERFACE) target_compile_options(GENERIC_L152C6TX_usb_none INTERFACE @@ -87761,15 +87761,15 @@ target_compile_options(GENERIC_L152C6TXA_serial_none INTERFACE ) add_library(GENERIC_L152C6TXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L152C6TXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152C6TXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152C6TXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152C6TXA_usb_HID INTERFACE) target_compile_options(GENERIC_L152C6TXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152C6TXA_usb_none INTERFACE) target_compile_options(GENERIC_L152C6TXA_usb_none INTERFACE @@ -87831,15 +87831,15 @@ target_compile_options(GENERIC_L152C6UX_serial_none INTERFACE ) add_library(GENERIC_L152C6UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L152C6UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152C6UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152C6UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152C6UX_usb_HID INTERFACE) target_compile_options(GENERIC_L152C6UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152C6UX_usb_none INTERFACE) target_compile_options(GENERIC_L152C6UX_usb_none INTERFACE @@ -87901,15 +87901,15 @@ target_compile_options(GENERIC_L152C6UXA_serial_none INTERFACE ) add_library(GENERIC_L152C6UXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L152C6UXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152C6UXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152C6UXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152C6UXA_usb_HID INTERFACE) target_compile_options(GENERIC_L152C6UXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152C6UXA_usb_none INTERFACE) target_compile_options(GENERIC_L152C6UXA_usb_none INTERFACE @@ -87971,15 +87971,15 @@ target_compile_options(GENERIC_L152C8TX_serial_none INTERFACE ) add_library(GENERIC_L152C8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L152C8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152C8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152C8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152C8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L152C8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152C8TX_usb_none INTERFACE) target_compile_options(GENERIC_L152C8TX_usb_none INTERFACE @@ -88041,15 +88041,15 @@ target_compile_options(GENERIC_L152C8TXA_serial_none INTERFACE ) add_library(GENERIC_L152C8TXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L152C8TXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152C8TXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152C8TXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152C8TXA_usb_HID INTERFACE) target_compile_options(GENERIC_L152C8TXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152C8TXA_usb_none INTERFACE) target_compile_options(GENERIC_L152C8TXA_usb_none INTERFACE @@ -88111,15 +88111,15 @@ target_compile_options(GENERIC_L152C8UX_serial_none INTERFACE ) add_library(GENERIC_L152C8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L152C8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152C8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152C8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152C8UX_usb_HID INTERFACE) target_compile_options(GENERIC_L152C8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152C8UX_usb_none INTERFACE) target_compile_options(GENERIC_L152C8UX_usb_none INTERFACE @@ -88181,15 +88181,15 @@ target_compile_options(GENERIC_L152C8UXA_serial_none INTERFACE ) add_library(GENERIC_L152C8UXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L152C8UXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152C8UXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152C8UXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152C8UXA_usb_HID INTERFACE) target_compile_options(GENERIC_L152C8UXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152C8UXA_usb_none INTERFACE) target_compile_options(GENERIC_L152C8UXA_usb_none INTERFACE @@ -88251,15 +88251,15 @@ target_compile_options(GENERIC_L152CBTX_serial_none INTERFACE ) add_library(GENERIC_L152CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L152CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L152CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152CBTX_usb_none INTERFACE) target_compile_options(GENERIC_L152CBTX_usb_none INTERFACE @@ -88321,15 +88321,15 @@ target_compile_options(GENERIC_L152CBTXA_serial_none INTERFACE ) add_library(GENERIC_L152CBTXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L152CBTXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152CBTXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152CBTXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152CBTXA_usb_HID INTERFACE) target_compile_options(GENERIC_L152CBTXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152CBTXA_usb_none INTERFACE) target_compile_options(GENERIC_L152CBTXA_usb_none INTERFACE @@ -88391,15 +88391,15 @@ target_compile_options(GENERIC_L152CBUX_serial_none INTERFACE ) add_library(GENERIC_L152CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L152CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L152CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152CBUX_usb_none INTERFACE) target_compile_options(GENERIC_L152CBUX_usb_none INTERFACE @@ -88461,15 +88461,15 @@ target_compile_options(GENERIC_L152CBUXA_serial_none INTERFACE ) add_library(GENERIC_L152CBUXA_usb_CDC INTERFACE) target_compile_options(GENERIC_L152CBUXA_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152CBUXA_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152CBUXA_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152CBUXA_usb_HID INTERFACE) target_compile_options(GENERIC_L152CBUXA_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152CBUXA_usb_none INTERFACE) target_compile_options(GENERIC_L152CBUXA_usb_none INTERFACE @@ -88531,15 +88531,15 @@ target_compile_options(GENERIC_L152RETX_serial_none INTERFACE ) add_library(GENERIC_L152RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L152RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152RETX_usb_HID INTERFACE) target_compile_options(GENERIC_L152RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152RETX_usb_none INTERFACE) target_compile_options(GENERIC_L152RETX_usb_none INTERFACE @@ -88601,15 +88601,15 @@ target_compile_options(GENERIC_L152ZDTX_serial_none INTERFACE ) add_library(GENERIC_L152ZDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L152ZDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L152ZDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L152ZDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L152ZDTX_usb_HID INTERFACE) target_compile_options(GENERIC_L152ZDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L152ZDTX_usb_none INTERFACE) target_compile_options(GENERIC_L152ZDTX_usb_none INTERFACE @@ -88671,15 +88671,15 @@ target_compile_options(GENERIC_L162RETX_serial_none INTERFACE ) add_library(GENERIC_L162RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L162RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L162RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L162RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L162RETX_usb_HID INTERFACE) target_compile_options(GENERIC_L162RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L162RETX_usb_none INTERFACE) target_compile_options(GENERIC_L162RETX_usb_none INTERFACE @@ -88741,15 +88741,15 @@ target_compile_options(GENERIC_L162ZDTX_serial_none INTERFACE ) add_library(GENERIC_L162ZDTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L162ZDTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L162ZDTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L162ZDTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L162ZDTX_usb_HID INTERFACE) target_compile_options(GENERIC_L162ZDTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L162ZDTX_usb_none INTERFACE) target_compile_options(GENERIC_L162ZDTX_usb_none INTERFACE @@ -88811,15 +88811,15 @@ target_compile_options(GENERIC_L412K8TX_serial_none INTERFACE ) add_library(GENERIC_L412K8TX_usb_CDC INTERFACE) target_compile_options(GENERIC_L412K8TX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L412K8TX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L412K8TX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L412K8TX_usb_HID INTERFACE) target_compile_options(GENERIC_L412K8TX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L412K8TX_usb_none INTERFACE) target_compile_options(GENERIC_L412K8TX_usb_none INTERFACE @@ -88893,15 +88893,15 @@ target_compile_options(GENERIC_L412K8UX_serial_none INTERFACE ) add_library(GENERIC_L412K8UX_usb_CDC INTERFACE) target_compile_options(GENERIC_L412K8UX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L412K8UX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L412K8UX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L412K8UX_usb_HID INTERFACE) target_compile_options(GENERIC_L412K8UX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L412K8UX_usb_none INTERFACE) target_compile_options(GENERIC_L412K8UX_usb_none INTERFACE @@ -88975,15 +88975,15 @@ target_compile_options(GENERIC_L412KBTX_serial_none INTERFACE ) add_library(GENERIC_L412KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L412KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L412KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L412KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L412KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L412KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L412KBTX_usb_none INTERFACE) target_compile_options(GENERIC_L412KBTX_usb_none INTERFACE @@ -89057,15 +89057,15 @@ target_compile_options(GENERIC_L412KBUX_serial_none INTERFACE ) add_library(GENERIC_L412KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L412KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L412KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L412KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L412KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L412KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L412KBUX_usb_none INTERFACE) target_compile_options(GENERIC_L412KBUX_usb_none INTERFACE @@ -89139,15 +89139,15 @@ target_compile_options(GENERIC_L422KBTX_serial_none INTERFACE ) add_library(GENERIC_L422KBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L422KBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L422KBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L422KBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L422KBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L422KBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L422KBTX_usb_none INTERFACE) target_compile_options(GENERIC_L422KBTX_usb_none INTERFACE @@ -89221,15 +89221,15 @@ target_compile_options(GENERIC_L422KBUX_serial_none INTERFACE ) add_library(GENERIC_L422KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L422KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L422KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L422KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L422KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L422KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L422KBUX_usb_none INTERFACE) target_compile_options(GENERIC_L422KBUX_usb_none INTERFACE @@ -89303,15 +89303,15 @@ target_compile_options(GENERIC_L431RBIX_serial_none INTERFACE ) add_library(GENERIC_L431RBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L431RBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L431RBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L431RBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L431RBIX_usb_HID INTERFACE) target_compile_options(GENERIC_L431RBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L431RBIX_usb_none INTERFACE) target_compile_options(GENERIC_L431RBIX_usb_none INTERFACE @@ -89385,15 +89385,15 @@ target_compile_options(GENERIC_L431RBTX_serial_none INTERFACE ) add_library(GENERIC_L431RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L431RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L431RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L431RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L431RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L431RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L431RBTX_usb_none INTERFACE) target_compile_options(GENERIC_L431RBTX_usb_none INTERFACE @@ -89467,15 +89467,15 @@ target_compile_options(GENERIC_L431RBYX_serial_none INTERFACE ) add_library(GENERIC_L431RBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L431RBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L431RBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L431RBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L431RBYX_usb_HID INTERFACE) target_compile_options(GENERIC_L431RBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L431RBYX_usb_none INTERFACE) target_compile_options(GENERIC_L431RBYX_usb_none INTERFACE @@ -89549,15 +89549,15 @@ target_compile_options(GENERIC_L431RCIX_serial_none INTERFACE ) add_library(GENERIC_L431RCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L431RCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L431RCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L431RCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L431RCIX_usb_HID INTERFACE) target_compile_options(GENERIC_L431RCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L431RCIX_usb_none INTERFACE) target_compile_options(GENERIC_L431RCIX_usb_none INTERFACE @@ -89631,15 +89631,15 @@ target_compile_options(GENERIC_L431RCTX_serial_none INTERFACE ) add_library(GENERIC_L431RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L431RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L431RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L431RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L431RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L431RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L431RCTX_usb_none INTERFACE) target_compile_options(GENERIC_L431RCTX_usb_none INTERFACE @@ -89713,15 +89713,15 @@ target_compile_options(GENERIC_L431RCYX_serial_none INTERFACE ) add_library(GENERIC_L431RCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L431RCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L431RCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L431RCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L431RCYX_usb_HID INTERFACE) target_compile_options(GENERIC_L431RCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L431RCYX_usb_none INTERFACE) target_compile_options(GENERIC_L431RCYX_usb_none INTERFACE @@ -89795,15 +89795,15 @@ target_compile_options(GENERIC_L432KBUX_serial_none INTERFACE ) add_library(GENERIC_L432KBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L432KBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L432KBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L432KBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L432KBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L432KBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L432KBUX_usb_none INTERFACE) target_compile_options(GENERIC_L432KBUX_usb_none INTERFACE @@ -89877,15 +89877,15 @@ target_compile_options(GENERIC_L432KCUX_serial_none INTERFACE ) add_library(GENERIC_L432KCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L432KCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L432KCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L432KCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L432KCUX_usb_HID INTERFACE) target_compile_options(GENERIC_L432KCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L432KCUX_usb_none INTERFACE) target_compile_options(GENERIC_L432KCUX_usb_none INTERFACE @@ -89959,15 +89959,15 @@ target_compile_options(GENERIC_L433CBTX_serial_none INTERFACE ) add_library(GENERIC_L433CBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433CBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433CBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433CBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433CBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L433CBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433CBTX_usb_none INTERFACE) target_compile_options(GENERIC_L433CBTX_usb_none INTERFACE @@ -90041,15 +90041,15 @@ target_compile_options(GENERIC_L433CBUX_serial_none INTERFACE ) add_library(GENERIC_L433CBUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433CBUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433CBUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433CBUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433CBUX_usb_HID INTERFACE) target_compile_options(GENERIC_L433CBUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433CBUX_usb_none INTERFACE) target_compile_options(GENERIC_L433CBUX_usb_none INTERFACE @@ -90123,15 +90123,15 @@ target_compile_options(GENERIC_L433CCTX_serial_none INTERFACE ) add_library(GENERIC_L433CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L433CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433CCTX_usb_none INTERFACE) target_compile_options(GENERIC_L433CCTX_usb_none INTERFACE @@ -90205,15 +90205,15 @@ target_compile_options(GENERIC_L433CCUX_serial_none INTERFACE ) add_library(GENERIC_L433CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_L433CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433CCUX_usb_none INTERFACE) target_compile_options(GENERIC_L433CCUX_usb_none INTERFACE @@ -90287,15 +90287,15 @@ target_compile_options(GENERIC_L433RBIX_serial_none INTERFACE ) add_library(GENERIC_L433RBIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433RBIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433RBIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433RBIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433RBIX_usb_HID INTERFACE) target_compile_options(GENERIC_L433RBIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433RBIX_usb_none INTERFACE) target_compile_options(GENERIC_L433RBIX_usb_none INTERFACE @@ -90369,15 +90369,15 @@ target_compile_options(GENERIC_L433RBTX_serial_none INTERFACE ) add_library(GENERIC_L433RBTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433RBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433RBTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433RBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433RBTX_usb_HID INTERFACE) target_compile_options(GENERIC_L433RBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433RBTX_usb_none INTERFACE) target_compile_options(GENERIC_L433RBTX_usb_none INTERFACE @@ -90451,15 +90451,15 @@ target_compile_options(GENERIC_L433RBYX_serial_none INTERFACE ) add_library(GENERIC_L433RBYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433RBYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433RBYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433RBYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433RBYX_usb_HID INTERFACE) target_compile_options(GENERIC_L433RBYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433RBYX_usb_none INTERFACE) target_compile_options(GENERIC_L433RBYX_usb_none INTERFACE @@ -90533,15 +90533,15 @@ target_compile_options(GENERIC_L433RCIX_serial_none INTERFACE ) add_library(GENERIC_L433RCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433RCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433RCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433RCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433RCIX_usb_HID INTERFACE) target_compile_options(GENERIC_L433RCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433RCIX_usb_none INTERFACE) target_compile_options(GENERIC_L433RCIX_usb_none INTERFACE @@ -90615,15 +90615,15 @@ target_compile_options(GENERIC_L433RCTX_serial_none INTERFACE ) add_library(GENERIC_L433RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L433RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433RCTX_usb_none INTERFACE) target_compile_options(GENERIC_L433RCTX_usb_none INTERFACE @@ -90697,15 +90697,15 @@ target_compile_options(GENERIC_L433RCTXP_serial_none INTERFACE ) add_library(GENERIC_L433RCTXP_usb_CDC INTERFACE) target_compile_options(GENERIC_L433RCTXP_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433RCTXP_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433RCTXP_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433RCTXP_usb_HID INTERFACE) target_compile_options(GENERIC_L433RCTXP_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433RCTXP_usb_none INTERFACE) target_compile_options(GENERIC_L433RCTXP_usb_none INTERFACE @@ -90779,15 +90779,15 @@ target_compile_options(GENERIC_L433RCYX_serial_none INTERFACE ) add_library(GENERIC_L433RCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L433RCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L433RCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L433RCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L433RCYX_usb_HID INTERFACE) target_compile_options(GENERIC_L433RCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L433RCYX_usb_none INTERFACE) target_compile_options(GENERIC_L433RCYX_usb_none INTERFACE @@ -90861,15 +90861,15 @@ target_compile_options(GENERIC_L442KCUX_serial_none INTERFACE ) add_library(GENERIC_L442KCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L442KCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L442KCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L442KCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L442KCUX_usb_HID INTERFACE) target_compile_options(GENERIC_L442KCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L442KCUX_usb_none INTERFACE) target_compile_options(GENERIC_L442KCUX_usb_none INTERFACE @@ -90943,15 +90943,15 @@ target_compile_options(GENERIC_L443CCTX_serial_none INTERFACE ) add_library(GENERIC_L443CCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L443CCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L443CCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L443CCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L443CCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L443CCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L443CCTX_usb_none INTERFACE) target_compile_options(GENERIC_L443CCTX_usb_none INTERFACE @@ -91025,15 +91025,15 @@ target_compile_options(GENERIC_L443CCUX_serial_none INTERFACE ) add_library(GENERIC_L443CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_L443CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L443CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L443CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L443CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_L443CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L443CCUX_usb_none INTERFACE) target_compile_options(GENERIC_L443CCUX_usb_none INTERFACE @@ -91107,15 +91107,15 @@ target_compile_options(GENERIC_L443RCIX_serial_none INTERFACE ) add_library(GENERIC_L443RCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L443RCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L443RCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L443RCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L443RCIX_usb_HID INTERFACE) target_compile_options(GENERIC_L443RCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L443RCIX_usb_none INTERFACE) target_compile_options(GENERIC_L443RCIX_usb_none INTERFACE @@ -91189,15 +91189,15 @@ target_compile_options(GENERIC_L443RCTX_serial_none INTERFACE ) add_library(GENERIC_L443RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L443RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L443RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L443RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L443RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L443RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L443RCTX_usb_none INTERFACE) target_compile_options(GENERIC_L443RCTX_usb_none INTERFACE @@ -91271,15 +91271,15 @@ target_compile_options(GENERIC_L443RCYX_serial_none INTERFACE ) add_library(GENERIC_L443RCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L443RCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L443RCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L443RCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L443RCYX_usb_HID INTERFACE) target_compile_options(GENERIC_L443RCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L443RCYX_usb_none INTERFACE) target_compile_options(GENERIC_L443RCYX_usb_none INTERFACE @@ -91353,15 +91353,15 @@ target_compile_options(GENERIC_L452RCIX_serial_none INTERFACE ) add_library(GENERIC_L452RCIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L452RCIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L452RCIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L452RCIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L452RCIX_usb_HID INTERFACE) target_compile_options(GENERIC_L452RCIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L452RCIX_usb_none INTERFACE) target_compile_options(GENERIC_L452RCIX_usb_none INTERFACE @@ -91435,15 +91435,15 @@ target_compile_options(GENERIC_L452RCTX_serial_none INTERFACE ) add_library(GENERIC_L452RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L452RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L452RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L452RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L452RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L452RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L452RCTX_usb_none INTERFACE) target_compile_options(GENERIC_L452RCTX_usb_none INTERFACE @@ -91517,15 +91517,15 @@ target_compile_options(GENERIC_L452RCYX_serial_none INTERFACE ) add_library(GENERIC_L452RCYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L452RCYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L452RCYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L452RCYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L452RCYX_usb_HID INTERFACE) target_compile_options(GENERIC_L452RCYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L452RCYX_usb_none INTERFACE) target_compile_options(GENERIC_L452RCYX_usb_none INTERFACE @@ -91599,15 +91599,15 @@ target_compile_options(GENERIC_L452REIX_serial_none INTERFACE ) add_library(GENERIC_L452REIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L452REIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L452REIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L452REIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L452REIX_usb_HID INTERFACE) target_compile_options(GENERIC_L452REIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L452REIX_usb_none INTERFACE) target_compile_options(GENERIC_L452REIX_usb_none INTERFACE @@ -91681,15 +91681,15 @@ target_compile_options(GENERIC_L452RETX_serial_none INTERFACE ) add_library(GENERIC_L452RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L452RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L452RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L452RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L452RETX_usb_HID INTERFACE) target_compile_options(GENERIC_L452RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L452RETX_usb_none INTERFACE) target_compile_options(GENERIC_L452RETX_usb_none INTERFACE @@ -91763,15 +91763,15 @@ target_compile_options(GENERIC_L452RETXP_serial_none INTERFACE ) add_library(GENERIC_L452RETXP_usb_CDC INTERFACE) target_compile_options(GENERIC_L452RETXP_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L452RETXP_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L452RETXP_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L452RETXP_usb_HID INTERFACE) target_compile_options(GENERIC_L452RETXP_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L452RETXP_usb_none INTERFACE) target_compile_options(GENERIC_L452RETXP_usb_none INTERFACE @@ -91845,15 +91845,15 @@ target_compile_options(GENERIC_L452REYX_serial_none INTERFACE ) add_library(GENERIC_L452REYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L452REYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L452REYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L452REYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L452REYX_usb_HID INTERFACE) target_compile_options(GENERIC_L452REYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L452REYX_usb_none INTERFACE) target_compile_options(GENERIC_L452REYX_usb_none INTERFACE @@ -91927,15 +91927,15 @@ target_compile_options(GENERIC_L462REIX_serial_none INTERFACE ) add_library(GENERIC_L462REIX_usb_CDC INTERFACE) target_compile_options(GENERIC_L462REIX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L462REIX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L462REIX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L462REIX_usb_HID INTERFACE) target_compile_options(GENERIC_L462REIX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L462REIX_usb_none INTERFACE) target_compile_options(GENERIC_L462REIX_usb_none INTERFACE @@ -92009,15 +92009,15 @@ target_compile_options(GENERIC_L462RETX_serial_none INTERFACE ) add_library(GENERIC_L462RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L462RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L462RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L462RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L462RETX_usb_HID INTERFACE) target_compile_options(GENERIC_L462RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L462RETX_usb_none INTERFACE) target_compile_options(GENERIC_L462RETX_usb_none INTERFACE @@ -92091,15 +92091,15 @@ target_compile_options(GENERIC_L462REYX_serial_none INTERFACE ) add_library(GENERIC_L462REYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L462REYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L462REYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L462REYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L462REYX_usb_HID INTERFACE) target_compile_options(GENERIC_L462REYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L462REYX_usb_none INTERFACE) target_compile_options(GENERIC_L462REYX_usb_none INTERFACE @@ -92173,15 +92173,15 @@ target_compile_options(GENERIC_L475RCTX_serial_none INTERFACE ) add_library(GENERIC_L475RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L475RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L475RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L475RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L475RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L475RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L475RCTX_usb_none INTERFACE) target_compile_options(GENERIC_L475RCTX_usb_none INTERFACE @@ -92255,15 +92255,15 @@ target_compile_options(GENERIC_L475RETX_serial_none INTERFACE ) add_library(GENERIC_L475RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L475RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L475RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L475RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L475RETX_usb_HID INTERFACE) target_compile_options(GENERIC_L475RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L475RETX_usb_none INTERFACE) target_compile_options(GENERIC_L475RETX_usb_none INTERFACE @@ -92337,15 +92337,15 @@ target_compile_options(GENERIC_L475RGTX_serial_none INTERFACE ) add_library(GENERIC_L475RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L475RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L475RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L475RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L475RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L475RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L475RGTX_usb_none INTERFACE) target_compile_options(GENERIC_L475RGTX_usb_none INTERFACE @@ -92419,15 +92419,15 @@ target_compile_options(GENERIC_L475VCTX_serial_none INTERFACE ) add_library(GENERIC_L475VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L475VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L475VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L475VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L475VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L475VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L475VCTX_usb_none INTERFACE) target_compile_options(GENERIC_L475VCTX_usb_none INTERFACE @@ -92501,15 +92501,15 @@ target_compile_options(GENERIC_L475VETX_serial_none INTERFACE ) add_library(GENERIC_L475VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L475VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L475VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L475VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L475VETX_usb_HID INTERFACE) target_compile_options(GENERIC_L475VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L475VETX_usb_none INTERFACE) target_compile_options(GENERIC_L475VETX_usb_none INTERFACE @@ -92583,15 +92583,15 @@ target_compile_options(GENERIC_L475VGTX_serial_none INTERFACE ) add_library(GENERIC_L475VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L475VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L475VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L475VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L475VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L475VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L475VGTX_usb_none INTERFACE) target_compile_options(GENERIC_L475VGTX_usb_none INTERFACE @@ -92665,15 +92665,15 @@ target_compile_options(GENERIC_L476RCTX_serial_none INTERFACE ) add_library(GENERIC_L476RCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L476RCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L476RCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L476RCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L476RCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L476RCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L476RCTX_usb_none INTERFACE) target_compile_options(GENERIC_L476RCTX_usb_none INTERFACE @@ -92747,15 +92747,15 @@ target_compile_options(GENERIC_L476RETX_serial_none INTERFACE ) add_library(GENERIC_L476RETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L476RETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L476RETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L476RETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L476RETX_usb_HID INTERFACE) target_compile_options(GENERIC_L476RETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L476RETX_usb_none INTERFACE) target_compile_options(GENERIC_L476RETX_usb_none INTERFACE @@ -92829,15 +92829,15 @@ target_compile_options(GENERIC_L476RGTX_serial_none INTERFACE ) add_library(GENERIC_L476RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L476RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L476RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L476RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L476RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L476RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L476RGTX_usb_none INTERFACE) target_compile_options(GENERIC_L476RGTX_usb_none INTERFACE @@ -92911,15 +92911,15 @@ target_compile_options(GENERIC_L476VCTX_serial_none INTERFACE ) add_library(GENERIC_L476VCTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L476VCTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L476VCTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L476VCTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L476VCTX_usb_HID INTERFACE) target_compile_options(GENERIC_L476VCTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L476VCTX_usb_none INTERFACE) target_compile_options(GENERIC_L476VCTX_usb_none INTERFACE @@ -92993,15 +92993,15 @@ target_compile_options(GENERIC_L476VETX_serial_none INTERFACE ) add_library(GENERIC_L476VETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L476VETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L476VETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L476VETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L476VETX_usb_HID INTERFACE) target_compile_options(GENERIC_L476VETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L476VETX_usb_none INTERFACE) target_compile_options(GENERIC_L476VETX_usb_none INTERFACE @@ -93075,15 +93075,15 @@ target_compile_options(GENERIC_L476VGTX_serial_none INTERFACE ) add_library(GENERIC_L476VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L476VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L476VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L476VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L476VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L476VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L476VGTX_usb_none INTERFACE) target_compile_options(GENERIC_L476VGTX_usb_none INTERFACE @@ -93157,15 +93157,15 @@ target_compile_options(GENERIC_L486RGTX_serial_none INTERFACE ) add_library(GENERIC_L486RGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L486RGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L486RGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L486RGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L486RGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L486RGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L486RGTX_usb_none INTERFACE) target_compile_options(GENERIC_L486RGTX_usb_none INTERFACE @@ -93239,15 +93239,15 @@ target_compile_options(GENERIC_L486VGTX_serial_none INTERFACE ) add_library(GENERIC_L486VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L486VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L486VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L486VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L486VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L486VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L486VGTX_usb_none INTERFACE) target_compile_options(GENERIC_L486VGTX_usb_none INTERFACE @@ -93321,15 +93321,15 @@ target_compile_options(GENERIC_L496ZETX_serial_none INTERFACE ) add_library(GENERIC_L496ZETX_usb_CDC INTERFACE) target_compile_options(GENERIC_L496ZETX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L496ZETX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L496ZETX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L496ZETX_usb_HID INTERFACE) target_compile_options(GENERIC_L496ZETX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L496ZETX_usb_none INTERFACE) target_compile_options(GENERIC_L496ZETX_usb_none INTERFACE @@ -93403,15 +93403,15 @@ target_compile_options(GENERIC_L496ZGTX_serial_none INTERFACE ) add_library(GENERIC_L496ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L496ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L496ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L496ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L496ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L496ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L496ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_L496ZGTX_usb_none INTERFACE @@ -93485,15 +93485,15 @@ target_compile_options(GENERIC_L496ZGTXP_serial_none INTERFACE ) add_library(GENERIC_L496ZGTXP_usb_CDC INTERFACE) target_compile_options(GENERIC_L496ZGTXP_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L496ZGTXP_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L496ZGTXP_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L496ZGTXP_usb_HID INTERFACE) target_compile_options(GENERIC_L496ZGTXP_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L496ZGTXP_usb_none INTERFACE) target_compile_options(GENERIC_L496ZGTXP_usb_none INTERFACE @@ -93567,15 +93567,15 @@ target_compile_options(GENERIC_L4A6ZGTX_serial_none INTERFACE ) add_library(GENERIC_L4A6ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4A6ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4A6ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4A6ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4A6ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L4A6ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4A6ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_L4A6ZGTX_usb_none INTERFACE @@ -93649,15 +93649,15 @@ target_compile_options(GENERIC_L4A6ZGTXP_serial_none INTERFACE ) add_library(GENERIC_L4A6ZGTXP_usb_CDC INTERFACE) target_compile_options(GENERIC_L4A6ZGTXP_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4A6ZGTXP_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4A6ZGTXP_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4A6ZGTXP_usb_HID INTERFACE) target_compile_options(GENERIC_L4A6ZGTXP_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4A6ZGTXP_usb_none INTERFACE) target_compile_options(GENERIC_L4A6ZGTXP_usb_none INTERFACE @@ -93731,15 +93731,15 @@ target_compile_options(GENERIC_L4R5VGTX_serial_none INTERFACE ) add_library(GENERIC_L4R5VGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R5VGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R5VGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R5VGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R5VGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R5VGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R5VGTX_usb_none INTERFACE) target_compile_options(GENERIC_L4R5VGTX_usb_none INTERFACE @@ -93813,15 +93813,15 @@ target_compile_options(GENERIC_L4R5VITX_serial_none INTERFACE ) add_library(GENERIC_L4R5VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R5VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R5VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R5VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R5VITX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R5VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R5VITX_usb_none INTERFACE) target_compile_options(GENERIC_L4R5VITX_usb_none INTERFACE @@ -93895,15 +93895,15 @@ target_compile_options(GENERIC_L4R5ZGTX_serial_none INTERFACE ) add_library(GENERIC_L4R5ZGTX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R5ZGTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R5ZGTX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R5ZGTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R5ZGTX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R5ZGTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R5ZGTX_usb_none INTERFACE) target_compile_options(GENERIC_L4R5ZGTX_usb_none INTERFACE @@ -93977,15 +93977,15 @@ target_compile_options(GENERIC_L4R5ZGYX_serial_none INTERFACE ) add_library(GENERIC_L4R5ZGYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R5ZGYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R5ZGYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R5ZGYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R5ZGYX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R5ZGYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R5ZGYX_usb_none INTERFACE) target_compile_options(GENERIC_L4R5ZGYX_usb_none INTERFACE @@ -94059,15 +94059,15 @@ target_compile_options(GENERIC_L4R5ZITX_serial_none INTERFACE ) add_library(GENERIC_L4R5ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R5ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R5ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R5ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R5ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R5ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R5ZITX_usb_none INTERFACE) target_compile_options(GENERIC_L4R5ZITX_usb_none INTERFACE @@ -94141,15 +94141,15 @@ target_compile_options(GENERIC_L4R5ZITXP_serial_none INTERFACE ) add_library(GENERIC_L4R5ZITXP_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R5ZITXP_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R5ZITXP_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R5ZITXP_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R5ZITXP_usb_HID INTERFACE) target_compile_options(GENERIC_L4R5ZITXP_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R5ZITXP_usb_none INTERFACE) target_compile_options(GENERIC_L4R5ZITXP_usb_none INTERFACE @@ -94223,15 +94223,15 @@ target_compile_options(GENERIC_L4R5ZIYX_serial_none INTERFACE ) add_library(GENERIC_L4R5ZIYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R5ZIYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R5ZIYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R5ZIYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R5ZIYX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R5ZIYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R5ZIYX_usb_none INTERFACE) target_compile_options(GENERIC_L4R5ZIYX_usb_none INTERFACE @@ -94305,15 +94305,15 @@ target_compile_options(GENERIC_L4R7VITX_serial_none INTERFACE ) add_library(GENERIC_L4R7VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R7VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R7VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R7VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R7VITX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R7VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R7VITX_usb_none INTERFACE) target_compile_options(GENERIC_L4R7VITX_usb_none INTERFACE @@ -94387,15 +94387,15 @@ target_compile_options(GENERIC_L4R7ZITX_serial_none INTERFACE ) add_library(GENERIC_L4R7ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R7ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R7ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R7ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R7ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R7ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R7ZITX_usb_none INTERFACE) target_compile_options(GENERIC_L4R7ZITX_usb_none INTERFACE @@ -94469,15 +94469,15 @@ target_compile_options(GENERIC_L4R9ZGJX_serial_none INTERFACE ) add_library(GENERIC_L4R9ZGJX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R9ZGJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R9ZGJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R9ZGJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R9ZGJX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R9ZGJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R9ZGJX_usb_none INTERFACE) target_compile_options(GENERIC_L4R9ZGJX_usb_none INTERFACE @@ -94551,15 +94551,15 @@ target_compile_options(GENERIC_L4R9ZGYX_serial_none INTERFACE ) add_library(GENERIC_L4R9ZGYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R9ZGYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R9ZGYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R9ZGYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R9ZGYX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R9ZGYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R9ZGYX_usb_none INTERFACE) target_compile_options(GENERIC_L4R9ZGYX_usb_none INTERFACE @@ -94633,15 +94633,15 @@ target_compile_options(GENERIC_L4R9ZIJX_serial_none INTERFACE ) add_library(GENERIC_L4R9ZIJX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R9ZIJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R9ZIJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R9ZIJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R9ZIJX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R9ZIJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R9ZIJX_usb_none INTERFACE) target_compile_options(GENERIC_L4R9ZIJX_usb_none INTERFACE @@ -94715,15 +94715,15 @@ target_compile_options(GENERIC_L4R9ZIYX_serial_none INTERFACE ) add_library(GENERIC_L4R9ZIYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4R9ZIYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4R9ZIYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4R9ZIYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4R9ZIYX_usb_HID INTERFACE) target_compile_options(GENERIC_L4R9ZIYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4R9ZIYX_usb_none INTERFACE) target_compile_options(GENERIC_L4R9ZIYX_usb_none INTERFACE @@ -94797,15 +94797,15 @@ target_compile_options(GENERIC_L4S5VITX_serial_none INTERFACE ) add_library(GENERIC_L4S5VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4S5VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4S5VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4S5VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4S5VITX_usb_HID INTERFACE) target_compile_options(GENERIC_L4S5VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4S5VITX_usb_none INTERFACE) target_compile_options(GENERIC_L4S5VITX_usb_none INTERFACE @@ -94879,15 +94879,15 @@ target_compile_options(GENERIC_L4S5ZITX_serial_none INTERFACE ) add_library(GENERIC_L4S5ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4S5ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4S5ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4S5ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4S5ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_L4S5ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4S5ZITX_usb_none INTERFACE) target_compile_options(GENERIC_L4S5ZITX_usb_none INTERFACE @@ -94961,15 +94961,15 @@ target_compile_options(GENERIC_L4S5ZIYX_serial_none INTERFACE ) add_library(GENERIC_L4S5ZIYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4S5ZIYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4S5ZIYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4S5ZIYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4S5ZIYX_usb_HID INTERFACE) target_compile_options(GENERIC_L4S5ZIYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4S5ZIYX_usb_none INTERFACE) target_compile_options(GENERIC_L4S5ZIYX_usb_none INTERFACE @@ -95043,15 +95043,15 @@ target_compile_options(GENERIC_L4S7VITX_serial_none INTERFACE ) add_library(GENERIC_L4S7VITX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4S7VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4S7VITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4S7VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4S7VITX_usb_HID INTERFACE) target_compile_options(GENERIC_L4S7VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4S7VITX_usb_none INTERFACE) target_compile_options(GENERIC_L4S7VITX_usb_none INTERFACE @@ -95125,15 +95125,15 @@ target_compile_options(GENERIC_L4S7ZITX_serial_none INTERFACE ) add_library(GENERIC_L4S7ZITX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4S7ZITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4S7ZITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4S7ZITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4S7ZITX_usb_HID INTERFACE) target_compile_options(GENERIC_L4S7ZITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4S7ZITX_usb_none INTERFACE) target_compile_options(GENERIC_L4S7ZITX_usb_none INTERFACE @@ -95207,15 +95207,15 @@ target_compile_options(GENERIC_L4S9ZIJX_serial_none INTERFACE ) add_library(GENERIC_L4S9ZIJX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4S9ZIJX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4S9ZIJX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4S9ZIJX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4S9ZIJX_usb_HID INTERFACE) target_compile_options(GENERIC_L4S9ZIJX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4S9ZIJX_usb_none INTERFACE) target_compile_options(GENERIC_L4S9ZIJX_usb_none INTERFACE @@ -95289,15 +95289,15 @@ target_compile_options(GENERIC_L4S9ZIYX_serial_none INTERFACE ) add_library(GENERIC_L4S9ZIYX_usb_CDC INTERFACE) target_compile_options(GENERIC_L4S9ZIYX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L4S9ZIYX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L4S9ZIYX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L4S9ZIYX_usb_HID INTERFACE) target_compile_options(GENERIC_L4S9ZIYX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L4S9ZIYX_usb_none INTERFACE) target_compile_options(GENERIC_L4S9ZIYX_usb_none INTERFACE @@ -95371,15 +95371,15 @@ target_compile_options(GENERIC_L552ZCTXQ_serial_none INTERFACE ) add_library(GENERIC_L552ZCTXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_L552ZCTXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L552ZCTXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L552ZCTXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L552ZCTXQ_usb_HID INTERFACE) target_compile_options(GENERIC_L552ZCTXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L552ZCTXQ_usb_none INTERFACE) target_compile_options(GENERIC_L552ZCTXQ_usb_none INTERFACE @@ -95453,15 +95453,15 @@ target_compile_options(GENERIC_L552ZETXQ_serial_none INTERFACE ) add_library(GENERIC_L552ZETXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_L552ZETXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L552ZETXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L552ZETXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L552ZETXQ_usb_HID INTERFACE) target_compile_options(GENERIC_L552ZETXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L552ZETXQ_usb_none INTERFACE) target_compile_options(GENERIC_L552ZETXQ_usb_none INTERFACE @@ -95535,15 +95535,15 @@ target_compile_options(GENERIC_L562ZETXQ_serial_none INTERFACE ) add_library(GENERIC_L562ZETXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_L562ZETXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_L562ZETXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_L562ZETXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_L562ZETXQ_usb_HID INTERFACE) target_compile_options(GENERIC_L562ZETXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_L562ZETXQ_usb_none INTERFACE) target_compile_options(GENERIC_L562ZETXQ_usb_none INTERFACE @@ -95671,15 +95671,15 @@ target_compile_options(GENERIC_U575AGIXQ_serial_none INTERFACE ) add_library(GENERIC_U575AGIXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_U575AGIXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U575AGIXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U575AGIXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U575AGIXQ_usb_HID INTERFACE) target_compile_options(GENERIC_U575AGIXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U575AGIXQ_usb_none INTERFACE) target_compile_options(GENERIC_U575AGIXQ_usb_none INTERFACE @@ -95753,15 +95753,15 @@ target_compile_options(GENERIC_U575AIIXQ_serial_none INTERFACE ) add_library(GENERIC_U575AIIXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_U575AIIXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U575AIIXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U575AIIXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U575AIIXQ_usb_HID INTERFACE) target_compile_options(GENERIC_U575AIIXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U575AIIXQ_usb_none INTERFACE) target_compile_options(GENERIC_U575AIIXQ_usb_none INTERFACE @@ -95835,15 +95835,15 @@ target_compile_options(GENERIC_U575CITX_serial_none INTERFACE ) add_library(GENERIC_U575CITX_usb_CDC INTERFACE) target_compile_options(GENERIC_U575CITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U575CITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U575CITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U575CITX_usb_HID INTERFACE) target_compile_options(GENERIC_U575CITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U575CITX_usb_none INTERFACE) target_compile_options(GENERIC_U575CITX_usb_none INTERFACE @@ -95917,15 +95917,15 @@ target_compile_options(GENERIC_U575CIUX_serial_none INTERFACE ) add_library(GENERIC_U575CIUX_usb_CDC INTERFACE) target_compile_options(GENERIC_U575CIUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U575CIUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U575CIUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U575CIUX_usb_HID INTERFACE) target_compile_options(GENERIC_U575CIUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U575CIUX_usb_none INTERFACE) target_compile_options(GENERIC_U575CIUX_usb_none INTERFACE @@ -95999,15 +95999,15 @@ target_compile_options(GENERIC_U575ZGTXQ_serial_none INTERFACE ) add_library(GENERIC_U575ZGTXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_U575ZGTXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U575ZGTXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U575ZGTXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U575ZGTXQ_usb_HID INTERFACE) target_compile_options(GENERIC_U575ZGTXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U575ZGTXQ_usb_none INTERFACE) target_compile_options(GENERIC_U575ZGTXQ_usb_none INTERFACE @@ -96081,15 +96081,15 @@ target_compile_options(GENERIC_U575ZITXQ_serial_none INTERFACE ) add_library(GENERIC_U575ZITXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_U575ZITXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U575ZITXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U575ZITXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U575ZITXQ_usb_HID INTERFACE) target_compile_options(GENERIC_U575ZITXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U575ZITXQ_usb_none INTERFACE) target_compile_options(GENERIC_U575ZITXQ_usb_none INTERFACE @@ -96163,15 +96163,15 @@ target_compile_options(GENERIC_U585AIIXQ_serial_none INTERFACE ) add_library(GENERIC_U585AIIXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_U585AIIXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U585AIIXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U585AIIXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U585AIIXQ_usb_HID INTERFACE) target_compile_options(GENERIC_U585AIIXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U585AIIXQ_usb_none INTERFACE) target_compile_options(GENERIC_U585AIIXQ_usb_none INTERFACE @@ -96245,15 +96245,15 @@ target_compile_options(GENERIC_U585CITX_serial_none INTERFACE ) add_library(GENERIC_U585CITX_usb_CDC INTERFACE) target_compile_options(GENERIC_U585CITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U585CITX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U585CITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U585CITX_usb_HID INTERFACE) target_compile_options(GENERIC_U585CITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U585CITX_usb_none INTERFACE) target_compile_options(GENERIC_U585CITX_usb_none INTERFACE @@ -96327,15 +96327,15 @@ target_compile_options(GENERIC_U585CIUX_serial_none INTERFACE ) add_library(GENERIC_U585CIUX_usb_CDC INTERFACE) target_compile_options(GENERIC_U585CIUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U585CIUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U585CIUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U585CIUX_usb_HID INTERFACE) target_compile_options(GENERIC_U585CIUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U585CIUX_usb_none INTERFACE) target_compile_options(GENERIC_U585CIUX_usb_none INTERFACE @@ -96409,15 +96409,15 @@ target_compile_options(GENERIC_U585ZITXQ_serial_none INTERFACE ) add_library(GENERIC_U585ZITXQ_usb_CDC INTERFACE) target_compile_options(GENERIC_U585ZITXQ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_U585ZITXQ_usb_CDCgen INTERFACE) target_compile_options(GENERIC_U585ZITXQ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_U585ZITXQ_usb_HID INTERFACE) target_compile_options(GENERIC_U585ZITXQ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_U585ZITXQ_usb_none INTERFACE) target_compile_options(GENERIC_U585ZITXQ_usb_none INTERFACE @@ -96491,15 +96491,15 @@ target_compile_options(GENERIC_WB15CCUX_serial_none INTERFACE ) add_library(GENERIC_WB15CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_WB15CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_WB15CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_WB15CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_WB15CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_WB15CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_WB15CCUX_usb_none INTERFACE) target_compile_options(GENERIC_WB15CCUX_usb_none INTERFACE @@ -96573,15 +96573,15 @@ target_compile_options(GENERIC_WB55CCUX_serial_none INTERFACE ) add_library(GENERIC_WB55CCUX_usb_CDC INTERFACE) target_compile_options(GENERIC_WB55CCUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_WB55CCUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_WB55CCUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_WB55CCUX_usb_HID INTERFACE) target_compile_options(GENERIC_WB55CCUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_WB55CCUX_usb_none INTERFACE) target_compile_options(GENERIC_WB55CCUX_usb_none INTERFACE @@ -96655,15 +96655,15 @@ target_compile_options(GENERIC_WB55CEUX_serial_none INTERFACE ) add_library(GENERIC_WB55CEUX_usb_CDC INTERFACE) target_compile_options(GENERIC_WB55CEUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_WB55CEUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_WB55CEUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_WB55CEUX_usb_HID INTERFACE) target_compile_options(GENERIC_WB55CEUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_WB55CEUX_usb_none INTERFACE) target_compile_options(GENERIC_WB55CEUX_usb_none INTERFACE @@ -96737,15 +96737,15 @@ target_compile_options(GENERIC_WB55CGUX_serial_none INTERFACE ) add_library(GENERIC_WB55CGUX_usb_CDC INTERFACE) target_compile_options(GENERIC_WB55CGUX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_WB55CGUX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_WB55CGUX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_WB55CGUX_usb_HID INTERFACE) target_compile_options(GENERIC_WB55CGUX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_WB55CGUX_usb_none INTERFACE) target_compile_options(GENERIC_WB55CGUX_usb_none INTERFACE @@ -96819,15 +96819,15 @@ target_compile_options(GENERIC_WB55RCVX_serial_none INTERFACE ) add_library(GENERIC_WB55RCVX_usb_CDC INTERFACE) target_compile_options(GENERIC_WB55RCVX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_WB55RCVX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_WB55RCVX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_WB55RCVX_usb_HID INTERFACE) target_compile_options(GENERIC_WB55RCVX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_WB55RCVX_usb_none INTERFACE) target_compile_options(GENERIC_WB55RCVX_usb_none INTERFACE @@ -96901,15 +96901,15 @@ target_compile_options(GENERIC_WB55REVX_serial_none INTERFACE ) add_library(GENERIC_WB55REVX_usb_CDC INTERFACE) target_compile_options(GENERIC_WB55REVX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_WB55REVX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_WB55REVX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_WB55REVX_usb_HID INTERFACE) target_compile_options(GENERIC_WB55REVX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_WB55REVX_usb_none INTERFACE) target_compile_options(GENERIC_WB55REVX_usb_none INTERFACE @@ -96983,15 +96983,15 @@ target_compile_options(GENERIC_WB55RGVX_serial_none INTERFACE ) add_library(GENERIC_WB55RGVX_usb_CDC INTERFACE) target_compile_options(GENERIC_WB55RGVX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_WB55RGVX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_WB55RGVX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_WB55RGVX_usb_HID INTERFACE) target_compile_options(GENERIC_WB55RGVX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_WB55RGVX_usb_none INTERFACE) target_compile_options(GENERIC_WB55RGVX_usb_none INTERFACE @@ -97065,15 +97065,15 @@ target_compile_options(GENERIC_WB5MMGHX_serial_none INTERFACE ) add_library(GENERIC_WB5MMGHX_usb_CDC INTERFACE) target_compile_options(GENERIC_WB5MMGHX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(GENERIC_WB5MMGHX_usb_CDCgen INTERFACE) target_compile_options(GENERIC_WB5MMGHX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(GENERIC_WB5MMGHX_usb_HID INTERFACE) target_compile_options(GENERIC_WB5MMGHX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(GENERIC_WB5MMGHX_usb_none INTERFACE) target_compile_options(GENERIC_WB5MMGHX_usb_none INTERFACE @@ -98011,15 +98011,15 @@ target_compile_options(HY_TINYSTM103TB_serial_none INTERFACE ) add_library(HY_TINYSTM103TB_usb_CDC INTERFACE) target_compile_options(HY_TINYSTM103TB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(HY_TINYSTM103TB_usb_CDCgen INTERFACE) target_compile_options(HY_TINYSTM103TB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(HY_TINYSTM103TB_usb_HID INTERFACE) target_compile_options(HY_TINYSTM103TB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(HY_TINYSTM103TB_usb_none INTERFACE) target_compile_options(HY_TINYSTM103TB_usb_none INTERFACE @@ -98219,15 +98219,15 @@ target_compile_options(LEAFONY_AP03_serial_none INTERFACE ) add_library(LEAFONY_AP03_usb_CDC INTERFACE) target_compile_options(LEAFONY_AP03_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(LEAFONY_AP03_usb_CDCgen INTERFACE) target_compile_options(LEAFONY_AP03_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(LEAFONY_AP03_usb_HID INTERFACE) target_compile_options(LEAFONY_AP03_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(LEAFONY_AP03_usb_none INTERFACE) target_compile_options(LEAFONY_AP03_usb_none INTERFACE @@ -98355,11 +98355,11 @@ target_compile_options(MALYANM200_F070CB_serial_none INTERFACE ) add_library(MALYANM200_F070CB_usb_CDC INTERFACE) target_compile_options(MALYANM200_F070CB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(MALYANM200_F070CB_usb_CDCgen INTERFACE) target_compile_options(MALYANM200_F070CB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(MALYANM200_F070CB_usb_none INTERFACE) target_compile_options(MALYANM200_F070CB_usb_none INTERFACE @@ -98433,11 +98433,11 @@ target_compile_options(MALYANM200_F103CB_serial_none INTERFACE ) add_library(MALYANM200_F103CB_usb_CDC INTERFACE) target_compile_options(MALYANM200_F103CB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(MALYANM200_F103CB_usb_CDCgen INTERFACE) target_compile_options(MALYANM200_F103CB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(MALYANM200_F103CB_usb_none INTERFACE) target_compile_options(MALYANM200_F103CB_usb_none INTERFACE @@ -98511,11 +98511,11 @@ target_compile_options(MALYANM300_F070CB_serial_none INTERFACE ) add_library(MALYANM300_F070CB_usb_CDC INTERFACE) target_compile_options(MALYANM300_F070CB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(MALYANM300_F070CB_usb_CDCgen INTERFACE) target_compile_options(MALYANM300_F070CB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(MALYANM300_F070CB_usb_none INTERFACE) target_compile_options(MALYANM300_F070CB_usb_none INTERFACE @@ -98589,15 +98589,15 @@ target_compile_options(MAPLEMINI_F103CB_serial_none INTERFACE ) add_library(MAPLEMINI_F103CB_usb_CDC INTERFACE) target_compile_options(MAPLEMINI_F103CB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(MAPLEMINI_F103CB_usb_CDCgen INTERFACE) target_compile_options(MAPLEMINI_F103CB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(MAPLEMINI_F103CB_usb_HID INTERFACE) target_compile_options(MAPLEMINI_F103CB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(MAPLEMINI_F103CB_usb_none INTERFACE) target_compile_options(MAPLEMINI_F103CB_usb_none INTERFACE @@ -98879,15 +98879,15 @@ target_compile_options(MKR_SHARKY_serial_none INTERFACE ) add_library(MKR_SHARKY_usb_CDC INTERFACE) target_compile_options(MKR_SHARKY_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(MKR_SHARKY_usb_CDCgen INTERFACE) target_compile_options(MKR_SHARKY_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(MKR_SHARKY_usb_HID INTERFACE) target_compile_options(MKR_SHARKY_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(MKR_SHARKY_usb_none INTERFACE) target_compile_options(MKR_SHARKY_usb_none INTERFACE @@ -98961,15 +98961,15 @@ target_compile_options(NUCLEO_C031C6_serial_none INTERFACE ) add_library(NUCLEO_C031C6_usb_CDC INTERFACE) target_compile_options(NUCLEO_C031C6_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_C031C6_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_C031C6_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_C031C6_usb_HID INTERFACE) target_compile_options(NUCLEO_C031C6_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_C031C6_usb_none INTERFACE) target_compile_options(NUCLEO_C031C6_usb_none INTERFACE @@ -99043,15 +99043,15 @@ target_compile_options(NUCLEO_F030R8_serial_none INTERFACE ) add_library(NUCLEO_F030R8_usb_CDC INTERFACE) target_compile_options(NUCLEO_F030R8_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F030R8_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F030R8_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F030R8_usb_HID INTERFACE) target_compile_options(NUCLEO_F030R8_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F030R8_usb_none INTERFACE) target_compile_options(NUCLEO_F030R8_usb_none INTERFACE @@ -99125,15 +99125,15 @@ target_compile_options(NUCLEO_F031K6_serial_none INTERFACE ) add_library(NUCLEO_F031K6_usb_CDC INTERFACE) target_compile_options(NUCLEO_F031K6_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F031K6_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F031K6_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F031K6_usb_HID INTERFACE) target_compile_options(NUCLEO_F031K6_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F031K6_usb_none INTERFACE) target_compile_options(NUCLEO_F031K6_usb_none INTERFACE @@ -99207,15 +99207,15 @@ target_compile_options(NUCLEO_F042K6_serial_none INTERFACE ) add_library(NUCLEO_F042K6_usb_CDC INTERFACE) target_compile_options(NUCLEO_F042K6_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F042K6_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F042K6_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F042K6_usb_HID INTERFACE) target_compile_options(NUCLEO_F042K6_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F042K6_usb_none INTERFACE) target_compile_options(NUCLEO_F042K6_usb_none INTERFACE @@ -99289,15 +99289,15 @@ target_compile_options(NUCLEO_F070RB_serial_none INTERFACE ) add_library(NUCLEO_F070RB_usb_CDC INTERFACE) target_compile_options(NUCLEO_F070RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F070RB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F070RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F070RB_usb_HID INTERFACE) target_compile_options(NUCLEO_F070RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F070RB_usb_none INTERFACE) target_compile_options(NUCLEO_F070RB_usb_none INTERFACE @@ -99371,15 +99371,15 @@ target_compile_options(NUCLEO_F072RB_serial_none INTERFACE ) add_library(NUCLEO_F072RB_usb_CDC INTERFACE) target_compile_options(NUCLEO_F072RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F072RB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F072RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F072RB_usb_HID INTERFACE) target_compile_options(NUCLEO_F072RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F072RB_usb_none INTERFACE) target_compile_options(NUCLEO_F072RB_usb_none INTERFACE @@ -99453,15 +99453,15 @@ target_compile_options(NUCLEO_F091RC_serial_none INTERFACE ) add_library(NUCLEO_F091RC_usb_CDC INTERFACE) target_compile_options(NUCLEO_F091RC_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F091RC_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F091RC_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F091RC_usb_HID INTERFACE) target_compile_options(NUCLEO_F091RC_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F091RC_usb_none INTERFACE) target_compile_options(NUCLEO_F091RC_usb_none INTERFACE @@ -99535,15 +99535,15 @@ target_compile_options(NUCLEO_F103RB_serial_none INTERFACE ) add_library(NUCLEO_F103RB_usb_CDC INTERFACE) target_compile_options(NUCLEO_F103RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F103RB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F103RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F103RB_usb_HID INTERFACE) target_compile_options(NUCLEO_F103RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F103RB_usb_none INTERFACE) target_compile_options(NUCLEO_F103RB_usb_none INTERFACE @@ -99617,15 +99617,15 @@ target_compile_options(NUCLEO_F207ZG_serial_none INTERFACE ) add_library(NUCLEO_F207ZG_usb_CDC INTERFACE) target_compile_options(NUCLEO_F207ZG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F207ZG_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F207ZG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F207ZG_usb_HID INTERFACE) target_compile_options(NUCLEO_F207ZG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F207ZG_usb_none INTERFACE) target_compile_options(NUCLEO_F207ZG_usb_none INTERFACE @@ -99699,15 +99699,15 @@ target_compile_options(NUCLEO_F302R8_serial_none INTERFACE ) add_library(NUCLEO_F302R8_usb_CDC INTERFACE) target_compile_options(NUCLEO_F302R8_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F302R8_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F302R8_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F302R8_usb_HID INTERFACE) target_compile_options(NUCLEO_F302R8_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F302R8_usb_none INTERFACE) target_compile_options(NUCLEO_F302R8_usb_none INTERFACE @@ -99781,15 +99781,15 @@ target_compile_options(NUCLEO_F303K8_serial_none INTERFACE ) add_library(NUCLEO_F303K8_usb_CDC INTERFACE) target_compile_options(NUCLEO_F303K8_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F303K8_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F303K8_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F303K8_usb_HID INTERFACE) target_compile_options(NUCLEO_F303K8_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F303K8_usb_none INTERFACE) target_compile_options(NUCLEO_F303K8_usb_none INTERFACE @@ -99863,15 +99863,15 @@ target_compile_options(NUCLEO_F303RE_serial_none INTERFACE ) add_library(NUCLEO_F303RE_usb_CDC INTERFACE) target_compile_options(NUCLEO_F303RE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F303RE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F303RE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F303RE_usb_HID INTERFACE) target_compile_options(NUCLEO_F303RE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F303RE_usb_none INTERFACE) target_compile_options(NUCLEO_F303RE_usb_none INTERFACE @@ -99945,15 +99945,15 @@ target_compile_options(NUCLEO_F401RE_serial_none INTERFACE ) add_library(NUCLEO_F401RE_usb_CDC INTERFACE) target_compile_options(NUCLEO_F401RE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F401RE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F401RE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F401RE_usb_HID INTERFACE) target_compile_options(NUCLEO_F401RE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F401RE_usb_none INTERFACE) target_compile_options(NUCLEO_F401RE_usb_none INTERFACE @@ -100027,15 +100027,15 @@ target_compile_options(NUCLEO_F411RE_serial_none INTERFACE ) add_library(NUCLEO_F411RE_usb_CDC INTERFACE) target_compile_options(NUCLEO_F411RE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F411RE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F411RE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F411RE_usb_HID INTERFACE) target_compile_options(NUCLEO_F411RE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F411RE_usb_none INTERFACE) target_compile_options(NUCLEO_F411RE_usb_none INTERFACE @@ -100109,15 +100109,15 @@ target_compile_options(NUCLEO_F412ZG_serial_none INTERFACE ) add_library(NUCLEO_F412ZG_usb_CDC INTERFACE) target_compile_options(NUCLEO_F412ZG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F412ZG_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F412ZG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F412ZG_usb_HID INTERFACE) target_compile_options(NUCLEO_F412ZG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F412ZG_usb_none INTERFACE) target_compile_options(NUCLEO_F412ZG_usb_none INTERFACE @@ -100191,15 +100191,15 @@ target_compile_options(NUCLEO_F413ZH_serial_none INTERFACE ) add_library(NUCLEO_F413ZH_usb_CDC INTERFACE) target_compile_options(NUCLEO_F413ZH_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F413ZH_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F413ZH_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F413ZH_usb_HID INTERFACE) target_compile_options(NUCLEO_F413ZH_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F413ZH_usb_none INTERFACE) target_compile_options(NUCLEO_F413ZH_usb_none INTERFACE @@ -100273,15 +100273,15 @@ target_compile_options(NUCLEO_F429ZI_serial_none INTERFACE ) add_library(NUCLEO_F429ZI_usb_CDC INTERFACE) target_compile_options(NUCLEO_F429ZI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F429ZI_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F429ZI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F429ZI_usb_HID INTERFACE) target_compile_options(NUCLEO_F429ZI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F429ZI_usb_none INTERFACE) target_compile_options(NUCLEO_F429ZI_usb_none INTERFACE @@ -100355,15 +100355,15 @@ target_compile_options(NUCLEO_F446RE_serial_none INTERFACE ) add_library(NUCLEO_F446RE_usb_CDC INTERFACE) target_compile_options(NUCLEO_F446RE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F446RE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F446RE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F446RE_usb_HID INTERFACE) target_compile_options(NUCLEO_F446RE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F446RE_usb_none INTERFACE) target_compile_options(NUCLEO_F446RE_usb_none INTERFACE @@ -100437,15 +100437,15 @@ target_compile_options(NUCLEO_F446ZE_serial_none INTERFACE ) add_library(NUCLEO_F446ZE_usb_CDC INTERFACE) target_compile_options(NUCLEO_F446ZE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F446ZE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F446ZE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F446ZE_usb_HID INTERFACE) target_compile_options(NUCLEO_F446ZE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F446ZE_usb_none INTERFACE) target_compile_options(NUCLEO_F446ZE_usb_none INTERFACE @@ -100519,15 +100519,15 @@ target_compile_options(NUCLEO_F722ZE_serial_none INTERFACE ) add_library(NUCLEO_F722ZE_usb_CDC INTERFACE) target_compile_options(NUCLEO_F722ZE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F722ZE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F722ZE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F722ZE_usb_HID INTERFACE) target_compile_options(NUCLEO_F722ZE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F722ZE_usb_none INTERFACE) target_compile_options(NUCLEO_F722ZE_usb_none INTERFACE @@ -100601,15 +100601,15 @@ target_compile_options(NUCLEO_F746ZG_serial_none INTERFACE ) add_library(NUCLEO_F746ZG_usb_CDC INTERFACE) target_compile_options(NUCLEO_F746ZG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F746ZG_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F746ZG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F746ZG_usb_HID INTERFACE) target_compile_options(NUCLEO_F746ZG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F746ZG_usb_none INTERFACE) target_compile_options(NUCLEO_F746ZG_usb_none INTERFACE @@ -100683,15 +100683,15 @@ target_compile_options(NUCLEO_F756ZG_serial_none INTERFACE ) add_library(NUCLEO_F756ZG_usb_CDC INTERFACE) target_compile_options(NUCLEO_F756ZG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F756ZG_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F756ZG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F756ZG_usb_HID INTERFACE) target_compile_options(NUCLEO_F756ZG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F756ZG_usb_none INTERFACE) target_compile_options(NUCLEO_F756ZG_usb_none INTERFACE @@ -100765,15 +100765,15 @@ target_compile_options(NUCLEO_F767ZI_serial_none INTERFACE ) add_library(NUCLEO_F767ZI_usb_CDC INTERFACE) target_compile_options(NUCLEO_F767ZI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_F767ZI_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_F767ZI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_F767ZI_usb_HID INTERFACE) target_compile_options(NUCLEO_F767ZI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_F767ZI_usb_none INTERFACE) target_compile_options(NUCLEO_F767ZI_usb_none INTERFACE @@ -100847,15 +100847,15 @@ target_compile_options(NUCLEO_G031K8_serial_none INTERFACE ) add_library(NUCLEO_G031K8_usb_CDC INTERFACE) target_compile_options(NUCLEO_G031K8_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_G031K8_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_G031K8_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_G031K8_usb_HID INTERFACE) target_compile_options(NUCLEO_G031K8_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_G031K8_usb_none INTERFACE) target_compile_options(NUCLEO_G031K8_usb_none INTERFACE @@ -100929,15 +100929,15 @@ target_compile_options(NUCLEO_G070RB_serial_none INTERFACE ) add_library(NUCLEO_G070RB_usb_CDC INTERFACE) target_compile_options(NUCLEO_G070RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_G070RB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_G070RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_G070RB_usb_HID INTERFACE) target_compile_options(NUCLEO_G070RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_G070RB_usb_none INTERFACE) target_compile_options(NUCLEO_G070RB_usb_none INTERFACE @@ -101011,15 +101011,15 @@ target_compile_options(NUCLEO_G071RB_serial_none INTERFACE ) add_library(NUCLEO_G071RB_usb_CDC INTERFACE) target_compile_options(NUCLEO_G071RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_G071RB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_G071RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_G071RB_usb_HID INTERFACE) target_compile_options(NUCLEO_G071RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_G071RB_usb_none INTERFACE) target_compile_options(NUCLEO_G071RB_usb_none INTERFACE @@ -101093,15 +101093,15 @@ target_compile_options(NUCLEO_G0B1RE_serial_none INTERFACE ) add_library(NUCLEO_G0B1RE_usb_CDC INTERFACE) target_compile_options(NUCLEO_G0B1RE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_G0B1RE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_G0B1RE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_G0B1RE_usb_HID INTERFACE) target_compile_options(NUCLEO_G0B1RE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_G0B1RE_usb_none INTERFACE) target_compile_options(NUCLEO_G0B1RE_usb_none INTERFACE @@ -101175,15 +101175,15 @@ target_compile_options(NUCLEO_G431KB_serial_none INTERFACE ) add_library(NUCLEO_G431KB_usb_CDC INTERFACE) target_compile_options(NUCLEO_G431KB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_G431KB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_G431KB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_G431KB_usb_HID INTERFACE) target_compile_options(NUCLEO_G431KB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_G431KB_usb_none INTERFACE) target_compile_options(NUCLEO_G431KB_usb_none INTERFACE @@ -101257,15 +101257,15 @@ target_compile_options(NUCLEO_G431RB_serial_none INTERFACE ) add_library(NUCLEO_G431RB_usb_CDC INTERFACE) target_compile_options(NUCLEO_G431RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_G431RB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_G431RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_G431RB_usb_HID INTERFACE) target_compile_options(NUCLEO_G431RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_G431RB_usb_none INTERFACE) target_compile_options(NUCLEO_G431RB_usb_none INTERFACE @@ -101339,15 +101339,15 @@ target_compile_options(NUCLEO_G474RE_serial_none INTERFACE ) add_library(NUCLEO_G474RE_usb_CDC INTERFACE) target_compile_options(NUCLEO_G474RE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_G474RE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_G474RE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_G474RE_usb_HID INTERFACE) target_compile_options(NUCLEO_G474RE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_G474RE_usb_none INTERFACE) target_compile_options(NUCLEO_G474RE_usb_none INTERFACE @@ -101421,15 +101421,15 @@ target_compile_options(NUCLEO_H503RB_serial_none INTERFACE ) add_library(NUCLEO_H503RB_usb_CDC INTERFACE) target_compile_options(NUCLEO_H503RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_H503RB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_H503RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_H503RB_usb_HID INTERFACE) target_compile_options(NUCLEO_H503RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_H503RB_usb_none INTERFACE) target_compile_options(NUCLEO_H503RB_usb_none INTERFACE @@ -101451,7 +101451,7 @@ target_compile_options(NUCLEO_H503RB_xusb_HSFS INTERFACE # NUCLEO_H563ZI # ----------------------------------------------------------------------------- -set(NUCLEO_H563ZI_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T") +set(NUCLEO_H563ZI_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T_H573ZIT") set(NUCLEO_H563ZI_MAXSIZE 2097152) set(NUCLEO_H563ZI_MAXDATASIZE 655360) set(NUCLEO_H563ZI_MCU cortex-m33) @@ -101503,15 +101503,15 @@ target_compile_options(NUCLEO_H563ZI_serial_none INTERFACE ) add_library(NUCLEO_H563ZI_usb_CDC INTERFACE) target_compile_options(NUCLEO_H563ZI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_H563ZI_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_H563ZI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_H563ZI_usb_HID INTERFACE) target_compile_options(NUCLEO_H563ZI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_H563ZI_usb_none INTERFACE) target_compile_options(NUCLEO_H563ZI_usb_none INTERFACE @@ -101585,15 +101585,15 @@ target_compile_options(NUCLEO_H723ZG_serial_none INTERFACE ) add_library(NUCLEO_H723ZG_usb_CDC INTERFACE) target_compile_options(NUCLEO_H723ZG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_H723ZG_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_H723ZG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_H723ZG_usb_HID INTERFACE) target_compile_options(NUCLEO_H723ZG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_H723ZG_usb_none INTERFACE) target_compile_options(NUCLEO_H723ZG_usb_none INTERFACE @@ -101667,15 +101667,15 @@ target_compile_options(NUCLEO_H743ZI_serial_none INTERFACE ) add_library(NUCLEO_H743ZI_usb_CDC INTERFACE) target_compile_options(NUCLEO_H743ZI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_H743ZI_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_H743ZI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_H743ZI_usb_HID INTERFACE) target_compile_options(NUCLEO_H743ZI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_H743ZI_usb_none INTERFACE) target_compile_options(NUCLEO_H743ZI_usb_none INTERFACE @@ -101749,15 +101749,15 @@ target_compile_options(NUCLEO_H743ZI2_serial_none INTERFACE ) add_library(NUCLEO_H743ZI2_usb_CDC INTERFACE) target_compile_options(NUCLEO_H743ZI2_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_H743ZI2_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_H743ZI2_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_H743ZI2_usb_HID INTERFACE) target_compile_options(NUCLEO_H743ZI2_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_H743ZI2_usb_none INTERFACE) target_compile_options(NUCLEO_H743ZI2_usb_none INTERFACE @@ -101831,15 +101831,15 @@ target_compile_options(NUCLEO_H753ZI_serial_none INTERFACE ) add_library(NUCLEO_H753ZI_usb_CDC INTERFACE) target_compile_options(NUCLEO_H753ZI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_H753ZI_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_H753ZI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_H753ZI_usb_HID INTERFACE) target_compile_options(NUCLEO_H753ZI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_H753ZI_usb_none INTERFACE) target_compile_options(NUCLEO_H753ZI_usb_none INTERFACE @@ -101913,15 +101913,15 @@ target_compile_options(NUCLEO_L010RB_serial_none INTERFACE ) add_library(NUCLEO_L010RB_usb_CDC INTERFACE) target_compile_options(NUCLEO_L010RB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L010RB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L010RB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L010RB_usb_HID INTERFACE) target_compile_options(NUCLEO_L010RB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L010RB_usb_none INTERFACE) target_compile_options(NUCLEO_L010RB_usb_none INTERFACE @@ -101995,15 +101995,15 @@ target_compile_options(NUCLEO_L031K6_serial_none INTERFACE ) add_library(NUCLEO_L031K6_usb_CDC INTERFACE) target_compile_options(NUCLEO_L031K6_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L031K6_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L031K6_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L031K6_usb_HID INTERFACE) target_compile_options(NUCLEO_L031K6_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L031K6_usb_none INTERFACE) target_compile_options(NUCLEO_L031K6_usb_none INTERFACE @@ -102077,15 +102077,15 @@ target_compile_options(NUCLEO_L053R8_serial_none INTERFACE ) add_library(NUCLEO_L053R8_usb_CDC INTERFACE) target_compile_options(NUCLEO_L053R8_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L053R8_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L053R8_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L053R8_usb_HID INTERFACE) target_compile_options(NUCLEO_L053R8_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L053R8_usb_none INTERFACE) target_compile_options(NUCLEO_L053R8_usb_none INTERFACE @@ -102159,15 +102159,15 @@ target_compile_options(NUCLEO_L073RZ_serial_none INTERFACE ) add_library(NUCLEO_L073RZ_usb_CDC INTERFACE) target_compile_options(NUCLEO_L073RZ_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L073RZ_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L073RZ_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L073RZ_usb_HID INTERFACE) target_compile_options(NUCLEO_L073RZ_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L073RZ_usb_none INTERFACE) target_compile_options(NUCLEO_L073RZ_usb_none INTERFACE @@ -102241,15 +102241,15 @@ target_compile_options(NUCLEO_L152RE_serial_none INTERFACE ) add_library(NUCLEO_L152RE_usb_CDC INTERFACE) target_compile_options(NUCLEO_L152RE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L152RE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L152RE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L152RE_usb_HID INTERFACE) target_compile_options(NUCLEO_L152RE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L152RE_usb_none INTERFACE) target_compile_options(NUCLEO_L152RE_usb_none INTERFACE @@ -102323,15 +102323,15 @@ target_compile_options(NUCLEO_L412KB_serial_none INTERFACE ) add_library(NUCLEO_L412KB_usb_CDC INTERFACE) target_compile_options(NUCLEO_L412KB_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L412KB_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L412KB_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L412KB_usb_HID INTERFACE) target_compile_options(NUCLEO_L412KB_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L412KB_usb_none INTERFACE) target_compile_options(NUCLEO_L412KB_usb_none INTERFACE @@ -102405,15 +102405,15 @@ target_compile_options(NUCLEO_L432KC_serial_none INTERFACE ) add_library(NUCLEO_L432KC_usb_CDC INTERFACE) target_compile_options(NUCLEO_L432KC_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L432KC_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L432KC_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L432KC_usb_HID INTERFACE) target_compile_options(NUCLEO_L432KC_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L432KC_usb_none INTERFACE) target_compile_options(NUCLEO_L432KC_usb_none INTERFACE @@ -102487,15 +102487,15 @@ target_compile_options(NUCLEO_L433RC_P_serial_none INTERFACE ) add_library(NUCLEO_L433RC_P_usb_CDC INTERFACE) target_compile_options(NUCLEO_L433RC_P_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L433RC_P_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L433RC_P_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L433RC_P_usb_HID INTERFACE) target_compile_options(NUCLEO_L433RC_P_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L433RC_P_usb_none INTERFACE) target_compile_options(NUCLEO_L433RC_P_usb_none INTERFACE @@ -102569,15 +102569,15 @@ target_compile_options(NUCLEO_L452RE_serial_none INTERFACE ) add_library(NUCLEO_L452RE_usb_CDC INTERFACE) target_compile_options(NUCLEO_L452RE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L452RE_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L452RE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L452RE_usb_HID INTERFACE) target_compile_options(NUCLEO_L452RE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L452RE_usb_none INTERFACE) target_compile_options(NUCLEO_L452RE_usb_none INTERFACE @@ -102651,15 +102651,15 @@ target_compile_options(NUCLEO_L452REP_serial_none INTERFACE ) add_library(NUCLEO_L452REP_usb_CDC INTERFACE) target_compile_options(NUCLEO_L452REP_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L452REP_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L452REP_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L452REP_usb_HID INTERFACE) target_compile_options(NUCLEO_L452REP_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L452REP_usb_none INTERFACE) target_compile_options(NUCLEO_L452REP_usb_none INTERFACE @@ -102733,15 +102733,15 @@ target_compile_options(NUCLEO_L476RG_serial_none INTERFACE ) add_library(NUCLEO_L476RG_usb_CDC INTERFACE) target_compile_options(NUCLEO_L476RG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L476RG_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L476RG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L476RG_usb_HID INTERFACE) target_compile_options(NUCLEO_L476RG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L476RG_usb_none INTERFACE) target_compile_options(NUCLEO_L476RG_usb_none INTERFACE @@ -102815,15 +102815,15 @@ target_compile_options(NUCLEO_L496ZG_serial_none INTERFACE ) add_library(NUCLEO_L496ZG_usb_CDC INTERFACE) target_compile_options(NUCLEO_L496ZG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L496ZG_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L496ZG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L496ZG_usb_HID INTERFACE) target_compile_options(NUCLEO_L496ZG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L496ZG_usb_none INTERFACE) target_compile_options(NUCLEO_L496ZG_usb_none INTERFACE @@ -102897,15 +102897,15 @@ target_compile_options(NUCLEO_L496ZG-P_serial_none INTERFACE ) add_library(NUCLEO_L496ZG-P_usb_CDC INTERFACE) target_compile_options(NUCLEO_L496ZG-P_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L496ZG-P_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L496ZG-P_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L496ZG-P_usb_HID INTERFACE) target_compile_options(NUCLEO_L496ZG-P_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L496ZG-P_usb_none INTERFACE) target_compile_options(NUCLEO_L496ZG-P_usb_none INTERFACE @@ -102979,15 +102979,15 @@ target_compile_options(NUCLEO_L4R5ZI_serial_none INTERFACE ) add_library(NUCLEO_L4R5ZI_usb_CDC INTERFACE) target_compile_options(NUCLEO_L4R5ZI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L4R5ZI_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L4R5ZI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L4R5ZI_usb_HID INTERFACE) target_compile_options(NUCLEO_L4R5ZI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L4R5ZI_usb_none INTERFACE) target_compile_options(NUCLEO_L4R5ZI_usb_none INTERFACE @@ -103061,15 +103061,15 @@ target_compile_options(NUCLEO_L4R5ZI_P_serial_none INTERFACE ) add_library(NUCLEO_L4R5ZI_P_usb_CDC INTERFACE) target_compile_options(NUCLEO_L4R5ZI_P_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L4R5ZI_P_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L4R5ZI_P_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L4R5ZI_P_usb_HID INTERFACE) target_compile_options(NUCLEO_L4R5ZI_P_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L4R5ZI_P_usb_none INTERFACE) target_compile_options(NUCLEO_L4R5ZI_P_usb_none INTERFACE @@ -103143,15 +103143,15 @@ target_compile_options(NUCLEO_L552ZE_Q_serial_none INTERFACE ) add_library(NUCLEO_L552ZE_Q_usb_CDC INTERFACE) target_compile_options(NUCLEO_L552ZE_Q_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_L552ZE_Q_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_L552ZE_Q_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_L552ZE_Q_usb_HID INTERFACE) target_compile_options(NUCLEO_L552ZE_Q_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_L552ZE_Q_usb_none INTERFACE) target_compile_options(NUCLEO_L552ZE_Q_usb_none INTERFACE @@ -103225,15 +103225,15 @@ target_compile_options(NUCLEO_U575ZI_Q_serial_none INTERFACE ) add_library(NUCLEO_U575ZI_Q_usb_CDC INTERFACE) target_compile_options(NUCLEO_U575ZI_Q_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_U575ZI_Q_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_U575ZI_Q_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_U575ZI_Q_usb_HID INTERFACE) target_compile_options(NUCLEO_U575ZI_Q_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_U575ZI_Q_usb_none INTERFACE) target_compile_options(NUCLEO_U575ZI_Q_usb_none INTERFACE @@ -103307,15 +103307,15 @@ target_compile_options(NUCLEO_WB15CC_serial_none INTERFACE ) add_library(NUCLEO_WB15CC_usb_CDC INTERFACE) target_compile_options(NUCLEO_WB15CC_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_WB15CC_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_WB15CC_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_WB15CC_usb_HID INTERFACE) target_compile_options(NUCLEO_WB15CC_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_WB15CC_usb_none INTERFACE) target_compile_options(NUCLEO_WB15CC_usb_none INTERFACE @@ -103389,15 +103389,15 @@ target_compile_options(NUCLEO_WL55JC1_serial_none INTERFACE ) add_library(NUCLEO_WL55JC1_usb_CDC INTERFACE) target_compile_options(NUCLEO_WL55JC1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(NUCLEO_WL55JC1_usb_CDCgen INTERFACE) target_compile_options(NUCLEO_WL55JC1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(NUCLEO_WL55JC1_usb_HID INTERFACE) target_compile_options(NUCLEO_WL55JC1_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(NUCLEO_WL55JC1_usb_none INTERFACE) target_compile_options(NUCLEO_WL55JC1_usb_none INTERFACE @@ -103471,15 +103471,15 @@ target_compile_options(OLIMEXINO_STM32F3_serial_none INTERFACE ) add_library(OLIMEXINO_STM32F3_usb_CDC INTERFACE) target_compile_options(OLIMEXINO_STM32F3_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(OLIMEXINO_STM32F3_usb_CDCgen INTERFACE) target_compile_options(OLIMEXINO_STM32F3_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(OLIMEXINO_STM32F3_usb_HID INTERFACE) target_compile_options(OLIMEXINO_STM32F3_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(OLIMEXINO_STM32F3_usb_none INTERFACE) target_compile_options(OLIMEXINO_STM32F3_usb_none INTERFACE @@ -103553,15 +103553,15 @@ target_compile_options(P_NUCLEO_WB55_USB_DONGLE_serial_none INTERFACE ) add_library(P_NUCLEO_WB55_USB_DONGLE_usb_CDC INTERFACE) target_compile_options(P_NUCLEO_WB55_USB_DONGLE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(P_NUCLEO_WB55_USB_DONGLE_usb_CDCgen INTERFACE) target_compile_options(P_NUCLEO_WB55_USB_DONGLE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(P_NUCLEO_WB55_USB_DONGLE_usb_HID INTERFACE) target_compile_options(P_NUCLEO_WB55_USB_DONGLE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(P_NUCLEO_WB55_USB_DONGLE_usb_none INTERFACE) target_compile_options(P_NUCLEO_WB55_USB_DONGLE_usb_none INTERFACE @@ -103635,15 +103635,15 @@ target_compile_options(P_NUCLEO_WB55RG_serial_none INTERFACE ) add_library(P_NUCLEO_WB55RG_usb_CDC INTERFACE) target_compile_options(P_NUCLEO_WB55RG_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(P_NUCLEO_WB55RG_usb_CDCgen INTERFACE) target_compile_options(P_NUCLEO_WB55RG_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(P_NUCLEO_WB55RG_usb_HID INTERFACE) target_compile_options(P_NUCLEO_WB55RG_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(P_NUCLEO_WB55RG_usb_none INTERFACE) target_compile_options(P_NUCLEO_WB55RG_usb_none INTERFACE @@ -103717,11 +103717,11 @@ target_compile_options(PRNTR_V1_serial_none INTERFACE ) add_library(PRNTR_V1_usb_CDC INTERFACE) target_compile_options(PRNTR_V1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(PRNTR_V1_usb_CDCgen INTERFACE) target_compile_options(PRNTR_V1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(PRNTR_V1_usb_none INTERFACE) target_compile_options(PRNTR_V1_usb_none INTERFACE @@ -103795,11 +103795,11 @@ target_compile_options(PRNTR_V2_serial_none INTERFACE ) add_library(PRNTR_V2_usb_CDC INTERFACE) target_compile_options(PRNTR_V2_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(PRNTR_V2_usb_CDCgen INTERFACE) target_compile_options(PRNTR_V2_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(PRNTR_V2_usb_none INTERFACE) target_compile_options(PRNTR_V2_usb_none INTERFACE @@ -103873,15 +103873,15 @@ target_compile_options(PX_HER0_serial_none INTERFACE ) add_library(PX_HER0_usb_CDC INTERFACE) target_compile_options(PX_HER0_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(PX_HER0_usb_CDCgen INTERFACE) target_compile_options(PX_HER0_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(PX_HER0_usb_HID INTERFACE) target_compile_options(PX_HER0_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(PX_HER0_usb_none INTERFACE) target_compile_options(PX_HER0_usb_none INTERFACE @@ -103943,15 +103943,15 @@ target_compile_options(PYBSTICK26_DUINO_serial_none INTERFACE ) add_library(PYBSTICK26_DUINO_usb_CDC INTERFACE) target_compile_options(PYBSTICK26_DUINO_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(PYBSTICK26_DUINO_usb_CDCgen INTERFACE) target_compile_options(PYBSTICK26_DUINO_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(PYBSTICK26_DUINO_usb_HID INTERFACE) target_compile_options(PYBSTICK26_DUINO_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(PYBSTICK26_DUINO_usb_none INTERFACE) target_compile_options(PYBSTICK26_DUINO_usb_none INTERFACE @@ -104013,15 +104013,15 @@ target_compile_options(PYBSTICK26_LITE_serial_none INTERFACE ) add_library(PYBSTICK26_LITE_usb_CDC INTERFACE) target_compile_options(PYBSTICK26_LITE_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(PYBSTICK26_LITE_usb_CDCgen INTERFACE) target_compile_options(PYBSTICK26_LITE_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(PYBSTICK26_LITE_usb_HID INTERFACE) target_compile_options(PYBSTICK26_LITE_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(PYBSTICK26_LITE_usb_none INTERFACE) target_compile_options(PYBSTICK26_LITE_usb_none INTERFACE @@ -104083,15 +104083,15 @@ target_compile_options(PYBSTICK26_PRO_serial_none INTERFACE ) add_library(PYBSTICK26_PRO_usb_CDC INTERFACE) target_compile_options(PYBSTICK26_PRO_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(PYBSTICK26_PRO_usb_CDCgen INTERFACE) target_compile_options(PYBSTICK26_PRO_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(PYBSTICK26_PRO_usb_HID INTERFACE) target_compile_options(PYBSTICK26_PRO_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(PYBSTICK26_PRO_usb_none INTERFACE) target_compile_options(PYBSTICK26_PRO_usb_none INTERFACE @@ -104153,15 +104153,15 @@ target_compile_options(PYBSTICK26_STD_serial_none INTERFACE ) add_library(PYBSTICK26_STD_usb_CDC INTERFACE) target_compile_options(PYBSTICK26_STD_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(PYBSTICK26_STD_usb_CDCgen INTERFACE) target_compile_options(PYBSTICK26_STD_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(PYBSTICK26_STD_usb_HID INTERFACE) target_compile_options(PYBSTICK26_STD_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(PYBSTICK26_STD_usb_none INTERFACE) target_compile_options(PYBSTICK26_STD_usb_none INTERFACE @@ -104385,11 +104385,11 @@ target_compile_options(REMRAM_V1_serial_none INTERFACE ) add_library(REMRAM_V1_usb_CDC INTERFACE) target_compile_options(REMRAM_V1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(REMRAM_V1_usb_CDCgen INTERFACE) target_compile_options(REMRAM_V1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(REMRAM_V1_usb_none INTERFACE) target_compile_options(REMRAM_V1_usb_none INTERFACE @@ -104517,11 +104517,11 @@ target_compile_options(RUMBA32_serial_none INTERFACE ) add_library(RUMBA32_usb_CDC INTERFACE) target_compile_options(RUMBA32_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(RUMBA32_usb_CDCgen INTERFACE) target_compile_options(RUMBA32_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(RUMBA32_usb_none INTERFACE) target_compile_options(RUMBA32_usb_none INTERFACE @@ -104677,15 +104677,15 @@ target_compile_options(Sparky_V1_serial_none INTERFACE ) add_library(Sparky_V1_usb_CDC INTERFACE) target_compile_options(Sparky_V1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(Sparky_V1_usb_CDCgen INTERFACE) target_compile_options(Sparky_V1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(Sparky_V1_usb_HID INTERFACE) target_compile_options(Sparky_V1_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(Sparky_V1_usb_none INTERFACE) target_compile_options(Sparky_V1_usb_none INTERFACE @@ -104885,11 +104885,11 @@ target_compile_options(ST3DP001_EVAL_serial_none INTERFACE ) add_library(ST3DP001_EVAL_usb_CDC INTERFACE) target_compile_options(ST3DP001_EVAL_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(ST3DP001_EVAL_usb_CDCgen INTERFACE) target_compile_options(ST3DP001_EVAL_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(ST3DP001_EVAL_usb_none INTERFACE) target_compile_options(ST3DP001_EVAL_usb_none INTERFACE @@ -104963,15 +104963,15 @@ target_compile_options(STEVAL_MKBOXPRO_serial_none INTERFACE ) add_library(STEVAL_MKBOXPRO_usb_CDC INTERFACE) target_compile_options(STEVAL_MKBOXPRO_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(STEVAL_MKBOXPRO_usb_CDCgen INTERFACE) target_compile_options(STEVAL_MKBOXPRO_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(STEVAL_MKBOXPRO_usb_HID INTERFACE) target_compile_options(STEVAL_MKBOXPRO_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(STEVAL_MKBOXPRO_usb_none INTERFACE) target_compile_options(STEVAL_MKBOXPRO_usb_none INTERFACE @@ -105045,15 +105045,15 @@ target_compile_options(STEVAL_MKSBOX1V1_serial_none INTERFACE ) add_library(STEVAL_MKSBOX1V1_usb_CDC INTERFACE) target_compile_options(STEVAL_MKSBOX1V1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(STEVAL_MKSBOX1V1_usb_CDCgen INTERFACE) target_compile_options(STEVAL_MKSBOX1V1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(STEVAL_MKSBOX1V1_usb_HID INTERFACE) target_compile_options(STEVAL_MKSBOX1V1_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(STEVAL_MKSBOX1V1_usb_none INTERFACE) target_compile_options(STEVAL_MKSBOX1V1_usb_none INTERFACE @@ -105127,15 +105127,15 @@ target_compile_options(STM32C0116_DK_serial_none INTERFACE ) add_library(STM32C0116_DK_usb_CDC INTERFACE) target_compile_options(STM32C0116_DK_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(STM32C0116_DK_usb_CDCgen INTERFACE) target_compile_options(STM32C0116_DK_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(STM32C0116_DK_usb_HID INTERFACE) target_compile_options(STM32C0116_DK_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(STM32C0116_DK_usb_none INTERFACE) target_compile_options(STM32C0116_DK_usb_none INTERFACE @@ -105209,15 +105209,15 @@ target_compile_options(STM32C0316_DK_serial_none INTERFACE ) add_library(STM32C0316_DK_usb_CDC INTERFACE) target_compile_options(STM32C0316_DK_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(STM32C0316_DK_usb_CDCgen INTERFACE) target_compile_options(STM32C0316_DK_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(STM32C0316_DK_usb_HID INTERFACE) target_compile_options(STM32C0316_DK_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(STM32C0316_DK_usb_none INTERFACE) target_compile_options(STM32C0316_DK_usb_none INTERFACE @@ -105239,7 +105239,7 @@ target_compile_options(STM32C0316_DK_xusb_HSFS INTERFACE # STM32H573I_DK # ----------------------------------------------------------------------------- -set(STM32H573I_DK_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H573IIKxQ") +set(STM32H573I_DK_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563IIKxQ_H573IIKxQ") set(STM32H573I_DK_MAXSIZE 2097152) set(STM32H573I_DK_MAXDATASIZE 655360) set(STM32H573I_DK_MCU cortex-m33) @@ -105291,15 +105291,15 @@ target_compile_options(STM32H573I_DK_serial_none INTERFACE ) add_library(STM32H573I_DK_usb_CDC INTERFACE) target_compile_options(STM32H573I_DK_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(STM32H573I_DK_usb_CDCgen INTERFACE) target_compile_options(STM32H573I_DK_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(STM32H573I_DK_usb_HID INTERFACE) target_compile_options(STM32H573I_DK_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(STM32H573I_DK_usb_none INTERFACE) target_compile_options(STM32H573I_DK_usb_none INTERFACE @@ -105373,15 +105373,15 @@ target_compile_options(STM32H747I_DISCO_serial_none INTERFACE ) add_library(STM32H747I_DISCO_usb_CDC INTERFACE) target_compile_options(STM32H747I_DISCO_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(STM32H747I_DISCO_usb_CDCgen INTERFACE) target_compile_options(STM32H747I_DISCO_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(STM32H747I_DISCO_usb_HID INTERFACE) target_compile_options(STM32H747I_DISCO_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(STM32H747I_DISCO_usb_none INTERFACE) target_compile_options(STM32H747I_DISCO_usb_none INTERFACE @@ -105587,15 +105587,15 @@ target_compile_options(STM32WB5MM_DK_serial_none INTERFACE ) add_library(STM32WB5MM_DK_usb_CDC INTERFACE) target_compile_options(STM32WB5MM_DK_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(STM32WB5MM_DK_usb_CDCgen INTERFACE) target_compile_options(STM32WB5MM_DK_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(STM32WB5MM_DK_usb_HID INTERFACE) target_compile_options(STM32WB5MM_DK_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(STM32WB5MM_DK_usb_none INTERFACE) target_compile_options(STM32WB5MM_DK_usb_none INTERFACE @@ -105669,11 +105669,11 @@ target_compile_options(STORM32_V1_31_RC_serial_none INTERFACE ) add_library(STORM32_V1_31_RC_usb_CDC INTERFACE) target_compile_options(STORM32_V1_31_RC_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(STORM32_V1_31_RC_usb_CDCgen INTERFACE) target_compile_options(STORM32_V1_31_RC_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(STORM32_V1_31_RC_usb_none INTERFACE) target_compile_options(STORM32_V1_31_RC_usb_none INTERFACE @@ -105747,15 +105747,15 @@ target_compile_options(SWAN_R5_serial_none INTERFACE ) add_library(SWAN_R5_usb_CDC INTERFACE) target_compile_options(SWAN_R5_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(SWAN_R5_usb_CDCgen INTERFACE) target_compile_options(SWAN_R5_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(SWAN_R5_usb_HID INTERFACE) target_compile_options(SWAN_R5_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(SWAN_R5_usb_none INTERFACE) target_compile_options(SWAN_R5_usb_none INTERFACE @@ -105829,15 +105829,15 @@ target_compile_options(THUNDERPACK_F411_serial_none INTERFACE ) add_library(THUNDERPACK_F411_usb_CDC INTERFACE) target_compile_options(THUNDERPACK_F411_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(THUNDERPACK_F411_usb_CDCgen INTERFACE) target_compile_options(THUNDERPACK_F411_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(THUNDERPACK_F411_usb_HID INTERFACE) target_compile_options(THUNDERPACK_F411_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(THUNDERPACK_F411_usb_none INTERFACE) target_compile_options(THUNDERPACK_F411_usb_none INTERFACE @@ -105953,15 +105953,15 @@ target_compile_options(THUNDERPACK_L072_serial_none INTERFACE ) add_library(THUNDERPACK_L072_usb_CDC INTERFACE) target_compile_options(THUNDERPACK_L072_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(THUNDERPACK_L072_usb_CDCgen INTERFACE) target_compile_options(THUNDERPACK_L072_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(THUNDERPACK_L072_usb_HID INTERFACE) target_compile_options(THUNDERPACK_L072_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(THUNDERPACK_L072_usb_none INTERFACE) target_compile_options(THUNDERPACK_L072_usb_none INTERFACE @@ -106023,11 +106023,11 @@ target_compile_options(VAKE_V1_serial_none INTERFACE ) add_library(VAKE_V1_usb_CDC INTERFACE) target_compile_options(VAKE_V1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(VAKE_V1_usb_CDCgen INTERFACE) target_compile_options(VAKE_V1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(VAKE_V1_usb_none INTERFACE) target_compile_options(VAKE_V1_usb_none INTERFACE @@ -106101,15 +106101,15 @@ target_compile_options(VCCGND_F103ZET6_serial_none INTERFACE ) add_library(VCCGND_F103ZET6_usb_CDC INTERFACE) target_compile_options(VCCGND_F103ZET6_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(VCCGND_F103ZET6_usb_CDCgen INTERFACE) target_compile_options(VCCGND_F103ZET6_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(VCCGND_F103ZET6_usb_HID INTERFACE) target_compile_options(VCCGND_F103ZET6_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(VCCGND_F103ZET6_usb_none INTERFACE) target_compile_options(VCCGND_F103ZET6_usb_none INTERFACE @@ -106309,15 +106309,15 @@ target_compile_options(VCCGND_F103ZET6_MINI_serial_none INTERFACE ) add_library(VCCGND_F103ZET6_MINI_usb_CDC INTERFACE) target_compile_options(VCCGND_F103ZET6_MINI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(VCCGND_F103ZET6_MINI_usb_CDCgen INTERFACE) target_compile_options(VCCGND_F103ZET6_MINI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(VCCGND_F103ZET6_MINI_usb_HID INTERFACE) target_compile_options(VCCGND_F103ZET6_MINI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(VCCGND_F103ZET6_MINI_usb_none INTERFACE) target_compile_options(VCCGND_F103ZET6_MINI_usb_none INTERFACE @@ -106517,15 +106517,15 @@ target_compile_options(VCCGND_F407ZG_MINI_serial_none INTERFACE ) add_library(VCCGND_F407ZG_MINI_usb_CDC INTERFACE) target_compile_options(VCCGND_F407ZG_MINI_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(VCCGND_F407ZG_MINI_usb_CDCgen INTERFACE) target_compile_options(VCCGND_F407ZG_MINI_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(VCCGND_F407ZG_MINI_usb_HID INTERFACE) target_compile_options(VCCGND_F407ZG_MINI_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(VCCGND_F407ZG_MINI_usb_none INTERFACE) target_compile_options(VCCGND_F407ZG_MINI_usb_none INTERFACE @@ -106641,15 +106641,15 @@ target_compile_options(WeActMiniH743VITX_serial_none INTERFACE ) add_library(WeActMiniH743VITX_usb_CDC INTERFACE) target_compile_options(WeActMiniH743VITX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(WeActMiniH743VITX_usb_CDCgen INTERFACE) target_compile_options(WeActMiniH743VITX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(WeActMiniH743VITX_usb_HID INTERFACE) target_compile_options(WeActMiniH743VITX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(WeActMiniH743VITX_usb_none INTERFACE) target_compile_options(WeActMiniH743VITX_usb_none INTERFACE @@ -106723,15 +106723,15 @@ target_compile_options(WeActMiniH750VBTX_serial_none INTERFACE ) add_library(WeActMiniH750VBTX_usb_CDC INTERFACE) target_compile_options(WeActMiniH750VBTX_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(WeActMiniH750VBTX_usb_CDCgen INTERFACE) target_compile_options(WeActMiniH750VBTX_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(WeActMiniH750VBTX_usb_HID INTERFACE) target_compile_options(WeActMiniH750VBTX_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(WeActMiniH750VBTX_usb_none INTERFACE) target_compile_options(WeActMiniH750VBTX_usb_none INTERFACE @@ -106805,11 +106805,11 @@ target_compile_options(WRAITH32_V1_serial_none INTERFACE ) add_library(WRAITH32_V1_usb_CDC INTERFACE) target_compile_options(WRAITH32_V1_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(WRAITH32_V1_usb_CDCgen INTERFACE) target_compile_options(WRAITH32_V1_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(WRAITH32_V1_usb_none INTERFACE) target_compile_options(WRAITH32_V1_usb_none INTERFACE diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/CMakeLists.txt b/variants/STM32H5xx/H563A(G-I)I_H573AII/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/CMakeLists.txt b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/CMakeLists.txt b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/CMakeLists.txt b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a21dc24a7 --- /dev/null +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/CMakeLists.txt @@ -0,0 +1,33 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + PeripheralPins_STM32H573I_DK.c + variant_generic.cpp + variant_STM32H573I_DK.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/CMakeLists.txt b/variants/STM32H5xx/H563IITxQ_H573IITxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/CMakeLists.txt b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/CMakeLists.txt b/variants/STM32H5xx/H563R(G-I)T_H573RIT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/CMakeLists.txt b/variants/STM32H5xx/H563R(G-I)V_H573RIV/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/CMakeLists.txt b/variants/STM32H5xx/H563V(G-I)T_H573VIT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/CMakeLists.txt b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/CMakeLists.txt new file mode 100644 index 0000000000..b30dd9bd31 --- /dev/null +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/CMakeLists.txt @@ -0,0 +1,32 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp + variant_NUCLEO_H563ZI.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/CMakeLists.txt b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + From 3638fc98ae402b355e4b324409b626964bf919a1 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 4 Jan 2024 16:27:31 +0100 Subject: [PATCH 72/83] ci(build): update generic variants list to skip Signed-off-by: Frederic Pillon --- CI/build/conf/cores_config.json | 2 ++ CI/build/conf/cores_config_ci.json | 2 ++ 2 files changed, 4 insertions(+) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index bd679e0924..0e9d49cd7b 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -540,7 +540,9 @@ "GENERIC_G4A1MESX", "GENERIC_G4A1REIX", "GENERIC_G4A1RETX", + "GENERIC_H563IIKXQ", "GENERIC_H563ZGTX", + "GENERIC_H563ZITX", "GENERIC_H723ZETX", "GENERIC_H723ZGTX", "GENERIC_H730ZBTX", diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json index d6510018ba..81e1333dfc 100644 --- a/CI/build/conf/cores_config_ci.json +++ b/CI/build/conf/cores_config_ci.json @@ -540,7 +540,9 @@ "GENERIC_G4A1MESX", "GENERIC_G4A1REIX", "GENERIC_G4A1RETX", + "GENERIC_H563IIKXQ", "GENERIC_H563ZGTX", + "GENERIC_H563ZITX", "GENERIC_H723ZETX", "GENERIC_H723ZGTX", "GENERIC_H730ZBTX", From 6e619060109b337d08cc48188b7d91e2e079d579 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 9 Jan 2024 10:47:02 +0100 Subject: [PATCH 73/83] fix(platform): wrong optimization_flags for Arduino 1.8.x Introduced by #2184. Fixes #2244. Signed-off-by: Frederic Pillon --- platform.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.txt b/platform.txt index 31fd90c28c..e8de0ea428 100644 --- a/platform.txt +++ b/platform.txt @@ -19,7 +19,7 @@ compiler.warning_flags.all=-Wall -Wextra # EXPERIMENTAL feature: optimization flags # - this is alpha and may be subject to change without notice -compiler.optimization_flags={compiler.optimization_flags} +compiler.optimization_flags={build.flags.optimize} {build.flags.debug} compiler.optimization_flags.release={build.flags.optimize} {build.flags.debug} compiler.optimization_flags.debug=-Og -g From 0c9cc7328ccc92a0867dba7bc7a58cdaaa93e266 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 11 Jan 2024 15:33:40 +0100 Subject: [PATCH 74/83] ci(stm32cube): update BLE path Signed-off-by: Frederic Pillon --- CI/update/stm32cube.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/CI/update/stm32cube.py b/CI/update/stm32cube.py index ae7023efb9..e9c87edcd2 100644 --- a/CI/update/stm32cube.py +++ b/CI/update/stm32cube.py @@ -688,7 +688,7 @@ def updateBleRepo(): def applyBlePatch(): print(" Applying patches to ble library") - BLE_patch_path = repo_local_path / repo_ble_name / "extras" / "STM32Cube_FW" + BLE_patch_path = repo_local_path / repo_ble_name / "extras" / "STM32_WPAN" patch_list = [] if BLE_patch_path.is_dir(): @@ -755,10 +755,10 @@ def updateBleLibrary(): else: cube_name = f"{repo_generic_name}WB" cube_path = repo_local_path / cube_name - ble_path = repo_local_path / repo_ble_name / "src" / "utility" / "STM32Cube_FW" + ble_path = repo_local_path / repo_ble_name / "src" / "utility" / "STM32_WPAN" cube_version = cube_versions["WB"] - ble_commit_msg = f"chore: update STM32Cube_FW from Cube version {cube_version}" + ble_commit_msg = f"chore: update STM32_WPAN from Cube version {cube_version}" for file in ble_file_list: file_path = Path(cube_path / file) From 73b834c8f9ef5722e3bd8d8f0b0f82ce0f9dcb4b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 10 Jan 2024 10:28:07 +0100 Subject: [PATCH 75/83] system(WB) update STM32WBxx HAL Drivers to v1.14.1 Included in STM32CubeWB FW v1.18.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 9 +- .../Inc/stm32wbxx_hal_i2c.h | 2 - .../Inc/stm32wbxx_hal_lptim.h | 4 +- .../Inc/stm32wbxx_hal_rtc_ex.h | 8 - .../Inc/stm32wbxx_hal_smbus.h | 2 - .../Inc/stm32wbxx_hal_tim.h | 40 ++--- .../Inc/stm32wbxx_ll_i2c.h | 9 +- .../Inc/stm32wbxx_ll_tim.h | 52 +++--- .../Inc/stm32wbxx_ll_usb.h | 22 +-- .../{License.md => LICENSE.md} | 0 .../STM32WBxx_HAL_Driver/Release_Notes.html | 164 ++++++++++++------ .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c | 2 +- .../Src/stm32wbxx_hal_i2c.c | 129 +++++++++----- .../Src/stm32wbxx_hal_lptim.c | 2 +- .../Src/stm32wbxx_hal_sai.c | 32 ++-- .../Src/stm32wbxx_hal_smbus.c | 10 +- .../Src/stm32wbxx_hal_tim.c | 30 ++-- .../Src/stm32wbxx_hal_tim_ex.c | 60 ++----- .../Src/stm32wbxx_hal_uart.c | 17 +- .../Src/stm32wbxx_ll_tim.c | 27 ++- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 21 files changed, 343 insertions(+), 280 deletions(-) rename system/Drivers/STM32WBxx_HAL_Driver/{License.md => LICENSE.md} (100%) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 2fccdc7ae9..00b3dac922 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -3643,7 +3643,8 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) + defined(STM32WL) || defined(STM32C0) + #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3892,7 +3893,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3929,7 +3931,8 @@ extern "C" { #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ defined (STM32H7) || \ - defined (STM32L0) || defined (STM32L1) + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG #endif diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h index c862c65ae2..0c959991dc 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h @@ -118,8 +118,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h index 7ca18f3bd9..24449219e3 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h @@ -657,9 +657,9 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @} diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc_ex.h index f660fb02d5..1715df8cce 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc_ex.h @@ -794,14 +794,6 @@ typedef struct * * @retval None */ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \ - ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \ - ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U)) -#else -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__)\ - == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U)) -#endif /* RTC_TAMPER1_SUPPORT || RTC_TAMPER3_SUPPORT */ /**************************************************************************************************/ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h index cdddf89b63..69a3aec552 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h @@ -100,8 +100,6 @@ typedef struct #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h index 95f1188fe4..18a619e3f6 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h @@ -402,29 +402,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1866,8 +1865,9 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ - ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -1920,7 +1920,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -2317,7 +2316,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h index 4d0c6f265c..0f5f380bea 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h @@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h index a7249def44..10fab60f55 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h @@ -664,10 +664,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR2, TIM_CR2_CCPC); } +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check @@ -3532,18 +3552,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); } -/** - * @brief Re-arm the break input (when it operates in bidirectional mode). - * @note The Break input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); -} - /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -3633,18 +3641,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); } -/** - * @brief Re-arm the break 2 input (when it operates in bidirectional mode). - * @note The Break 2 input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); -} - /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_usb.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_usb.h index 11211ffd68..52b7ec9275 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_usb.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_usb.h @@ -53,26 +53,26 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; typedef struct diff --git a/system/Drivers/STM32WBxx_HAL_Driver/License.md b/system/Drivers/STM32WBxx_HAL_Driver/LICENSE.md similarity index 100% rename from system/Drivers/STM32WBxx_HAL_Driver/License.md rename to system/Drivers/STM32WBxx_HAL_Driver/LICENSE.md diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html index 9b27cea24b..ad7371dbcb 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html @@ -40,7 +40,7 @@

                      Purpose

                      Update History

                      - +

                      Main Changes

                        @@ -50,6 +50,72 @@

                        Main Changes

                        Contents

                        HAL Drivers updates

                          +
                        • HAL I2C driver +
                            +
                          • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice
                            • +
                          • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE
                            • +
                          • Remove the unusable code in function HAL_I2C_IsDeviceReady
                            • +
                          • Update I2C_WaitOnFlagUntilTimeout to handle error case
                            • +
                          • +
                        • HAL SAI driver +
                            +
                          • Improve audio quality (avoid potential glitch)
                            • +
                          • +
                        • HAL QSPI driver +
                            +
                          • Clear the QSPI.AR register when sCommand.AddressMode is “QSPI_ADDRESS_NONE”
                            • +
                          • +
                        • HAL TIM driver +
                            +
                          • Removing multiple volatile reads or writes in interrupt handler
                            • +
                          • Improved period configuration parameter check
                            • +
                          • Assert check for the right channels
                            • +
                          • +
                        • HAL RTC driver +
                            +
                          • Remove macro __HAL_RTC_TAMPER_GET_IT() as it is redundant with macro __HAL_RTC_TAMPER_GET_FLAG() and create an alias into the hal_legacy.h file
                            • +
                          • +
                        • HAL UART driver +
                            +
                          • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to allow user Rx Event Callback registration when a transmit is ongoing
                            • +
                          • Avoid RTOF flag to be cleared by a transmit process in polling mode
                            • +
                          • +
                        +


                        +

                        +

                        LL Drivers updates

                        +
                          +
                        • LL I2C driver +
                            +
                          • Update LL_I2C_HandleTranfer function to prevent undefined behavior of volatile usage before updating the CR2 register
                            • +
                          • +
                        • LL TIM driver +
                            +
                          • Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init()
                            • +
                          • User manual quality improvement
                            • +
                          • +
                        • LL RTC driver +
                            +
                          • Correct misleading note about shadow registers
                            • +
                          • +
                        +


                        +

                        +

                        Backward Compatibility

                        +

                        This release is compatible with the previous versions.

                        +
                      +
                      +
                      + +
                      +

                      Main Changes

                      +
                        +
                      • Maintenance release of HAL and Low Layer drivers to include latest corrections
                        • +
                      • HAL/LL code quality enhancement
                        • +
                      +

                      Contents

                      +

                      HAL Drivers updates

                      +
                      • HAL CRYP driver
                        • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment
                          • @@ -87,7 +153,7 @@

                          HAL Drivers updates


                        -

                        LL Drivers updates

                        +

                        LL Drivers updates

                        • LL USB driver
                            @@ -96,20 +162,20 @@

                            LL Drivers updates


                          -

                          Backward Compatibility

                          +

                          Backward Compatibility

                          This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      • Maintenance release of HAL and Low Layer drivers to include latest corrections
                      • HAL/LL code quality enhancement
                      -

                      Contents

                      -

                      HAL Drivers updates

                      +

                      Contents

                      +

                      HAL Drivers updates

                      • HAL FLASH driver
                          @@ -140,20 +206,20 @@

                          HAL Drivers updates


                        -

                        Backward Compatibility

                        +

                        Backward Compatibility

                        This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      • Maintenance release of HAL and Low Layer drivers to include latest corrections
                      • Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (IRDA, LPTIM, SMARTCARD, TIM, UART, USART)
                      -

                      Contents

                      -

                      HAL Drivers updates

                      +

                      Contents

                      +

                      HAL Drivers updates

                      • HAL ADC driver
                          @@ -200,7 +266,7 @@

                          HAL Drivers updates


                        -

                        LL Drivers updates

                        +

                        LL Drivers updates

                        • LL ADC driver
                            @@ -221,20 +287,20 @@

                            LL Drivers updates


                          -

                          Backward Compatibility

                          +

                          Backward Compatibility

                          This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      • Maintenance release of HAL and Low Layer drivers to include latest corrections
                      • Correct English spelling errors and typos
                      -

                      Contents

                      -

                      HAL Drivers updates

                      +

                      Contents

                      +

                      HAL Drivers updates

                      • HAL EXTI driver
                          @@ -310,7 +376,7 @@

                          HAL Drivers updates


                        -

                        LL Drivers updates

                        +

                        LL Drivers updates

                        • LL I2C driver
                            @@ -346,19 +412,19 @@

                            LL Drivers updates


                          -

                          Backward Compatibility

                          +

                          Backward Compatibility

                          This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      • Patch release of HAL and Low Layer drivers
                      -

                      Contents

                      -

                      HAL Drivers updates

                      +

                      Contents

                      +

                      HAL Drivers updates

                      • HAL COMP driver
                          @@ -367,7 +433,7 @@

                          HAL Drivers updates


                        -

                        LL Drivers updates

                        +

                        LL Drivers updates

                        • LL COMP driver
                            @@ -376,21 +442,21 @@

                            LL Drivers updates


                          -

                          Backward Compatibility

                          +

                          Backward Compatibility

                          This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      • Maintenance release of HAL and Low Layer drivers to include latest corrections
                      • All source files: update disclaimer to add reference to the new license agreement
                      • Correct English spelling errors and typos
                      -

                      Contents

                      -

                      HAL Drivers updates

                      +

                      Contents

                      +

                      HAL Drivers updates

                      • HAL ADC driver
                          @@ -461,7 +527,7 @@

                          HAL Drivers updates


                        -

                        LL Drivers updates

                        +

                        LL Drivers updates

                        • LL ADC driver
                            @@ -476,14 +542,14 @@

                            LL Drivers updates


                          -

                          Backward Compatibility

                          +

                          Backward Compatibility

                          This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      • Maintenance release of HAL and Low Layer drivers to include latest corrections
                      • Update of HAL SMBUS driver to introduce fast mode and fast mode plus @@ -497,8 +563,8 @@

                        Main Changes


                      -

                      Contents

                      -

                      HAL Drivers updates

                      +

                      Contents

                      +

                      HAL Drivers updates

                      • HAL CORTEX driver
                          @@ -574,7 +640,7 @@

                          HAL Drivers updates


                        -

                        LL Drivers updates

                        +

                        LL Drivers updates

                        • LL DMA driver
                            @@ -601,14 +667,14 @@

                            LL Drivers updates


                          -

                          Backward Compatibility

                          +

                          Backward Compatibility

                          This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      Add support for STM32WB15xx and STM32WB10xx

                      @@ -744,14 +810,14 @@

                      Add support for STM32WB15xx

                      -

                      Backward Compatibility

                      +

                      Backward Compatibility

                      This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      Maitenance release

                      All peripheral

                      @@ -824,14 +890,14 @@

                      Maitenance release

                      -

                      Backward Compatibility

                      +

                      Backward Compatibility

                      This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      Maitenance release

                      All peripheral

                      @@ -936,14 +1002,14 @@

                      Maitenance release

                      -

                      Backward Compatibility

                      +

                      Backward Compatibility

                      This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product

                      This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

                      Added features:

                      @@ -988,14 +1054,14 @@

                      Introduct -

                      Backward Compatibility

                      +

                      Backward Compatibility

                      This release is compatible with the previous versions.

                      -

                      Main Changes

                      +

                      Main Changes

                      Maitenance release

                      @@ -1039,7 +1105,7 @@

                      Maitenance release

                      -

                      Backward Compatibility

                      +

                      Backward Compatibility

                      This release is compatible with the previous versions.

                      Dependencies

                      This software release is compatible with:

                      @@ -1049,7 +1115,7 @@

                      Dependencies

                      -

                      Main Changes

                      +

                      Main Changes

                      Maitenance release

                      @@ -1121,7 +1187,7 @@

                      Maitenance release

                      -

                      Backward Compatibility

                      +

                      Backward Compatibility

                      This release is compatible with the previous versions.

                      Dependencies

                      This software release is compatible with:

                      @@ -1131,7 +1197,7 @@

                      Dependencies

                      -

                      Main Changes

                      +

                      Main Changes

                      STM32WB50xx introduction and maintenance release

                      First release for STM32WBxx HAL drivers introducing stm32wb50xx devices.

                      @@ -1200,7 +1266,7 @@

                      STM32WB50xx introducti

                      -

                      Backward Compatibility

                      +

                      Backward Compatibility

                      This release is compatible with the previous versions.

                      Dependencies

                      This software release is compatible with:

                      @@ -1210,7 +1276,7 @@

                      Dependencies

                      -

                      Main Changes

                      +

                      Main Changes

                      Maintenance release

                      Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.

                      @@ -1264,7 +1330,7 @@

                      Maintenance release

                      -

                      Backward Compatibility

                      +

                      Backward Compatibility

                      This release is compatible with the previous versions.

                      Dependencies

                      This software release is compatible with:

                      @@ -1274,7 +1340,7 @@

                      Dependencies

                      -

                      Main Changes

                      +

                      Main Changes

                      First release

                      First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.

                      diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c index 7c01352a2c..ec62ac72f5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c @@ -56,7 +56,7 @@ */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WBxx_HAL_VERSION_SUB1 (0x0EU) /*!< [23:16] sub1 version */ -#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32WBxx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ |(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c index e2215532d2..05f58e6e54 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c @@ -3332,22 +3332,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - /* Increment Trials */ I2C_Trials++; } while (I2C_Trials < Trials); @@ -5251,9 +5235,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5682,9 +5665,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -6286,14 +6268,14 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Disable Interrupts and Store Previous state */ - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (tmpstate == HAL_I2C_STATE_LISTEN)) + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; @@ -6303,6 +6285,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } else { /* Do nothing */ @@ -6371,6 +6358,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -6905,6 +6943,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { @@ -7016,16 +7060,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -7033,19 +7079,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -7059,12 +7100,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) { @@ -7074,11 +7119,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; } } } - return HAL_OK; + return status; } /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c index 28e14a83fb..cbace79f81 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c @@ -43,7 +43,7 @@ (++) Clock: the counter clock. (+++) Source : it can be either the ULPTIM input (IN1) or one of the internal clock; (APB, LSE, LSI or MSI). - CAUTION: if LSI2 is selected as LPTIM cock source, LSI1 has + CAUTION: if LSI2 is selected as LPTIM clock source, LSI1 has to be enabled as well (for further information please refer to errata sheet ES0394). (+++) Prescaler: select the clock divider. diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c index 33b9b8694d..6ee833a3f5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c @@ -170,7 +170,7 @@ [..] Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. [..] @@ -185,10 +185,10 @@ [..] By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + reset to the legacy weak functions in the HAL_SAI_Init and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -205,7 +205,7 @@ [..] When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim ****************************************************************************** @@ -1343,6 +1343,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -1362,12 +1368,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) (void) HAL_DMA_Abort(hsai->hdmarx); } - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1393,6 +1393,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Check SAI DMA is enabled or not */ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { @@ -1420,12 +1426,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c index bb0cfb18de..84f93293fa 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c @@ -926,7 +926,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; - uint32_t sizetoxfer = 0U; + uint32_t sizetoxfer; /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -960,10 +960,10 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint } sizetoxfer = hsmbus->XferSize; - if ((hsmbus->XferSize > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) || - (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || - (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) || - (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) + if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || + (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) { if (hsmbus->pBuffPtr != NULL) { diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c index ddbb0cb1a7..930bb22575 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c @@ -3850,7 +3850,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3882,7 +3882,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3912,7 +3912,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3942,7 +3942,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3972,7 +3972,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3981,11 +3981,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else @@ -4011,7 +4012,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -4024,7 +4025,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else @@ -4575,7 +4576,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status; @@ -6988,6 +6990,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } } /** @@ -7112,7 +7121,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c index 5e90810ff9..8b327a5f41 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c @@ -873,7 +873,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1119,17 +1119,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1355,7 +1344,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -2090,6 +2079,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); @@ -2106,15 +2096,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - - /* Set BREAK AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -2122,20 +2104,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - - /* Set BREAK2 AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } /* Set TIMx_BDTR */ @@ -2159,7 +2134,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; @@ -2414,7 +2388,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B uint32_t tmpbdtr; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -2431,7 +2405,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } - case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -2469,7 +2442,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint3 uint32_t tickstart; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -2548,7 +2521,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint3 */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2562,7 +2535,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2577,7 +2550,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2592,7 +2565,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break2 detection callback in non blocking mode + * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ @@ -2743,15 +2716,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } else { /* nothing to do */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c index 57cd74c4be..bb6a338c2d 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c @@ -981,10 +981,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = pCallback; } @@ -995,9 +992,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -1011,10 +1005,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ } @@ -1025,8 +1016,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); return status; } @@ -3477,7 +3466,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_TIMEOUT; } - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) { diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c index e59f9c252d..643b2d8d8b 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c @@ -698,6 +698,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -710,8 +712,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); @@ -765,8 +765,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -794,8 +792,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -844,8 +844,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -873,8 +871,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -923,8 +923,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -952,8 +950,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -1002,8 +1002,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1031,7 +1029,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the Output Idle state */ @@ -1298,7 +1295,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index b2da27c6a7..ac1a8e75ff 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -17,7 +17,7 @@ * STM32L5: 1.0.5 * STM32MP1: 1.6.0 * STM32U5: 1.4.0 - * STM32WB: 1.14.0 + * STM32WB: 1.14.1 * STM32WL: 1.3.0 Release notes of each STM32YYxx HAL Drivers available here: From 75bda51e7c6d79415326ac43a199ee36200d93a1 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 15 Jan 2024 11:29:28 +0100 Subject: [PATCH 76/83] fix(C0): add missing include Raised in #2250. Signed-off-by: Frederic Pillon --- .../C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/generic_clock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/generic_clock.c b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/generic_clock.c index 70d1709d5d..8c71c8c77a 100644 --- a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/generic_clock.c +++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/generic_clock.c @@ -15,6 +15,7 @@ defined(ARDUINO_GENERIC_C011F6UX) || defined(ARDUINO_GENERIC_C031F4PX) ||\ defined(ARDUINO_GENERIC_C031F6PX) #include "pins_arduino.h" +#include "stm32yyxx_ll_utils.h" /** * @brief System Clock Configuration From 8f3eac4e182cef2c2a98ed301eb69a8b2bc5b2db Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 15 Jan 2024 15:12:13 +0100 Subject: [PATCH 77/83] fix(C0): menu entry for debug symbol Signed-off-by: Frederic Pillon --- boards.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards.txt b/boards.txt index ef0d7200fe..ef5443fc94 100644 --- a/boards.txt +++ b/boards.txt @@ -12501,7 +12501,7 @@ STM32MP1.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) STM32MP1.menu.dbg.enable_all.build.flags.debug=-g GenC0.menu.dbg.none=None -GenC0.menu.dbg.enable=Enabled (-g) +GenC0.menu.dbg.enable=Symbols Enabled (-g) GenC0.menu.dbg.enable.build.flags.debug=-g GenF0.menu.dbg.none=None From 1863c25025441c8c6dbcea5b8ed496db21c12785 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 15 Jan 2024 16:36:44 +0100 Subject: [PATCH 78/83] fix(i2c): prevent unused variable and functions when all I2C timings are defined Signed-off-by: Frederic Pillon --- libraries/Wire/src/utility/twi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/libraries/Wire/src/utility/twi.c b/libraries/Wire/src/utility/twi.c index 2f65b4a1ba..8cdca94c53 100644 --- a/libraries/Wire/src/utility/twi.c +++ b/libraries/Wire/src/utility/twi.c @@ -57,9 +57,13 @@ extern "C" { #if !defined (STM32F1xx) && !defined (STM32F2xx) && !defined (STM32F4xx) &&\ !defined (STM32L1xx) #define I2C_TIMING +#if !defined(I2C_TIMING_SM) || !defined(I2C_TIMING_FM) || !defined(I2C_TIMING_FMP) +#define I2C_TIMING_COMPUTE +#endif /* !(I2C_TIMING_SM) || !(I2C_TIMING_FM) || !(I2C_TIMING_FMP)*/ + #endif -#ifdef I2C_TIMING +#ifdef I2C_TIMING_COMPUTE #ifndef I2C_VALID_TIMING_NBR #define I2C_VALID_TIMING_NBR 8U #endif @@ -152,7 +156,7 @@ static const I2C_Charac_t I2C_Charac[] = { .dnf = I2C_DIGITAL_FILTER_COEF, } }; -#endif /* I2C_TIMING */ +#endif /* I2C_TIMING_COMPUTE */ /* Family specific description for I2C */ typedef enum { @@ -180,7 +184,7 @@ typedef enum { /* Private Variables */ static I2C_HandleTypeDef *i2c_handles[I2C_NUM]; -#ifdef I2C_TIMING +#ifdef I2C_TIMING_COMPUTE /** * @brief This function return the I2C clock source frequency. * @param i2c: I2C instance @@ -565,7 +569,7 @@ static uint32_t i2c_computeTiming(uint32_t clkSrcFreq, uint32_t i2c_speed) } return ret; } -#endif /* I2C_TIMING */ +#endif /* I2C_TIMING_COMPUTE */ /** * @brief Compute I2C timing according current I2C clock source and @@ -587,6 +591,9 @@ static uint32_t i2c_getTiming(i2c_t *obj, uint32_t frequency) i2c_speed = 1000000; } #ifdef I2C_TIMING +#ifndef I2C_TIMING_COMPUTE + UNUSED(obj); +#endif if (i2c_speed != 0U) { switch (i2c_speed) { default: From 49b8eef6d1a7afb5d78de114b581460df6a3f33c Mon Sep 17 00:00:00 2001 From: Ilias Lolis Date: Mon, 22 Jan 2024 17:53:20 +0200 Subject: [PATCH 79/83] HardwareSerial's flush() method to override the method of the base class Print (#2254) * add flush() method to HardwareSerial * remove default argument --- cores/arduino/HardwareSerial.cpp | 5 +++++ cores/arduino/HardwareSerial.h | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp index ff9ca2d2a5..146cfa234e 100644 --- a/cores/arduino/HardwareSerial.cpp +++ b/cores/arduino/HardwareSerial.cpp @@ -487,6 +487,11 @@ int HardwareSerial::availableForWrite(void) return tail - head - 1; } +void HardwareSerial::flush() +{ + flush(0); +} + void HardwareSerial::flush(uint32_t timeout) { // If we have never written a byte, no need to flush. This special diff --git a/cores/arduino/HardwareSerial.h b/cores/arduino/HardwareSerial.h index b0089bab19..bfd94620ba 100644 --- a/cores/arduino/HardwareSerial.h +++ b/cores/arduino/HardwareSerial.h @@ -125,7 +125,8 @@ class HardwareSerial : public Stream { virtual int peek(void); virtual int read(void); int availableForWrite(void); - virtual void flush(uint32_t timeout = 0); + virtual void flush(); + void flush(uint32_t timeout); virtual size_t write(uint8_t); inline size_t write(unsigned long n) { From de1e1c5d5092244727d98e4ac5848ff4d3a81550 Mon Sep 17 00:00:00 2001 From: ldursw <37294448+ldursw@users.noreply.github.com> Date: Tue, 23 Jan 2024 12:46:40 -0300 Subject: [PATCH 80/83] Fix compiler warning on HardwareTimer (#2256) Signed-off-by: ldursw <37294448+ldursw@users.noreply.github.com> Co-authored-by: Frederic Pillon --- libraries/SrcWrapper/src/HardwareTimer.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libraries/SrcWrapper/src/HardwareTimer.cpp b/libraries/SrcWrapper/src/HardwareTimer.cpp index f65a4f4f13..304b169c92 100644 --- a/libraries/SrcWrapper/src/HardwareTimer.cpp +++ b/libraries/SrcWrapper/src/HardwareTimer.cpp @@ -168,6 +168,10 @@ void HardwareTimer::pause() */ void HardwareTimer::pauseChannel(uint32_t channel) { + if ((channel < 1) || (channel > TIMER_CHANNELS)) { + return; + } + int timAssociatedInputChannel; int LLChannel = getLLChannel(channel); if (LLChannel == -1) { From bc75a21e38cdde15e15332335fad06786d3299bf Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 25 Jan 2024 09:36:58 +0100 Subject: [PATCH 81/83] fix(doc): link in README_CMAKE.md Signed-off-by: Frederic Pillon --- README_CMAKE.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README_CMAKE.md b/README_CMAKE.md index 7ce8bcaf19..ff15cc2ea1 100644 --- a/README_CMAKE.md +++ b/README_CMAKE.md @@ -2,7 +2,7 @@ CMake can now be used to build Arduino sketches with this core. Examples of use can be found on this repo: [stm32duino/CMake_workspace](https://github.com/stm32duino/CMake_workspace). This README only provides a quick walk-through. -For all the glorious details, please head over to [the wiki](https://github.com/stm32duino/Arduino_Core_STM32/wiki/CMake_presentation). +For all the glorious details, please head over to [the wiki](https://github.com/stm32duino/Arduino_Core_STM32/wiki/CMake-presentation). # Prerequisites From 50629bd31f2edc873363f0be13ce012c6974d9ff Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 25 Jan 2024 09:57:07 +0100 Subject: [PATCH 82/83] fix(doc): broken link Daisy Petal discontinued, see legacy on the manufacturer website. Signed-off-by: Frederic Pillon --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 4b4e410562..6d717fe09c 100644 --- a/README.md +++ b/README.md @@ -566,7 +566,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H750IB
                      STM32H750II | Generic Board | *2.0.0* | | | :green_heart: | STM32H750IB | [Daisy](https://www.electro-smith.com/daisy/daisy) | *1.9.0* | | | :green_heart: | STM32H750IB | [Daisy Patch SM](https://www.electro-smith.com/daisy/patch-sm) | *2.2.0* | | -| :green_heart: | STM32H750IB | [Daisy Petal SM](https://www.electro-smith.com/daisy/petal-125b-sm) | *2.2.0* | | +| :green_heart: | STM32H750IB | [Daisy Petal SM](https://www.electro-smith.com) | *2.2.0* | | | :green_heart: | STM32H750VB | Generic Board | *2.0.0* | | | :green_heart: | STM32H750VB | [DevEBox H750VBT6](https://github.com/mcauser/MCUDEV_DEVEBOX_H7XX_M) | *2.2.0* | | | :green_heart: | STM32H750VB | [WeAct MiniSTM32H750VBT6](https://github.com/WeActStudio/MiniSTM32H7xx) | *2.2.0* | [More info](https://github.com/stm32duino/Arduino_Core_STM32/pull/1552) | From 0ca1f4ca3d5936cf10855d2cde37e44735425edf Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 9 Feb 2024 17:27:43 +0100 Subject: [PATCH 83/83] ci(stm32cube): update parse version New series defined HAL version in header file instead of c source one. Signed-off-by: Frederic Pillon --- CI/update/stm32cube.py | 64 ++++++++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/CI/update/stm32cube.py b/CI/update/stm32cube.py index e9c87edcd2..9b1e0c10db 100644 --- a/CI/update/stm32cube.py +++ b/CI/update/stm32cube.py @@ -369,41 +369,23 @@ def latestTag(serie, repo_name, repo_path): # print(f"Latest tagged version available for {repo_name} is {version_tag}") -def parseVersion(path): +def parseVersion(path, patterns): main_found = False sub1_found = False sub2_found = False rc_found = False - if "HAL" in str(path): - main_pattern = re.compile(r"HAL_VERSION_MAIN.*0x([\dA-Fa-f]+)") - sub1_pattern = re.compile(r"HAL_VERSION_SUB1.*0x([\dA-Fa-f]+)") - sub2_pattern = re.compile(r"HAL_VERSION_SUB2.*0x([\dA-Fa-f]+)") - rc_pattern = re.compile(r"HAL_VERSION_RC.*0x([\dA-Fa-f]+)") - else: - main_pattern = re.compile( - r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_MAIN.*0x([\dA-Fa-f]+)" - ) - sub1_pattern = re.compile( - r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_SUB1.*0x([\dA-Fa-f]+)" - ) - sub2_pattern = re.compile( - r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_SUB2.*0x([\dA-Fa-f]+)" - ) - rc_pattern = re.compile( - r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_RC.*0x([\dA-Fa-f]+)" - ) for i, line in enumerate(open(path, encoding="utf8", errors="ignore")): - for match in re.finditer(main_pattern, line): + for match in re.finditer(patterns[0], line): VERSION_MAIN = int(match.group(1), 16) main_found = True - for match in re.finditer(sub1_pattern, line): + for match in re.finditer(patterns[1], line): VERSION_SUB1 = int(match.group(1), 16) sub1_found = True - for match in re.finditer(sub2_pattern, line): + for match in re.finditer(patterns[2], line): VERSION_SUB2 = int(match.group(1), 16) sub2_found = True - for match in re.finditer(rc_pattern, line): + for match in re.finditer(patterns[3], line): VERSION_RC = int(match.group(1), 16) rc_found = True if main_found and sub1_found and sub2_found and rc_found: @@ -434,6 +416,12 @@ def parseVersion(path): def checkVersion(serie, repo_path): lserie = serie.lower() userie = serie.upper() + + patterns = [re.compile(r"HAL_VERSION_MAIN.*0x([\dA-Fa-f]+)")] + patterns.append(re.compile(r"HAL_VERSION_SUB1.*0x([\dA-Fa-f]+)")) + patterns.append(re.compile(r"HAL_VERSION_SUB2.*0x([\dA-Fa-f]+)")) + patterns.append(re.compile(r"HAL_VERSION_RC.*0x([\dA-Fa-f]+)")) + HAL_file = ( repo_path / hal_src_path @@ -441,7 +429,17 @@ def checkVersion(serie, repo_path): / "Src" / f"stm32{lserie}xx_hal.c" ) - cube_HAL_versions[serie] = parseVersion(HAL_file) + with open(HAL_file, "r") as fp: + data = fp.read() + if "HAL_VERSION_MAIN" not in data: + HAL_file = ( + repo_path + / hal_src_path + / f"STM32{userie}xx_HAL_Driver" + / "Inc" + / f"stm32{lserie}xx_hal.h" + ) + cube_HAL_versions[serie] = parseVersion(HAL_file, patterns) if upargs.add: core_HAL_versions[serie] = "0.0.0" else: @@ -451,8 +449,20 @@ def checkVersion(serie, repo_path): / "Src" / f"stm32{lserie}xx_hal.c" ) - core_HAL_versions[serie] = parseVersion(HAL_file) + core_HAL_versions[serie] = parseVersion(HAL_file, patterns) + patterns = [ + re.compile(r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_MAIN.*0x([\dA-Fa-f]+)") + ] + patterns.append( + re.compile(r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_SUB1.*0x([\dA-Fa-f]+)") + ) + patterns.append( + re.compile(r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_SUB2.*0x([\dA-Fa-f]+)") + ) + patterns.append( + re.compile(r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_RC.*0x([\dA-Fa-f]+)") + ) CMSIS_file = ( repo_path / cmsis_src_path @@ -460,14 +470,14 @@ def checkVersion(serie, repo_path): / "Include" / f"stm32{lserie}xx.h" ) - cube_CMSIS_versions[serie] = parseVersion(CMSIS_file) + cube_CMSIS_versions[serie] = parseVersion(CMSIS_file, patterns) if upargs.add: core_CMSIS_versions[serie] = "0.0.0" else: CMSIS_file = ( cmsis_dest_path / f"STM32{userie}xx" / "Include" / f"stm32{lserie}xx.h" ) - core_CMSIS_versions[serie] = parseVersion(CMSIS_file) + core_CMSIS_versions[serie] = parseVersion(CMSIS_file, patterns) # print(f"STM32Cube{serie} HAL version: {cube_HAL_versions[serie]}") # print(f"STM32Core{serie} HAL version: {core_HAL_versions[serie]}")