Veryl.toml

[project]
name        = "veryl_testcase"
version     = "0.1.6"
authors     = ["dalance@gmail.com"]
description = "Testcases for test"
license     = "MIT"
repository  = "https://github.com/veryl-lang/veryl"

[build]
clock_type       = "posedge"
reset_type       = "async_low"
reset_low_suffix = "_n"
filelist_type    = "absolute"
target           = {type = "directory", path = "testcases/sv"}
sourcemap_target = {type = "directory", path = "testcases/map"}

[format]
indent_width = 4

[doc]
path = "target/veryl_doc"

[test]
simulator = "vcs"

[test.vcs]
compile_args = ["-full64"]

[dependencies]
"https://github.com/veryl-lang/sample" = [
    {version = "0.13.0", name = "veryl_sample1"},
    {version = "0.14.0", name = "veryl_sample2"},
    {version = "0.15.0", name = "veryl_sample3"},
]