Support for Xtensa architecture

[SergioGasquez]

First, I would like to thank you for your amazing work! We recently started working on HIL for esp-hal based on embedded-test which depends on semihosting.

As you may know, some ESP chips are Xtensa based, so I wanted to ask if you have any plans to add support for it.

Semihosting on Xtensa

I haven't found any documentation on the Xtensa semihosting standard, so I asked some of our colleagues, here is the information that I gathered:

When espressif added Xtensa support into OpenOCD, they chose to use ARM semihosting spec, instead, because OpenOCD already had good support for it. Besides, RISC-V also uses ARM semihosting spec.
For a reference of the "official" Xtensa semihosting standard (as used in Cadence tools and in QEMU), there is some code in https://github.com/qemu/qemu/blob/master/target/xtensa/xtensa-semi.c, https://github.com/espressif/newlib-esp32/blob/esp_based_on_4_1_0/libgloss/xtensa/syscalls.c — look for the branches with !OPENOCD_SEMIHOSTING and in Linux https://github.com/torvalds/linux/blob/master/arch/xtensa/platforms/iss/include/platform/simcall-iss.h.
This is the part of OpenOCD where the architecture-specific semihosting stuff happens and then call the "common" (ARM) semihosting code: https://github.com/espressif/openocd-esp32/blob/master/src/target/espressif/esp_xtensa_semihosting.c

https://github.com/espressif/esp-idf/blob/master/components/xtensa/include/xtensa/semihosting.h

[taiki-e]

I tried to implement this about a year ago but gave up because the compiler distributed via espup did not support the simcall instruction. (I didn't know about OpenOCD semihosting that using break instruction)

taiki-e/portable-atomic#86 (comment)

I mainly use QEMU and semihosting crate to test no-std targets, so I tried to do the same with Xtensa, but the compiler didn't seem to recognize the simcall instruction so I gave that up testing on CI and decided to test locally using your wokwi-server (it worked well).

If things haven't changed (and we need to use simcall instruction), implementing this would require some work on esp-rs/rust or espressif/llvm-project first. (Although technically we could use C FFI)

If it is OpenOCD semihosting (that using break instruction) that needs to be implemented (does this not seem to work with QEMU?) ), it is probably relatively easy to implement, but which is what you need for your use case?

[taiki-e]

When implementing this on my end, perhaps the hardest part is setting up a proper test environment.

Looking at the working branch at the time (which unfortunately contains code that cannot be made public), it appears that I tried to work around the above problem by calling SIMCALL via C FFI, but failed to properly set up the QEMU and startup code. (The implementation on the semihosting side or the testing side or both was incorrect.)

Perhaps it will not be possible to implement this on my end in the near term unless you or someone else can provide a proper QEMU setup to test, or test the implementation in some other way.

Therefore, marking this as help-wanted.

[SergioGasquez]

If things haven't changed (and we need to use simcall instruction), implementing this would require some work on esp-rs/rust or espressif/llvm-project first. (Although technically we could use C FFI)

Things havent change afaik.

If it is OpenOCD semihosting (that using break instruction) that needs to be implemented (does this not seem to work with QEMU?) ), it is probably relatively easy to implement, but which is what you need for your use case?

I think this is the case, in our end, the break approach should do the trick, and we could help with the testing, either with QEMU or doing it manually if needed.

As @MabezDev suggested, looks Ike what we need to do to get it working is having a https://github.com/espressif/esp-idf/blob/master/components/xtensa/include/xtensa/semihosting.h version of https://github.com/taiki-e/semihosting/blob/main/src/sys/arm_compat/syscall/riscv.rs