From e738fd86baa1264275c3b2af518f2700bf0ca843 Mon Sep 17 00:00:00 2001 From: John Gunn Date: Mon, 14 Jan 2019 17:00:20 +0000 Subject: [PATCH] xtensa: hkey960: Add initial qemu support for Hikey 960 DSP Add initial support for Hikey 960. Offiacial XAF firmware boots and sends some data to the UART. Not sure if XAF FW completes boot, but code does run. Signed-off-by: John Gunn --- hw/adsp/dsp/Makefile.objs | 1 + hw/adsp/dsp/hikey.c | 413 +++++++++++++++ hw/adsp/dsp/hikey.h | 45 ++ include/hw/adsp/hikey.h | 124 +++++ target/xtensa/Makefile.objs | 1 + target/xtensa/core-hikey.c | 63 +++ target/xtensa/core-hikey/core-isa.h | 694 ++++++++++++++++++++++++++ target/xtensa/core-hikey/gdb-config.c | 357 +++++++++++++ xtensa-host.sh | 8 +- 9 files changed, 1704 insertions(+), 2 deletions(-) create mode 100644 hw/adsp/dsp/hikey.c create mode 100644 hw/adsp/dsp/hikey.h create mode 100644 include/hw/adsp/hikey.h create mode 100644 target/xtensa/core-hikey.c create mode 100644 target/xtensa/core-hikey/core-isa.h create mode 100644 target/xtensa/core-hikey/gdb-config.c diff --git a/hw/adsp/dsp/Makefile.objs b/hw/adsp/dsp/Makefile.objs index 94bbd8a2277b..27c2e60b9dfd 100644 --- a/hw/adsp/dsp/Makefile.objs +++ b/hw/adsp/dsp/Makefile.objs @@ -5,4 +5,5 @@ obj-y += mbox.o obj-y += byt.o obj-y += hsw.o obj-y += cavs.o +obj-y += hikey.o obj-y += common.o diff --git a/hw/adsp/dsp/hikey.c b/hw/adsp/dsp/hikey.c new file mode 100644 index 000000000000..bc6cadb6a1b2 --- /dev/null +++ b/hw/adsp/dsp/hikey.c @@ -0,0 +1,413 @@ +/* Core DSP support HiKey960. + * + * Copyright (C) 2018 John Gunn + * + * Author: John Gunn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "qemu/timer.h" +#include "sysemu/sysemu.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/hw.h" +#include "exec/memory.h" +#include "exec/address-spaces.h" +#include "hw/sysbus.h" +#include "qemu/error-report.h" +#include "qemu/io-bridge.h" + +#include "hw/audio/adsp-dev.h" +#include "hw/adsp/shim.h" +#include "hw/adsp/log.h" + +#include "hw/adsp/hikey.h" +#include "mbox.h" +#include "hikey.h" +#include "common.h" +#include "manifest.h" + +#define MAX_IMAGE_SIZE (1024 * 1024 *4) + +static void adsp_reset(void *opaque) +{ +} + +static uint64_t io_read(void *opaque, hwaddr addr, + unsigned size) +{ + struct adsp_io_info *info = opaque; + struct adsp_dev *adsp = info->adsp; + struct adsp_reg_space *space = info->space; + + log_read(adsp->log, space, addr, size, + info->region[addr >> 2]); + + return info->region[addr >> 2]; +} + +/* SHIM IO from ADSP */ +static void io_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + struct adsp_io_info *info = opaque; + struct adsp_dev *adsp = info->adsp; + struct adsp_reg_space *space = info->space; + + info->region[addr >> 2] = val; + + log_write(adsp->log, space, addr, val, size, + info->region[addr >> 2]); +} + +const MemoryRegionOps hikey_io_ops = { + .read = io_read, + .write = io_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void adsp_pm_msg(struct adsp_dev *adsp, struct qemu_io_msg *msg) +{ +} + +static int bridge_cb(void *data, struct qemu_io_msg *msg) +{ + struct adsp_dev *adsp = (struct adsp_dev *)data; + + switch (msg->type) { + case QEMU_IO_TYPE_REG: + /* mostly handled by SHM, some exceptions */ + //adsp_hikey_shim_msg(adsp, msg); + break; + case QEMU_IO_TYPE_IRQ: + //adsp_hikey_irq_msg(adsp, msg); + break; + case QEMU_IO_TYPE_PM: + adsp_pm_msg(adsp, msg); + break; + case QEMU_IO_TYPE_DMA: + // dw_dma_msg(msg); + break; + case QEMU_IO_TYPE_MEM: + default: + break; + } + + return 0; +} + +enum DRV_HIFI_IMAGE_SEC_LOAD_ENUM { + DRV_HIFI_IMAGE_SEC_LOAD_STATIC = 0, + DRV_HIFI_IMAGE_SEC_LOAD_DYNAMIC, + DRV_HIFI_IMAGE_SEC_UNLOAD, + DRV_HIFI_IMAGE_SEC_UNINIT, + DRV_HIFI_IMAGE_SEC_LOAD_BUTT, +}; +typedef unsigned char DRV_HIFI_IMAGE_SEC_LOAD_ENUM_UINT8; + +enum DRV_HIFI_IMAGE_SEC_TYPE_ENUM { + DRV_HIFI_IMAGE_SEC_TYPE_CODE = 0, + DRV_HIFI_IMAGE_SEC_TYPE_DATA, + DRV_HIFI_IMAGE_SEC_TYPE_BSS, + DRV_HIFI_IMAGE_SEC_TYPE_BUTT, +}; +typedef unsigned char DRV_HIFI_IMAGE_SEC_TYPE_ENUM_UINT8; + +struct drv_hifi_image_sec { + unsigned short sn; + DRV_HIFI_IMAGE_SEC_TYPE_ENUM_UINT8 type; + DRV_HIFI_IMAGE_SEC_LOAD_ENUM_UINT8 load_attib; + unsigned int src_offset; + unsigned int des_addr; + unsigned int size; +}; + +#define HIFI_SEC_MAX_NUM 64 + +struct drv_hifi_image_head { + char time_stamp[24]; + unsigned int image_size; + unsigned int sections_num; + struct drv_hifi_image_sec sections[HIFI_SEC_MAX_NUM]; +}; + +struct image_partition_table { + unsigned long phy_addr_start; + unsigned long phy_addr_end; + unsigned int size; + unsigned long remap_addr; +}; + +static void load_legacy_fmt(const struct adsp_desc *board, + struct adsp_dev *adsp, void *img_ptr) +{ + unsigned int i = 0; + struct drv_hifi_image_head *hifi_img = NULL; + unsigned long remap_dest_addr; + struct adsp_mem_desc *mem; + + hifi_img = (struct drv_hifi_image_head *)img_ptr; + printf("sections :%u, image_size:%u\n", hifi_img->sections_num, + hifi_img->image_size); + + for (i = 0; i < hifi_img->sections_num; i++) { + remap_dest_addr = 0; + + printf("section: %u\n", i); + printf(" addr: 0x%x, load_attib:%u, size:%u, sn:%hu, src_offset:%x, type:%u\n", + hifi_img->sections[i].des_addr, hifi_img->sections[i].load_attib, + hifi_img->sections[i].size, hifi_img->sections[i].sn, + hifi_img->sections[i].src_offset, hifi_img->sections[i].type); + + remap_dest_addr = (unsigned long)hifi_img->sections[i].des_addr; + + if (hifi_img->sections[i].type != DRV_HIFI_IMAGE_SEC_TYPE_BSS) { + + if (hifi_img->sections[i].load_attib == + (unsigned char)DRV_HIFI_IMAGE_SEC_UNLOAD) { + printf("unload section\n"); + continue; + } + + mem = adsp_get_mem_space(adsp, remap_dest_addr); + if (!mem) { + printf("no mem for 0x%lx\n", remap_dest_addr); + continue; + } + printf(" mem %s base 0x%lx size 0x%lx\n", mem->name, mem->base, mem->size); + printf(" copy dest off 0x%lx src off 0x%x size 0x%x\n", remap_dest_addr - mem->base, + hifi_img->sections[i].src_offset, + hifi_img->sections[i].size); + memcpy(mem->ptr + (remap_dest_addr - mem->base), (void *)hifi_img + + hifi_img->sections[i].src_offset, + hifi_img->sections[i].size); + } else { + printf(" bss\n"); + } + } + +} + +static struct adsp_dev *adsp_init(const struct adsp_desc *board, + MachineState *machine, const char *name) +{ + struct adsp_dev *adsp; + void *img_ptr; + int n, size; + uint32_t id; + + adsp = g_malloc(sizeof(*adsp)); + adsp->log = log_init(NULL); /* TODO: add log name to cmd line */ + adsp->desc = board; + adsp->shm_idx = 0; + adsp->system_memory = get_system_memory(); + adsp->machine_opts = qemu_get_machine_opts(); + adsp->cpu_model = machine->cpu_model; + adsp->kernel_filename = qemu_opt_get(adsp->machine_opts, "kernel"); + + /* initialise CPU */ + if (!adsp->cpu_model) { + adsp->cpu_model = XTENSA_DEFAULT_CPU_MODEL; + } + + for (n = 0; n < smp_cpus; n++) { + + adsp->xtensa[n] = g_malloc(sizeof(struct adsp_xtensa)); + adsp->xtensa[n]->cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); + + if (adsp->xtensa[n]->cpu == NULL) { + error_report("unable to find CPU definition '%s'", + adsp->cpu_model); + exit(EXIT_FAILURE); + } + + adsp->xtensa[n]->env = &adsp->xtensa[n]->cpu->env; + adsp->xtensa[n]->env->sregs[PRID] = n; + + qemu_register_reset(adsp_reset, adsp->xtensa[n]->cpu); + + /* Need MMU initialized prior to ELF loading, + * so that ELF gets loaded into virtual addresses + */ + cpu_reset(CPU(adsp->xtensa[n]->cpu)); + } + + adsp_create_memory_regions(adsp); + adsp_create_io_devices(adsp, &hikey_io_ops); + + /* reset all devices to init state */ + qemu_devices_reset(); + + /* initialise bridge to x86 host driver */ + qemu_io_register_child(name, &bridge_cb, (void*)adsp); + + /* load binary file if one is specified on cmd line otherwise finish */ + if (adsp->kernel_filename == NULL) { + printf(" ** Hikey 960 Xtensa HiFi3 DSP initialised.\n" + " ** Waiting for host to load firmware...\n"); + return adsp; + } + + printf("now loading:\n kernel %s\n", adsp->kernel_filename); + + /* load the binary image and copy to SRAM */ + img_ptr = g_malloc(MAX_IMAGE_SIZE); + size = load_image_size(adsp->kernel_filename, img_ptr, + MAX_IMAGE_SIZE); + + id = *((uint32_t*)img_ptr); + + /* is file using legacy format or SOF format */ + if (id == 0x3a464948) { + + printf("Legacy Header 0x%x found\n", id); + + /* use lecagy fmt */ + load_legacy_fmt(board, adsp, img_ptr); + + } else { + + printf("SOF Header 0x%x\n", id); + + /* use SOF format */ + adsp_load_modules(adsp, img_ptr, size); + } + + return adsp; +} + +/* this option can be used to debug some memory spaces so that trace can be seen */ +#define SPACE_TRACE 0 + +/* hikey devices */ +static struct adsp_reg_space hikey_io[] = { + {.name = "hifi-uart", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_HIFI_UART_BASE, .size = ADSP_HIKEY_HIFI_UART_SIZE},}, + {.name = "icc-debug", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_ICC_DEBUG_BASE, .size = ADSP_HIKEY_ICC_DEBUG_SIZE},}, + {.name = "ddr-sechead", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_DDR_SEC_HEAD_BASE, .size = ADSP_HIKEY_DDR_SEC_HEAD_SIZE},}, + {.name = "sound-trigger", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_SOUND_TRIGGER_BASE, .size = ADSP_HIKEY_SOUND_TRIGGER_SIZE},}, + {.name = "codec-dma-config", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_CODEC_DMA_CONF_BASE, .size = ADSP_HIKEY_CODEC_DMA_CONF_SIZE},}, +#if SPACE_TRACE + {.name = "music-data", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_MUSIC_DATA_BASE, .size = ADSP_HIKEY_MUSIC_DATA_SIZE},}, + {.name = "pcm-data", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_PCM_DATA_BASE, .size = ADSP_HIKEY_PCM_DATA_SIZE},}, + {.name = "panic-stack", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_PANIC_STACK_BASE, .size = ADSP_HIKEY_PANIC_STACK_SIZE},}, + {.name = "flag-data", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_FLAG_DATA_BASE, .size = ADSP_HIKEY_FLAG_DATA_SIZE},}, + {.name = "ap-nv", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_AP_NV_BASE, .size = ADSP_HIKEY_AP_NV_SIZE},}, + {.name = "ap-hifimb", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_AP_HIFIMB_BASE, .size = ADSP_HIKEY_AP_HIFIMB_SIZE},}, + {.name = "codec-dmabuf", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_CODEC_DMA_BUF_BASE, .size = ADSP_HIKEY_CODEC_DMA_BUF_SIZE},}, + {.name = "pcm-upload", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_PCM_UPLOAD_BASE, .size = ADSP_HIKEY_PCM_UPLOAD_SIZE},}, + {.name = "share", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_SHARE_BASE, .size = ADSP_HIKEY_SHARE_SIZE},}, + {.name = "unsec-rsvd", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_UNSEC_RSVD_BASE, .size = ADSP_HIKEY_UNSEC_RSVD_SIZE},}, + {.name = "hifi-run", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_HIFI_RUN_BASE, .size = ADSP_HIKEY_HIFI_RUN_SIZE},}, + {.name = "ocram-back", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_OCRAM_BACK_BASE, .size = ADSP_HIKEY_OCRAM_BACK_SIZE},}, + {.name = "tcm-back", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_TCM_BACK_BASE, .size = ADSP_HIKEY_TCM_BACK_SIZE},}, + {.name = "img-back", .reg_count = 0, .reg = NULL, + .desc = {.base = ADSP_HIKEY_IMG_BACK_BASE, .size = ADSP_HIKEY_IMG_BACK_SIZE},}, +#endif +}; + +static struct adsp_mem_desc hikey_mem[] = { +#if !SPACE_TRACE + {.name = "music-data", .base = ADSP_HIKEY_MUSIC_DATA_BASE, + .size = ADSP_HIKEY_MUSIC_DATA_SIZE}, + {.name = "pcm-data", .base = ADSP_HIKEY_PCM_DATA_BASE, + .size = ADSP_HIKEY_PCM_DATA_SIZE,}, + {.name = "panic-stack", .base = ADSP_HIKEY_PANIC_STACK_BASE, + .size = ADSP_HIKEY_PANIC_STACK_SIZE}, + {.name = "flag-data", .base = ADSP_HIKEY_FLAG_DATA_BASE, + .size = ADSP_HIKEY_FLAG_DATA_SIZE}, + {.name = "ap-nv", .base = ADSP_HIKEY_AP_NV_BASE, + .size = ADSP_HIKEY_AP_NV_SIZE}, + {.name = "ap-hifimb", .base = ADSP_HIKEY_AP_HIFIMB_BASE, + .size = ADSP_HIKEY_AP_HIFIMB_SIZE}, + {.name = "codec-dmabuf", .base = ADSP_HIKEY_CODEC_DMA_BUF_BASE, + .size = ADSP_HIKEY_CODEC_DMA_BUF_SIZE}, + {.name = "pcm-upload", .base = ADSP_HIKEY_PCM_UPLOAD_BASE, + .size = ADSP_HIKEY_PCM_UPLOAD_SIZE}, + {.name = "share", .base = ADSP_HIKEY_SHARE_BASE, + .size = ADSP_HIKEY_SHARE_SIZE}, + {.name = "unsec-rsvd", .base = ADSP_HIKEY_UNSEC_RSVD_BASE, + .size = ADSP_HIKEY_UNSEC_RSVD_SIZE}, + {.name = "hifi-run", .base = ADSP_HIKEY_HIFI_RUN_BASE, + .size = ADSP_HIKEY_HIFI_RUN_SIZE}, + {.name = "ocram-back", .base = ADSP_HIKEY_OCRAM_BACK_BASE, + .size = ADSP_HIKEY_OCRAM_BACK_SIZE}, + {.name = "tcm-back", .base = ADSP_HIKEY_TCM_BACK_BASE, + .size = ADSP_HIKEY_TCM_BACK_SIZE}, + {.name = "img-back", .base = ADSP_HIKEY_IMG_BACK_BASE, + .size = ADSP_HIKEY_IMG_BACK_SIZE}, +#endif + {.name = "iram", .base = ADSP_HIKEY_HOST_RUN_ITCM_BASE, + .size = ADSP_HIKEY_HOST_RUN_ITCM_SIZE}, + {.name = "dram", .base = ADSP_HIKEY_HOST_RUN_DTCM_BASE, + .size = ADSP_HIKEY_HOST_RUN_DTCM_SIZE,}, + {.name = "imr", .base = ADSP_HIKEY_HOST_HIFI_RUN_BASE, + .size = 1024 * 1024 * 16,}, +}; + +/* Hikey 960 */ +static const struct adsp_desc hikey_dsp_desc = { + .ia_irq = IRQ_NUM_EXT_IPC, + .ext_timer_irq = IRQ_NUM_TIMER1, + + .num_mem = ARRAY_SIZE(hikey_mem), + .mem_region = hikey_mem, + + .num_io = ARRAY_SIZE(hikey_io), + .io_dev = hikey_io, +}; + +static void hikey_adsp_init(MachineState *machine) +{ + struct adsp_dev *adsp; + + adsp = adsp_init(&hikey_dsp_desc, machine, "hikey"); + if (!adsp) + printf("failed to init\n"); + + //adsp->ext_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cavs_ext_timer_cb, adsp); + //adsp->ext_clk_kHz = 2500; +} + +static void xtensa_hikey960_machine_init(MachineClass *mc) +{ + mc->desc = "Hikey 960 HiFi3"; + mc->is_default = true; + mc->init = hikey_adsp_init; + mc->max_cpus = 1; + mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; +} + +DEFINE_MACHINE("adsp_hikey", xtensa_hikey960_machine_init) diff --git a/hw/adsp/dsp/hikey.h b/hw/adsp/dsp/hikey.h new file mode 100644 index 000000000000..11ae86983abf --- /dev/null +++ b/hw/adsp/dsp/hikey.h @@ -0,0 +1,45 @@ +/* Core DSP SHIM support for Broadwell audio DSP. + * + * Copyright (C) 2018 John Gunn + * + * Author: John Gunn jgunn0262@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef __ADSP_HIKEY_H__ +#define __ADSP_HIKEY_H__ + +/* IRQ numbers - TODO: To be completed and confirmed */ +/* IRQ numbers - lots of external IRQs missing due to lack of docs */ +#define IRQ_NUM_EXT_IPC 3 /* Level 3 */ +#define IRQ_NUM_SOFTWARE1 1 /* Level 3 */ +#define IRQ_NUM_TIMER1 5 /* Level 3 */ +#define IRQ_NUM_TIMER2 6 /* Level 4 */ +#define IRQ_NUM_PROFILE 19 /* Level 3 */ +#define IRQ_NUM_WRITE_ERR 29 /* Level 3 */ +#define IRQ_NUM_NMI 0 /* Level 6 */ + +/* IRQ Masks */ +#define IRQ_MASK_EXT_IPC (1 << IRQ_NUM_EXT_IPC) +#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1) +#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1) +#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2) +#define IRQ_MASK_PROFILE (1 << IRQ_NUM_PROFILE) +#define IRQ_MASK_WRITE_ERR (1 << IRQ_NUM_WRITE_ERR) + + +struct adsp_dev; + +#endif diff --git a/include/hw/adsp/hikey.h b/include/hw/adsp/hikey.h new file mode 100644 index 000000000000..f8e7e0e7188a --- /dev/null +++ b/include/hw/adsp/hikey.h @@ -0,0 +1,124 @@ +/* Core DSP support HiKey960. + * + * Copyright (C) 2018 John Gunn + * + * Author: John Gunn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef __HW_ADSP_HIKEY_H__ +#define __HW_ADSP_HIKEY_H__ + +#include +#include +#include +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "exec/hwaddr.h" +#include "hw.h" + +/* + * Host Side + */ + + +#define ADSP_HIKEY_HOST_RUN_SIZE 0x600000 +#define ADSP_HIKEY_HOST_IMAGE_TCMBAK_SIZE 0x34000 +#define ADSP_HIKEY_HOST_IMAGE_SIZE 0x31C000 +#define ADSP_HIKEY_HOST_RUN_ITCM_BASE 0xe8080000 +#define ADSP_HIKEY_HOST_RUN_ITCM_SIZE 0x9000 +#define ADSP_HIKEY_HOST_RUN_DTCM_BASE 0xe8058000 +#define ADSP_HIKEY_HOST_RUN_DTCM_SIZE 0x28000 + +#define ADSP_HIKEY_HOST_PHYMEM_BASE 0x89200000 +#define ADSP_HIKEY_HOST_PHYMEM_SIZE 0x980000 + +#define ADSP_HIKEY_HOST_OCRAM_BACK_BASE 0xE8000000 +#define ADSP_HIKEY_HOST_TCM_BACK_BASE 0xE8058000 +#define ADSP_HIKEY_HOST_HIFI_RUN_BASE 0xC0000000 + + + +/* + * DSP Side - Non Secure 3.5M + */ + +#define ADSP_HIKEY_MUSIC_DATA_BASE 0x8B300000 +#define ADSP_HIKEY_MUSIC_DATA_SIZE 0x00132000 + +#define ADSP_HIKEY_PCM_DATA_BASE 0x8B432000 +#define ADSP_HIKEY_PCM_DATA_SIZE 0x00100000 + +#define ADSP_HIKEY_HIFI_UART_BASE 0x8B532000 +#define ADSP_HIKEY_HIFI_UART_SIZE 0x0007F000 + +#define ADSP_HIKEY_PANIC_STACK_BASE 0x8B5B1000 +#define ADSP_HIKEY_PANIC_STACK_SIZE 0x00001000 + +#define ADSP_HIKEY_ICC_DEBUG_BASE 0x8B5B2000 +#define ADSP_HIKEY_ICC_DEBUG_SIZE 0x00013000 + +#define ADSP_HIKEY_FLAG_DATA_BASE 0x8B5C5000 +#define ADSP_HIKEY_FLAG_DATA_SIZE 0x00001000 + +#define ADSP_HIKEY_DDR_SEC_HEAD_BASE 0x8B5C6000 +#define ADSP_HIKEY_DDR_SEC_HEAD_SIZE 0x00001000 + +#define ADSP_HIKEY_AP_NV_BASE 0x8B5C7000 +#define ADSP_HIKEY_AP_NV_SIZE 0x00032800 + +#define ADSP_HIKEY_AP_HIFIMB_BASE 0x8B5F9800 +#define ADSP_HIKEY_AP_HIFIMB_SIZE 0x00010000 + +#define ADSP_HIKEY_CODEC_DMA_BUF_BASE 0x8B609800 +#define ADSP_HIKEY_CODEC_DMA_BUF_SIZE 0x0000f000 + +#define ADSP_HIKEY_CODEC_DMA_CONF_BASE 0x8B618800 +#define ADSP_HIKEY_CODEC_DMA_CONF_SIZE 0x00000080 + +#define ADSP_HIKEY_SOUND_TRIGGER_BASE 0x8B618880 +#define ADSP_HIKEY_SOUND_TRIGGER_SIZE 0x0000f000 + +#define ADSP_HIKEY_PCM_UPLOAD_BASE 0x8B627880 +#define ADSP_HIKEY_PCM_UPLOAD_SIZE 0x00002000 + +#define ADSP_HIKEY_SHARE_BASE 0x8B629880 +#define ADSP_HIKEY_SHARE_SIZE 0x00003000 + +#define ADSP_HIKEY_UNSEC_RSVD_BASE 0x8B62C880 +#define ADSP_HIKEY_UNSEC_RSVD_SIZE 0x00053780 + +/* + * DSP Side - Secure 9.5M + */ + +#define ADSP_HIKEY_HIFI_RUN_BASE 0x89200000 +#define ADSP_HIKEY_HIFI_RUN_SIZE 0x00600000 + +#define ADSP_HIKEY_OCRAM_BACK_BASE 0x89800000 +#define ADSP_HIKEY_OCRAM_BACK_SIZE 0x00030000 + +#define ADSP_HIKEY_TCM_BACK_BASE 0x89830000 +#define ADSP_HIKEY_TCM_BACK_SIZE 0x00034000 + +#define ADSP_HIKEY_IMG_BACK_BASE 0x89864000 +#define ADSP_HIKEY_IMG_BACK_SIZE 0x0031C000 + +/* mailbox */ +#define ADSP_HIKEY_DSP_MAILBOX_SIZE 0x4000 + + +#endif diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index 2630ecf71603..8323e0ccfa4a 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -7,6 +7,7 @@ obj-y += core-broxton.o obj-y += core-suecreek.o obj-y += core-cannonlake.o obj-y += core-icelake.o +obj-y += core-hikey.o obj-y += core-fsf.o obj-$(CONFIG_SOFTMMU) += monitor.o obj-y += translate.o op_helper.o helper.o cpu.o diff --git a/target/xtensa/core-hikey.c b/target/xtensa/core-hikey.c new file mode 100644 index 000000000000..25aab1ae24ed --- /dev/null +++ b/target/xtensa/core-hikey.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018, John Gunn + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/gdbstub.h" +#include "qemu/host-utils.h" + +#include "core-hikey/core-isa.h" +#include "overlay_tool.h" + +typedef struct +{ + int reg_num; + int bit_start; + int bit_size; +} xtensa_reg_mask_t; + +typedef struct +{ + int count; + xtensa_reg_mask_t *mask; +} xtensa_mask_t; + +static XtensaConfig hikey __attribute__((unused)) = { + .name = "hikey", + .gdb_regmap = { + .num_regs = 158, + .num_core_regs = 52, + .reg = { +#include "core-hikey/gdb-config.c" + } + }, + .clock_freq_khz = 5000, + DEFAULT_SECTIONS +}; + +REGISTER_CORE(hikey) diff --git a/target/xtensa/core-hikey/core-isa.h b/target/xtensa/core-hikey/core-isa.h new file mode 100644 index 000000000000..43c0d82c1afe --- /dev/null +++ b/target/xtensa/core-hikey/core-isa.h @@ -0,0 +1,694 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Customer ID=7729; Build=0x71521; Copyright (c) 1999-2018 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_PDX 0 /* PDX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_PDX8 0 /* PDX8 */ +#define XCHAL_HAVE_PDX16 0 /* PDX16 */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1200005 /* sw version of this header */ + +#define XCHAL_CORE_ID "hifi3_hikey960" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x00071521 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC3B3DFFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1C86D768 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 260002 /* major*100+minor */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_2 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 65536 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 65536 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 1 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 1 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 7 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS 4 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 8 +#define XCHAL_DCACHE_ACCESS_SIZE 8 + +#define XCHAL_DCACHE_BANKS 1 /* number of banks */ + +/* Number of encoded cache attr bits (see for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0xE8080000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0xE8080000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 32768 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Instruction RAM 1: */ +#define XCHAL_INSTRAM1_VADDR 0xE8088000 /* virtual address */ +#define XCHAL_INSTRAM1_PADDR 0xE8088000 /* physical address */ +#define XCHAL_INSTRAM1_SIZE 16384 /* size in bytes */ +#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM1 +#define XCHAL_INSTRAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0xE8058000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0xE8058000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 32768 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 +#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0xE8060000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0xE8060000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 131072 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ +#define XCHAL_HAVE_DATARAM1 +#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +#define XCHAL_HAVE_IDMA 0 +#define XCHAL_HAVE_IDMA_TRANSPOSE 0 + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 27 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 5 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0xDFF7F000 +#define XCHAL_INTLEVEL2_MASK 0x00000F00 +#define XCHAL_INTLEVEL3_MASK 0x200800BE +#define XCHAL_INTLEVEL4_MASK 0x00000040 +#define XCHAL_INTLEVEL5_MASK 0x00000000 +#define XCHAL_INTLEVEL6_MASK 0x00000001 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0xDFF7F000 +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0xDFF7FF00 +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0xFFFFFFBE +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0xFFFFFFFE +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFFFFE +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFFFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 6 +#define XCHAL_INT1_LEVEL 3 +#define XCHAL_INT2_LEVEL 3 +#define XCHAL_INT3_LEVEL 3 +#define XCHAL_INT4_LEVEL 3 +#define XCHAL_INT5_LEVEL 3 +#define XCHAL_INT6_LEVEL 4 +#define XCHAL_INT7_LEVEL 3 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 2 +#define XCHAL_INT10_LEVEL 2 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_INT13_LEVEL 1 +#define XCHAL_INT14_LEVEL 1 +#define XCHAL_INT15_LEVEL 1 +#define XCHAL_INT16_LEVEL 1 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 3 +#define XCHAL_INT20_LEVEL 1 +#define XCHAL_INT21_LEVEL 1 +#define XCHAL_INT22_LEVEL 1 +#define XCHAL_INT23_LEVEL 1 +#define XCHAL_INT24_LEVEL 1 +#define XCHAL_INT25_LEVEL 1 +#define XCHAL_INT26_LEVEL 1 +#define XCHAL_INT27_LEVEL 1 +#define XCHAL_INT28_LEVEL 1 +#define XCHAL_INT29_LEVEL 3 +#define XCHAL_INT30_LEVEL 1 +#define XCHAL_INT31_LEVEL 1 +#define XCHAL_DEBUGLEVEL 5 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 6 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_WRITE_ERROR +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000002 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0xDFF7FF9C +#define XCHAL_INTTYPE_MASK_TIMER 0x00000060 +#define XCHAL_INTTYPE_MASK_NMI 0x00000001 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x20000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00080000 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 5 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 6 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 0 /* non-maskable interrupt */ +#define XCHAL_WRITE_ERROR_INTERRUPT 29 +#define XCHAL_PROFILING_INTERRUPT 19 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL4_NUM 6 +#define XCHAL_INTLEVEL6_NUM 0 +/* (There are many interrupts each at level(s) 1, 2, 3.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 6) */ +#define XCHAL_EXTINT1_NUM 2 /* (intlevel 3) */ +#define XCHAL_EXTINT2_NUM 3 /* (intlevel 3) */ +#define XCHAL_EXTINT3_NUM 4 /* (intlevel 3) */ +#define XCHAL_EXTINT4_NUM 7 /* (intlevel 3) */ +#define XCHAL_EXTINT5_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT6_NUM 9 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 10 /* (intlevel 2) */ +#define XCHAL_EXTINT8_NUM 11 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ +#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 14 /* (intlevel 1) */ +#define XCHAL_EXTINT12_NUM 15 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 16 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT15_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT16_NUM 20 /* (intlevel 1) */ +#define XCHAL_EXTINT17_NUM 21 /* (intlevel 1) */ +#define XCHAL_EXTINT18_NUM 22 /* (intlevel 1) */ +#define XCHAL_EXTINT19_NUM 23 /* (intlevel 1) */ +#define XCHAL_EXTINT20_NUM 24 /* (intlevel 1) */ +#define XCHAL_EXTINT21_NUM 25 /* (intlevel 1) */ +#define XCHAL_EXTINT22_NUM 26 /* (intlevel 1) */ +#define XCHAL_EXTINT23_NUM 27 /* (intlevel 1) */ +#define XCHAL_EXTINT24_NUM 28 /* (intlevel 1) */ +#define XCHAL_EXTINT25_NUM 30 /* (intlevel 1) */ +#define XCHAL_EXTINT26_NUM 31 /* (intlevel 1) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 6) */ +#define XCHAL_INT2_EXTNUM 1 /* (intlevel 3) */ +#define XCHAL_INT3_EXTNUM 2 /* (intlevel 3) */ +#define XCHAL_INT4_EXTNUM 3 /* (intlevel 3) */ +#define XCHAL_INT7_EXTNUM 4 /* (intlevel 3) */ +#define XCHAL_INT8_EXTNUM 5 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 6 /* (intlevel 2) */ +#define XCHAL_INT10_EXTNUM 7 /* (intlevel 2) */ +#define XCHAL_INT11_EXTNUM 8 /* (intlevel 2) */ +#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ +#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT14_EXTNUM 11 /* (intlevel 1) */ +#define XCHAL_INT15_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT16_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT17_EXTNUM 14 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 15 /* (intlevel 1) */ +#define XCHAL_INT20_EXTNUM 16 /* (intlevel 1) */ +#define XCHAL_INT21_EXTNUM 17 /* (intlevel 1) */ +#define XCHAL_INT22_EXTNUM 18 /* (intlevel 1) */ +#define XCHAL_INT23_EXTNUM 19 /* (intlevel 1) */ +#define XCHAL_INT24_EXTNUM 20 /* (intlevel 1) */ +#define XCHAL_INT25_EXTNUM 21 /* (intlevel 1) */ +#define XCHAL_INT26_EXTNUM 22 /* (intlevel 1) */ +#define XCHAL_INT27_EXTNUM 23 /* (intlevel 1) */ +#define XCHAL_INT28_EXTNUM 24 /* (intlevel 1) */ +#define XCHAL_INT30_EXTNUM 25 /* (intlevel 1) */ +#define XCHAL_INT31_EXTNUM 26 /* (intlevel 1) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0xE8080400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0xE8080400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0xE8080000 +#define XCHAL_RESET_VECTOR0_PADDR 0xE8080000 +#define XCHAL_RESET_VECTOR1_VADDR 0xC0000000 +#define XCHAL_RESET_VECTOR1_PADDR 0xC0000000 +#define XCHAL_RESET_VECTOR_VADDR 0xE8080000 +#define XCHAL_RESET_VECTOR_PADDR 0xE8080000 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0xE8080740 +#define XCHAL_USER_VECTOR_PADDR 0xE8080740 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0xE8080700 +#define XCHAL_KERNEL_VECTOR_PADDR 0xE8080700 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xE80807C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xE80807C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0xE8080400 +#define XCHAL_WINDOW_VECTORS_PADDR 0xE8080400 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xE8080580 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xE8080580 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xE80805C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xE80805C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xE8080600 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xE8080600 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xE8080640 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xE8080640 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL5_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL5_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL5_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0xE80806C0 +#define XCHAL_NMI_VECTOR_PADDR 0xE80806C0 +#define XCHAL_INTLEVEL6_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL6_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL6_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 4096 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 4 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ +#define XCHAL_HAVE_MPU 0 +#define XCHAL_MPU_ENTRIES 0 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 0 +#define XCHAL_MPU_ALIGN 0 + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/target/xtensa/core-hikey/gdb-config.c b/target/xtensa/core-hikey/gdb-config.c new file mode 100644 index 000000000000..45b43773b118 --- /dev/null +++ b/target/xtensa/core-hikey/gdb-config.c @@ -0,0 +1,357 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Customer ID=7729; Build=0x71521; Copyright (c) 2003-2018 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + + + /* idx ofs bi sz al targno flags cp typ group name */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, 0,0,0,0,0,0) + XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, 0,0,0,0,0,0) + XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, 0,0,0,0,0,0) + XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, 0,0,0,0,0,0) + XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, 0,0,0,0,0,0) + XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, 0,0,0,0,0,0) + XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, 0,0,0,0,0,0) + XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, 0,0,0,0,0,0) + XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, 0,0,0,0,0,0) + XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, 0,0,0,0,0,0) + XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, 0,0,0,0,0,0) + XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, 0,0,0,0,0,0) + XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, 0,0,0,0,0,0) + XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, 0,0,0,0,0,0) + XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, 0,0,0,0,0,0) + XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, 0,0,0,0,0,0) + XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, 0,0,0,0,0,0) + XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, 0,0,0,0,0,0) + XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, 0,0,0,0,0,0) + XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, 0,0,0,0,0,0) + XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, 0,0,0,0,0,0) + XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, 0,0,0,0,0,0) + XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, 0,0,0,0,0,0) + XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, 0,0,0,0,0,0) + XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, 0,0,0,0,0,0) + XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, 0,0,0,0,0,0) + XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, 0,0,0,0,0,0) + XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 69,276,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0) + XTREG( 70,280, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 71,284,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 72,288,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 73,292,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 74,296,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 75,300,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 76,304,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) + XTREG( 77,308,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0) + XTREG( 78,312, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0) + XTREG( 79,316,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0) + XTREG( 80,320,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0) + XTREG( 81,324,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0) + XTREG( 82,328,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0) + XTREG( 83,332,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) + XTREG( 84,336, 8, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) + XTREG( 85,340,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) + XTREG( 86,344,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) + XTREG( 87,348,29, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_cw_sd_no, 0,0,0,0,0,0) + XTREG( 88,352,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0) + XTREG( 89,356,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0) + XTREG( 90,360,64, 8, 8,0x1010,0x0006, 1, 4,0x0101,aed0, + "03:04:04:01","03:04:04:cf",0,0,0,0) + XTREG( 91,368,64, 8, 8,0x1011,0x0006, 1, 4,0x0101,aed1, + "03:04:14:01","03:04:14:cf",0,0,0,0) + XTREG( 92,376,64, 8, 8,0x1012,0x0006, 1, 4,0x0101,aed2, + "03:04:24:01","03:04:24:cf",0,0,0,0) + XTREG( 93,384,64, 8, 8,0x1013,0x0006, 1, 4,0x0101,aed3, + "03:04:34:01","03:04:34:cf",0,0,0,0) + XTREG( 94,392,64, 8, 8,0x1014,0x0006, 1, 4,0x0101,aed4, + "03:04:44:01","03:04:44:cf",0,0,0,0) + XTREG( 95,400,64, 8, 8,0x1015,0x0006, 1, 4,0x0101,aed5, + "03:04:54:01","03:04:54:cf",0,0,0,0) + XTREG( 96,408,64, 8, 8,0x1016,0x0006, 1, 4,0x0101,aed6, + "03:04:64:01","03:04:64:cf",0,0,0,0) + XTREG( 97,416,64, 8, 8,0x1017,0x0006, 1, 4,0x0101,aed7, + "03:04:74:01","03:04:74:cf",0,0,0,0) + XTREG( 98,424,64, 8, 8,0x1018,0x0006, 1, 4,0x0101,aed8, + "03:04:84:01","03:04:84:cf",0,0,0,0) + XTREG( 99,432,64, 8, 8,0x1019,0x0006, 1, 4,0x0101,aed9, + "03:04:94:01","03:04:94:cf",0,0,0,0) + XTREG(100,440,64, 8, 8,0x101a,0x0006, 1, 4,0x0101,aed10, + "03:04:a4:01","03:04:a4:cf",0,0,0,0) + XTREG(101,448,64, 8, 8,0x101b,0x0006, 1, 4,0x0101,aed11, + "03:04:b4:01","03:04:b4:cf",0,0,0,0) + XTREG(102,456,64, 8, 8,0x101c,0x0006, 1, 4,0x0101,aed12, + "03:04:c4:01","03:04:c4:cf",0,0,0,0) + XTREG(103,464,64, 8, 8,0x101d,0x0006, 1, 4,0x0101,aed13, + "03:04:d4:01","03:04:d4:cf",0,0,0,0) + XTREG(104,472,64, 8, 8,0x101e,0x0006, 1, 4,0x0101,aed14, + "03:04:e4:01","03:04:e4:cf",0,0,0,0) + XTREG(105,480,64, 8, 8,0x101f,0x0006, 1, 4,0x0101,aed15, + "03:04:f4:01","03:04:f4:cf",0,0,0,0) + XTREG(106,488,64, 8, 8,0x1020,0x0006, 1, 4,0x0101,u0, + "08:0f:14:00:0f:00:dc:fb:eb","08:0f:04:00:0f:00:dc:fb:eb",0,0,0,0) + XTREG(107,496,64, 8, 8,0x1021,0x0006, 1, 4,0x0101,u1, + "08:2f:14:00:0f:00:dc:fb:eb","08:2f:04:00:0f:00:dc:fb:eb",0,0,0,0) + XTREG(108,504,64, 8, 8,0x1022,0x0006, 1, 4,0x0101,u2, + "08:4f:14:00:0f:00:dc:fb:eb","08:4f:04:00:0f:00:dc:fb:eb",0,0,0,0) + XTREG(109,512,64, 8, 8,0x1023,0x0006, 1, 4,0x0101,u3, + "08:6f:14:00:0f:00:dc:fb:eb","08:6f:04:00:0f:00:dc:fb:eb",0,0,0,0) + XTREG(110,520,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG(111,524, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG(112,528, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0) + XTREG(113,532, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG(114,536,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG(115,540,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG(116,544,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG(117,548,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG(118,552,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG(119,556,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG(120,560,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG(121,564,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG(122,568,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG(123,572,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG(124,576,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG(125,580,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG(126,584,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) + XTREG(127,588,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG(128,592,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG(129,596,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG(130,600,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG(131,604,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG(132,608,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) + XTREG(133,612,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG(134,616,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG(135,620,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG(136,624,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG(137,628,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG(138,632,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) + XTREG(139,636, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG(140,640,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG(141,644,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG(142,648,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG(143,652,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG(144,656,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG(145,660, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG(146,664,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG(147,668,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG(148,672,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG(149,676,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG(150,680, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG(151,684,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG(152,688,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG(153,692,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG(154,696,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG(155,700,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG(156,704,32, 4, 4,0x201e,0x000f,-2, 4,0x0101,pwrctl, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(157,708,32, 4, 4,0x201f,0x000f,-2, 4,0x0101,pwrstat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(158,712, 1, 4, 4,0x2020,0x000f,-2, 4,0x0101,eristat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(159,716,32, 4, 4,0x2021,0x000f,-2, 4,0x0101,cs_itctrl, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(160,720,16, 4, 4,0x2022,0x000f,-2, 4,0x0101,cs_claimset, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(161,724,16, 4, 4,0x2023,0x000f,-2, 4,0x0101,cs_claimclr, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(162,728,32, 4, 4,0x2024,0x000d,-2, 4,0x0101,cs_lockaccess, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(163,732,32, 4, 4,0x2025,0x000b,-2, 4,0x0101,cs_lockstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(164,736, 1, 4, 4,0x2026,0x000b,-2, 4,0x0101,cs_authstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(165,740,32, 4, 4,0x2035,0x0003,-2, 4,0x0101,trax_id, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(166,744,32, 4, 4,0x2036,0x000f,-2, 4,0x0101,trax_control, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(167,748,32, 4, 4,0x2037,0x000b,-2, 4,0x0101,trax_status, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(168,752,32, 4, 4,0x2038,0x000f,-2, 4,0x0101,trax_data, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(169,756,32, 4, 4,0x2039,0x000f,-2, 4,0x0101,trax_address, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(170,760,32, 4, 4,0x203a,0x000f,-2, 4,0x0101,trax_pctrigger, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(171,764,32, 4, 4,0x203b,0x000f,-2, 4,0x0101,trax_pcmatch, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(172,768,32, 4, 4,0x203c,0x000f,-2, 4,0x0101,trax_delay, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(173,772,32, 4, 4,0x203d,0x000f,-2, 4,0x0101,trax_memstart, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(174,776,32, 4, 4,0x203e,0x000f,-2, 4,0x0101,trax_memend, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(175,780,32, 4, 4,0x204c,0x000f,-2, 4,0x0101,pmg, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(176,784,32, 4, 4,0x204d,0x000f,-2, 4,0x0101,pmpc, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(177,788,32, 4, 4,0x204e,0x000f,-2, 4,0x0101,pm0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(178,792,32, 4, 4,0x204f,0x000f,-2, 4,0x0101,pm1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(179,796,32, 4, 4,0x2050,0x000f,-2, 4,0x0101,pm2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(180,800,32, 4, 4,0x2051,0x000f,-2, 4,0x0101,pm3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(181,804,32, 4, 4,0x2052,0x000f,-2, 4,0x0101,pmctrl0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(182,808,32, 4, 4,0x2053,0x000f,-2, 4,0x0101,pmctrl1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(183,812,32, 4, 4,0x2054,0x000f,-2, 4,0x0101,pmctrl2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(184,816,32, 4, 4,0x2055,0x000f,-2, 4,0x0101,pmctrl3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(185,820,32, 4, 4,0x2056,0x000f,-2, 4,0x0101,pmstat0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(186,824,32, 4, 4,0x2057,0x000f,-2, 4,0x0101,pmstat1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(187,828,32, 4, 4,0x2058,0x000f,-2, 4,0x0101,pmstat2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(188,832,32, 4, 4,0x2059,0x000f,-2, 4,0x0101,pmstat3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(189,836,32, 4, 4,0x205a,0x0003,-2, 4,0x0101,ocdid, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(190,840,32, 4, 4,0x205b,0x000f,-2, 4,0x0101,ocd_dcrclr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(191,844,32, 4, 4,0x205c,0x000f,-2, 4,0x0101,ocd_dcrset, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(192,848,32, 4, 4,0x205d,0x000f,-2, 4,0x0101,ocd_dsr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(193,852,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) + XTREG(194,856,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) + XTREG(195,860,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) + XTREG(196,864,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) + XTREG(197,868,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) + XTREG(198,872,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) + XTREG(199,876,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) + XTREG(200,880,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) + XTREG(201,884,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) + XTREG(202,888,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) + XTREG(203,892,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) + XTREG(204,896,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) + XTREG(205,900,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) + XTREG(206,904,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) + XTREG(207,908,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) + XTREG(208,912,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) + XTREG(209,916, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(210,917, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(211,918, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(212,919, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(213,920, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(214,921, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(215,922, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(216,923, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(217,924, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(218,925, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(219,926, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(220,927, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(221,928, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(222,929, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(223,930, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(224,931, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(225,932, 4, 4, 4,0x2007,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask16,0,0,0) + XTREG(226,936, 1, 4, 4,0x2008,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask17,0,0,0) + XTREG(227,940, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask18,0,0,0) + XTREG(228,944, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask19,0,0,0) + XTREG(229,948, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask20,0,0,0) + XTREG(230,952, 4, 4, 4,0x200c,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask21,0,0,0) + XTREG(231,956,40, 8, 4,0x200d,0x0006,-2, 6,0x1010,acc, + 0,0,&xtensa_mask22,0,0,0) + XTREG(232,964, 4, 4, 4,0x2012,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask23,0,0,0) + XTREG(233,968, 1, 4, 4,0x2015,0x0006, 1, 5,0x1010,ae_overflow, + 0,0,&xtensa_mask24,0,0,0) + XTREG(234,972, 7, 4, 4,0x2016,0x0006, 1, 5,0x1010,ae_sar, + 0,0,&xtensa_mask25,0,0,0) + XTREG(235,976, 1, 4, 4,0x2017,0x0006, 1, 5,0x1010,ae_cwrap, + 0,0,&xtensa_mask26,0,0,0) + XTREG(236,980, 4, 4, 4,0x2018,0x0006, 1, 5,0x1010,ae_bitptr, + 0,0,&xtensa_mask27,0,0,0) + XTREG(237,984, 4, 4, 4,0x2019,0x0006, 1, 5,0x1010,ae_bitsused, + 0,0,&xtensa_mask28,0,0,0) + XTREG(238,988, 4, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_tablesize, + 0,0,&xtensa_mask29,0,0,0) + XTREG(239,992, 4, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_first_ts, + 0,0,&xtensa_mask30,0,0,0) + XTREG(240,996,27, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_nextoffset, + 0,0,&xtensa_mask31,0,0,0) + diff --git a/xtensa-host.sh b/xtensa-host.sh index 11ae9d7b2068..8496a412193c 100755 --- a/xtensa-host.sh +++ b/xtensa-host.sh @@ -1,7 +1,7 @@ if [ $# -lt 1 ] then echo "usage: $0 device [-k kernel] [-t] [-d] [-i] [-r rom] [-c] [-g] [-o time log]" - echo "supported devices: byt, cht, hsw, bdw, bxt, sue, cnl, icl, skl, kbl" + echo "supported devices: byt, cht, hsw, bdw, bxt, sue, cnl, icl, skl, kbl, hky" echo "[-k] | [--kernel]: load firmware kernel image" echo "[-r] | [--rom]: load firmware ROM image" echo "[-t] | [--trace]: trace DSP instructions" @@ -59,9 +59,13 @@ case $1 in CPU="icelake" ADSP="adsp_icl" ;; +*hky) + CPU="hikey" + ADSP="adsp_hikey" + ;; *) echo "usage: $0 device" - echo "supported devices: byt, cht, hsw, bdw, bxt, sue, cnl, icl" + echo "supported devices: byt, cht, hsw, bdw, bxt, sue, cnl, icl, hky" ./xtensa-softmmu/qemu-system-xtensa -machine help exit ;;