diff --git a/src/platform/mt8196/include/platform/drivers/mt_reg_base.h b/src/platform/mt8196/include/platform/drivers/mt_reg_base.h
index 21605116506b..bb990270512e 100644
--- a/src/platform/mt8196/include/platform/drivers/mt_reg_base.h
+++ b/src/platform/mt8196/include/platform/drivers/mt_reg_base.h
@@ -22,7 +22,6 @@
 #define MTK_ADSP_GENERAL_IRQ_CLR	(MTK_DSP_CFGREG_BASE + 0x0038)
 #define MTK_ADSP_DVFSRC_STATE		(MTK_DSP_CFGREG_BASE + 0x003c)
 #define MTK_ADSP_DVFSRC_REQ		(MTK_DSP_CFGREG_BASE + 0x0040)
-//todo
 #define MTK_ADSP_DDREN_REQ_0		(MTK_DSP_CFGREG_BASE + 0x0044)
 #define MTK_ADSP_SPM_ACK		(MTK_DSP_CFGREG_BASE + 0x004c)
 #define MTK_ADSP_IRQ_EN			(MTK_DSP_CFGREG_BASE + 0x0050)
@@ -53,7 +52,6 @@
 #define INTC_IRQ_GRP0_STA0               (MTK_ADSP_INTC_BASE + 0x0C0)
 #define INTC_GRP_IRQ_OUT_STA             (MTK_ADSP_INTC_BASE + 0x140)
 
-//todo
 #define MTK_GPR_RW_REG0			(MTK_DSP_CFGREG_BASE + 0x0440)
 #define MTK_GPR_RW_REG1			(MTK_DSP_CFGREG_BASE + 0x0444)
 #define MTK_GPR_RW_REG2			(MTK_DSP_CFGREG_BASE + 0x0448)
@@ -91,7 +89,6 @@
 #define MTK_DSP_CKCTRL_BASE		(MTK_DSP_CFGREG_BASE + 0x1000)
 #define MTK_DSP_CKCTRL_SIZE		0x1000
 
-//todo
 #define MTK_DSP_OS_TIMER_BASE		(MTK_DSP_CFGREG_BASE + 0xB000)
 #define MTK_DSP_OS_TIMER_SIZE		0x1000
 
@@ -106,35 +103,6 @@
 #define MTK_DSP_SECURE_BASE		(MTK_DSP_CFGREG_BASE + 0x345000)
 #define MTK_MBOX_IRQ_IN                 (MTK_DSP_SECURE_BASE + 0x70)
 
-#define MTK_REG_TOPCKGEN_BASE		0x10000000
-#define MTK_REG_TOPCKGEN_SIZE		0x1000
-#define MTK_CLK_CFG_UPDATE1                  (MTK_REG_TOPCKGEN_BASE + 0x0008)
-#define MTK_CLK_CFG_13_STA                   (MTK_REG_TOPCKGEN_BASE + 0x00E0)
-#define MTK_CLK_CFG_13_SET                   (MTK_REG_TOPCKGEN_BASE + 0x00E4)
-#define MTK_CLK_CFG_13_CLR                   (MTK_REG_TOPCKGEN_BASE + 0x00E8)
-#define MTK_ADSP_CK_UPDATE                   (0x1 << 23)
-#define MTK_ADSP_SEL_BASE                    (16)
-
-//todo
-#define MTK_CLK_CFG_UPDATE2		(MTK_REG_TOPCKGEN_BASE + 0x000C)
-#define MTK_CLK_CFG_17			(MTK_REG_TOPCKGEN_BASE + 0x0EC)
-#define MTK_CLK_CFG_17_SET		(MTK_REG_TOPCKGEN_BASE + 0x0F0)
-#define MTK_CLK_CFG_17_CLR		(MTK_REG_TOPCKGEN_BASE + 0x0F4)
-#define MTK_CLK_CFG_17_CLR		(MTK_REG_TOPCKGEN_BASE + 0x0F4)
-
-//todo, pll base?
-#define MTK_REG_APMIXDSYS_BASE		0x10000800
-#define MTK_REG_APMIXDSYS_SIZE		0x1000
-
-//todo
-#define MTK_PLLEN_ALL_EN        (MTK_REG_APMIXDSYS_BASE + 0x0080)
-#define MTK_PLLEN_ALL_SET       (MTK_REG_APMIXDSYS_BASE + 0x0084)
-#define MTK_PLLEN_ALL_CLR       (MTK_REG_APMIXDSYS_BASE + 0x0088)
-#define MTK_ADSPPLL_CON0		(MTK_REG_APMIXDSYS_BASE + 0x028c)
-#define MTK_ADSPPLL_CON1		(MTK_REG_APMIXDSYS_BASE + 0x0290)
-#define MTK_PLL_ADSP_EN_BIT     (0x1 << 3)
-
-
 /* MBOX registers */
 #define MTK_ADSP_MBOX_BASE		(MTK_DSP_CFGREG_BASE + 0x350000)
 #define MTK_ADSP_MBOX_REG_BASE(x)	(MTK_ADSP_MBOX_BASE + (0x10000 * (x)))
diff --git a/src/platform/mt8196/include/platform/lib/clk.h b/src/platform/mt8196/include/platform/lib/clk.h
index eb6687a679ca..f4f311948fb4 100644
--- a/src/platform/mt8196/include/platform/lib/clk.h
+++ b/src/platform/mt8196/include/platform/lib/clk.h
@@ -22,41 +22,6 @@ struct sof;
 #define NUM_CLOCKS				1
 #define NUM_CPU_FREQ				2
 
-/* MTK_ADSPPLL_CON1 */
-#define MTK_PLL_DIV_RATIO_800M			0x810F6276
-#define MTK_PLL_DIV_RATIO_400M			0x831EC4ED
-
-/* MTK_ADSPPLL_CON3 */
-#define MTK_PLL_EN				BIT(9)
-#define MTK_PLL_PWR_ON				BIT(0)
-#define MTK_PLL_ISO_EN				BIT(1)
-
-/* MTK_CLK_CFG_UPDATE2 */
-#define MTK_CLK_UPDATE_ADSK_CLK			BIT(4)
-#define MTK_CLK_UPDATE_AUDIO_LOCAL_BUS_CLK	BIT(5)
-
-/* MTK_CLK_CFG_17[3:0] */
-#define MTK_CLK_ADSP_OFFSET			0
-#define MTK_CLK_ADSP_MASK			0xF
-#define MTK_CLK_ADSP_26M			0
-#define MTK_CLK_ADSP_ADSPPLL			8 /* 800M */
-#define MTK_CLK_ADSP_ADSPPLL_D_2		9 /* 400M */
-
-/* MTK_CLK_CFG_17[11:8] */
-#define MTK_CLK_AUDIO_LOCAL_BUS_OFFSET		8
-#define MTK_CLK_AUDIO_LOCAL_BUS_MASK		0xF
-#define MTK_CLK_AUDIO_LOCAL_BUS_26M		0
-#define MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_7	6 /* 312M */
-#define MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_4	7 /* 546M */
-
-/* List resource from low to high request */
-/* 0 is the lowest request */
-enum ADSP_HW_DSP_CLK {
-	ADSP_CLK_26M = 0,
-	ADSP_CLK_PLL_400M,
-	ADSP_CLK_PLL_800M,
-};
-
 void platform_clock_init(struct sof *sof);
 
 #endif /* __PLATFORM_LIB_CLK_H__ */
diff --git a/src/platform/mt8196/lib/clk.c b/src/platform/mt8196/lib/clk.c
index 4273d95f0529..69af725dec73 100644
--- a/src/platform/mt8196/lib/clk.c
+++ b/src/platform/mt8196/lib/clk.c
@@ -32,97 +32,18 @@ STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
 
 static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS];
 
-static void clk_dsppll_enable(uint32_t value)
-{
-	tr_dbg(&clkdrv_tr, "clk_dsppll_enable %d\n", value);
-
-	switch (value) {
-	case ADSP_CLK_PLL_400M:
-		io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_400M);
-		break;
-	case ADSP_CLK_PLL_800M:
-		io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_800M);
-		break;
-	default:
-		tr_err(&clkdrv_tr, "invalid dsppll: %d\n", value);
-		return;
-	}
-
-	//todo
-	//io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, MTK_PLL_PWR_ON);
-	wait_delay_us(1);
-	//io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, 0);
-	wait_delay_us(1);
-	io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_EN, MTK_PLL_EN);
-	wait_delay_us(20);
-}
-
-static void clk_dsppll_disable(void)
-{
-	tr_dbg(&clkdrv_tr, "clk_dsppll_disable\n");
-
-	io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_EN, 0);
-	wait_delay_us(1);
-	//io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, MTK_PLL_ISO_EN);
-	wait_delay_us(1);
-	//io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, 0);
-}
-
-static void set_mux_adsp_sel(uint32_t value)
-{
-	io_reg_write(MTK_CLK_CFG_17_CLR, MTK_CLK_ADSP_MASK << MTK_CLK_ADSP_OFFSET);
-	io_reg_write(MTK_CLK_CFG_17_SET, value << MTK_CLK_ADSP_OFFSET);
-	io_reg_write(MTK_CLK_CFG_UPDATE2, MTK_CLK_UPDATE_ADSK_CLK);
-
-	tr_dbg(&clkdrv_tr, "adsp_clk_mux=%x, CLK_CFG_17=0x%08x\n",
-	       value, io_reg_read(MTK_CLK_CFG_17));
-}
-
-static void set_mux_adsp_bus_sel(uint32_t value)
-{
-	io_reg_write(MTK_CLK_CFG_17_CLR,
-		     MTK_CLK_AUDIO_LOCAL_BUS_MASK << MTK_CLK_AUDIO_LOCAL_BUS_OFFSET);
-	io_reg_write(MTK_CLK_CFG_17_SET, value << MTK_CLK_AUDIO_LOCAL_BUS_OFFSET);
-	io_reg_write(MTK_CLK_CFG_UPDATE2, MTK_CLK_UPDATE_AUDIO_LOCAL_BUS_CLK);
-
-	tr_dbg(&clkdrv_tr, "audio_local_bus_mux=%x, CLK_CFG_17=0x%08x\n",
-	       value, io_reg_read(MTK_CLK_CFG_17));
-}
-
-static int clock_platform_set_dsp_freq(int clock, int freq_idx)
-{
-	int freq = platform_cpu_freq[freq_idx].freq;
-
-	tr_info(&clkdrv_tr, "clock_platform_set_cpu_freq %d\n", freq);
-
-	switch (freq_idx) {
-	case ADSP_CLK_26M:
-		set_mux_adsp_sel(MTK_CLK_ADSP_26M);
-		set_mux_adsp_bus_sel(MTK_CLK_AUDIO_LOCAL_BUS_26M);
-		clk_dsppll_disable();
-		break;
-	case ADSP_CLK_PLL_400M:
-		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
-		clk_dsppll_enable(ADSP_CLK_PLL_400M);
-		set_mux_adsp_sel(MTK_CLK_ADSP_ADSPPLL);
-		set_mux_adsp_bus_sel(MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_7);
-		break;
-	case ADSP_CLK_PLL_800M:
-		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
-		clk_dsppll_enable(ADSP_CLK_PLL_800M);
-		set_mux_adsp_sel(MTK_CLK_ADSP_ADSPPLL);
-		set_mux_adsp_bus_sel(MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_4);
-		break;
-	}
-
-	return 0;
-}
-
 void platform_clock_init(struct sof *sof)
 {
 	int i;
 
+	tr_dbg(&clkdrv_tr, "clock init\n");
 	sof->clocks = platform_shared_get(platform_clocks_info, sizeof(platform_clocks_info));
+
+	/* When the system is in an active state, the DSP clock operates at 800MHz (0.75V).
+	 * In a low power scenario, the DSP enters WFI state, and the clock reduces to 26MHz.
+	 * The clock selection is controlled by the host, and we do not allow SOF to change
+	 * the ADSP frequency.
+	 */
 	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
 		sof->clocks[i] = (struct clock_info){
 			.freqs_num = NUM_CPU_FREQ,
@@ -131,7 +52,7 @@ void platform_clock_init(struct sof *sof)
 			.current_freq_idx = CPU_DEFAULT_IDX,
 			.notification_id = NOTIFIER_ID_CPU_FREQ,
 			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
-			.set_freq = clock_platform_set_dsp_freq,
+			.set_freq = NULL,
 		};
 	}
 }
diff --git a/src/platform/mt8196/platform.c b/src/platform/mt8196/platform.c
index dce816456f8e..714d5ac8961d 100644
--- a/src/platform/mt8196/platform.c
+++ b/src/platform/mt8196/platform.c
@@ -156,7 +156,6 @@ int platform_boot_complete(uint32_t boot_message)
 	return 0;
 }
 
-
 int platform_init(struct sof *sof)
 {
 	int ret;
@@ -185,7 +184,7 @@ int platform_init(struct sof *sof)
 
 	scheduler_init_ll(sof->platform_dma_domain);
 
-	/* initialize the host IPC mechanims */
+	/* initialize the host IPC mechanisms */
 	ipc_init(sof);
 
 #if CONFIG_TRACE