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LiteX currently supports the lm32, mor1k & risc-v architectures. It would be nice if it also support the J2 open processor.
Expected results
LiteX is able to use the J2 core as an option when building SoC components.
Detailed Explanation
J2 open processor
This page describes the j-core processor, a clean-room open source processor and SOC design using the SuperH instruction set, implemented in VHDL and available royalty and patent free under a BSD license.
The current j-core generation, j2, is compatible with the sh2 instruction set, plus two backported sh3 barrel shift instructions (SHAD and SHLD) and a new cmpxchg (mnemonic CAS.L Rm, Rn, @r0 opcode 0010-nnnn-mmmm-0011) based on the IBM 360 instruction. Because it uses an existing instruction set, Linux and gcc and such require only minor tweaking to support this processor.
Brief explanation
LiteX currently supports the lm32, mor1k & risc-v architectures. It would be nice if it also support the J2 open processor.
Expected results
LiteX is able to use the J2 core as an option when building SoC components.
Detailed Explanation
J2 open processor
This page describes the j-core processor, a clean-room open source processor and SOC design using the SuperH instruction set, implemented in VHDL and available royalty and patent free under a BSD license.
The current j-core generation, j2, is compatible with the sh2 instruction set, plus two backported sh3 barrel shift instructions (SHAD and SHLD) and a new cmpxchg (mnemonic CAS.L Rm, Rn, @r0 opcode 0010-nnnn-mmmm-0011) based on the IBM 360 instruction. Because it uses an existing instruction set, Linux and gcc and such require only minor tweaking to support this processor.
Further reading
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