diff --git a/src/machine/machine_stm32_adc_f1.go b/src/machine/machine_stm32_adc_f1.go
index f852f402b3..dedfea8694 100644
--- a/src/machine/machine_stm32_adc_f1.go
+++ b/src/machine/machine_stm32_adc_f1.go
@@ -23,15 +23,6 @@ func InitADC() {
 	// Enable ADC clock
 	enableAltFuncClock(unsafe.Pointer(stm32.ADC1))
 
-	// set scan mode
-	stm32.ADC1.CR1.SetBits(stm32.ADC_CR1_SCAN)
-
-	// clear CONT, ALIGN, EXTRIG and EXTSEL bits from CR2
-	stm32.ADC1.CR2.ClearBits(stm32.ADC_CR2_CONT | stm32.ADC_CR2_ALIGN | stm32.ADC_CR2_EXTTRIG_Msk | stm32.ADC_CR2_EXTSEL_Msk)
-
-	stm32.ADC1.SQR1.ClearBits(stm32.ADC_SQR1_L_Msk)
-	stm32.ADC1.SQR1.SetBits(2 << stm32.ADC_SQR1_L_Pos) // 2 means 3 conversions
-
 	// enable
 	stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_ADON)
 
@@ -61,7 +52,7 @@ func (a ADC) Get() uint16 {
 	stm32.ADC1.SQR3.SetBits(ch)
 
 	// start conversion
-	stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_SWSTART)
+	stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_ADON)
 
 	// wait for conversion to complete
 	for !stm32.ADC1.SR.HasBits(stm32.ADC_SR_EOC) {
@@ -70,12 +61,6 @@ func (a ADC) Get() uint16 {
 	// read result as 16 bit value
 	result := uint16(stm32.ADC1.DR.Get()) << 4
 
-	// clear flag
-	stm32.ADC1.SR.ClearBits(stm32.ADC_SR_EOC)
-
-	// clear rank
-	stm32.ADC1.SQR3.ClearBits(ch)
-
 	return result
 }
 
diff --git a/src/machine/machine_stm32f103.go b/src/machine/machine_stm32f103.go
index 545c431110..b8d494ad7b 100644
--- a/src/machine/machine_stm32f103.go
+++ b/src/machine/machine_stm32f103.go
@@ -221,14 +221,19 @@ func (p Pin) enableClock() {
 
 // Enable peripheral clock. Expand to include all the desired peripherals
 func enableAltFuncClock(bus unsafe.Pointer) {
-	if bus == unsafe.Pointer(stm32.USART1) {
+	switch bus {
+	case unsafe.Pointer(stm32.USART1):
 		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
-	} else if bus == unsafe.Pointer(stm32.USART2) {
+	case unsafe.Pointer(stm32.USART2):
 		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN)
-	} else if bus == unsafe.Pointer(stm32.I2C1) {
+	case unsafe.Pointer(stm32.I2C1):
 		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN)
-	} else if bus == unsafe.Pointer(stm32.SPI1) {
+	case unsafe.Pointer(stm32.SPI1):
 		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
+	case unsafe.Pointer(stm32.ADC1):
+		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC1EN)
+	default:
+		panic("machine: unknown peripheral")
 	}
 }
 
diff --git a/src/runtime/runtime_stm32f103.go b/src/runtime/runtime_stm32f103.go
index ac98de674c..702d773897 100644
--- a/src/runtime/runtime_stm32f103.go
+++ b/src/runtime/runtime_stm32f103.go
@@ -33,10 +33,11 @@ func buffered() int {
 
 // initCLK sets clock to 72MHz using HSE 8MHz crystal w/ PLL X 9 (8MHz x 9 = 72MHz).
 func initCLK() {
-	stm32.FLASH.ACR.SetBits(stm32.FLASH_ACR_LATENCY_WS2)                          // Two wait states, per datasheet
-	stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div2 << stm32.RCC_CFGR_PPRE1_Pos) // prescale PCLK1 = HCLK/2
-	stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div1 << stm32.RCC_CFGR_PPRE2_Pos) // prescale PCLK2 = HCLK/1
-	stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON)                                      // enable HSE clock
+	stm32.FLASH.ACR.SetBits(stm32.FLASH_ACR_LATENCY_WS2)                            // Two wait states, per datasheet
+	stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div2 << stm32.RCC_CFGR_PPRE1_Pos)   // prescale PCLK1 = HCLK/2
+	stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div1 << stm32.RCC_CFGR_PPRE2_Pos)   // prescale PCLK2 = HCLK/1
+	stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_ADCPRE_Div6 << stm32.RCC_CFGR_ADCPRE_Pos) // prescale ADCCLK = PCLK2/6
+	stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON)                                        // enable HSE clock
 
 	// wait for the HSEREADY flag
 	for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) {